1236324Sraj/*- 2236324Sraj * Copyright (c) 2011-2012 Semihalf. 3236324Sraj * All rights reserved. 4236324Sraj * 5236324Sraj * Redistribution and use in source and binary forms, with or without 6236324Sraj * modification, are permitted provided that the following conditions 7236324Sraj * are met: 8236324Sraj * 1. Redistributions of source code must retain the above copyright 9236324Sraj * notice, this list of conditions and the following disclaimer. 10236324Sraj * 2. Redistributions in binary form must reproduce the above copyright 11236324Sraj * notice, this list of conditions and the following disclaimer in the 12236324Sraj * documentation and/or other materials provided with the distribution. 13236324Sraj * 14236324Sraj * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 15236324Sraj * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 16236324Sraj * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 17236324Sraj * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 18236324Sraj * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 19236324Sraj * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 20236324Sraj * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 21236324Sraj * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 22236324Sraj * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 23236324Sraj * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 24236324Sraj * SUCH DAMAGE. 25236324Sraj */ 26236324Sraj 27236324Sraj#include <sys/cdefs.h> 28236324Sraj__FBSDID("$FreeBSD$"); 29236324Sraj 30236324Sraj#include <sys/types.h> 31236324Sraj#include <sys/reboot.h> 32236324Sraj 33236324Sraj#include <machine/machdep.h> 34236324Sraj 35236324Sraj#include <dev/fdt/fdt_common.h> 36236324Sraj 37236324Sraj#include <powerpc/mpc85xx/mpc85xx.h> 38236324Sraj 39236324Srajextern void dcache_enable(void); 40236324Srajextern void dcache_inval(void); 41236324Srajextern void icache_enable(void); 42236324Srajextern void icache_inval(void); 43236324Srajextern void l2cache_enable(void); 44236324Srajextern void l2cache_inval(void); 45236324Sraj 46236324Srajvoid 47236324Srajbooke_init_tlb(vm_paddr_t fdt_immr_pa) 48236324Sraj{ 49236324Sraj 50236324Sraj} 51236324Sraj 52236324Srajvoid 53236324Srajbooke_enable_l1_cache(void) 54236324Sraj{ 55236324Sraj uint32_t csr; 56236324Sraj 57236324Sraj /* Enable D-cache if applicable */ 58236324Sraj csr = mfspr(SPR_L1CSR0); 59236324Sraj if ((csr & L1CSR0_DCE) == 0) { 60236324Sraj dcache_inval(); 61236324Sraj dcache_enable(); 62236324Sraj } 63236324Sraj 64236324Sraj csr = mfspr(SPR_L1CSR0); 65236324Sraj if ((boothowto & RB_VERBOSE) != 0 || (csr & L1CSR0_DCE) == 0) 66236324Sraj printf("L1 D-cache %sabled\n", 67236324Sraj (csr & L1CSR0_DCE) ? "en" : "dis"); 68236324Sraj 69236324Sraj /* Enable L1 I-cache if applicable. */ 70236324Sraj csr = mfspr(SPR_L1CSR1); 71236324Sraj if ((csr & L1CSR1_ICE) == 0) { 72236324Sraj icache_inval(); 73236324Sraj icache_enable(); 74236324Sraj } 75236324Sraj 76236324Sraj csr = mfspr(SPR_L1CSR1); 77236324Sraj if ((boothowto & RB_VERBOSE) != 0 || (csr & L1CSR1_ICE) == 0) 78236324Sraj printf("L1 I-cache %sabled\n", 79236324Sraj (csr & L1CSR1_ICE) ? "en" : "dis"); 80236324Sraj} 81236324Sraj 82236324Sraj#if 0 83236324Srajvoid 84236324Srajbooke_enable_l2_cache(void) 85236324Sraj{ 86236324Sraj uint32_t csr; 87236324Sraj 88236324Sraj /* Enable L2 cache on E500mc */ 89236324Sraj if ((((mfpvr() >> 16) & 0xFFFF) == FSL_E500mc) || 90236324Sraj (((mfpvr() >> 16) & 0xFFFF) == FSL_E5500)) { 91236324Sraj csr = mfspr(SPR_L2CSR0); 92236324Sraj if ((csr & L2CSR0_L2E) == 0) { 93236324Sraj l2cache_inval(); 94236324Sraj l2cache_enable(); 95236324Sraj } 96236324Sraj 97236324Sraj csr = mfspr(SPR_L2CSR0); 98236324Sraj if ((boothowto & RB_VERBOSE) != 0 || (csr & L2CSR0_L2E) == 0) 99236324Sraj printf("L2 cache %sabled\n", 100236324Sraj (csr & L2CSR0_L2E) ? "en" : "dis"); 101236324Sraj } 102236324Sraj} 103236324Sraj 104236324Srajvoid 105236324Srajbooke_enable_l3_cache(void) 106236324Sraj{ 107236324Sraj uint32_t csr, size, ver; 108236324Sraj 109236324Sraj /* Enable L3 CoreNet Platform Cache (CPC) */ 110236324Sraj ver = SVR_VER(mfspr(SPR_SVR)); 111236324Sraj if (ver == SVR_P2041 || ver == SVR_P2041E || ver == SVR_P3041 || 112236324Sraj ver == SVR_P3041E || ver == SVR_P5020 || ver == SVR_P5020E) { 113236324Sraj csr = ccsr_read4(OCP85XX_CPC_CSR0); 114236324Sraj if ((csr & OCP85XX_CPC_CSR0_CE) == 0) { 115236324Sraj l3cache_inval(); 116236324Sraj l3cache_enable(); 117236324Sraj } 118236324Sraj 119236324Sraj csr = ccsr_read4(OCP85XX_CPC_CSR0); 120236324Sraj if ((boothowto & RB_VERBOSE) != 0 || 121236324Sraj (csr & OCP85XX_CPC_CSR0_CE) == 0) { 122236324Sraj size = OCP85XX_CPC_CFG0_SZ_K(ccsr_read4(OCP85XX_CPC_CFG0)); 123236324Sraj printf("L3 Corenet Platform Cache: %d KB %sabled\n", 124236324Sraj size, (csr & OCP85XX_CPC_CSR0_CE) == 0 ? 125236324Sraj "dis" : "en"); 126236324Sraj } 127236324Sraj } 128236324Sraj} 129236324Sraj 130236324Srajvoid 131236324Srajbooke_disable_l2_cache(void) 132236324Sraj{ 133236324Sraj} 134236324Sraj 135236324Srajstatic void 136236324Srajl3cache_inval(void) 137236324Sraj{ 138236324Sraj 139236324Sraj /* Flash invalidate the CPC and clear all the locks */ 140236324Sraj ccsr_write4(OCP85XX_CPC_CSR0, OCP85XX_CPC_CSR0_FI | 141236324Sraj OCP85XX_CPC_CSR0_LFC); 142236324Sraj while (ccsr_read4(OCP85XX_CPC_CSR0) & (OCP85XX_CPC_CSR0_FI | 143236324Sraj OCP85XX_CPC_CSR0_LFC)) 144236324Sraj ; 145236324Sraj} 146236324Sraj 147236324Srajstatic void 148236324Srajl3cache_enable(void) 149236324Sraj{ 150236324Sraj 151236324Sraj ccsr_write4(OCP85XX_CPC_CSR0, OCP85XX_CPC_CSR0_CE | 152236324Sraj OCP85XX_CPC_CSR0_PE); 153236324Sraj /* Read back to sync write */ 154236324Sraj ccsr_read4(OCP85XX_CPC_CSR0); 155236324Sraj} 156236324Sraj#endif 157