mlx4_en.h revision 257867
1/* 2 * Copyright (c) 2007 Mellanox Technologies. All rights reserved. 3 * 4 * This software is available to you under a choice of one of two 5 * licenses. You may choose to be licensed under the terms of the GNU 6 * General Public License (GPL) Version 2, available from the file 7 * COPYING in the main directory of this source tree, or the 8 * OpenIB.org BSD license below: 9 * 10 * Redistribution and use in source and binary forms, with or 11 * without modification, are permitted provided that the following 12 * conditions are met: 13 * 14 * - Redistributions of source code must retain the above 15 * copyright notice, this list of conditions and the following 16 * disclaimer. 17 * 18 * - Redistributions in binary form must reproduce the above 19 * copyright notice, this list of conditions and the following 20 * disclaimer in the documentation and/or other materials 21 * provided with the distribution. 22 * 23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN 28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 30 * SOFTWARE. 31 * 32 */ 33 34#ifndef _MLX4_EN_H_ 35#define _MLX4_EN_H_ 36 37#include <sys/cdefs.h> 38 39#include <linux/types.h> 40#include <linux/compiler.h> 41#include <linux/list.h> 42#include <linux/mutex.h> 43#include <linux/netdevice.h> 44 45#include <linux/mlx4/device.h> 46#include <linux/mlx4/qp.h> 47#include <linux/mlx4/cq.h> 48#include <linux/mlx4/srq.h> 49#include <linux/mlx4/doorbell.h> 50#include <linux/mlx4/cmd.h> 51 52#include <net/if_media.h> 53#include <netinet/tcp_lro.h> 54 55#include "en_port.h" 56 57#define DRV_NAME "mlx4_en" 58#define DRV_VERSION "1.5.2" 59#define DRV_RELDATE "July 2010" 60 61/* XXX */ 62#define NETIF_MSG_LINK 0x1 63#define NETIF_MSG_IFDOWN 0x2 64#define NETIF_MSG_HW 0x4 65#define NETIF_MSG_DRV 0x8 66#define NETIF_MSG_INTR 0x10 67#define NETIF_MSG_RX_ERR 0x20 68 69#define MLX4_EN_MSG_LEVEL (NETIF_MSG_LINK | NETIF_MSG_IFDOWN) 70 71#define en_print(level, priv, format, arg...) \ 72 { \ 73 if ((priv)->registered) \ 74 printk(level "%s: %s: " format, DRV_NAME, \ 75 (priv->dev)->if_xname, ## arg); \ 76 else \ 77 printk(level "%s: %s: Port %d: " format, \ 78 DRV_NAME, dev_name(&priv->mdev->pdev->dev), \ 79 (priv)->port, ## arg); \ 80 } 81 82#define en_dbg(mlevel, priv, format, arg...) \ 83 if (NETIF_MSG_##mlevel & priv->msg_enable) \ 84 en_print(KERN_DEBUG, priv, format, ## arg) 85#define en_warn(priv, format, arg...) \ 86 en_print(KERN_WARNING, priv, format, ## arg) 87#define en_err(priv, format, arg...) \ 88 en_print(KERN_ERR, priv, format, ## arg) 89#define en_info(priv, format, arg...) \ 90 en_print(KERN_INFO, priv, format, ## arg) 91 92#define mlx4_err(mdev, format, arg...) \ 93 printk(KERN_ERR "%s %s: " format , DRV_NAME ,\ 94 dev_name(&mdev->pdev->dev) , ## arg) 95#define mlx4_info(mdev, format, arg...) \ 96 printk(KERN_INFO "%s %s: " format , DRV_NAME ,\ 97 dev_name(&mdev->pdev->dev) , ## arg) 98#define mlx4_warn(mdev, format, arg...) \ 99 printk(KERN_WARNING "%s %s: " format , DRV_NAME ,\ 100 dev_name(&mdev->pdev->dev) , ## arg) 101 102/* 103 * Device constants 104 */ 105 106 107#define MLX4_EN_PAGE_SHIFT 12 108#define MLX4_EN_PAGE_SIZE (1 << MLX4_EN_PAGE_SHIFT) 109#define MAX_TX_RINGS (MLX4_EN_NUM_HASH_RINGS + 1 + MLX4_EN_NUM_PPP_RINGS) 110#define MAX_RX_RINGS 16 111#define TXBB_SIZE 64 112#define HEADROOM (2048 / TXBB_SIZE + 1) 113#define STAMP_STRIDE 64 114#define STAMP_DWORDS (STAMP_STRIDE / 4) 115#define STAMP_SHIFT 31 116#define STAMP_VAL 0x7fffffff 117#define STATS_DELAY (HZ / 4) 118 119/* Typical TSO descriptor with 16 gather entries is 352 bytes... */ 120#define MAX_DESC_SIZE 512 121#define MAX_DESC_TXBBS (MAX_DESC_SIZE / TXBB_SIZE) 122 123/* 124 * OS related constants and tunables 125 */ 126 127#define MLX4_EN_WATCHDOG_TIMEOUT (15 * HZ) 128 129#define MLX4_EN_MAX_LRO_DESCRIPTORS 32 130#define MLX4_EN_NUM_IPFRAG_SESSIONS 16 131 132/* Receive fragment sizes; we use at most 3 fragments (for 9600 byte MTU 133 * and 4K allocations) */ 134#if MJUMPAGESIZE == 4096 135enum { 136 FRAG_SZ0 = MCLBYTES, 137 FRAG_SZ1 = MJUMPAGESIZE, 138 FRAG_SZ2 = MJUMPAGESIZE, 139}; 140#define MLX4_EN_MAX_RX_FRAGS 3 141#elif MJUMPAGESIZE == 8192 142enum { 143 FRAG_SZ0 = MCLBYTES, 144 FRAG_SZ1 = MJUMPAGESIZE, 145}; 146#define MLX4_EN_MAX_RX_FRAGS 2 147#elif MJUMPAGESIZE == 8192 148#else 149#error "Unknown PAGE_SIZE" 150#endif 151 152/* Maximum ring sizes */ 153#define MLX4_EN_MAX_TX_SIZE 8192 154#define MLX4_EN_MAX_RX_SIZE 8192 155 156#define MLX4_EN_MIN_RX_SIZE (128) 157#define MLX4_EN_MIN_TX_SIZE (4096 / TXBB_SIZE) 158 159#define MLX4_EN_SMALL_PKT_SIZE 64 160#define MLX4_EN_TX_HASH_SIZE 256 161#define MLX4_EN_TX_HASH_MASK (MLX4_EN_TX_HASH_SIZE - 1) 162#define MLX4_EN_NUM_HASH_RINGS 4 163#define MLX4_EN_NUM_PPP_RINGS 8 164#define MLX4_EN_DEF_TX_RING_SIZE 512 165#define MLX4_EN_DEF_TX_QUEUE_SIZE 4096 166#define MLX4_EN_DEF_RX_RING_SIZE 1024 167#define MLX4_EN_MAX_RX_POLL 1024 168 169/* Target number of bytes to coalesce with interrupt moderation */ 170#define MLX4_EN_RX_COAL_TARGET 0x20000 171#define MLX4_EN_RX_COAL_TIME 0x10 172 173#define MLX4_EN_TX_COAL_PKTS 5 174#define MLX4_EN_TX_COAL_TIME 0x80 175 176#define MLX4_EN_RX_RATE_LOW 400000 177#define MLX4_EN_RX_COAL_TIME_LOW 0 178#define MLX4_EN_RX_RATE_HIGH 450000 179#define MLX4_EN_RX_COAL_TIME_HIGH 128 180#define MLX4_EN_RX_SIZE_THRESH 1024 181#define MLX4_EN_RX_RATE_THRESH (1000000 / MLX4_EN_RX_COAL_TIME_HIGH) 182#define MLX4_EN_SAMPLE_INTERVAL 0 183#define MLX4_EN_AVG_PKT_SMALL 256 184 185#define MLX4_EN_AUTO_CONF 0xffff 186 187#define MLX4_EN_DEF_RX_PAUSE 1 188#define MLX4_EN_DEF_TX_PAUSE 1 189 190/* Interval between sucessive polls in the Tx routine when polling is used 191 instead of interrupts (in per-core Tx rings) - should be power of 2 */ 192#define MLX4_EN_TX_POLL_MODER 16 193#define MLX4_EN_TX_POLL_TIMEOUT (HZ / 4) 194 195#define ETH_LLC_SNAP_SIZE 8 196 197#define SMALL_PACKET_SIZE (MHLEN) 198#define HEADER_COPY_SIZE (128) 199#define MLX4_LOOPBACK_TEST_PAYLOAD (HEADER_COPY_SIZE - ETHER_HDR_LEN) 200 201#define MLX4_EN_MIN_MTU 46 202#define ETH_BCAST 0xffffffffffffULL 203 204#define MLX4_EN_LOOPBACK_RETRIES 5 205#define MLX4_EN_LOOPBACK_TIMEOUT 100 206 207#ifdef MLX4_EN_PERF_STAT 208/* Number of samples to 'average' */ 209#define AVG_SIZE 128 210#define AVG_FACTOR 1024 211#define NUM_PERF_STATS NUM_PERF_COUNTERS 212 213#define INC_PERF_COUNTER(cnt) (++(cnt)) 214#define ADD_PERF_COUNTER(cnt, add) ((cnt) += (add)) 215#define AVG_PERF_COUNTER(cnt, sample) \ 216 ((cnt) = ((cnt) * (AVG_SIZE - 1) + (sample) * AVG_FACTOR) / AVG_SIZE) 217#define GET_PERF_COUNTER(cnt) (cnt) 218#define GET_AVG_PERF_COUNTER(cnt) ((cnt) / AVG_FACTOR) 219 220#else 221 222#define NUM_PERF_STATS 0 223#define INC_PERF_COUNTER(cnt) do {} while (0) 224#define ADD_PERF_COUNTER(cnt, add) do {} while (0) 225#define AVG_PERF_COUNTER(cnt, sample) do {} while (0) 226#define GET_PERF_COUNTER(cnt) (0) 227#define GET_AVG_PERF_COUNTER(cnt) (0) 228#endif /* MLX4_EN_PERF_STAT */ 229 230/* 231 * Configurables 232 */ 233 234enum cq_type { 235 RX = 0, 236 TX = 1, 237}; 238 239 240/* 241 * Useful macros 242 */ 243#define ROUNDUP_LOG2(x) ilog2(roundup_pow_of_two(x)) 244#define XNOR(x, y) (!(x) == !(y)) 245#define ILLEGAL_MAC(addr) (addr == 0xffffffffffffULL || addr == 0x0) 246 247 248struct mlx4_en_tx_info { 249 struct mbuf *mb; 250 u32 nr_txbb; 251 u8 nr_segs; 252 u8 data_offset; 253 u8 inl; 254}; 255 256 257#define MLX4_EN_BIT_DESC_OWN 0x80000000 258#define CTRL_SIZE sizeof(struct mlx4_wqe_ctrl_seg) 259#define MLX4_EN_MEMTYPE_PAD 0x100 260#define DS_SIZE sizeof(struct mlx4_wqe_data_seg) 261 262 263struct mlx4_en_tx_desc { 264 struct mlx4_wqe_ctrl_seg ctrl; 265 union { 266 struct mlx4_wqe_data_seg data; /* at least one data segment */ 267 struct mlx4_wqe_lso_seg lso; 268 struct mlx4_wqe_inline_seg inl; 269 }; 270}; 271 272#define MLX4_EN_USE_SRQ 0x01000000 273 274struct mlx4_en_tx_ring { 275 spinlock_t tx_lock; 276 struct mlx4_hwq_resources wqres; 277 u32 size ; /* number of TXBBs */ 278 u32 size_mask; 279 u16 stride; 280 u16 cqn; /* index of port CQ associated with this ring */ 281 u32 prod; 282 u32 cons; 283 u32 buf_size; 284 u32 doorbell_qpn; 285 void *buf; 286 u16 poll_cnt; 287 int blocked; 288 struct buf_ring *br; 289 struct mlx4_en_tx_info *tx_info; 290 u8 *bounce_buf; 291 u32 last_nr_txbb; 292 struct mlx4_qp qp; 293 struct mlx4_qp_context context; 294 int qpn; 295 enum mlx4_qp_state qp_state; 296 struct mlx4_srq dummy; 297 unsigned long bytes; 298 unsigned long packets; 299 unsigned long errors; 300 spinlock_t comp_lock; 301 struct mlx4_bf bf; 302 bool bf_enabled; 303 u64 watchdog_time; 304}; 305 306struct mlx4_en_ipfrag { 307 struct mbuf *fragments; 308 struct mbuf *last; 309 __be32 saddr; 310 __be32 daddr; 311 __be16 id; 312 u8 protocol; 313 int total_len; 314 u16 offset; 315}; 316 317struct mlx4_en_rx_desc { 318 /* actual number of entries depends on rx ring stride */ 319 struct mlx4_wqe_data_seg data[0]; 320}; 321 322struct mlx4_en_rx_ring { 323 struct mlx4_hwq_resources wqres; 324 u32 size ; /* number of Rx descs*/ 325 u32 actual_size; 326 u32 size_mask; 327 u16 stride; 328 u16 log_stride; 329 u16 cqn; /* index of port CQ associated with this ring */ 330 u32 prod; 331 u32 cons; 332 u32 buf_size; 333 void *buf; 334 void *rx_info; 335 unsigned long bytes; 336 unsigned long packets; 337 unsigned long errors; 338 struct lro_ctrl lro; 339 struct mlx4_en_ipfrag ipfrag[MLX4_EN_NUM_IPFRAG_SESSIONS]; 340}; 341 342 343static inline int mlx4_en_can_lro(__be16 status) 344{ 345 return (status & cpu_to_be16(MLX4_CQE_STATUS_IPV4 | 346 MLX4_CQE_STATUS_IPV4F | 347 MLX4_CQE_STATUS_IPV6 | 348 MLX4_CQE_STATUS_IPV4OPT | 349 MLX4_CQE_STATUS_TCP | 350 MLX4_CQE_STATUS_UDP | 351 MLX4_CQE_STATUS_IPOK)) == 352 cpu_to_be16(MLX4_CQE_STATUS_IPV4 | 353 MLX4_CQE_STATUS_IPOK | 354 MLX4_CQE_STATUS_TCP); 355} 356 357struct mlx4_en_cq { 358 struct mlx4_cq mcq; 359 struct mlx4_hwq_resources wqres; 360 int ring; 361 spinlock_t lock; 362 struct net_device *dev; 363 /* Per-core Tx cq processing support */ 364 struct timer_list timer; 365 int size; 366 int buf_size; 367 unsigned vector; 368 enum cq_type is_tx; 369 u16 moder_time; 370 u16 moder_cnt; 371 struct mlx4_cqe *buf; 372 struct task cq_task; 373 struct taskqueue *tq; 374#define MLX4_EN_OPCODE_ERROR 0x1e 375 u32 tot_rx; 376}; 377 378struct mlx4_en_port_profile { 379 u32 flags; 380 u32 tx_ring_num; 381 u32 rx_ring_num; 382 u32 tx_ring_size; 383 u32 rx_ring_size; 384 u8 rx_pause; 385 u8 tx_pause; 386 u32 rx_ppp; 387 u32 tx_ppp; 388}; 389 390struct mlx4_en_profile { 391 int rss_xor; 392 int num_lro; 393 int ip_reasm; 394 int tcp_rss; 395 int udp_rss; 396 u8 rss_mask; 397 u32 active_ports; 398 u32 small_pkt_int; 399 u8 no_reset; 400 struct mlx4_en_port_profile prof[MLX4_MAX_PORTS + 1]; 401}; 402 403struct mlx4_en_dev { 404 struct mlx4_dev *dev; 405 struct pci_dev *pdev; 406 struct mutex state_lock; 407 struct net_device *pndev[MLX4_MAX_PORTS + 1]; 408 u32 port_cnt; 409 bool device_up; 410 struct mlx4_en_profile profile; 411 u32 LSO_support; 412 struct workqueue_struct *workqueue; 413 struct device *dma_device; 414 void __iomem *uar_map; 415 struct mlx4_uar priv_uar; 416 struct mlx4_mr mr; 417 u32 priv_pdn; 418 spinlock_t uar_lock; 419 u8 mac_removed[MLX4_MAX_PORTS + 1]; 420}; 421 422 423struct mlx4_en_rss_map { 424 int base_qpn; 425 struct mlx4_qp qps[MAX_RX_RINGS]; 426 enum mlx4_qp_state state[MAX_RX_RINGS]; 427 struct mlx4_qp indir_qp; 428 enum mlx4_qp_state indir_state; 429}; 430 431struct mlx4_en_rss_context { 432 __be32 base_qpn; 433 __be32 default_qpn; 434 u16 reserved; 435 u8 hash_fn; 436 u8 flags; 437 __be32 rss_key[10]; 438 __be32 base_qpn_udp; 439}; 440 441struct mlx4_en_port_state { 442 int link_state; 443 int link_speed; 444 int transciver; 445}; 446 447struct mlx4_en_pkt_stats { 448 unsigned long broadcast; 449 unsigned long rx_prio[8]; 450 unsigned long tx_prio[8]; 451#define NUM_PKT_STATS 17 452}; 453 454struct mlx4_en_port_stats { 455 unsigned long tso_packets; 456 unsigned long queue_stopped; 457 unsigned long wake_queue; 458 unsigned long tx_timeout; 459 unsigned long rx_alloc_failed; 460 unsigned long rx_chksum_good; 461 unsigned long rx_chksum_none; 462 unsigned long tx_chksum_offload; 463}; 464 465struct mlx4_en_perf_stats { 466 u32 tx_poll; 467 u64 tx_pktsz_avg; 468 u32 inflight_avg; 469 u32 tx_coal_avg; 470 u32 rx_coal_avg; 471}; 472 473struct mlx4_en_frag_info { 474 u16 frag_size; 475 u16 frag_prefix_size; 476}; 477 478struct mlx4_en_tx_hash_entry { 479 u8 cnt; 480 unsigned int small_pkts; 481 unsigned int big_pkts; 482 unsigned int ring; 483}; 484 485struct mlx4_en_priv { 486 struct mlx4_en_dev *mdev; 487 struct mlx4_en_port_profile *prof; 488 struct net_device *dev; 489 bool vlgrp_modified; 490 u32 vlan_register[VLAN_FLTR_SIZE]; 491 u32 vlan_unregister[VLAN_FLTR_SIZE]; 492 u32 vlans[VLAN_FLTR_SIZE]; 493 spinlock_t vlan_lock; 494 struct mlx4_en_port_state port_state; 495 spinlock_t stats_lock; 496 spinlock_t ioctl_lock; 497 498 unsigned long last_moder_packets[MAX_RX_RINGS]; 499 unsigned long last_moder_tx_packets; 500 unsigned long last_moder_bytes[MAX_RX_RINGS]; 501 unsigned long last_moder_jiffies; 502 int last_moder_time[MAX_RX_RINGS]; 503 u16 rx_usecs; 504 u16 rx_frames; 505 u16 tx_usecs; 506 u16 tx_frames; 507 u32 pkt_rate_low; 508 u16 rx_usecs_low; 509 u32 pkt_rate_high; 510 u16 rx_usecs_high; 511 u16 sample_interval; 512 u16 adaptive_rx_coal; 513 u32 msg_enable; 514 u32 loopback_ok; 515 u32 validate_loopback; 516 517 struct mlx4_hwq_resources res; 518 int link_state; 519 int last_link_state; 520 bool port_up; 521 int port; 522 int registered; 523 int allocated; 524 int rx_csum; 525 u64 mac; 526 int mac_index; 527 unsigned max_mtu; 528 int base_qpn; 529 530 struct mlx4_en_rss_map rss_map; 531 u16 tx_prio_map[8]; 532 u32 flags; 533#define MLX4_EN_FLAG_PROMISC 0x1 534 u32 tx_ring_num; 535 u32 rx_ring_num; 536 u32 rx_mb_size; 537 struct mlx4_en_frag_info frag_info[MLX4_EN_MAX_RX_FRAGS]; 538 u16 num_frags; 539 u16 log_rx_info; 540 int ip_reasm; 541 bool wol; 542 543 struct mlx4_en_tx_ring tx_ring[MAX_TX_RINGS]; 544 struct mlx4_en_rx_ring rx_ring[MAX_RX_RINGS]; 545 struct mlx4_en_cq tx_cq[MAX_TX_RINGS]; 546 struct mlx4_en_cq rx_cq[MAX_RX_RINGS]; 547 struct mlx4_en_tx_hash_entry tx_hash[MLX4_EN_TX_HASH_SIZE]; 548 struct work_struct mcast_task; 549 struct work_struct watchdog_task; 550 struct work_struct linkstate_task; 551 struct delayed_work stats_task; 552 struct mlx4_en_perf_stats pstats; 553 struct mlx4_en_pkt_stats pkstats; 554 struct mlx4_en_port_stats port_stats; 555 struct mlx4_en_stat_out_mbox hw_stats; 556 struct ifmedia media; 557 eventhandler_tag vlan_attach; 558 eventhandler_tag vlan_detach; 559 struct callout watchdog_timer; 560 volatile int blocked; 561 struct sysctl_oid *sysctl; 562 struct sysctl_ctx_list conf_ctx; 563 struct sysctl_ctx_list stat_ctx; 564}; 565 566enum mlx4_en_wol { 567 MLX4_EN_WOL_MAGIC = (1ULL << 61), 568 MLX4_EN_WOL_ENABLED = (1ULL << 62), 569 MLX4_EN_WOL_DO_MODIFY = (1ULL << 63), 570}; 571 572int mlx4_en_transmit(struct net_device *dev, struct mbuf *mb); 573void mlx4_en_qflush(struct net_device *dev); 574 575int mlx4_en_rx_frags(struct mlx4_en_priv *priv, struct mlx4_en_rx_ring *ring, 576 struct mbuf *mb, struct mlx4_cqe *cqe); 577void mlx4_en_flush_frags(struct mlx4_en_priv *priv, 578 struct mlx4_en_rx_ring *ring); 579void mlx4_en_destroy_netdev(struct net_device *dev); 580int mlx4_en_init_netdev(struct mlx4_en_dev *mdev, int port, 581 struct mlx4_en_port_profile *prof); 582 583int mlx4_en_start_port(struct net_device *dev); 584void mlx4_en_stop_port(struct net_device *dev); 585 586void mlx4_en_free_resources(struct mlx4_en_priv *priv); 587int mlx4_en_alloc_resources(struct mlx4_en_priv *priv); 588 589int mlx4_en_create_cq(struct mlx4_en_priv *priv, struct mlx4_en_cq *cq, 590 int entries, int ring, enum cq_type mode); 591void mlx4_en_destroy_cq(struct mlx4_en_priv *priv, struct mlx4_en_cq *cq); 592int mlx4_en_activate_cq(struct mlx4_en_priv *priv, struct mlx4_en_cq *cq); 593void mlx4_en_deactivate_cq(struct mlx4_en_priv *priv, struct mlx4_en_cq *cq); 594int mlx4_en_set_cq_moder(struct mlx4_en_priv *priv, struct mlx4_en_cq *cq); 595int mlx4_en_arm_cq(struct mlx4_en_priv *priv, struct mlx4_en_cq *cq); 596 597void mlx4_en_poll_tx_cq(unsigned long data); 598void mlx4_en_tx_irq(struct mlx4_cq *mcq); 599u16 mlx4_en_select_queue(struct net_device *dev, struct mbuf *mb); 600 601int mlx4_en_create_tx_ring(struct mlx4_en_priv *priv, struct mlx4_en_tx_ring *ring, 602 u32 size, u16 stride); 603void mlx4_en_destroy_tx_ring(struct mlx4_en_priv *priv, struct mlx4_en_tx_ring *ring); 604int mlx4_en_activate_tx_ring(struct mlx4_en_priv *priv, 605 struct mlx4_en_tx_ring *ring, 606 int cq); 607void mlx4_en_deactivate_tx_ring(struct mlx4_en_priv *priv, 608 struct mlx4_en_tx_ring *ring); 609 610int mlx4_en_create_rx_ring(struct mlx4_en_priv *priv, 611 struct mlx4_en_rx_ring *ring, u32 size); 612void mlx4_en_destroy_rx_ring(struct mlx4_en_priv *priv, 613 struct mlx4_en_rx_ring *ring); 614int mlx4_en_activate_rx_rings(struct mlx4_en_priv *priv); 615void mlx4_en_deactivate_rx_ring(struct mlx4_en_priv *priv, 616 struct mlx4_en_rx_ring *ring); 617int mlx4_en_process_rx_cq(struct net_device *dev, 618 struct mlx4_en_cq *cq, 619 int budget); 620int mlx4_en_process_rx_cq_mb(struct net_device *dev, 621 struct mlx4_en_cq *cq, 622 int budget); 623void mlx4_en_tx_que(void *context, int pending); 624void mlx4_en_rx_que(void *context, int pending); 625void mlx4_en_fill_qp_context(struct mlx4_en_priv *priv, int size, int stride, 626 int is_tx, int rss, int qpn, int cqn, 627 struct mlx4_qp_context *context); 628void mlx4_en_sqp_event(struct mlx4_qp *qp, enum mlx4_event event); 629int mlx4_en_map_buffer(struct mlx4_buf *buf); 630void mlx4_en_unmap_buffer(struct mlx4_buf *buf); 631 632void mlx4_en_calc_rx_buf(struct net_device *dev); 633void mlx4_en_set_prio_map(struct mlx4_en_priv *priv, u16 *prio_map, u32 ring_num); 634int mlx4_en_config_rss_steer(struct mlx4_en_priv *priv); 635void mlx4_en_release_rss_steer(struct mlx4_en_priv *priv); 636int mlx4_en_free_tx_buf(struct net_device *dev, struct mlx4_en_tx_ring *ring); 637void mlx4_en_rx_irq(struct mlx4_cq *mcq); 638 639//int mlx4_SET_MCAST_FLTR(struct mlx4_dev *dev, u8 port, u64 mac, u64 clear, u8 mode); 640int mlx4_SET_VLAN_FLTR(struct mlx4_dev *dev, u8 port, u32 *vlans); 641//int mlx4_SET_PORT_general(struct mlx4_dev *dev, u8 port, int mtu, 642// u8 pptx, u8 pfctx, u8 pprx, u8 pfcrx); 643//int mlx4_SET_PORT_qpn_calc(struct mlx4_dev *dev, u8 port, u32 base_qpn, 644// u8 promisc); 645 646int mlx4_en_DUMP_ETH_STATS(struct mlx4_en_dev *mdev, u8 port, u8 reset); 647int mlx4_en_QUERY_PORT(struct mlx4_en_dev *mdev, u8 port); 648 649#define MLX4_EN_NUM_SELF_TEST 5 650void mlx4_en_ex_selftest(struct net_device *dev, u32 *flags, u64 *buf); 651u64 mlx4_en_mac_to_u64(u8 *addr); 652 653/* 654 * Globals 655 */ 656extern const struct ethtool_ops mlx4_en_ethtool_ops; 657#endif 658