cq.c revision 271127
1/* 2 * Copyright (c) 2004, 2005 Topspin Communications. All rights reserved. 3 * Copyright (c) 2005 Sun Microsystems, Inc. All rights reserved. 4 * Copyright (c) 2005, 2006, 2007 Cisco Systems, Inc. All rights reserved. 5 * Copyright (c) 2005, 2006, 2007, 2008 Mellanox Technologies. All rights reserved. 6 * Copyright (c) 2004 Voltaire, Inc. All rights reserved. 7 * 8 * This software is available to you under a choice of one of two 9 * licenses. You may choose to be licensed under the terms of the GNU 10 * General Public License (GPL) Version 2, available from the file 11 * COPYING in the main directory of this source tree, or the 12 * OpenIB.org BSD license below: 13 * 14 * Redistribution and use in source and binary forms, with or 15 * without modification, are permitted provided that the following 16 * conditions are met: 17 * 18 * - Redistributions of source code must retain the above 19 * copyright notice, this list of conditions and the following 20 * disclaimer. 21 * 22 * - Redistributions in binary form must reproduce the above 23 * copyright notice, this list of conditions and the following 24 * disclaimer in the documentation and/or other materials 25 * provided with the distribution. 26 * 27 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 28 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 29 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 30 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 31 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN 32 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 33 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 34 * SOFTWARE. 35 */ 36 37#include <linux/hardirq.h> 38 39#include <linux/mlx4/cmd.h> 40#include <linux/mlx4/cq.h> 41 42#include "mlx4.h" 43#include "icm.h" 44 45#define MLX4_CQ_STATUS_OK ( 0 << 28) 46#define MLX4_CQ_STATUS_OVERFLOW ( 9 << 28) 47#define MLX4_CQ_STATUS_WRITE_FAIL (10 << 28) 48#define MLX4_CQ_FLAG_CC ( 1 << 18) 49#define MLX4_CQ_FLAG_OI ( 1 << 17) 50#define MLX4_CQ_STATE_ARMED ( 9 << 8) 51#define MLX4_CQ_STATE_ARMED_SOL ( 6 << 8) 52#define MLX4_EQ_STATE_FIRED (10 << 8) 53 54void mlx4_cq_completion(struct mlx4_dev *dev, u32 cqn) 55{ 56 struct mlx4_cq_table *cq_table = &mlx4_priv(dev)->cq_table; 57 struct mlx4_cq *cq; 58 59 spin_lock(&cq_table->lock); 60 cq = radix_tree_lookup(&mlx4_priv(dev)->cq_table.tree, 61 cqn & (dev->caps.num_cqs - 1)); 62 if (cq) 63 atomic_inc(&cq->refcount); 64 spin_unlock(&cq_table->lock); 65 66 if (!cq) { 67 mlx4_dbg(dev, "Completion event for bogus CQ %08x\n", cqn); 68 return; 69 } 70 71 ++cq->arm_sn; 72 73 cq->comp(cq); 74 75 if (atomic_dec_and_test(&cq->refcount)) 76 complete(&cq->free); 77} 78 79void mlx4_cq_event(struct mlx4_dev *dev, u32 cqn, int event_type) 80{ 81 struct mlx4_cq_table *cq_table = &mlx4_priv(dev)->cq_table; 82 struct mlx4_cq *cq; 83 84 spin_lock(&cq_table->lock); 85 86 cq = radix_tree_lookup(&cq_table->tree, cqn & (dev->caps.num_cqs - 1)); 87 if (cq) 88 atomic_inc(&cq->refcount); 89 90 spin_unlock(&cq_table->lock); 91 92 if (!cq) { 93 mlx4_warn(dev, "Async event for bogus CQ %08x\n", cqn); 94 return; 95 } 96 97 cq->event(cq, event_type); 98 99 if (atomic_dec_and_test(&cq->refcount)) 100 complete(&cq->free); 101} 102 103static int mlx4_SW2HW_CQ(struct mlx4_dev *dev, struct mlx4_cmd_mailbox *mailbox, 104 int cq_num) 105{ 106 return mlx4_cmd(dev, mailbox->dma, cq_num, 0, 107 MLX4_CMD_SW2HW_CQ, MLX4_CMD_TIME_CLASS_A, 108 MLX4_CMD_WRAPPED); 109} 110 111static int mlx4_MODIFY_CQ(struct mlx4_dev *dev, struct mlx4_cmd_mailbox *mailbox, 112 int cq_num, u32 opmod) 113{ 114 return mlx4_cmd(dev, mailbox->dma, cq_num, opmod, MLX4_CMD_MODIFY_CQ, 115 MLX4_CMD_TIME_CLASS_A, MLX4_CMD_WRAPPED); 116} 117 118static int mlx4_HW2SW_CQ(struct mlx4_dev *dev, struct mlx4_cmd_mailbox *mailbox, 119 int cq_num) 120{ 121 return mlx4_cmd_box(dev, 0, mailbox ? mailbox->dma : 0, 122 cq_num, mailbox ? 0 : 1, MLX4_CMD_HW2SW_CQ, 123 MLX4_CMD_TIME_CLASS_A, MLX4_CMD_WRAPPED); 124} 125 126int mlx4_cq_modify(struct mlx4_dev *dev, struct mlx4_cq *cq, 127 u16 count, u16 period) 128{ 129 struct mlx4_cmd_mailbox *mailbox; 130 struct mlx4_cq_context *cq_context; 131 int err; 132 133 mailbox = mlx4_alloc_cmd_mailbox(dev); 134 if (IS_ERR(mailbox)) 135 return PTR_ERR(mailbox); 136 137 cq_context = mailbox->buf; 138 memset(cq_context, 0, sizeof *cq_context); 139 140 cq_context->cq_max_count = cpu_to_be16(count); 141 cq_context->cq_period = cpu_to_be16(period); 142 143 err = mlx4_MODIFY_CQ(dev, mailbox, cq->cqn, 1); 144 145 mlx4_free_cmd_mailbox(dev, mailbox); 146 return err; 147} 148EXPORT_SYMBOL_GPL(mlx4_cq_modify); 149 150int mlx4_cq_resize(struct mlx4_dev *dev, struct mlx4_cq *cq, 151 int entries, struct mlx4_mtt *mtt) 152{ 153 struct mlx4_cmd_mailbox *mailbox; 154 struct mlx4_cq_context *cq_context; 155 u64 mtt_addr; 156 int err; 157 158 mailbox = mlx4_alloc_cmd_mailbox(dev); 159 if (IS_ERR(mailbox)) 160 return PTR_ERR(mailbox); 161 162 cq_context = mailbox->buf; 163 memset(cq_context, 0, sizeof *cq_context); 164 165 cq_context->logsize_usrpage = cpu_to_be32(ilog2(entries) << 24); 166 cq_context->log_page_size = mtt->page_shift - 12; 167 mtt_addr = mlx4_mtt_addr(dev, mtt); 168 cq_context->mtt_base_addr_h = mtt_addr >> 32; 169 cq_context->mtt_base_addr_l = cpu_to_be32(mtt_addr & 0xffffffff); 170 171 err = mlx4_MODIFY_CQ(dev, mailbox, cq->cqn, 0); 172 173 mlx4_free_cmd_mailbox(dev, mailbox); 174 return err; 175} 176EXPORT_SYMBOL_GPL(mlx4_cq_resize); 177 178int mlx4_cq_ignore_overrun(struct mlx4_dev *dev, struct mlx4_cq *cq) 179{ 180 struct mlx4_cmd_mailbox *mailbox; 181 struct mlx4_cq_context *cq_context; 182 int err; 183 184 mailbox = mlx4_alloc_cmd_mailbox(dev); 185 if (IS_ERR(mailbox)) 186 return PTR_ERR(mailbox); 187 188 cq_context = mailbox->buf; 189 memset(cq_context, 0, sizeof *cq_context); 190 191 cq_context->flags |= cpu_to_be32(MLX4_CQ_FLAG_OI); 192 193 err = mlx4_MODIFY_CQ(dev, mailbox, cq->cqn, 3); 194 195 mlx4_free_cmd_mailbox(dev, mailbox); 196 return err; 197} 198EXPORT_SYMBOL_GPL(mlx4_cq_ignore_overrun); 199 200int __mlx4_cq_alloc_icm(struct mlx4_dev *dev, int *cqn) 201{ 202 struct mlx4_priv *priv = mlx4_priv(dev); 203 struct mlx4_cq_table *cq_table = &priv->cq_table; 204 int err; 205 206 *cqn = mlx4_bitmap_alloc(&cq_table->bitmap); 207 if (*cqn == -1) 208 return -ENOMEM; 209 210 err = mlx4_table_get(dev, &cq_table->table, *cqn); 211 if (err) 212 goto err_out; 213 214 err = mlx4_table_get(dev, &cq_table->cmpt_table, *cqn); 215 if (err) 216 goto err_put; 217 return 0; 218 219err_put: 220 mlx4_table_put(dev, &cq_table->table, *cqn); 221 222err_out: 223 mlx4_bitmap_free(&cq_table->bitmap, *cqn); 224 return err; 225} 226 227static int mlx4_cq_alloc_icm(struct mlx4_dev *dev, int *cqn) 228{ 229 u64 out_param; 230 int err; 231 232 if (mlx4_is_mfunc(dev)) { 233 err = mlx4_cmd_imm(dev, 0, &out_param, RES_CQ, 234 RES_OP_RESERVE_AND_MAP, MLX4_CMD_ALLOC_RES, 235 MLX4_CMD_TIME_CLASS_A, MLX4_CMD_WRAPPED); 236 if (err) 237 return err; 238 else { 239 *cqn = get_param_l(&out_param); 240 return 0; 241 } 242 } 243 return __mlx4_cq_alloc_icm(dev, cqn); 244} 245 246void __mlx4_cq_free_icm(struct mlx4_dev *dev, int cqn) 247{ 248 struct mlx4_priv *priv = mlx4_priv(dev); 249 struct mlx4_cq_table *cq_table = &priv->cq_table; 250 251 mlx4_table_put(dev, &cq_table->cmpt_table, cqn); 252 mlx4_table_put(dev, &cq_table->table, cqn); 253 mlx4_bitmap_free(&cq_table->bitmap, cqn); 254} 255 256static void mlx4_cq_free_icm(struct mlx4_dev *dev, int cqn) 257{ 258 u64 in_param = 0; 259 int err; 260 261 if (mlx4_is_mfunc(dev)) { 262 set_param_l(&in_param, cqn); 263 err = mlx4_cmd(dev, in_param, RES_CQ, RES_OP_RESERVE_AND_MAP, 264 MLX4_CMD_FREE_RES, 265 MLX4_CMD_TIME_CLASS_A, MLX4_CMD_WRAPPED); 266 if (err) 267 mlx4_warn(dev, "Failed freeing cq:%d\n", cqn); 268 } else 269 __mlx4_cq_free_icm(dev, cqn); 270} 271 272static int mlx4_find_least_loaded_vector(struct mlx4_priv *priv) 273{ 274 int i; 275 int index = 0; 276 int min = priv->eq_table.eq[0].load; 277 278 for (i = 1; i < priv->dev.caps.num_comp_vectors; i++) { 279 if (priv->eq_table.eq[i].load < min) { 280 index = i; 281 min = priv->eq_table.eq[i].load; 282 } 283 } 284 285 return index; 286} 287 288 289int mlx4_cq_alloc(struct mlx4_dev *dev, int nent, 290 struct mlx4_mtt *mtt, struct mlx4_uar *uar, u64 db_rec, 291 struct mlx4_cq *cq, unsigned vector, int collapsed, 292 int timestamp_en) 293{ 294 struct mlx4_priv *priv = mlx4_priv(dev); 295 struct mlx4_cq_table *cq_table = &priv->cq_table; 296 struct mlx4_cmd_mailbox *mailbox; 297 struct mlx4_cq_context *cq_context; 298 u64 mtt_addr; 299 int err; 300 301 cq->vector = (vector == MLX4_LEAST_ATTACHED_VECTOR) ? 302 mlx4_find_least_loaded_vector(priv) : vector; 303 304 if (cq->vector > dev->caps.num_comp_vectors + dev->caps.comp_pool) { 305 return -EINVAL; 306 } 307 308 err = mlx4_cq_alloc_icm(dev, &cq->cqn); 309 if (err) { 310 return err; 311 } 312 313 spin_lock_irq(&cq_table->lock); 314 err = radix_tree_insert(&cq_table->tree, cq->cqn, cq); 315 spin_unlock_irq(&cq_table->lock); 316 if (err){ 317 goto err_icm; 318 } 319 320 mailbox = mlx4_alloc_cmd_mailbox(dev); 321 if (IS_ERR(mailbox)) { 322 err = PTR_ERR(mailbox); 323 goto err_radix; 324 } 325 326 cq_context = mailbox->buf; 327 memset(cq_context, 0, sizeof *cq_context); 328 329 cq_context->flags = cpu_to_be32(!!collapsed << 18); 330 if (timestamp_en) 331 cq_context->flags |= cpu_to_be32(1 << 19); 332 333 cq_context->logsize_usrpage = cpu_to_be32((ilog2(nent) << 24) | uar->index); 334 cq_context->comp_eqn = priv->eq_table.eq[cq->vector].eqn; 335 cq_context->log_page_size = mtt->page_shift - MLX4_ICM_PAGE_SHIFT; 336 337 mtt_addr = mlx4_mtt_addr(dev, mtt); 338 cq_context->mtt_base_addr_h = mtt_addr >> 32; 339 cq_context->mtt_base_addr_l = cpu_to_be32(mtt_addr & 0xffffffff); 340 cq_context->db_rec_addr = cpu_to_be64(db_rec); 341 342 err = mlx4_SW2HW_CQ(dev, mailbox, cq->cqn); 343 mlx4_free_cmd_mailbox(dev, mailbox); 344 if (err) 345 goto err_radix; 346 347 priv->eq_table.eq[cq->vector].load++; 348 cq->cons_index = 0; 349 cq->arm_sn = 1; 350 cq->uar = uar; 351 atomic_set(&cq->refcount, 1); 352 init_completion(&cq->free); 353 354 cq->eqn = priv->eq_table.eq[cq->vector].eqn; 355 cq->irq = priv->eq_table.eq[cq->vector].irq; 356 357 return 0; 358 359err_radix: 360 spin_lock_irq(&cq_table->lock); 361 radix_tree_delete(&cq_table->tree, cq->cqn); 362 spin_unlock_irq(&cq_table->lock); 363 364err_icm: 365 mlx4_cq_free_icm(dev, cq->cqn); 366 367 return err; 368} 369EXPORT_SYMBOL_GPL(mlx4_cq_alloc); 370 371void mlx4_cq_free(struct mlx4_dev *dev, struct mlx4_cq *cq) 372{ 373 struct mlx4_priv *priv = mlx4_priv(dev); 374 struct mlx4_cq_table *cq_table = &priv->cq_table; 375 int err; 376 377 err = mlx4_HW2SW_CQ(dev, NULL, cq->cqn); 378 if (err) 379 mlx4_warn(dev, "HW2SW_CQ failed (%d) for CQN %06x\n", err, cq->cqn); 380 381 382 priv->eq_table.eq[cq->vector].load--; 383 synchronize_irq(priv->eq_table.eq[cq->vector].irq); 384 385 spin_lock_irq(&cq_table->lock); 386 radix_tree_delete(&cq_table->tree, cq->cqn); 387 spin_unlock_irq(&cq_table->lock); 388 389 if (atomic_dec_and_test(&cq->refcount)) 390 complete(&cq->free); 391 wait_for_completion(&cq->free); 392 393 mlx4_cq_free_icm(dev, cq->cqn); 394} 395EXPORT_SYMBOL_GPL(mlx4_cq_free); 396 397int mlx4_init_cq_table(struct mlx4_dev *dev) 398{ 399 struct mlx4_cq_table *cq_table = &mlx4_priv(dev)->cq_table; 400 int err; 401 402 spin_lock_init(&cq_table->lock); 403 INIT_RADIX_TREE(&cq_table->tree, GFP_ATOMIC); 404 if (mlx4_is_slave(dev)) 405 return 0; 406 407 err = mlx4_bitmap_init(&cq_table->bitmap, dev->caps.num_cqs, 408 dev->caps.num_cqs - 1, dev->caps.reserved_cqs, 0); 409 if (err) 410 return err; 411 412 return 0; 413} 414 415void mlx4_cleanup_cq_table(struct mlx4_dev *dev) 416{ 417 if (mlx4_is_slave(dev)) 418 return; 419 /* Nothing to do to clean up radix_tree */ 420 mlx4_bitmap_cleanup(&mlx4_priv(dev)->cq_table.bitmap); 421} 422