1219820Sjeff/* 2219820Sjeff * Copyright (c) 2004, 2005 Topspin Communications. All rights reserved. 3219820Sjeff * Copyright (c) 2005 Mellanox Technologies. All rights reserved. 4219820Sjeff * Copyright (c) 2005, 2006 Cisco Systems. All rights reserved. 5219820Sjeff * 6219820Sjeff * This software is available to you under a choice of one of two 7219820Sjeff * licenses. You may choose to be licensed under the terms of the GNU 8219820Sjeff * General Public License (GPL) Version 2, available from the file 9219820Sjeff * COPYING in the main directory of this source tree, or the 10219820Sjeff * OpenIB.org BSD license below: 11219820Sjeff * 12219820Sjeff * Redistribution and use in source and binary forms, with or 13219820Sjeff * without modification, are permitted provided that the following 14219820Sjeff * conditions are met: 15219820Sjeff * 16219820Sjeff * - Redistributions of source code must retain the above 17219820Sjeff * copyright notice, this list of conditions and the following 18219820Sjeff * disclaimer. 19219820Sjeff * 20219820Sjeff * - Redistributions in binary form must reproduce the above 21219820Sjeff * copyright notice, this list of conditions and the following 22219820Sjeff * disclaimer in the documentation and/or other materials 23219820Sjeff * provided with the distribution. 24219820Sjeff * 25219820Sjeff * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 26219820Sjeff * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 27219820Sjeff * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 28219820Sjeff * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 29219820Sjeff * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN 30219820Sjeff * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 31219820Sjeff * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 32219820Sjeff * SOFTWARE. 33219820Sjeff */ 34219820Sjeff 35324685Shselasky#define LINUXKPI_PARAM_PREFIX mthca_ 36324685Shselasky 37219820Sjeff#include <linux/completion.h> 38219820Sjeff#include <linux/pci.h> 39219820Sjeff#include <linux/errno.h> 40219820Sjeff#include <linux/sched.h> 41219820Sjeff#include <asm/io.h> 42219820Sjeff#include <rdma/ib_mad.h> 43219820Sjeff 44219820Sjeff#include "mthca_dev.h" 45219820Sjeff#include "mthca_config_reg.h" 46219820Sjeff#include "mthca_cmd.h" 47219820Sjeff#include "mthca_memfree.h" 48219820Sjeff 49219820Sjeff#define CMD_POLL_TOKEN 0xffff 50219820Sjeff 51219820Sjeffenum { 52219820Sjeff HCR_IN_PARAM_OFFSET = 0x00, 53219820Sjeff HCR_IN_MODIFIER_OFFSET = 0x08, 54219820Sjeff HCR_OUT_PARAM_OFFSET = 0x0c, 55219820Sjeff HCR_TOKEN_OFFSET = 0x14, 56219820Sjeff HCR_STATUS_OFFSET = 0x18, 57219820Sjeff 58219820Sjeff HCR_OPMOD_SHIFT = 12, 59219820Sjeff HCA_E_BIT = 22, 60219820Sjeff HCR_GO_BIT = 23 61219820Sjeff}; 62219820Sjeff 63219820Sjeffenum { 64219820Sjeff /* initialization and general commands */ 65219820Sjeff CMD_SYS_EN = 0x1, 66219820Sjeff CMD_SYS_DIS = 0x2, 67219820Sjeff CMD_MAP_FA = 0xfff, 68219820Sjeff CMD_UNMAP_FA = 0xffe, 69219820Sjeff CMD_RUN_FW = 0xff6, 70219820Sjeff CMD_MOD_STAT_CFG = 0x34, 71219820Sjeff CMD_QUERY_DEV_LIM = 0x3, 72219820Sjeff CMD_QUERY_FW = 0x4, 73219820Sjeff CMD_ENABLE_LAM = 0xff8, 74219820Sjeff CMD_DISABLE_LAM = 0xff7, 75219820Sjeff CMD_QUERY_DDR = 0x5, 76219820Sjeff CMD_QUERY_ADAPTER = 0x6, 77219820Sjeff CMD_INIT_HCA = 0x7, 78219820Sjeff CMD_CLOSE_HCA = 0x8, 79219820Sjeff CMD_INIT_IB = 0x9, 80219820Sjeff CMD_CLOSE_IB = 0xa, 81219820Sjeff CMD_QUERY_HCA = 0xb, 82219820Sjeff CMD_SET_IB = 0xc, 83219820Sjeff CMD_ACCESS_DDR = 0x2e, 84219820Sjeff CMD_MAP_ICM = 0xffa, 85219820Sjeff CMD_UNMAP_ICM = 0xff9, 86219820Sjeff CMD_MAP_ICM_AUX = 0xffc, 87219820Sjeff CMD_UNMAP_ICM_AUX = 0xffb, 88219820Sjeff CMD_SET_ICM_SIZE = 0xffd, 89219820Sjeff 90219820Sjeff /* TPT commands */ 91219820Sjeff CMD_SW2HW_MPT = 0xd, 92219820Sjeff CMD_QUERY_MPT = 0xe, 93219820Sjeff CMD_HW2SW_MPT = 0xf, 94219820Sjeff CMD_READ_MTT = 0x10, 95219820Sjeff CMD_WRITE_MTT = 0x11, 96219820Sjeff CMD_SYNC_TPT = 0x2f, 97219820Sjeff 98219820Sjeff /* EQ commands */ 99219820Sjeff CMD_MAP_EQ = 0x12, 100219820Sjeff CMD_SW2HW_EQ = 0x13, 101219820Sjeff CMD_HW2SW_EQ = 0x14, 102219820Sjeff CMD_QUERY_EQ = 0x15, 103219820Sjeff 104219820Sjeff /* CQ commands */ 105219820Sjeff CMD_SW2HW_CQ = 0x16, 106219820Sjeff CMD_HW2SW_CQ = 0x17, 107219820Sjeff CMD_QUERY_CQ = 0x18, 108219820Sjeff CMD_RESIZE_CQ = 0x2c, 109219820Sjeff 110219820Sjeff /* SRQ commands */ 111219820Sjeff CMD_SW2HW_SRQ = 0x35, 112219820Sjeff CMD_HW2SW_SRQ = 0x36, 113219820Sjeff CMD_QUERY_SRQ = 0x37, 114219820Sjeff CMD_ARM_SRQ = 0x40, 115219820Sjeff 116219820Sjeff /* QP/EE commands */ 117219820Sjeff CMD_RST2INIT_QPEE = 0x19, 118219820Sjeff CMD_INIT2RTR_QPEE = 0x1a, 119219820Sjeff CMD_RTR2RTS_QPEE = 0x1b, 120219820Sjeff CMD_RTS2RTS_QPEE = 0x1c, 121219820Sjeff CMD_SQERR2RTS_QPEE = 0x1d, 122219820Sjeff CMD_2ERR_QPEE = 0x1e, 123219820Sjeff CMD_RTS2SQD_QPEE = 0x1f, 124219820Sjeff CMD_SQD2SQD_QPEE = 0x38, 125219820Sjeff CMD_SQD2RTS_QPEE = 0x20, 126219820Sjeff CMD_ERR2RST_QPEE = 0x21, 127219820Sjeff CMD_QUERY_QPEE = 0x22, 128219820Sjeff CMD_INIT2INIT_QPEE = 0x2d, 129219820Sjeff CMD_SUSPEND_QPEE = 0x32, 130219820Sjeff CMD_UNSUSPEND_QPEE = 0x33, 131219820Sjeff /* special QPs and management commands */ 132219820Sjeff CMD_CONF_SPECIAL_QP = 0x23, 133219820Sjeff CMD_MAD_IFC = 0x24, 134219820Sjeff 135219820Sjeff /* multicast commands */ 136219820Sjeff CMD_READ_MGM = 0x25, 137219820Sjeff CMD_WRITE_MGM = 0x26, 138219820Sjeff CMD_MGID_HASH = 0x27, 139219820Sjeff 140219820Sjeff /* miscellaneous commands */ 141219820Sjeff CMD_DIAG_RPRT = 0x30, 142219820Sjeff CMD_NOP = 0x31, 143219820Sjeff 144219820Sjeff /* debug commands */ 145219820Sjeff CMD_QUERY_DEBUG_MSG = 0x2a, 146219820Sjeff CMD_SET_DEBUG_MSG = 0x2b, 147219820Sjeff}; 148219820Sjeff 149219820Sjeff/* 150219820Sjeff * According to Mellanox code, FW may be starved and never complete 151219820Sjeff * commands. So we can't use strict timeouts described in PRM -- we 152219820Sjeff * just arbitrarily select 60 seconds for now. 153219820Sjeff */ 154219820Sjeff#if 0 155219820Sjeff/* 156219820Sjeff * Round up and add 1 to make sure we get the full wait time (since we 157219820Sjeff * will be starting in the middle of a jiffy) 158219820Sjeff */ 159219820Sjeffenum { 160219820Sjeff CMD_TIME_CLASS_A = (HZ + 999) / 1000 + 1, 161219820Sjeff CMD_TIME_CLASS_B = (HZ + 99) / 100 + 1, 162219820Sjeff CMD_TIME_CLASS_C = (HZ + 9) / 10 + 1, 163219820Sjeff CMD_TIME_CLASS_D = 60 * HZ 164219820Sjeff}; 165219820Sjeff#else 166219820Sjeff#define CMD_TIME_CLASS_A (60 * HZ) 167219820Sjeff#define CMD_TIME_CLASS_B (60 * HZ) 168219820Sjeff#define CMD_TIME_CLASS_C (60 * HZ) 169219820Sjeff#define CMD_TIME_CLASS_D (60 * HZ) 170219820Sjeff#endif 171219820Sjeff 172219820Sjeff#define GO_BIT_TIMEOUT (HZ * 10) 173219820Sjeff 174219820Sjeffstruct mthca_cmd_context { 175219820Sjeff struct completion done; 176219820Sjeff int result; 177219820Sjeff int next; 178219820Sjeff u64 out_param; 179219820Sjeff u16 token; 180219820Sjeff u8 status; 181219820Sjeff}; 182219820Sjeff 183219820Sjeffstatic int fw_cmd_doorbell = 0; 184219820Sjeffmodule_param(fw_cmd_doorbell, int, 0644); 185219820SjeffMODULE_PARM_DESC(fw_cmd_doorbell, "post FW commands through doorbell page if nonzero " 186219820Sjeff "(and supported by FW)"); 187219820Sjeff 188219820Sjeffstatic inline int go_bit(struct mthca_dev *dev) 189219820Sjeff{ 190219820Sjeff return readl(dev->hcr + HCR_STATUS_OFFSET) & 191219820Sjeff swab32(1 << HCR_GO_BIT); 192219820Sjeff} 193219820Sjeff 194219820Sjeffstatic void mthca_cmd_post_dbell(struct mthca_dev *dev, 195219820Sjeff u64 in_param, 196219820Sjeff u64 out_param, 197219820Sjeff u32 in_modifier, 198219820Sjeff u8 op_modifier, 199219820Sjeff u16 op, 200219820Sjeff u16 token) 201219820Sjeff{ 202219820Sjeff void __iomem *ptr = dev->cmd.dbell_map; 203219820Sjeff u16 *offs = dev->cmd.dbell_offsets; 204219820Sjeff 205219820Sjeff __raw_writel((__force u32) cpu_to_be32(in_param >> 32), ptr + offs[0]); 206219820Sjeff wmb(); 207219820Sjeff __raw_writel((__force u32) cpu_to_be32(in_param & 0xfffffffful), ptr + offs[1]); 208219820Sjeff wmb(); 209219820Sjeff __raw_writel((__force u32) cpu_to_be32(in_modifier), ptr + offs[2]); 210219820Sjeff wmb(); 211219820Sjeff __raw_writel((__force u32) cpu_to_be32(out_param >> 32), ptr + offs[3]); 212219820Sjeff wmb(); 213219820Sjeff __raw_writel((__force u32) cpu_to_be32(out_param & 0xfffffffful), ptr + offs[4]); 214219820Sjeff wmb(); 215219820Sjeff __raw_writel((__force u32) cpu_to_be32(token << 16), ptr + offs[5]); 216219820Sjeff wmb(); 217219820Sjeff __raw_writel((__force u32) cpu_to_be32((1 << HCR_GO_BIT) | 218219820Sjeff (1 << HCA_E_BIT) | 219219820Sjeff (op_modifier << HCR_OPMOD_SHIFT) | 220219820Sjeff op), ptr + offs[6]); 221219820Sjeff wmb(); 222219820Sjeff __raw_writel((__force u32) 0, ptr + offs[7]); 223219820Sjeff wmb(); 224219820Sjeff} 225219820Sjeff 226219820Sjeffstatic int mthca_cmd_post_hcr(struct mthca_dev *dev, 227219820Sjeff u64 in_param, 228219820Sjeff u64 out_param, 229219820Sjeff u32 in_modifier, 230219820Sjeff u8 op_modifier, 231219820Sjeff u16 op, 232219820Sjeff u16 token, 233219820Sjeff int event) 234219820Sjeff{ 235219820Sjeff if (event) { 236219820Sjeff unsigned long end = jiffies + GO_BIT_TIMEOUT; 237219820Sjeff 238219820Sjeff while (go_bit(dev) && time_before(jiffies, end)) 239219820Sjeff sched_yield(); 240219820Sjeff } 241219820Sjeff 242219820Sjeff if (go_bit(dev)) 243219820Sjeff return -EAGAIN; 244219820Sjeff 245219820Sjeff /* 246219820Sjeff * We use writel (instead of something like memcpy_toio) 247219820Sjeff * because writes of less than 32 bits to the HCR don't work 248219820Sjeff * (and some architectures such as ia64 implement memcpy_toio 249219820Sjeff * in terms of writeb). 250219820Sjeff */ 251219820Sjeff __raw_writel((__force u32) cpu_to_be32(in_param >> 32), dev->hcr + 0 * 4); 252219820Sjeff __raw_writel((__force u32) cpu_to_be32(in_param & 0xfffffffful), dev->hcr + 1 * 4); 253219820Sjeff __raw_writel((__force u32) cpu_to_be32(in_modifier), dev->hcr + 2 * 4); 254219820Sjeff __raw_writel((__force u32) cpu_to_be32(out_param >> 32), dev->hcr + 3 * 4); 255219820Sjeff __raw_writel((__force u32) cpu_to_be32(out_param & 0xfffffffful), dev->hcr + 4 * 4); 256219820Sjeff __raw_writel((__force u32) cpu_to_be32(token << 16), dev->hcr + 5 * 4); 257219820Sjeff 258219820Sjeff /* __raw_writel may not order writes. */ 259219820Sjeff wmb(); 260219820Sjeff 261219820Sjeff __raw_writel((__force u32) cpu_to_be32((1 << HCR_GO_BIT) | 262219820Sjeff (event ? (1 << HCA_E_BIT) : 0) | 263219820Sjeff (op_modifier << HCR_OPMOD_SHIFT) | 264219820Sjeff op), dev->hcr + 6 * 4); 265219820Sjeff 266219820Sjeff return 0; 267219820Sjeff} 268219820Sjeff 269219820Sjeffstatic int mthca_cmd_post(struct mthca_dev *dev, 270219820Sjeff u64 in_param, 271219820Sjeff u64 out_param, 272219820Sjeff u32 in_modifier, 273219820Sjeff u8 op_modifier, 274219820Sjeff u16 op, 275219820Sjeff u16 token, 276219820Sjeff int event) 277219820Sjeff{ 278219820Sjeff int err = 0; 279219820Sjeff 280219820Sjeff mutex_lock(&dev->cmd.hcr_mutex); 281219820Sjeff 282219820Sjeff if (event && dev->cmd.flags & MTHCA_CMD_POST_DOORBELLS && fw_cmd_doorbell) 283219820Sjeff mthca_cmd_post_dbell(dev, in_param, out_param, in_modifier, 284219820Sjeff op_modifier, op, token); 285219820Sjeff else 286219820Sjeff err = mthca_cmd_post_hcr(dev, in_param, out_param, in_modifier, 287219820Sjeff op_modifier, op, token, event); 288219820Sjeff 289219820Sjeff /* 290219820Sjeff * Make sure that our HCR writes don't get mixed in with 291219820Sjeff * writes from another CPU starting a FW command. 292219820Sjeff */ 293219820Sjeff mmiowb(); 294219820Sjeff 295219820Sjeff mutex_unlock(&dev->cmd.hcr_mutex); 296219820Sjeff return err; 297219820Sjeff} 298219820Sjeff 299219820Sjeffstatic int mthca_cmd_poll(struct mthca_dev *dev, 300219820Sjeff u64 in_param, 301219820Sjeff u64 *out_param, 302219820Sjeff int out_is_imm, 303219820Sjeff u32 in_modifier, 304219820Sjeff u8 op_modifier, 305219820Sjeff u16 op, 306219820Sjeff unsigned long timeout, 307219820Sjeff u8 *status) 308219820Sjeff{ 309219820Sjeff int err = 0; 310219820Sjeff unsigned long end; 311219820Sjeff 312219820Sjeff down(&dev->cmd.poll_sem); 313219820Sjeff 314219820Sjeff err = mthca_cmd_post(dev, in_param, 315219820Sjeff out_param ? *out_param : 0, 316219820Sjeff in_modifier, op_modifier, 317219820Sjeff op, CMD_POLL_TOKEN, 0); 318219820Sjeff if (err) 319219820Sjeff goto out; 320219820Sjeff 321219820Sjeff end = timeout + jiffies; 322219820Sjeff while (go_bit(dev) && time_before(jiffies, end)) 323219820Sjeff sched_yield(); 324219820Sjeff 325219820Sjeff if (go_bit(dev)) { 326219820Sjeff err = -EBUSY; 327219820Sjeff goto out; 328219820Sjeff } 329219820Sjeff 330219820Sjeff if (out_is_imm) 331219820Sjeff *out_param = 332219820Sjeff (u64) be32_to_cpu((__force __be32) 333219820Sjeff __raw_readl(dev->hcr + HCR_OUT_PARAM_OFFSET)) << 32 | 334219820Sjeff (u64) be32_to_cpu((__force __be32) 335219820Sjeff __raw_readl(dev->hcr + HCR_OUT_PARAM_OFFSET + 4)); 336219820Sjeff 337219820Sjeff *status = be32_to_cpu((__force __be32) __raw_readl(dev->hcr + HCR_STATUS_OFFSET)) >> 24; 338219820Sjeff 339219820Sjeffout: 340219820Sjeff up(&dev->cmd.poll_sem); 341219820Sjeff return err; 342219820Sjeff} 343219820Sjeff 344219820Sjeffvoid mthca_cmd_event(struct mthca_dev *dev, 345219820Sjeff u16 token, 346219820Sjeff u8 status, 347219820Sjeff u64 out_param) 348219820Sjeff{ 349219820Sjeff struct mthca_cmd_context *context = 350219820Sjeff &dev->cmd.context[token & dev->cmd.token_mask]; 351219820Sjeff 352219820Sjeff /* previously timed out command completing at long last */ 353219820Sjeff if (token != context->token) 354219820Sjeff return; 355219820Sjeff 356219820Sjeff context->result = 0; 357219820Sjeff context->status = status; 358219820Sjeff context->out_param = out_param; 359219820Sjeff 360219820Sjeff complete(&context->done); 361219820Sjeff} 362219820Sjeff 363219820Sjeffstatic int mthca_cmd_wait(struct mthca_dev *dev, 364219820Sjeff u64 in_param, 365219820Sjeff u64 *out_param, 366219820Sjeff int out_is_imm, 367219820Sjeff u32 in_modifier, 368219820Sjeff u8 op_modifier, 369219820Sjeff u16 op, 370219820Sjeff unsigned long timeout, 371219820Sjeff u8 *status) 372219820Sjeff{ 373219820Sjeff int err = 0; 374219820Sjeff struct mthca_cmd_context *context; 375219820Sjeff 376219820Sjeff down(&dev->cmd.event_sem); 377219820Sjeff 378219820Sjeff spin_lock(&dev->cmd.context_lock); 379219820Sjeff BUG_ON(dev->cmd.free_head < 0); 380219820Sjeff context = &dev->cmd.context[dev->cmd.free_head]; 381219820Sjeff context->token += dev->cmd.token_mask + 1; 382219820Sjeff dev->cmd.free_head = context->next; 383219820Sjeff spin_unlock(&dev->cmd.context_lock); 384219820Sjeff 385219820Sjeff init_completion(&context->done); 386219820Sjeff 387219820Sjeff err = mthca_cmd_post(dev, in_param, 388219820Sjeff out_param ? *out_param : 0, 389219820Sjeff in_modifier, op_modifier, 390219820Sjeff op, context->token, 1); 391219820Sjeff if (err) 392219820Sjeff goto out; 393219820Sjeff 394219820Sjeff if (!wait_for_completion_timeout(&context->done, timeout)) { 395219820Sjeff err = -EBUSY; 396219820Sjeff goto out; 397219820Sjeff } 398219820Sjeff 399219820Sjeff err = context->result; 400219820Sjeff if (err) 401219820Sjeff goto out; 402219820Sjeff 403219820Sjeff *status = context->status; 404219820Sjeff if (*status) 405219820Sjeff mthca_dbg(dev, "Command %02x completed with status %02x\n", 406219820Sjeff op, *status); 407219820Sjeff 408219820Sjeff if (out_is_imm) 409219820Sjeff *out_param = context->out_param; 410219820Sjeff 411219820Sjeffout: 412219820Sjeff spin_lock(&dev->cmd.context_lock); 413219820Sjeff context->next = dev->cmd.free_head; 414219820Sjeff dev->cmd.free_head = context - dev->cmd.context; 415219820Sjeff spin_unlock(&dev->cmd.context_lock); 416219820Sjeff 417219820Sjeff up(&dev->cmd.event_sem); 418219820Sjeff return err; 419219820Sjeff} 420219820Sjeff 421219820Sjeff/* Invoke a command with an output mailbox */ 422219820Sjeffstatic int mthca_cmd_box(struct mthca_dev *dev, 423219820Sjeff u64 in_param, 424219820Sjeff u64 out_param, 425219820Sjeff u32 in_modifier, 426219820Sjeff u8 op_modifier, 427219820Sjeff u16 op, 428219820Sjeff unsigned long timeout, 429219820Sjeff u8 *status) 430219820Sjeff{ 431219820Sjeff if (dev->cmd.flags & MTHCA_CMD_USE_EVENTS) 432219820Sjeff return mthca_cmd_wait(dev, in_param, &out_param, 0, 433219820Sjeff in_modifier, op_modifier, op, 434219820Sjeff timeout, status); 435219820Sjeff else 436219820Sjeff return mthca_cmd_poll(dev, in_param, &out_param, 0, 437219820Sjeff in_modifier, op_modifier, op, 438219820Sjeff timeout, status); 439219820Sjeff} 440219820Sjeff 441219820Sjeff/* Invoke a command with no output parameter */ 442219820Sjeffstatic int mthca_cmd(struct mthca_dev *dev, 443219820Sjeff u64 in_param, 444219820Sjeff u32 in_modifier, 445219820Sjeff u8 op_modifier, 446219820Sjeff u16 op, 447219820Sjeff unsigned long timeout, 448219820Sjeff u8 *status) 449219820Sjeff{ 450219820Sjeff return mthca_cmd_box(dev, in_param, 0, in_modifier, 451219820Sjeff op_modifier, op, timeout, status); 452219820Sjeff} 453219820Sjeff 454219820Sjeff/* 455219820Sjeff * Invoke a command with an immediate output parameter (and copy the 456219820Sjeff * output into the caller's out_param pointer after the command 457219820Sjeff * executes). 458219820Sjeff */ 459219820Sjeffstatic int mthca_cmd_imm(struct mthca_dev *dev, 460219820Sjeff u64 in_param, 461219820Sjeff u64 *out_param, 462219820Sjeff u32 in_modifier, 463219820Sjeff u8 op_modifier, 464219820Sjeff u16 op, 465219820Sjeff unsigned long timeout, 466219820Sjeff u8 *status) 467219820Sjeff{ 468219820Sjeff if (dev->cmd.flags & MTHCA_CMD_USE_EVENTS) 469219820Sjeff return mthca_cmd_wait(dev, in_param, out_param, 1, 470219820Sjeff in_modifier, op_modifier, op, 471219820Sjeff timeout, status); 472219820Sjeff else 473219820Sjeff return mthca_cmd_poll(dev, in_param, out_param, 1, 474219820Sjeff in_modifier, op_modifier, op, 475219820Sjeff timeout, status); 476219820Sjeff} 477219820Sjeff 478219820Sjeffint mthca_cmd_init(struct mthca_dev *dev) 479219820Sjeff{ 480219820Sjeff mutex_init(&dev->cmd.hcr_mutex); 481219820Sjeff sema_init(&dev->cmd.poll_sem, 1); 482219820Sjeff dev->cmd.flags = 0; 483219820Sjeff 484219820Sjeff dev->hcr = ioremap(pci_resource_start(dev->pdev, 0) + MTHCA_HCR_BASE, 485219820Sjeff MTHCA_HCR_SIZE); 486219820Sjeff if (!dev->hcr) { 487219820Sjeff mthca_err(dev, "Couldn't map command register."); 488219820Sjeff return -ENOMEM; 489219820Sjeff } 490219820Sjeff 491219820Sjeff dev->cmd.pool = pci_pool_create("mthca_cmd", dev->pdev, 492219820Sjeff MTHCA_MAILBOX_SIZE, 493219820Sjeff MTHCA_MAILBOX_SIZE, 0); 494219820Sjeff if (!dev->cmd.pool) { 495219820Sjeff iounmap(dev->hcr); 496219820Sjeff return -ENOMEM; 497219820Sjeff } 498219820Sjeff 499219820Sjeff return 0; 500219820Sjeff} 501219820Sjeff 502219820Sjeffvoid mthca_cmd_cleanup(struct mthca_dev *dev) 503219820Sjeff{ 504219820Sjeff pci_pool_destroy(dev->cmd.pool); 505219820Sjeff iounmap(dev->hcr); 506219820Sjeff if (dev->cmd.flags & MTHCA_CMD_POST_DOORBELLS) 507219820Sjeff iounmap(dev->cmd.dbell_map); 508219820Sjeff} 509219820Sjeff 510219820Sjeff/* 511219820Sjeff * Switch to using events to issue FW commands (should be called after 512219820Sjeff * event queue to command events has been initialized). 513219820Sjeff */ 514219820Sjeffint mthca_cmd_use_events(struct mthca_dev *dev) 515219820Sjeff{ 516219820Sjeff int i; 517219820Sjeff 518219820Sjeff dev->cmd.context = kmalloc(dev->cmd.max_cmds * 519219820Sjeff sizeof (struct mthca_cmd_context), 520219820Sjeff GFP_KERNEL); 521219820Sjeff if (!dev->cmd.context) 522219820Sjeff return -ENOMEM; 523219820Sjeff 524219820Sjeff for (i = 0; i < dev->cmd.max_cmds; ++i) { 525219820Sjeff dev->cmd.context[i].token = i; 526219820Sjeff dev->cmd.context[i].next = i + 1; 527219820Sjeff } 528219820Sjeff 529219820Sjeff dev->cmd.context[dev->cmd.max_cmds - 1].next = -1; 530219820Sjeff dev->cmd.free_head = 0; 531219820Sjeff 532219820Sjeff sema_init(&dev->cmd.event_sem, dev->cmd.max_cmds); 533219820Sjeff spin_lock_init(&dev->cmd.context_lock); 534219820Sjeff 535219820Sjeff for (dev->cmd.token_mask = 1; 536219820Sjeff dev->cmd.token_mask < dev->cmd.max_cmds; 537219820Sjeff dev->cmd.token_mask <<= 1) 538219820Sjeff ; /* nothing */ 539219820Sjeff --dev->cmd.token_mask; 540219820Sjeff 541219820Sjeff dev->cmd.flags |= MTHCA_CMD_USE_EVENTS; 542219820Sjeff 543219820Sjeff down(&dev->cmd.poll_sem); 544219820Sjeff 545219820Sjeff return 0; 546219820Sjeff} 547219820Sjeff 548219820Sjeff/* 549219820Sjeff * Switch back to polling (used when shutting down the device) 550219820Sjeff */ 551219820Sjeffvoid mthca_cmd_use_polling(struct mthca_dev *dev) 552219820Sjeff{ 553219820Sjeff int i; 554219820Sjeff 555219820Sjeff dev->cmd.flags &= ~MTHCA_CMD_USE_EVENTS; 556219820Sjeff 557219820Sjeff for (i = 0; i < dev->cmd.max_cmds; ++i) 558219820Sjeff down(&dev->cmd.event_sem); 559219820Sjeff 560219820Sjeff kfree(dev->cmd.context); 561219820Sjeff 562219820Sjeff up(&dev->cmd.poll_sem); 563219820Sjeff} 564219820Sjeff 565219820Sjeffstruct mthca_mailbox *mthca_alloc_mailbox(struct mthca_dev *dev, 566219820Sjeff gfp_t gfp_mask) 567219820Sjeff{ 568219820Sjeff struct mthca_mailbox *mailbox; 569219820Sjeff 570219820Sjeff mailbox = kmalloc(sizeof *mailbox, gfp_mask); 571219820Sjeff if (!mailbox) 572219820Sjeff return ERR_PTR(-ENOMEM); 573219820Sjeff 574219820Sjeff mailbox->buf = pci_pool_alloc(dev->cmd.pool, gfp_mask, &mailbox->dma); 575219820Sjeff if (!mailbox->buf) { 576219820Sjeff kfree(mailbox); 577219820Sjeff return ERR_PTR(-ENOMEM); 578219820Sjeff } 579219820Sjeff 580219820Sjeff return mailbox; 581219820Sjeff} 582219820Sjeff 583219820Sjeffvoid mthca_free_mailbox(struct mthca_dev *dev, struct mthca_mailbox *mailbox) 584219820Sjeff{ 585219820Sjeff if (!mailbox) 586219820Sjeff return; 587219820Sjeff 588219820Sjeff pci_pool_free(dev->cmd.pool, mailbox->buf, mailbox->dma); 589219820Sjeff kfree(mailbox); 590219820Sjeff} 591219820Sjeff 592219820Sjeffint mthca_SYS_EN(struct mthca_dev *dev, u8 *status) 593219820Sjeff{ 594219820Sjeff u64 out; 595219820Sjeff int ret; 596219820Sjeff 597219820Sjeff ret = mthca_cmd_imm(dev, 0, &out, 0, 0, CMD_SYS_EN, CMD_TIME_CLASS_D, status); 598219820Sjeff 599219820Sjeff if (*status == MTHCA_CMD_STAT_DDR_MEM_ERR) 600219820Sjeff mthca_warn(dev, "SYS_EN DDR error: syn=%x, sock=%d, " 601219820Sjeff "sladdr=%d, SPD source=%s\n", 602219820Sjeff (int) (out >> 6) & 0xf, (int) (out >> 4) & 3, 603219820Sjeff (int) (out >> 1) & 7, (int) out & 1 ? "NVMEM" : "DIMM"); 604219820Sjeff 605219820Sjeff return ret; 606219820Sjeff} 607219820Sjeff 608219820Sjeffint mthca_SYS_DIS(struct mthca_dev *dev, u8 *status) 609219820Sjeff{ 610219820Sjeff return mthca_cmd(dev, 0, 0, 0, CMD_SYS_DIS, CMD_TIME_CLASS_C, status); 611219820Sjeff} 612219820Sjeff 613219820Sjeffstatic int mthca_map_cmd(struct mthca_dev *dev, u16 op, struct mthca_icm *icm, 614219820Sjeff u64 virt, u8 *status) 615219820Sjeff{ 616219820Sjeff struct mthca_mailbox *mailbox; 617219820Sjeff struct mthca_icm_iter iter; 618219820Sjeff __be64 *pages; 619219820Sjeff int lg; 620219820Sjeff int nent = 0; 621219820Sjeff int i; 622219820Sjeff int err = 0; 623219820Sjeff int ts = 0, tc = 0; 624219820Sjeff 625219820Sjeff mailbox = mthca_alloc_mailbox(dev, GFP_KERNEL); 626219820Sjeff if (IS_ERR(mailbox)) 627219820Sjeff return PTR_ERR(mailbox); 628219820Sjeff memset(mailbox->buf, 0, MTHCA_MAILBOX_SIZE); 629219820Sjeff pages = mailbox->buf; 630219820Sjeff 631219820Sjeff for (mthca_icm_first(icm, &iter); 632219820Sjeff !mthca_icm_last(&iter); 633219820Sjeff mthca_icm_next(&iter)) { 634219820Sjeff /* 635219820Sjeff * We have to pass pages that are aligned to their 636219820Sjeff * size, so find the least significant 1 in the 637219820Sjeff * address or size and use that as our log2 size. 638219820Sjeff */ 639219820Sjeff lg = ffs(mthca_icm_addr(&iter) | mthca_icm_size(&iter)) - 1; 640219820Sjeff if (lg < MTHCA_ICM_PAGE_SHIFT) { 641219820Sjeff mthca_warn(dev, "Got FW area not aligned to %d (%llx/%lx).\n", 642219820Sjeff MTHCA_ICM_PAGE_SIZE, 643219820Sjeff (unsigned long long) mthca_icm_addr(&iter), 644219820Sjeff mthca_icm_size(&iter)); 645219820Sjeff err = -EINVAL; 646219820Sjeff goto out; 647219820Sjeff } 648219820Sjeff for (i = 0; i < mthca_icm_size(&iter) >> lg; ++i) { 649219820Sjeff if (virt != -1) { 650219820Sjeff pages[nent * 2] = cpu_to_be64(virt); 651219820Sjeff virt += 1 << lg; 652219820Sjeff } 653219820Sjeff 654219820Sjeff pages[nent * 2 + 1] = 655219820Sjeff cpu_to_be64((mthca_icm_addr(&iter) + (i << lg)) | 656219820Sjeff (lg - MTHCA_ICM_PAGE_SHIFT)); 657219820Sjeff ts += 1 << (lg - 10); 658219820Sjeff ++tc; 659219820Sjeff 660219820Sjeff if (++nent == MTHCA_MAILBOX_SIZE / 16) { 661219820Sjeff err = mthca_cmd(dev, mailbox->dma, nent, 0, op, 662219820Sjeff CMD_TIME_CLASS_B, status); 663219820Sjeff if (err || *status) 664219820Sjeff goto out; 665219820Sjeff nent = 0; 666219820Sjeff } 667219820Sjeff } 668219820Sjeff } 669219820Sjeff 670219820Sjeff if (nent) 671219820Sjeff err = mthca_cmd(dev, mailbox->dma, nent, 0, op, 672219820Sjeff CMD_TIME_CLASS_B, status); 673219820Sjeff 674219820Sjeff switch (op) { 675219820Sjeff case CMD_MAP_FA: 676219820Sjeff mthca_dbg(dev, "Mapped %d chunks/%d KB for FW.\n", tc, ts); 677219820Sjeff break; 678219820Sjeff case CMD_MAP_ICM_AUX: 679219820Sjeff mthca_dbg(dev, "Mapped %d chunks/%d KB for ICM aux.\n", tc, ts); 680219820Sjeff break; 681219820Sjeff case CMD_MAP_ICM: 682219820Sjeff mthca_dbg(dev, "Mapped %d chunks/%d KB at %llx for ICM.\n", 683219820Sjeff tc, ts, (unsigned long long) virt - (ts << 10)); 684219820Sjeff break; 685219820Sjeff } 686219820Sjeff 687219820Sjeffout: 688219820Sjeff mthca_free_mailbox(dev, mailbox); 689219820Sjeff return err; 690219820Sjeff} 691219820Sjeff 692219820Sjeffint mthca_MAP_FA(struct mthca_dev *dev, struct mthca_icm *icm, u8 *status) 693219820Sjeff{ 694219820Sjeff return mthca_map_cmd(dev, CMD_MAP_FA, icm, -1, status); 695219820Sjeff} 696219820Sjeff 697219820Sjeffint mthca_UNMAP_FA(struct mthca_dev *dev, u8 *status) 698219820Sjeff{ 699219820Sjeff return mthca_cmd(dev, 0, 0, 0, CMD_UNMAP_FA, CMD_TIME_CLASS_B, status); 700219820Sjeff} 701219820Sjeff 702219820Sjeffint mthca_RUN_FW(struct mthca_dev *dev, u8 *status) 703219820Sjeff{ 704219820Sjeff return mthca_cmd(dev, 0, 0, 0, CMD_RUN_FW, CMD_TIME_CLASS_A, status); 705219820Sjeff} 706219820Sjeff 707219820Sjeffstatic void mthca_setup_cmd_doorbells(struct mthca_dev *dev, u64 base) 708219820Sjeff{ 709219820Sjeff unsigned long addr; 710219820Sjeff u16 max_off = 0; 711219820Sjeff int i; 712219820Sjeff 713219820Sjeff for (i = 0; i < 8; ++i) 714219820Sjeff max_off = max(max_off, dev->cmd.dbell_offsets[i]); 715219820Sjeff 716219820Sjeff if ((base & PAGE_MASK) != ((base + max_off) & PAGE_MASK)) { 717219820Sjeff mthca_warn(dev, "Firmware doorbell region at 0x%016llx, " 718219820Sjeff "length 0x%x crosses a page boundary\n", 719219820Sjeff (unsigned long long) base, max_off); 720219820Sjeff return; 721219820Sjeff } 722219820Sjeff 723219820Sjeff addr = pci_resource_start(dev->pdev, 2) + 724219820Sjeff ((pci_resource_len(dev->pdev, 2) - 1) & base); 725219820Sjeff dev->cmd.dbell_map = ioremap(addr, max_off + sizeof(u32)); 726219820Sjeff if (!dev->cmd.dbell_map) 727219820Sjeff return; 728219820Sjeff 729219820Sjeff dev->cmd.flags |= MTHCA_CMD_POST_DOORBELLS; 730219820Sjeff mthca_dbg(dev, "Mapped doorbell page for posting FW commands\n"); 731219820Sjeff} 732219820Sjeff 733219820Sjeffint mthca_QUERY_FW(struct mthca_dev *dev, u8 *status) 734219820Sjeff{ 735219820Sjeff struct mthca_mailbox *mailbox; 736219820Sjeff u32 *outbox; 737219820Sjeff u64 base; 738219820Sjeff u32 tmp; 739219820Sjeff int err = 0; 740219820Sjeff u8 lg; 741219820Sjeff int i; 742219820Sjeff 743219820Sjeff#define QUERY_FW_OUT_SIZE 0x100 744219820Sjeff#define QUERY_FW_VER_OFFSET 0x00 745219820Sjeff#define QUERY_FW_MAX_CMD_OFFSET 0x0f 746219820Sjeff#define QUERY_FW_ERR_START_OFFSET 0x30 747219820Sjeff#define QUERY_FW_ERR_SIZE_OFFSET 0x38 748219820Sjeff 749219820Sjeff#define QUERY_FW_CMD_DB_EN_OFFSET 0x10 750219820Sjeff#define QUERY_FW_CMD_DB_OFFSET 0x50 751219820Sjeff#define QUERY_FW_CMD_DB_BASE 0x60 752219820Sjeff 753219820Sjeff#define QUERY_FW_START_OFFSET 0x20 754219820Sjeff#define QUERY_FW_END_OFFSET 0x28 755219820Sjeff 756219820Sjeff#define QUERY_FW_SIZE_OFFSET 0x00 757219820Sjeff#define QUERY_FW_CLR_INT_BASE_OFFSET 0x20 758219820Sjeff#define QUERY_FW_EQ_ARM_BASE_OFFSET 0x40 759219820Sjeff#define QUERY_FW_EQ_SET_CI_BASE_OFFSET 0x48 760219820Sjeff 761219820Sjeff mailbox = mthca_alloc_mailbox(dev, GFP_KERNEL); 762219820Sjeff if (IS_ERR(mailbox)) 763219820Sjeff return PTR_ERR(mailbox); 764219820Sjeff outbox = mailbox->buf; 765219820Sjeff 766219820Sjeff err = mthca_cmd_box(dev, 0, mailbox->dma, 0, 0, CMD_QUERY_FW, 767219820Sjeff CMD_TIME_CLASS_A, status); 768219820Sjeff 769219820Sjeff if (err) 770219820Sjeff goto out; 771219820Sjeff 772219820Sjeff MTHCA_GET(dev->fw_ver, outbox, QUERY_FW_VER_OFFSET); 773219820Sjeff /* 774219820Sjeff * FW subminor version is at more significant bits than minor 775219820Sjeff * version, so swap here. 776219820Sjeff */ 777219820Sjeff dev->fw_ver = (dev->fw_ver & 0xffff00000000ull) | 778219820Sjeff ((dev->fw_ver & 0xffff0000ull) >> 16) | 779219820Sjeff ((dev->fw_ver & 0x0000ffffull) << 16); 780219820Sjeff 781219820Sjeff MTHCA_GET(lg, outbox, QUERY_FW_MAX_CMD_OFFSET); 782219820Sjeff dev->cmd.max_cmds = 1 << lg; 783219820Sjeff 784219820Sjeff mthca_dbg(dev, "FW version %012llx, max commands %d\n", 785219820Sjeff (unsigned long long) dev->fw_ver, dev->cmd.max_cmds); 786219820Sjeff 787219820Sjeff MTHCA_GET(dev->catas_err.addr, outbox, QUERY_FW_ERR_START_OFFSET); 788219820Sjeff MTHCA_GET(dev->catas_err.size, outbox, QUERY_FW_ERR_SIZE_OFFSET); 789219820Sjeff 790219820Sjeff mthca_dbg(dev, "Catastrophic error buffer at 0x%llx, size 0x%x\n", 791219820Sjeff (unsigned long long) dev->catas_err.addr, dev->catas_err.size); 792219820Sjeff 793219820Sjeff MTHCA_GET(tmp, outbox, QUERY_FW_CMD_DB_EN_OFFSET); 794219820Sjeff if (tmp & 0x1) { 795219820Sjeff mthca_dbg(dev, "FW supports commands through doorbells\n"); 796219820Sjeff 797219820Sjeff MTHCA_GET(base, outbox, QUERY_FW_CMD_DB_BASE); 798219820Sjeff for (i = 0; i < MTHCA_CMD_NUM_DBELL_DWORDS; ++i) 799219820Sjeff MTHCA_GET(dev->cmd.dbell_offsets[i], outbox, 800219820Sjeff QUERY_FW_CMD_DB_OFFSET + (i << 1)); 801219820Sjeff 802219820Sjeff mthca_setup_cmd_doorbells(dev, base); 803219820Sjeff } 804219820Sjeff 805219820Sjeff if (mthca_is_memfree(dev)) { 806219820Sjeff MTHCA_GET(dev->fw.arbel.fw_pages, outbox, QUERY_FW_SIZE_OFFSET); 807219820Sjeff MTHCA_GET(dev->fw.arbel.clr_int_base, outbox, QUERY_FW_CLR_INT_BASE_OFFSET); 808219820Sjeff MTHCA_GET(dev->fw.arbel.eq_arm_base, outbox, QUERY_FW_EQ_ARM_BASE_OFFSET); 809219820Sjeff MTHCA_GET(dev->fw.arbel.eq_set_ci_base, outbox, QUERY_FW_EQ_SET_CI_BASE_OFFSET); 810219820Sjeff mthca_dbg(dev, "FW size %d KB\n", dev->fw.arbel.fw_pages << 2); 811219820Sjeff 812219820Sjeff /* 813219820Sjeff * Round up number of system pages needed in case 814219820Sjeff * MTHCA_ICM_PAGE_SIZE < PAGE_SIZE. 815219820Sjeff */ 816219820Sjeff dev->fw.arbel.fw_pages = 817219820Sjeff ALIGN(dev->fw.arbel.fw_pages, PAGE_SIZE / MTHCA_ICM_PAGE_SIZE) >> 818219820Sjeff (PAGE_SHIFT - MTHCA_ICM_PAGE_SHIFT); 819219820Sjeff 820219820Sjeff mthca_dbg(dev, "Clear int @ %llx, EQ arm @ %llx, EQ set CI @ %llx\n", 821219820Sjeff (unsigned long long) dev->fw.arbel.clr_int_base, 822219820Sjeff (unsigned long long) dev->fw.arbel.eq_arm_base, 823219820Sjeff (unsigned long long) dev->fw.arbel.eq_set_ci_base); 824219820Sjeff } else { 825219820Sjeff MTHCA_GET(dev->fw.tavor.fw_start, outbox, QUERY_FW_START_OFFSET); 826219820Sjeff MTHCA_GET(dev->fw.tavor.fw_end, outbox, QUERY_FW_END_OFFSET); 827219820Sjeff 828219820Sjeff mthca_dbg(dev, "FW size %d KB (start %llx, end %llx)\n", 829219820Sjeff (int) ((dev->fw.tavor.fw_end - dev->fw.tavor.fw_start) >> 10), 830219820Sjeff (unsigned long long) dev->fw.tavor.fw_start, 831219820Sjeff (unsigned long long) dev->fw.tavor.fw_end); 832219820Sjeff } 833219820Sjeff 834219820Sjeffout: 835219820Sjeff mthca_free_mailbox(dev, mailbox); 836219820Sjeff return err; 837219820Sjeff} 838219820Sjeff 839219820Sjeffint mthca_ENABLE_LAM(struct mthca_dev *dev, u8 *status) 840219820Sjeff{ 841219820Sjeff struct mthca_mailbox *mailbox; 842219820Sjeff u8 info; 843219820Sjeff u32 *outbox; 844219820Sjeff int err = 0; 845219820Sjeff 846219820Sjeff#define ENABLE_LAM_OUT_SIZE 0x100 847219820Sjeff#define ENABLE_LAM_START_OFFSET 0x00 848219820Sjeff#define ENABLE_LAM_END_OFFSET 0x08 849219820Sjeff#define ENABLE_LAM_INFO_OFFSET 0x13 850219820Sjeff 851219820Sjeff#define ENABLE_LAM_INFO_HIDDEN_FLAG (1 << 4) 852219820Sjeff#define ENABLE_LAM_INFO_ECC_MASK 0x3 853219820Sjeff 854219820Sjeff mailbox = mthca_alloc_mailbox(dev, GFP_KERNEL); 855219820Sjeff if (IS_ERR(mailbox)) 856219820Sjeff return PTR_ERR(mailbox); 857219820Sjeff outbox = mailbox->buf; 858219820Sjeff 859219820Sjeff err = mthca_cmd_box(dev, 0, mailbox->dma, 0, 0, CMD_ENABLE_LAM, 860219820Sjeff CMD_TIME_CLASS_C, status); 861219820Sjeff 862219820Sjeff if (err) 863219820Sjeff goto out; 864219820Sjeff 865219820Sjeff if (*status == MTHCA_CMD_STAT_LAM_NOT_PRE) 866219820Sjeff goto out; 867219820Sjeff 868219820Sjeff MTHCA_GET(dev->ddr_start, outbox, ENABLE_LAM_START_OFFSET); 869219820Sjeff MTHCA_GET(dev->ddr_end, outbox, ENABLE_LAM_END_OFFSET); 870219820Sjeff MTHCA_GET(info, outbox, ENABLE_LAM_INFO_OFFSET); 871219820Sjeff 872219820Sjeff if (!!(info & ENABLE_LAM_INFO_HIDDEN_FLAG) != 873219820Sjeff !!(dev->mthca_flags & MTHCA_FLAG_DDR_HIDDEN)) { 874219820Sjeff mthca_info(dev, "FW reports that HCA-attached memory " 875219820Sjeff "is %s hidden; does not match PCI config\n", 876219820Sjeff (info & ENABLE_LAM_INFO_HIDDEN_FLAG) ? 877219820Sjeff "" : "not"); 878219820Sjeff } 879219820Sjeff if (info & ENABLE_LAM_INFO_HIDDEN_FLAG) 880219820Sjeff mthca_dbg(dev, "HCA-attached memory is hidden.\n"); 881219820Sjeff 882219820Sjeff mthca_dbg(dev, "HCA memory size %d KB (start %llx, end %llx)\n", 883219820Sjeff (int) ((dev->ddr_end - dev->ddr_start) >> 10), 884219820Sjeff (unsigned long long) dev->ddr_start, 885219820Sjeff (unsigned long long) dev->ddr_end); 886219820Sjeff 887219820Sjeffout: 888219820Sjeff mthca_free_mailbox(dev, mailbox); 889219820Sjeff return err; 890219820Sjeff} 891219820Sjeff 892219820Sjeffint mthca_DISABLE_LAM(struct mthca_dev *dev, u8 *status) 893219820Sjeff{ 894219820Sjeff return mthca_cmd(dev, 0, 0, 0, CMD_SYS_DIS, CMD_TIME_CLASS_C, status); 895219820Sjeff} 896219820Sjeff 897219820Sjeffint mthca_QUERY_DDR(struct mthca_dev *dev, u8 *status) 898219820Sjeff{ 899219820Sjeff struct mthca_mailbox *mailbox; 900219820Sjeff u8 info; 901219820Sjeff u32 *outbox; 902219820Sjeff int err = 0; 903219820Sjeff 904219820Sjeff#define QUERY_DDR_OUT_SIZE 0x100 905219820Sjeff#define QUERY_DDR_START_OFFSET 0x00 906219820Sjeff#define QUERY_DDR_END_OFFSET 0x08 907219820Sjeff#define QUERY_DDR_INFO_OFFSET 0x13 908219820Sjeff 909219820Sjeff#define QUERY_DDR_INFO_HIDDEN_FLAG (1 << 4) 910219820Sjeff#define QUERY_DDR_INFO_ECC_MASK 0x3 911219820Sjeff 912219820Sjeff mailbox = mthca_alloc_mailbox(dev, GFP_KERNEL); 913219820Sjeff if (IS_ERR(mailbox)) 914219820Sjeff return PTR_ERR(mailbox); 915219820Sjeff outbox = mailbox->buf; 916219820Sjeff 917219820Sjeff err = mthca_cmd_box(dev, 0, mailbox->dma, 0, 0, CMD_QUERY_DDR, 918219820Sjeff CMD_TIME_CLASS_A, status); 919219820Sjeff 920219820Sjeff if (err) 921219820Sjeff goto out; 922219820Sjeff 923219820Sjeff MTHCA_GET(dev->ddr_start, outbox, QUERY_DDR_START_OFFSET); 924219820Sjeff MTHCA_GET(dev->ddr_end, outbox, QUERY_DDR_END_OFFSET); 925219820Sjeff MTHCA_GET(info, outbox, QUERY_DDR_INFO_OFFSET); 926219820Sjeff 927219820Sjeff if (!!(info & QUERY_DDR_INFO_HIDDEN_FLAG) != 928219820Sjeff !!(dev->mthca_flags & MTHCA_FLAG_DDR_HIDDEN)) { 929219820Sjeff mthca_info(dev, "FW reports that HCA-attached memory " 930219820Sjeff "is %s hidden; does not match PCI config\n", 931219820Sjeff (info & QUERY_DDR_INFO_HIDDEN_FLAG) ? 932219820Sjeff "" : "not"); 933219820Sjeff } 934219820Sjeff if (info & QUERY_DDR_INFO_HIDDEN_FLAG) 935219820Sjeff mthca_dbg(dev, "HCA-attached memory is hidden.\n"); 936219820Sjeff 937219820Sjeff mthca_dbg(dev, "HCA memory size %d KB (start %llx, end %llx)\n", 938219820Sjeff (int) ((dev->ddr_end - dev->ddr_start) >> 10), 939219820Sjeff (unsigned long long) dev->ddr_start, 940219820Sjeff (unsigned long long) dev->ddr_end); 941219820Sjeff 942219820Sjeffout: 943219820Sjeff mthca_free_mailbox(dev, mailbox); 944219820Sjeff return err; 945219820Sjeff} 946219820Sjeff 947219820Sjeffint mthca_QUERY_DEV_LIM(struct mthca_dev *dev, 948219820Sjeff struct mthca_dev_lim *dev_lim, u8 *status) 949219820Sjeff{ 950219820Sjeff struct mthca_mailbox *mailbox; 951219820Sjeff u32 *outbox; 952219820Sjeff u8 field; 953219820Sjeff u16 size; 954219820Sjeff u16 stat_rate; 955219820Sjeff int err; 956219820Sjeff 957219820Sjeff#define QUERY_DEV_LIM_OUT_SIZE 0x100 958219820Sjeff#define QUERY_DEV_LIM_MAX_SRQ_SZ_OFFSET 0x10 959219820Sjeff#define QUERY_DEV_LIM_MAX_QP_SZ_OFFSET 0x11 960219820Sjeff#define QUERY_DEV_LIM_RSVD_QP_OFFSET 0x12 961219820Sjeff#define QUERY_DEV_LIM_MAX_QP_OFFSET 0x13 962219820Sjeff#define QUERY_DEV_LIM_RSVD_SRQ_OFFSET 0x14 963219820Sjeff#define QUERY_DEV_LIM_MAX_SRQ_OFFSET 0x15 964219820Sjeff#define QUERY_DEV_LIM_RSVD_EEC_OFFSET 0x16 965219820Sjeff#define QUERY_DEV_LIM_MAX_EEC_OFFSET 0x17 966219820Sjeff#define QUERY_DEV_LIM_MAX_CQ_SZ_OFFSET 0x19 967219820Sjeff#define QUERY_DEV_LIM_RSVD_CQ_OFFSET 0x1a 968219820Sjeff#define QUERY_DEV_LIM_MAX_CQ_OFFSET 0x1b 969219820Sjeff#define QUERY_DEV_LIM_MAX_MPT_OFFSET 0x1d 970219820Sjeff#define QUERY_DEV_LIM_RSVD_EQ_OFFSET 0x1e 971219820Sjeff#define QUERY_DEV_LIM_MAX_EQ_OFFSET 0x1f 972219820Sjeff#define QUERY_DEV_LIM_RSVD_MTT_OFFSET 0x20 973219820Sjeff#define QUERY_DEV_LIM_MAX_MRW_SZ_OFFSET 0x21 974219820Sjeff#define QUERY_DEV_LIM_RSVD_MRW_OFFSET 0x22 975219820Sjeff#define QUERY_DEV_LIM_MAX_MTT_SEG_OFFSET 0x23 976219820Sjeff#define QUERY_DEV_LIM_MAX_AV_OFFSET 0x27 977219820Sjeff#define QUERY_DEV_LIM_MAX_REQ_QP_OFFSET 0x29 978219820Sjeff#define QUERY_DEV_LIM_MAX_RES_QP_OFFSET 0x2b 979219820Sjeff#define QUERY_DEV_LIM_MAX_RDMA_OFFSET 0x2f 980219820Sjeff#define QUERY_DEV_LIM_RSZ_SRQ_OFFSET 0x33 981219820Sjeff#define QUERY_DEV_LIM_ACK_DELAY_OFFSET 0x35 982219820Sjeff#define QUERY_DEV_LIM_MTU_WIDTH_OFFSET 0x36 983219820Sjeff#define QUERY_DEV_LIM_VL_PORT_OFFSET 0x37 984219820Sjeff#define QUERY_DEV_LIM_MAX_GID_OFFSET 0x3b 985219820Sjeff#define QUERY_DEV_LIM_RATE_SUPPORT_OFFSET 0x3c 986219820Sjeff#define QUERY_DEV_LIM_MAX_PKEY_OFFSET 0x3f 987219820Sjeff#define QUERY_DEV_LIM_FLAGS_OFFSET 0x44 988219820Sjeff#define QUERY_DEV_LIM_RSVD_UAR_OFFSET 0x48 989219820Sjeff#define QUERY_DEV_LIM_UAR_SZ_OFFSET 0x49 990219820Sjeff#define QUERY_DEV_LIM_PAGE_SZ_OFFSET 0x4b 991219820Sjeff#define QUERY_DEV_LIM_MAX_SG_OFFSET 0x51 992219820Sjeff#define QUERY_DEV_LIM_MAX_DESC_SZ_OFFSET 0x52 993219820Sjeff#define QUERY_DEV_LIM_MAX_SG_RQ_OFFSET 0x55 994219820Sjeff#define QUERY_DEV_LIM_MAX_DESC_SZ_RQ_OFFSET 0x56 995219820Sjeff#define QUERY_DEV_LIM_MAX_QP_MCG_OFFSET 0x61 996219820Sjeff#define QUERY_DEV_LIM_RSVD_MCG_OFFSET 0x62 997219820Sjeff#define QUERY_DEV_LIM_MAX_MCG_OFFSET 0x63 998219820Sjeff#define QUERY_DEV_LIM_RSVD_PD_OFFSET 0x64 999219820Sjeff#define QUERY_DEV_LIM_MAX_PD_OFFSET 0x65 1000219820Sjeff#define QUERY_DEV_LIM_RSVD_RDD_OFFSET 0x66 1001219820Sjeff#define QUERY_DEV_LIM_MAX_RDD_OFFSET 0x67 1002219820Sjeff#define QUERY_DEV_LIM_EEC_ENTRY_SZ_OFFSET 0x80 1003219820Sjeff#define QUERY_DEV_LIM_QPC_ENTRY_SZ_OFFSET 0x82 1004219820Sjeff#define QUERY_DEV_LIM_EEEC_ENTRY_SZ_OFFSET 0x84 1005219820Sjeff#define QUERY_DEV_LIM_EQPC_ENTRY_SZ_OFFSET 0x86 1006219820Sjeff#define QUERY_DEV_LIM_EQC_ENTRY_SZ_OFFSET 0x88 1007219820Sjeff#define QUERY_DEV_LIM_CQC_ENTRY_SZ_OFFSET 0x8a 1008219820Sjeff#define QUERY_DEV_LIM_SRQ_ENTRY_SZ_OFFSET 0x8c 1009219820Sjeff#define QUERY_DEV_LIM_UAR_ENTRY_SZ_OFFSET 0x8e 1010219820Sjeff#define QUERY_DEV_LIM_MTT_ENTRY_SZ_OFFSET 0x90 1011219820Sjeff#define QUERY_DEV_LIM_MPT_ENTRY_SZ_OFFSET 0x92 1012219820Sjeff#define QUERY_DEV_LIM_PBL_SZ_OFFSET 0x96 1013219820Sjeff#define QUERY_DEV_LIM_BMME_FLAGS_OFFSET 0x97 1014219820Sjeff#define QUERY_DEV_LIM_RSVD_LKEY_OFFSET 0x98 1015219820Sjeff#define QUERY_DEV_LIM_LAMR_OFFSET 0x9f 1016219820Sjeff#define QUERY_DEV_LIM_MAX_ICM_SZ_OFFSET 0xa0 1017219820Sjeff 1018219820Sjeff mailbox = mthca_alloc_mailbox(dev, GFP_KERNEL); 1019219820Sjeff if (IS_ERR(mailbox)) 1020219820Sjeff return PTR_ERR(mailbox); 1021219820Sjeff outbox = mailbox->buf; 1022219820Sjeff 1023219820Sjeff err = mthca_cmd_box(dev, 0, mailbox->dma, 0, 0, CMD_QUERY_DEV_LIM, 1024219820Sjeff CMD_TIME_CLASS_A, status); 1025219820Sjeff 1026219820Sjeff if (err) 1027219820Sjeff goto out; 1028219820Sjeff 1029219820Sjeff MTHCA_GET(field, outbox, QUERY_DEV_LIM_RSVD_QP_OFFSET); 1030219820Sjeff dev_lim->reserved_qps = 1 << (field & 0xf); 1031219820Sjeff MTHCA_GET(field, outbox, QUERY_DEV_LIM_MAX_QP_OFFSET); 1032219820Sjeff dev_lim->max_qps = 1 << (field & 0x1f); 1033219820Sjeff MTHCA_GET(field, outbox, QUERY_DEV_LIM_RSVD_SRQ_OFFSET); 1034219820Sjeff dev_lim->reserved_srqs = 1 << (field >> 4); 1035219820Sjeff MTHCA_GET(field, outbox, QUERY_DEV_LIM_MAX_SRQ_OFFSET); 1036219820Sjeff dev_lim->max_srqs = 1 << (field & 0x1f); 1037219820Sjeff MTHCA_GET(field, outbox, QUERY_DEV_LIM_RSVD_EEC_OFFSET); 1038219820Sjeff dev_lim->reserved_eecs = 1 << (field & 0xf); 1039219820Sjeff MTHCA_GET(field, outbox, QUERY_DEV_LIM_MAX_EEC_OFFSET); 1040219820Sjeff dev_lim->max_eecs = 1 << (field & 0x1f); 1041219820Sjeff MTHCA_GET(field, outbox, QUERY_DEV_LIM_MAX_CQ_SZ_OFFSET); 1042219820Sjeff dev_lim->max_cq_sz = 1 << field; 1043219820Sjeff MTHCA_GET(field, outbox, QUERY_DEV_LIM_RSVD_CQ_OFFSET); 1044219820Sjeff dev_lim->reserved_cqs = 1 << (field & 0xf); 1045219820Sjeff MTHCA_GET(field, outbox, QUERY_DEV_LIM_MAX_CQ_OFFSET); 1046219820Sjeff dev_lim->max_cqs = 1 << (field & 0x1f); 1047219820Sjeff MTHCA_GET(field, outbox, QUERY_DEV_LIM_MAX_MPT_OFFSET); 1048219820Sjeff dev_lim->max_mpts = 1 << (field & 0x3f); 1049219820Sjeff MTHCA_GET(field, outbox, QUERY_DEV_LIM_RSVD_EQ_OFFSET); 1050219820Sjeff dev_lim->reserved_eqs = 1 << (field & 0xf); 1051219820Sjeff MTHCA_GET(field, outbox, QUERY_DEV_LIM_MAX_EQ_OFFSET); 1052219820Sjeff dev_lim->max_eqs = 1 << (field & 0x7); 1053219820Sjeff MTHCA_GET(field, outbox, QUERY_DEV_LIM_RSVD_MTT_OFFSET); 1054219820Sjeff if (mthca_is_memfree(dev)) 1055219820Sjeff dev_lim->reserved_mtts = ALIGN((1 << (field >> 4)) * sizeof(u64), 1056219820Sjeff dev->limits.mtt_seg_size) / dev->limits.mtt_seg_size; 1057219820Sjeff else 1058219820Sjeff dev_lim->reserved_mtts = 1 << (field >> 4); 1059219820Sjeff MTHCA_GET(field, outbox, QUERY_DEV_LIM_MAX_MRW_SZ_OFFSET); 1060219820Sjeff dev_lim->max_mrw_sz = 1 << field; 1061219820Sjeff MTHCA_GET(field, outbox, QUERY_DEV_LIM_RSVD_MRW_OFFSET); 1062219820Sjeff dev_lim->reserved_mrws = 1 << (field & 0xf); 1063219820Sjeff MTHCA_GET(field, outbox, QUERY_DEV_LIM_MAX_MTT_SEG_OFFSET); 1064219820Sjeff dev_lim->max_mtt_seg = 1 << (field & 0x3f); 1065219820Sjeff MTHCA_GET(field, outbox, QUERY_DEV_LIM_MAX_REQ_QP_OFFSET); 1066219820Sjeff dev_lim->max_requester_per_qp = 1 << (field & 0x3f); 1067219820Sjeff MTHCA_GET(field, outbox, QUERY_DEV_LIM_MAX_RES_QP_OFFSET); 1068219820Sjeff dev_lim->max_responder_per_qp = 1 << (field & 0x3f); 1069219820Sjeff MTHCA_GET(field, outbox, QUERY_DEV_LIM_MAX_RDMA_OFFSET); 1070219820Sjeff dev_lim->max_rdma_global = 1 << (field & 0x3f); 1071219820Sjeff MTHCA_GET(field, outbox, QUERY_DEV_LIM_ACK_DELAY_OFFSET); 1072219820Sjeff dev_lim->local_ca_ack_delay = field & 0x1f; 1073219820Sjeff MTHCA_GET(field, outbox, QUERY_DEV_LIM_MTU_WIDTH_OFFSET); 1074219820Sjeff dev_lim->max_mtu = field >> 4; 1075219820Sjeff dev_lim->max_port_width = field & 0xf; 1076219820Sjeff MTHCA_GET(field, outbox, QUERY_DEV_LIM_VL_PORT_OFFSET); 1077219820Sjeff dev_lim->max_vl = field >> 4; 1078219820Sjeff dev_lim->num_ports = field & 0xf; 1079219820Sjeff MTHCA_GET(field, outbox, QUERY_DEV_LIM_MAX_GID_OFFSET); 1080219820Sjeff dev_lim->max_gids = 1 << (field & 0xf); 1081219820Sjeff MTHCA_GET(stat_rate, outbox, QUERY_DEV_LIM_RATE_SUPPORT_OFFSET); 1082219820Sjeff dev_lim->stat_rate_support = stat_rate; 1083219820Sjeff MTHCA_GET(field, outbox, QUERY_DEV_LIM_MAX_PKEY_OFFSET); 1084219820Sjeff dev_lim->max_pkeys = 1 << (field & 0xf); 1085219820Sjeff MTHCA_GET(dev_lim->flags, outbox, QUERY_DEV_LIM_FLAGS_OFFSET); 1086219820Sjeff MTHCA_GET(field, outbox, QUERY_DEV_LIM_RSVD_UAR_OFFSET); 1087219820Sjeff dev_lim->reserved_uars = field >> 4; 1088219820Sjeff MTHCA_GET(field, outbox, QUERY_DEV_LIM_UAR_SZ_OFFSET); 1089219820Sjeff dev_lim->uar_size = 1 << ((field & 0x3f) + 20); 1090219820Sjeff MTHCA_GET(field, outbox, QUERY_DEV_LIM_PAGE_SZ_OFFSET); 1091219820Sjeff dev_lim->min_page_sz = 1 << field; 1092219820Sjeff MTHCA_GET(field, outbox, QUERY_DEV_LIM_MAX_SG_OFFSET); 1093219820Sjeff dev_lim->max_sg = field; 1094219820Sjeff 1095219820Sjeff MTHCA_GET(size, outbox, QUERY_DEV_LIM_MAX_DESC_SZ_OFFSET); 1096219820Sjeff dev_lim->max_desc_sz = size; 1097219820Sjeff 1098219820Sjeff MTHCA_GET(field, outbox, QUERY_DEV_LIM_MAX_QP_MCG_OFFSET); 1099219820Sjeff dev_lim->max_qp_per_mcg = 1 << field; 1100219820Sjeff MTHCA_GET(field, outbox, QUERY_DEV_LIM_RSVD_MCG_OFFSET); 1101219820Sjeff dev_lim->reserved_mgms = field & 0xf; 1102219820Sjeff MTHCA_GET(field, outbox, QUERY_DEV_LIM_MAX_MCG_OFFSET); 1103219820Sjeff dev_lim->max_mcgs = 1 << field; 1104219820Sjeff MTHCA_GET(field, outbox, QUERY_DEV_LIM_RSVD_PD_OFFSET); 1105219820Sjeff dev_lim->reserved_pds = field >> 4; 1106219820Sjeff MTHCA_GET(field, outbox, QUERY_DEV_LIM_MAX_PD_OFFSET); 1107219820Sjeff dev_lim->max_pds = 1 << (field & 0x3f); 1108219820Sjeff MTHCA_GET(field, outbox, QUERY_DEV_LIM_RSVD_RDD_OFFSET); 1109219820Sjeff dev_lim->reserved_rdds = field >> 4; 1110219820Sjeff MTHCA_GET(field, outbox, QUERY_DEV_LIM_MAX_RDD_OFFSET); 1111219820Sjeff dev_lim->max_rdds = 1 << (field & 0x3f); 1112219820Sjeff 1113219820Sjeff MTHCA_GET(size, outbox, QUERY_DEV_LIM_EEC_ENTRY_SZ_OFFSET); 1114219820Sjeff dev_lim->eec_entry_sz = size; 1115219820Sjeff MTHCA_GET(size, outbox, QUERY_DEV_LIM_QPC_ENTRY_SZ_OFFSET); 1116219820Sjeff dev_lim->qpc_entry_sz = size; 1117219820Sjeff MTHCA_GET(size, outbox, QUERY_DEV_LIM_EEEC_ENTRY_SZ_OFFSET); 1118219820Sjeff dev_lim->eeec_entry_sz = size; 1119219820Sjeff MTHCA_GET(size, outbox, QUERY_DEV_LIM_EQPC_ENTRY_SZ_OFFSET); 1120219820Sjeff dev_lim->eqpc_entry_sz = size; 1121219820Sjeff MTHCA_GET(size, outbox, QUERY_DEV_LIM_EQC_ENTRY_SZ_OFFSET); 1122219820Sjeff dev_lim->eqc_entry_sz = size; 1123219820Sjeff MTHCA_GET(size, outbox, QUERY_DEV_LIM_CQC_ENTRY_SZ_OFFSET); 1124219820Sjeff dev_lim->cqc_entry_sz = size; 1125219820Sjeff MTHCA_GET(size, outbox, QUERY_DEV_LIM_SRQ_ENTRY_SZ_OFFSET); 1126219820Sjeff dev_lim->srq_entry_sz = size; 1127219820Sjeff MTHCA_GET(size, outbox, QUERY_DEV_LIM_UAR_ENTRY_SZ_OFFSET); 1128219820Sjeff dev_lim->uar_scratch_entry_sz = size; 1129219820Sjeff 1130219820Sjeff if (mthca_is_memfree(dev)) { 1131219820Sjeff MTHCA_GET(field, outbox, QUERY_DEV_LIM_MAX_SRQ_SZ_OFFSET); 1132219820Sjeff dev_lim->max_srq_sz = 1 << field; 1133219820Sjeff MTHCA_GET(field, outbox, QUERY_DEV_LIM_MAX_QP_SZ_OFFSET); 1134219820Sjeff dev_lim->max_qp_sz = 1 << field; 1135219820Sjeff MTHCA_GET(field, outbox, QUERY_DEV_LIM_RSZ_SRQ_OFFSET); 1136219820Sjeff dev_lim->hca.arbel.resize_srq = field & 1; 1137219820Sjeff MTHCA_GET(field, outbox, QUERY_DEV_LIM_MAX_SG_RQ_OFFSET); 1138219820Sjeff dev_lim->max_sg = min_t(int, field, dev_lim->max_sg); 1139219820Sjeff MTHCA_GET(size, outbox, QUERY_DEV_LIM_MAX_DESC_SZ_RQ_OFFSET); 1140219820Sjeff dev_lim->max_desc_sz = min_t(int, size, dev_lim->max_desc_sz); 1141219820Sjeff MTHCA_GET(size, outbox, QUERY_DEV_LIM_MPT_ENTRY_SZ_OFFSET); 1142219820Sjeff dev_lim->mpt_entry_sz = size; 1143219820Sjeff MTHCA_GET(field, outbox, QUERY_DEV_LIM_PBL_SZ_OFFSET); 1144219820Sjeff dev_lim->hca.arbel.max_pbl_sz = 1 << (field & 0x3f); 1145219820Sjeff MTHCA_GET(dev_lim->hca.arbel.bmme_flags, outbox, 1146219820Sjeff QUERY_DEV_LIM_BMME_FLAGS_OFFSET); 1147219820Sjeff MTHCA_GET(dev_lim->hca.arbel.reserved_lkey, outbox, 1148219820Sjeff QUERY_DEV_LIM_RSVD_LKEY_OFFSET); 1149219820Sjeff MTHCA_GET(field, outbox, QUERY_DEV_LIM_LAMR_OFFSET); 1150219820Sjeff dev_lim->hca.arbel.lam_required = field & 1; 1151219820Sjeff MTHCA_GET(dev_lim->hca.arbel.max_icm_sz, outbox, 1152219820Sjeff QUERY_DEV_LIM_MAX_ICM_SZ_OFFSET); 1153219820Sjeff 1154219820Sjeff if (dev_lim->hca.arbel.bmme_flags & 1) 1155219820Sjeff mthca_dbg(dev, "Base MM extensions: yes " 1156219820Sjeff "(flags %d, max PBL %d, rsvd L_Key %08x)\n", 1157219820Sjeff dev_lim->hca.arbel.bmme_flags, 1158219820Sjeff dev_lim->hca.arbel.max_pbl_sz, 1159219820Sjeff dev_lim->hca.arbel.reserved_lkey); 1160219820Sjeff else 1161219820Sjeff mthca_dbg(dev, "Base MM extensions: no\n"); 1162219820Sjeff 1163219820Sjeff mthca_dbg(dev, "Max ICM size %lld MB\n", 1164219820Sjeff (unsigned long long) dev_lim->hca.arbel.max_icm_sz >> 20); 1165219820Sjeff } else { 1166219820Sjeff MTHCA_GET(field, outbox, QUERY_DEV_LIM_MAX_SRQ_SZ_OFFSET); 1167219820Sjeff dev_lim->max_srq_sz = (1 << field) - 1; 1168219820Sjeff MTHCA_GET(field, outbox, QUERY_DEV_LIM_MAX_QP_SZ_OFFSET); 1169219820Sjeff dev_lim->max_qp_sz = (1 << field) - 1; 1170219820Sjeff MTHCA_GET(field, outbox, QUERY_DEV_LIM_MAX_AV_OFFSET); 1171219820Sjeff dev_lim->hca.tavor.max_avs = 1 << (field & 0x3f); 1172219820Sjeff dev_lim->mpt_entry_sz = MTHCA_MPT_ENTRY_SIZE; 1173219820Sjeff } 1174219820Sjeff 1175219820Sjeff mthca_dbg(dev, "Max QPs: %d, reserved QPs: %d, entry size: %d\n", 1176219820Sjeff dev_lim->max_qps, dev_lim->reserved_qps, dev_lim->qpc_entry_sz); 1177219820Sjeff mthca_dbg(dev, "Max SRQs: %d, reserved SRQs: %d, entry size: %d\n", 1178219820Sjeff dev_lim->max_srqs, dev_lim->reserved_srqs, dev_lim->srq_entry_sz); 1179219820Sjeff mthca_dbg(dev, "Max CQs: %d, reserved CQs: %d, entry size: %d\n", 1180219820Sjeff dev_lim->max_cqs, dev_lim->reserved_cqs, dev_lim->cqc_entry_sz); 1181219820Sjeff mthca_dbg(dev, "Max EQs: %d, reserved EQs: %d, entry size: %d\n", 1182219820Sjeff dev_lim->max_eqs, dev_lim->reserved_eqs, dev_lim->eqc_entry_sz); 1183219820Sjeff mthca_dbg(dev, "reserved MPTs: %d, reserved MTTs: %d\n", 1184219820Sjeff dev_lim->reserved_mrws, dev_lim->reserved_mtts); 1185219820Sjeff mthca_dbg(dev, "Max PDs: %d, reserved PDs: %d, reserved UARs: %d\n", 1186219820Sjeff dev_lim->max_pds, dev_lim->reserved_pds, dev_lim->reserved_uars); 1187219820Sjeff mthca_dbg(dev, "Max QP/MCG: %d, reserved MGMs: %d\n", 1188219820Sjeff dev_lim->max_pds, dev_lim->reserved_mgms); 1189219820Sjeff mthca_dbg(dev, "Max CQEs: %d, max WQEs: %d, max SRQ WQEs: %d\n", 1190219820Sjeff dev_lim->max_cq_sz, dev_lim->max_qp_sz, dev_lim->max_srq_sz); 1191219820Sjeff 1192219820Sjeff mthca_dbg(dev, "Flags: %08x\n", dev_lim->flags); 1193219820Sjeff 1194219820Sjeffout: 1195219820Sjeff mthca_free_mailbox(dev, mailbox); 1196219820Sjeff return err; 1197219820Sjeff} 1198219820Sjeff 1199219820Sjeffstatic void get_board_id(void *vsd, char *board_id) 1200219820Sjeff{ 1201219820Sjeff int i; 1202219820Sjeff 1203219820Sjeff#define VSD_OFFSET_SIG1 0x00 1204219820Sjeff#define VSD_OFFSET_SIG2 0xde 1205219820Sjeff#define VSD_OFFSET_MLX_BOARD_ID 0xd0 1206219820Sjeff#define VSD_OFFSET_TS_BOARD_ID 0x20 1207219820Sjeff 1208219820Sjeff#define VSD_SIGNATURE_TOPSPIN 0x5ad 1209219820Sjeff 1210219820Sjeff memset(board_id, 0, MTHCA_BOARD_ID_LEN); 1211219820Sjeff 1212219820Sjeff if (be16_to_cpup(vsd + VSD_OFFSET_SIG1) == VSD_SIGNATURE_TOPSPIN && 1213219820Sjeff be16_to_cpup(vsd + VSD_OFFSET_SIG2) == VSD_SIGNATURE_TOPSPIN) { 1214219820Sjeff strlcpy(board_id, vsd + VSD_OFFSET_TS_BOARD_ID, MTHCA_BOARD_ID_LEN); 1215219820Sjeff } else { 1216219820Sjeff /* 1217219820Sjeff * The board ID is a string but the firmware byte 1218219820Sjeff * swaps each 4-byte word before passing it back to 1219219820Sjeff * us. Therefore we need to swab it before printing. 1220219820Sjeff */ 1221219820Sjeff for (i = 0; i < 4; ++i) 1222219820Sjeff ((u32 *) board_id)[i] = 1223219820Sjeff swab32(*(u32 *) (vsd + VSD_OFFSET_MLX_BOARD_ID + i * 4)); 1224219820Sjeff } 1225219820Sjeff} 1226219820Sjeff 1227219820Sjeffint mthca_QUERY_ADAPTER(struct mthca_dev *dev, 1228219820Sjeff struct mthca_adapter *adapter, u8 *status) 1229219820Sjeff{ 1230219820Sjeff struct mthca_mailbox *mailbox; 1231219820Sjeff u32 *outbox; 1232219820Sjeff int err; 1233219820Sjeff 1234219820Sjeff#define QUERY_ADAPTER_OUT_SIZE 0x100 1235219820Sjeff#define QUERY_ADAPTER_VENDOR_ID_OFFSET 0x00 1236219820Sjeff#define QUERY_ADAPTER_DEVICE_ID_OFFSET 0x04 1237219820Sjeff#define QUERY_ADAPTER_REVISION_ID_OFFSET 0x08 1238219820Sjeff#define QUERY_ADAPTER_INTA_PIN_OFFSET 0x10 1239219820Sjeff#define QUERY_ADAPTER_VSD_OFFSET 0x20 1240219820Sjeff 1241219820Sjeff mailbox = mthca_alloc_mailbox(dev, GFP_KERNEL); 1242219820Sjeff if (IS_ERR(mailbox)) 1243219820Sjeff return PTR_ERR(mailbox); 1244219820Sjeff outbox = mailbox->buf; 1245219820Sjeff 1246219820Sjeff err = mthca_cmd_box(dev, 0, mailbox->dma, 0, 0, CMD_QUERY_ADAPTER, 1247219820Sjeff CMD_TIME_CLASS_A, status); 1248219820Sjeff 1249219820Sjeff if (err) 1250219820Sjeff goto out; 1251219820Sjeff 1252219820Sjeff if (!mthca_is_memfree(dev)) { 1253219820Sjeff MTHCA_GET(adapter->vendor_id, outbox, 1254219820Sjeff QUERY_ADAPTER_VENDOR_ID_OFFSET); 1255219820Sjeff MTHCA_GET(adapter->device_id, outbox, 1256219820Sjeff QUERY_ADAPTER_DEVICE_ID_OFFSET); 1257219820Sjeff MTHCA_GET(adapter->revision_id, outbox, 1258219820Sjeff QUERY_ADAPTER_REVISION_ID_OFFSET); 1259219820Sjeff } 1260219820Sjeff MTHCA_GET(adapter->inta_pin, outbox, QUERY_ADAPTER_INTA_PIN_OFFSET); 1261219820Sjeff 1262219820Sjeff get_board_id(outbox + QUERY_ADAPTER_VSD_OFFSET / 4, 1263219820Sjeff adapter->board_id); 1264219820Sjeff 1265219820Sjeffout: 1266219820Sjeff mthca_free_mailbox(dev, mailbox); 1267219820Sjeff return err; 1268219820Sjeff} 1269219820Sjeff 1270219820Sjeffint mthca_INIT_HCA(struct mthca_dev *dev, 1271219820Sjeff struct mthca_init_hca_param *param, 1272219820Sjeff u8 *status) 1273219820Sjeff{ 1274219820Sjeff struct mthca_mailbox *mailbox; 1275219820Sjeff __be32 *inbox; 1276219820Sjeff int err; 1277219820Sjeff 1278219820Sjeff#define INIT_HCA_IN_SIZE 0x200 1279219820Sjeff#define INIT_HCA_FLAGS1_OFFSET 0x00c 1280219820Sjeff#define INIT_HCA_FLAGS2_OFFSET 0x014 1281219820Sjeff#define INIT_HCA_QPC_OFFSET 0x020 1282219820Sjeff#define INIT_HCA_QPC_BASE_OFFSET (INIT_HCA_QPC_OFFSET + 0x10) 1283219820Sjeff#define INIT_HCA_LOG_QP_OFFSET (INIT_HCA_QPC_OFFSET + 0x17) 1284219820Sjeff#define INIT_HCA_EEC_BASE_OFFSET (INIT_HCA_QPC_OFFSET + 0x20) 1285219820Sjeff#define INIT_HCA_LOG_EEC_OFFSET (INIT_HCA_QPC_OFFSET + 0x27) 1286219820Sjeff#define INIT_HCA_SRQC_BASE_OFFSET (INIT_HCA_QPC_OFFSET + 0x28) 1287219820Sjeff#define INIT_HCA_LOG_SRQ_OFFSET (INIT_HCA_QPC_OFFSET + 0x2f) 1288219820Sjeff#define INIT_HCA_CQC_BASE_OFFSET (INIT_HCA_QPC_OFFSET + 0x30) 1289219820Sjeff#define INIT_HCA_LOG_CQ_OFFSET (INIT_HCA_QPC_OFFSET + 0x37) 1290219820Sjeff#define INIT_HCA_EQPC_BASE_OFFSET (INIT_HCA_QPC_OFFSET + 0x40) 1291219820Sjeff#define INIT_HCA_EEEC_BASE_OFFSET (INIT_HCA_QPC_OFFSET + 0x50) 1292219820Sjeff#define INIT_HCA_EQC_BASE_OFFSET (INIT_HCA_QPC_OFFSET + 0x60) 1293219820Sjeff#define INIT_HCA_LOG_EQ_OFFSET (INIT_HCA_QPC_OFFSET + 0x67) 1294219820Sjeff#define INIT_HCA_RDB_BASE_OFFSET (INIT_HCA_QPC_OFFSET + 0x70) 1295219820Sjeff#define INIT_HCA_UDAV_OFFSET 0x0b0 1296219820Sjeff#define INIT_HCA_UDAV_LKEY_OFFSET (INIT_HCA_UDAV_OFFSET + 0x0) 1297219820Sjeff#define INIT_HCA_UDAV_PD_OFFSET (INIT_HCA_UDAV_OFFSET + 0x4) 1298219820Sjeff#define INIT_HCA_MCAST_OFFSET 0x0c0 1299219820Sjeff#define INIT_HCA_MC_BASE_OFFSET (INIT_HCA_MCAST_OFFSET + 0x00) 1300219820Sjeff#define INIT_HCA_LOG_MC_ENTRY_SZ_OFFSET (INIT_HCA_MCAST_OFFSET + 0x12) 1301219820Sjeff#define INIT_HCA_MC_HASH_SZ_OFFSET (INIT_HCA_MCAST_OFFSET + 0x16) 1302219820Sjeff#define INIT_HCA_LOG_MC_TABLE_SZ_OFFSET (INIT_HCA_MCAST_OFFSET + 0x1b) 1303219820Sjeff#define INIT_HCA_TPT_OFFSET 0x0f0 1304219820Sjeff#define INIT_HCA_MPT_BASE_OFFSET (INIT_HCA_TPT_OFFSET + 0x00) 1305219820Sjeff#define INIT_HCA_MTT_SEG_SZ_OFFSET (INIT_HCA_TPT_OFFSET + 0x09) 1306219820Sjeff#define INIT_HCA_LOG_MPT_SZ_OFFSET (INIT_HCA_TPT_OFFSET + 0x0b) 1307219820Sjeff#define INIT_HCA_MTT_BASE_OFFSET (INIT_HCA_TPT_OFFSET + 0x10) 1308219820Sjeff#define INIT_HCA_UAR_OFFSET 0x120 1309219820Sjeff#define INIT_HCA_UAR_BASE_OFFSET (INIT_HCA_UAR_OFFSET + 0x00) 1310219820Sjeff#define INIT_HCA_UARC_SZ_OFFSET (INIT_HCA_UAR_OFFSET + 0x09) 1311219820Sjeff#define INIT_HCA_LOG_UAR_SZ_OFFSET (INIT_HCA_UAR_OFFSET + 0x0a) 1312219820Sjeff#define INIT_HCA_UAR_PAGE_SZ_OFFSET (INIT_HCA_UAR_OFFSET + 0x0b) 1313219820Sjeff#define INIT_HCA_UAR_SCATCH_BASE_OFFSET (INIT_HCA_UAR_OFFSET + 0x10) 1314219820Sjeff#define INIT_HCA_UAR_CTX_BASE_OFFSET (INIT_HCA_UAR_OFFSET + 0x18) 1315219820Sjeff 1316219820Sjeff mailbox = mthca_alloc_mailbox(dev, GFP_KERNEL); 1317219820Sjeff if (IS_ERR(mailbox)) 1318219820Sjeff return PTR_ERR(mailbox); 1319219820Sjeff inbox = mailbox->buf; 1320219820Sjeff 1321219820Sjeff memset(inbox, 0, INIT_HCA_IN_SIZE); 1322219820Sjeff 1323219820Sjeff if (dev->mthca_flags & MTHCA_FLAG_SINAI_OPT) 1324219820Sjeff MTHCA_PUT(inbox, 0x1, INIT_HCA_FLAGS1_OFFSET); 1325219820Sjeff 1326219820Sjeff#if defined(__LITTLE_ENDIAN) 1327219820Sjeff *(inbox + INIT_HCA_FLAGS2_OFFSET / 4) &= ~cpu_to_be32(1 << 1); 1328219820Sjeff#elif defined(__BIG_ENDIAN) 1329219820Sjeff *(inbox + INIT_HCA_FLAGS2_OFFSET / 4) |= cpu_to_be32(1 << 1); 1330219820Sjeff#else 1331219820Sjeff#error Host endianness not defined 1332219820Sjeff#endif 1333219820Sjeff /* Check port for UD address vector: */ 1334219820Sjeff *(inbox + INIT_HCA_FLAGS2_OFFSET / 4) |= cpu_to_be32(1); 1335219820Sjeff 1336219820Sjeff /* Enable IPoIB checksumming if we can: */ 1337219820Sjeff if (dev->device_cap_flags & IB_DEVICE_UD_IP_CSUM) 1338219820Sjeff *(inbox + INIT_HCA_FLAGS2_OFFSET / 4) |= cpu_to_be32(7 << 3); 1339219820Sjeff 1340219820Sjeff /* We leave wqe_quota, responder_exu, etc as 0 (default) */ 1341219820Sjeff 1342219820Sjeff /* QPC/EEC/CQC/EQC/RDB attributes */ 1343219820Sjeff 1344219820Sjeff MTHCA_PUT(inbox, param->qpc_base, INIT_HCA_QPC_BASE_OFFSET); 1345219820Sjeff MTHCA_PUT(inbox, param->log_num_qps, INIT_HCA_LOG_QP_OFFSET); 1346219820Sjeff MTHCA_PUT(inbox, param->eec_base, INIT_HCA_EEC_BASE_OFFSET); 1347219820Sjeff MTHCA_PUT(inbox, param->log_num_eecs, INIT_HCA_LOG_EEC_OFFSET); 1348219820Sjeff MTHCA_PUT(inbox, param->srqc_base, INIT_HCA_SRQC_BASE_OFFSET); 1349219820Sjeff MTHCA_PUT(inbox, param->log_num_srqs, INIT_HCA_LOG_SRQ_OFFSET); 1350219820Sjeff MTHCA_PUT(inbox, param->cqc_base, INIT_HCA_CQC_BASE_OFFSET); 1351219820Sjeff MTHCA_PUT(inbox, param->log_num_cqs, INIT_HCA_LOG_CQ_OFFSET); 1352219820Sjeff MTHCA_PUT(inbox, param->eqpc_base, INIT_HCA_EQPC_BASE_OFFSET); 1353219820Sjeff MTHCA_PUT(inbox, param->eeec_base, INIT_HCA_EEEC_BASE_OFFSET); 1354219820Sjeff MTHCA_PUT(inbox, param->eqc_base, INIT_HCA_EQC_BASE_OFFSET); 1355219820Sjeff MTHCA_PUT(inbox, param->log_num_eqs, INIT_HCA_LOG_EQ_OFFSET); 1356219820Sjeff MTHCA_PUT(inbox, param->rdb_base, INIT_HCA_RDB_BASE_OFFSET); 1357219820Sjeff 1358219820Sjeff /* UD AV attributes */ 1359219820Sjeff 1360219820Sjeff /* multicast attributes */ 1361219820Sjeff 1362219820Sjeff MTHCA_PUT(inbox, param->mc_base, INIT_HCA_MC_BASE_OFFSET); 1363219820Sjeff MTHCA_PUT(inbox, param->log_mc_entry_sz, INIT_HCA_LOG_MC_ENTRY_SZ_OFFSET); 1364219820Sjeff MTHCA_PUT(inbox, param->mc_hash_sz, INIT_HCA_MC_HASH_SZ_OFFSET); 1365219820Sjeff MTHCA_PUT(inbox, param->log_mc_table_sz, INIT_HCA_LOG_MC_TABLE_SZ_OFFSET); 1366219820Sjeff 1367219820Sjeff /* TPT attributes */ 1368219820Sjeff 1369219820Sjeff MTHCA_PUT(inbox, param->mpt_base, INIT_HCA_MPT_BASE_OFFSET); 1370219820Sjeff if (!mthca_is_memfree(dev)) 1371219820Sjeff MTHCA_PUT(inbox, param->mtt_seg_sz, INIT_HCA_MTT_SEG_SZ_OFFSET); 1372219820Sjeff MTHCA_PUT(inbox, param->log_mpt_sz, INIT_HCA_LOG_MPT_SZ_OFFSET); 1373219820Sjeff MTHCA_PUT(inbox, param->mtt_base, INIT_HCA_MTT_BASE_OFFSET); 1374219820Sjeff 1375219820Sjeff /* UAR attributes */ 1376219820Sjeff { 1377219820Sjeff u8 uar_page_sz = PAGE_SHIFT - 12; 1378219820Sjeff MTHCA_PUT(inbox, uar_page_sz, INIT_HCA_UAR_PAGE_SZ_OFFSET); 1379219820Sjeff } 1380219820Sjeff 1381219820Sjeff MTHCA_PUT(inbox, param->uar_scratch_base, INIT_HCA_UAR_SCATCH_BASE_OFFSET); 1382219820Sjeff 1383219820Sjeff if (mthca_is_memfree(dev)) { 1384219820Sjeff MTHCA_PUT(inbox, param->log_uarc_sz, INIT_HCA_UARC_SZ_OFFSET); 1385219820Sjeff MTHCA_PUT(inbox, param->log_uar_sz, INIT_HCA_LOG_UAR_SZ_OFFSET); 1386219820Sjeff MTHCA_PUT(inbox, param->uarc_base, INIT_HCA_UAR_CTX_BASE_OFFSET); 1387219820Sjeff } 1388219820Sjeff 1389219820Sjeff err = mthca_cmd(dev, mailbox->dma, 0, 0, CMD_INIT_HCA, CMD_TIME_CLASS_D, status); 1390219820Sjeff 1391219820Sjeff mthca_free_mailbox(dev, mailbox); 1392219820Sjeff return err; 1393219820Sjeff} 1394219820Sjeff 1395219820Sjeffint mthca_INIT_IB(struct mthca_dev *dev, 1396219820Sjeff struct mthca_init_ib_param *param, 1397219820Sjeff int port, u8 *status) 1398219820Sjeff{ 1399219820Sjeff struct mthca_mailbox *mailbox; 1400219820Sjeff u32 *inbox; 1401219820Sjeff int err; 1402219820Sjeff u32 flags; 1403219820Sjeff 1404219820Sjeff#define INIT_IB_IN_SIZE 56 1405219820Sjeff#define INIT_IB_FLAGS_OFFSET 0x00 1406219820Sjeff#define INIT_IB_FLAG_SIG (1 << 18) 1407219820Sjeff#define INIT_IB_FLAG_NG (1 << 17) 1408219820Sjeff#define INIT_IB_FLAG_G0 (1 << 16) 1409219820Sjeff#define INIT_IB_VL_SHIFT 4 1410219820Sjeff#define INIT_IB_PORT_WIDTH_SHIFT 8 1411219820Sjeff#define INIT_IB_MTU_SHIFT 12 1412219820Sjeff#define INIT_IB_MAX_GID_OFFSET 0x06 1413219820Sjeff#define INIT_IB_MAX_PKEY_OFFSET 0x0a 1414219820Sjeff#define INIT_IB_GUID0_OFFSET 0x10 1415219820Sjeff#define INIT_IB_NODE_GUID_OFFSET 0x18 1416219820Sjeff#define INIT_IB_SI_GUID_OFFSET 0x20 1417219820Sjeff 1418219820Sjeff mailbox = mthca_alloc_mailbox(dev, GFP_KERNEL); 1419219820Sjeff if (IS_ERR(mailbox)) 1420219820Sjeff return PTR_ERR(mailbox); 1421219820Sjeff inbox = mailbox->buf; 1422219820Sjeff 1423219820Sjeff memset(inbox, 0, INIT_IB_IN_SIZE); 1424219820Sjeff 1425219820Sjeff flags = 0; 1426219820Sjeff flags |= param->set_guid0 ? INIT_IB_FLAG_G0 : 0; 1427219820Sjeff flags |= param->set_node_guid ? INIT_IB_FLAG_NG : 0; 1428219820Sjeff flags |= param->set_si_guid ? INIT_IB_FLAG_SIG : 0; 1429219820Sjeff flags |= param->vl_cap << INIT_IB_VL_SHIFT; 1430219820Sjeff flags |= param->port_width << INIT_IB_PORT_WIDTH_SHIFT; 1431219820Sjeff flags |= param->mtu_cap << INIT_IB_MTU_SHIFT; 1432219820Sjeff MTHCA_PUT(inbox, flags, INIT_IB_FLAGS_OFFSET); 1433219820Sjeff 1434219820Sjeff MTHCA_PUT(inbox, param->gid_cap, INIT_IB_MAX_GID_OFFSET); 1435219820Sjeff MTHCA_PUT(inbox, param->pkey_cap, INIT_IB_MAX_PKEY_OFFSET); 1436219820Sjeff MTHCA_PUT(inbox, param->guid0, INIT_IB_GUID0_OFFSET); 1437219820Sjeff MTHCA_PUT(inbox, param->node_guid, INIT_IB_NODE_GUID_OFFSET); 1438219820Sjeff MTHCA_PUT(inbox, param->si_guid, INIT_IB_SI_GUID_OFFSET); 1439219820Sjeff 1440219820Sjeff err = mthca_cmd(dev, mailbox->dma, port, 0, CMD_INIT_IB, 1441219820Sjeff CMD_TIME_CLASS_A, status); 1442219820Sjeff 1443219820Sjeff mthca_free_mailbox(dev, mailbox); 1444219820Sjeff return err; 1445219820Sjeff} 1446219820Sjeff 1447219820Sjeffint mthca_CLOSE_IB(struct mthca_dev *dev, int port, u8 *status) 1448219820Sjeff{ 1449219820Sjeff return mthca_cmd(dev, 0, port, 0, CMD_CLOSE_IB, CMD_TIME_CLASS_A, status); 1450219820Sjeff} 1451219820Sjeff 1452219820Sjeffint mthca_CLOSE_HCA(struct mthca_dev *dev, int panic, u8 *status) 1453219820Sjeff{ 1454219820Sjeff return mthca_cmd(dev, 0, 0, panic, CMD_CLOSE_HCA, CMD_TIME_CLASS_C, status); 1455219820Sjeff} 1456219820Sjeff 1457219820Sjeffint mthca_SET_IB(struct mthca_dev *dev, struct mthca_set_ib_param *param, 1458219820Sjeff int port, u8 *status) 1459219820Sjeff{ 1460219820Sjeff struct mthca_mailbox *mailbox; 1461219820Sjeff u32 *inbox; 1462219820Sjeff int err; 1463219820Sjeff u32 flags = 0; 1464219820Sjeff 1465219820Sjeff#define SET_IB_IN_SIZE 0x40 1466219820Sjeff#define SET_IB_FLAGS_OFFSET 0x00 1467219820Sjeff#define SET_IB_FLAG_SIG (1 << 18) 1468219820Sjeff#define SET_IB_FLAG_RQK (1 << 0) 1469219820Sjeff#define SET_IB_CAP_MASK_OFFSET 0x04 1470219820Sjeff#define SET_IB_SI_GUID_OFFSET 0x08 1471219820Sjeff 1472219820Sjeff mailbox = mthca_alloc_mailbox(dev, GFP_KERNEL); 1473219820Sjeff if (IS_ERR(mailbox)) 1474219820Sjeff return PTR_ERR(mailbox); 1475219820Sjeff inbox = mailbox->buf; 1476219820Sjeff 1477219820Sjeff memset(inbox, 0, SET_IB_IN_SIZE); 1478219820Sjeff 1479219820Sjeff flags |= param->set_si_guid ? SET_IB_FLAG_SIG : 0; 1480219820Sjeff flags |= param->reset_qkey_viol ? SET_IB_FLAG_RQK : 0; 1481219820Sjeff MTHCA_PUT(inbox, flags, SET_IB_FLAGS_OFFSET); 1482219820Sjeff 1483219820Sjeff MTHCA_PUT(inbox, param->cap_mask, SET_IB_CAP_MASK_OFFSET); 1484219820Sjeff MTHCA_PUT(inbox, param->si_guid, SET_IB_SI_GUID_OFFSET); 1485219820Sjeff 1486219820Sjeff err = mthca_cmd(dev, mailbox->dma, port, 0, CMD_SET_IB, 1487219820Sjeff CMD_TIME_CLASS_B, status); 1488219820Sjeff 1489219820Sjeff mthca_free_mailbox(dev, mailbox); 1490219820Sjeff return err; 1491219820Sjeff} 1492219820Sjeff 1493219820Sjeffint mthca_MAP_ICM(struct mthca_dev *dev, struct mthca_icm *icm, u64 virt, u8 *status) 1494219820Sjeff{ 1495219820Sjeff return mthca_map_cmd(dev, CMD_MAP_ICM, icm, virt, status); 1496219820Sjeff} 1497219820Sjeff 1498219820Sjeffint mthca_MAP_ICM_page(struct mthca_dev *dev, u64 dma_addr, u64 virt, u8 *status) 1499219820Sjeff{ 1500219820Sjeff struct mthca_mailbox *mailbox; 1501219820Sjeff __be64 *inbox; 1502219820Sjeff int err; 1503219820Sjeff 1504219820Sjeff mailbox = mthca_alloc_mailbox(dev, GFP_KERNEL); 1505219820Sjeff if (IS_ERR(mailbox)) 1506219820Sjeff return PTR_ERR(mailbox); 1507219820Sjeff inbox = mailbox->buf; 1508219820Sjeff 1509219820Sjeff inbox[0] = cpu_to_be64(virt); 1510219820Sjeff inbox[1] = cpu_to_be64(dma_addr); 1511219820Sjeff 1512219820Sjeff err = mthca_cmd(dev, mailbox->dma, 1, 0, CMD_MAP_ICM, 1513219820Sjeff CMD_TIME_CLASS_B, status); 1514219820Sjeff 1515219820Sjeff mthca_free_mailbox(dev, mailbox); 1516219820Sjeff 1517219820Sjeff if (!err) 1518219820Sjeff mthca_dbg(dev, "Mapped page at %llx to %llx for ICM.\n", 1519219820Sjeff (unsigned long long) dma_addr, (unsigned long long) virt); 1520219820Sjeff 1521219820Sjeff return err; 1522219820Sjeff} 1523219820Sjeff 1524219820Sjeffint mthca_UNMAP_ICM(struct mthca_dev *dev, u64 virt, u32 page_count, u8 *status) 1525219820Sjeff{ 1526219820Sjeff mthca_dbg(dev, "Unmapping %d pages at %llx from ICM.\n", 1527219820Sjeff page_count, (unsigned long long) virt); 1528219820Sjeff 1529219820Sjeff return mthca_cmd(dev, virt, page_count, 0, CMD_UNMAP_ICM, CMD_TIME_CLASS_B, status); 1530219820Sjeff} 1531219820Sjeff 1532219820Sjeffint mthca_MAP_ICM_AUX(struct mthca_dev *dev, struct mthca_icm *icm, u8 *status) 1533219820Sjeff{ 1534219820Sjeff return mthca_map_cmd(dev, CMD_MAP_ICM_AUX, icm, -1, status); 1535219820Sjeff} 1536219820Sjeff 1537219820Sjeffint mthca_UNMAP_ICM_AUX(struct mthca_dev *dev, u8 *status) 1538219820Sjeff{ 1539219820Sjeff return mthca_cmd(dev, 0, 0, 0, CMD_UNMAP_ICM_AUX, CMD_TIME_CLASS_B, status); 1540219820Sjeff} 1541219820Sjeff 1542219820Sjeffint mthca_SET_ICM_SIZE(struct mthca_dev *dev, u64 icm_size, u64 *aux_pages, 1543219820Sjeff u8 *status) 1544219820Sjeff{ 1545219820Sjeff int ret = mthca_cmd_imm(dev, icm_size, aux_pages, 0, 0, CMD_SET_ICM_SIZE, 1546219820Sjeff CMD_TIME_CLASS_A, status); 1547219820Sjeff 1548219820Sjeff if (ret || status) 1549219820Sjeff return ret; 1550219820Sjeff 1551219820Sjeff /* 1552219820Sjeff * Round up number of system pages needed in case 1553219820Sjeff * MTHCA_ICM_PAGE_SIZE < PAGE_SIZE. 1554219820Sjeff */ 1555219820Sjeff *aux_pages = ALIGN(*aux_pages, PAGE_SIZE / MTHCA_ICM_PAGE_SIZE) >> 1556219820Sjeff (PAGE_SHIFT - MTHCA_ICM_PAGE_SHIFT); 1557219820Sjeff 1558219820Sjeff return 0; 1559219820Sjeff} 1560219820Sjeff 1561219820Sjeffint mthca_SW2HW_MPT(struct mthca_dev *dev, struct mthca_mailbox *mailbox, 1562219820Sjeff int mpt_index, u8 *status) 1563219820Sjeff{ 1564219820Sjeff return mthca_cmd(dev, mailbox->dma, mpt_index, 0, CMD_SW2HW_MPT, 1565219820Sjeff CMD_TIME_CLASS_B, status); 1566219820Sjeff} 1567219820Sjeff 1568219820Sjeffint mthca_HW2SW_MPT(struct mthca_dev *dev, struct mthca_mailbox *mailbox, 1569219820Sjeff int mpt_index, u8 *status) 1570219820Sjeff{ 1571219820Sjeff return mthca_cmd_box(dev, 0, mailbox ? mailbox->dma : 0, mpt_index, 1572219820Sjeff !mailbox, CMD_HW2SW_MPT, 1573219820Sjeff CMD_TIME_CLASS_B, status); 1574219820Sjeff} 1575219820Sjeff 1576219820Sjeffint mthca_WRITE_MTT(struct mthca_dev *dev, struct mthca_mailbox *mailbox, 1577219820Sjeff int num_mtt, u8 *status) 1578219820Sjeff{ 1579219820Sjeff return mthca_cmd(dev, mailbox->dma, num_mtt, 0, CMD_WRITE_MTT, 1580219820Sjeff CMD_TIME_CLASS_B, status); 1581219820Sjeff} 1582219820Sjeff 1583219820Sjeffint mthca_SYNC_TPT(struct mthca_dev *dev, u8 *status) 1584219820Sjeff{ 1585219820Sjeff return mthca_cmd(dev, 0, 0, 0, CMD_SYNC_TPT, CMD_TIME_CLASS_B, status); 1586219820Sjeff} 1587219820Sjeff 1588219820Sjeffint mthca_MAP_EQ(struct mthca_dev *dev, u64 event_mask, int unmap, 1589219820Sjeff int eq_num, u8 *status) 1590219820Sjeff{ 1591219820Sjeff mthca_dbg(dev, "%s mask %016llx for eqn %d\n", 1592219820Sjeff unmap ? "Clearing" : "Setting", 1593219820Sjeff (unsigned long long) event_mask, eq_num); 1594219820Sjeff return mthca_cmd(dev, event_mask, (unmap << 31) | eq_num, 1595219820Sjeff 0, CMD_MAP_EQ, CMD_TIME_CLASS_B, status); 1596219820Sjeff} 1597219820Sjeff 1598219820Sjeffint mthca_SW2HW_EQ(struct mthca_dev *dev, struct mthca_mailbox *mailbox, 1599219820Sjeff int eq_num, u8 *status) 1600219820Sjeff{ 1601219820Sjeff return mthca_cmd(dev, mailbox->dma, eq_num, 0, CMD_SW2HW_EQ, 1602219820Sjeff CMD_TIME_CLASS_A, status); 1603219820Sjeff} 1604219820Sjeff 1605219820Sjeffint mthca_HW2SW_EQ(struct mthca_dev *dev, struct mthca_mailbox *mailbox, 1606219820Sjeff int eq_num, u8 *status) 1607219820Sjeff{ 1608219820Sjeff return mthca_cmd_box(dev, 0, mailbox->dma, eq_num, 0, 1609219820Sjeff CMD_HW2SW_EQ, 1610219820Sjeff CMD_TIME_CLASS_A, status); 1611219820Sjeff} 1612219820Sjeff 1613219820Sjeffint mthca_SW2HW_CQ(struct mthca_dev *dev, struct mthca_mailbox *mailbox, 1614219820Sjeff int cq_num, u8 *status) 1615219820Sjeff{ 1616219820Sjeff return mthca_cmd(dev, mailbox->dma, cq_num, 0, CMD_SW2HW_CQ, 1617219820Sjeff CMD_TIME_CLASS_A, status); 1618219820Sjeff} 1619219820Sjeff 1620219820Sjeffint mthca_HW2SW_CQ(struct mthca_dev *dev, struct mthca_mailbox *mailbox, 1621219820Sjeff int cq_num, u8 *status) 1622219820Sjeff{ 1623219820Sjeff return mthca_cmd_box(dev, 0, mailbox->dma, cq_num, 0, 1624219820Sjeff CMD_HW2SW_CQ, 1625219820Sjeff CMD_TIME_CLASS_A, status); 1626219820Sjeff} 1627219820Sjeff 1628219820Sjeffint mthca_RESIZE_CQ(struct mthca_dev *dev, int cq_num, u32 lkey, u8 log_size, 1629219820Sjeff u8 *status) 1630219820Sjeff{ 1631219820Sjeff struct mthca_mailbox *mailbox; 1632219820Sjeff __be32 *inbox; 1633219820Sjeff int err; 1634219820Sjeff 1635219820Sjeff#define RESIZE_CQ_IN_SIZE 0x40 1636219820Sjeff#define RESIZE_CQ_LOG_SIZE_OFFSET 0x0c 1637219820Sjeff#define RESIZE_CQ_LKEY_OFFSET 0x1c 1638219820Sjeff 1639219820Sjeff mailbox = mthca_alloc_mailbox(dev, GFP_KERNEL); 1640219820Sjeff if (IS_ERR(mailbox)) 1641219820Sjeff return PTR_ERR(mailbox); 1642219820Sjeff inbox = mailbox->buf; 1643219820Sjeff 1644219820Sjeff memset(inbox, 0, RESIZE_CQ_IN_SIZE); 1645219820Sjeff /* 1646219820Sjeff * Leave start address fields zeroed out -- mthca assumes that 1647219820Sjeff * MRs for CQs always start at virtual address 0. 1648219820Sjeff */ 1649219820Sjeff MTHCA_PUT(inbox, log_size, RESIZE_CQ_LOG_SIZE_OFFSET); 1650219820Sjeff MTHCA_PUT(inbox, lkey, RESIZE_CQ_LKEY_OFFSET); 1651219820Sjeff 1652219820Sjeff err = mthca_cmd(dev, mailbox->dma, cq_num, 1, CMD_RESIZE_CQ, 1653219820Sjeff CMD_TIME_CLASS_B, status); 1654219820Sjeff 1655219820Sjeff mthca_free_mailbox(dev, mailbox); 1656219820Sjeff return err; 1657219820Sjeff} 1658219820Sjeff 1659219820Sjeffint mthca_SW2HW_SRQ(struct mthca_dev *dev, struct mthca_mailbox *mailbox, 1660219820Sjeff int srq_num, u8 *status) 1661219820Sjeff{ 1662219820Sjeff return mthca_cmd(dev, mailbox->dma, srq_num, 0, CMD_SW2HW_SRQ, 1663219820Sjeff CMD_TIME_CLASS_A, status); 1664219820Sjeff} 1665219820Sjeff 1666219820Sjeffint mthca_HW2SW_SRQ(struct mthca_dev *dev, struct mthca_mailbox *mailbox, 1667219820Sjeff int srq_num, u8 *status) 1668219820Sjeff{ 1669219820Sjeff return mthca_cmd_box(dev, 0, mailbox->dma, srq_num, 0, 1670219820Sjeff CMD_HW2SW_SRQ, 1671219820Sjeff CMD_TIME_CLASS_A, status); 1672219820Sjeff} 1673219820Sjeff 1674219820Sjeffint mthca_QUERY_SRQ(struct mthca_dev *dev, u32 num, 1675219820Sjeff struct mthca_mailbox *mailbox, u8 *status) 1676219820Sjeff{ 1677219820Sjeff return mthca_cmd_box(dev, 0, mailbox->dma, num, 0, 1678219820Sjeff CMD_QUERY_SRQ, CMD_TIME_CLASS_A, status); 1679219820Sjeff} 1680219820Sjeff 1681219820Sjeffint mthca_ARM_SRQ(struct mthca_dev *dev, int srq_num, int limit, u8 *status) 1682219820Sjeff{ 1683219820Sjeff return mthca_cmd(dev, limit, srq_num, 0, CMD_ARM_SRQ, 1684219820Sjeff CMD_TIME_CLASS_B, status); 1685219820Sjeff} 1686219820Sjeff 1687219820Sjeffint mthca_MODIFY_QP(struct mthca_dev *dev, enum ib_qp_state cur, 1688219820Sjeff enum ib_qp_state next, u32 num, int is_ee, 1689219820Sjeff struct mthca_mailbox *mailbox, u32 optmask, 1690219820Sjeff u8 *status) 1691219820Sjeff{ 1692219820Sjeff static const u16 op[IB_QPS_ERR + 1][IB_QPS_ERR + 1] = { 1693219820Sjeff [IB_QPS_RESET] = { 1694219820Sjeff [IB_QPS_RESET] = CMD_ERR2RST_QPEE, 1695219820Sjeff [IB_QPS_ERR] = CMD_2ERR_QPEE, 1696219820Sjeff [IB_QPS_INIT] = CMD_RST2INIT_QPEE, 1697219820Sjeff }, 1698219820Sjeff [IB_QPS_INIT] = { 1699219820Sjeff [IB_QPS_RESET] = CMD_ERR2RST_QPEE, 1700219820Sjeff [IB_QPS_ERR] = CMD_2ERR_QPEE, 1701219820Sjeff [IB_QPS_INIT] = CMD_INIT2INIT_QPEE, 1702219820Sjeff [IB_QPS_RTR] = CMD_INIT2RTR_QPEE, 1703219820Sjeff }, 1704219820Sjeff [IB_QPS_RTR] = { 1705219820Sjeff [IB_QPS_RESET] = CMD_ERR2RST_QPEE, 1706219820Sjeff [IB_QPS_ERR] = CMD_2ERR_QPEE, 1707219820Sjeff [IB_QPS_RTS] = CMD_RTR2RTS_QPEE, 1708219820Sjeff }, 1709219820Sjeff [IB_QPS_RTS] = { 1710219820Sjeff [IB_QPS_RESET] = CMD_ERR2RST_QPEE, 1711219820Sjeff [IB_QPS_ERR] = CMD_2ERR_QPEE, 1712219820Sjeff [IB_QPS_RTS] = CMD_RTS2RTS_QPEE, 1713219820Sjeff [IB_QPS_SQD] = CMD_RTS2SQD_QPEE, 1714219820Sjeff }, 1715219820Sjeff [IB_QPS_SQD] = { 1716219820Sjeff [IB_QPS_RESET] = CMD_ERR2RST_QPEE, 1717219820Sjeff [IB_QPS_ERR] = CMD_2ERR_QPEE, 1718219820Sjeff [IB_QPS_RTS] = CMD_SQD2RTS_QPEE, 1719219820Sjeff [IB_QPS_SQD] = CMD_SQD2SQD_QPEE, 1720219820Sjeff }, 1721219820Sjeff [IB_QPS_SQE] = { 1722219820Sjeff [IB_QPS_RESET] = CMD_ERR2RST_QPEE, 1723219820Sjeff [IB_QPS_ERR] = CMD_2ERR_QPEE, 1724219820Sjeff [IB_QPS_RTS] = CMD_SQERR2RTS_QPEE, 1725219820Sjeff }, 1726219820Sjeff [IB_QPS_ERR] = { 1727219820Sjeff [IB_QPS_RESET] = CMD_ERR2RST_QPEE, 1728219820Sjeff [IB_QPS_ERR] = CMD_2ERR_QPEE, 1729219820Sjeff } 1730219820Sjeff }; 1731219820Sjeff 1732219820Sjeff u8 op_mod = 0; 1733219820Sjeff int my_mailbox = 0; 1734219820Sjeff int err; 1735219820Sjeff 1736219820Sjeff if (op[cur][next] == CMD_ERR2RST_QPEE) { 1737219820Sjeff op_mod = 3; /* don't write outbox, any->reset */ 1738219820Sjeff 1739219820Sjeff /* For debugging */ 1740219820Sjeff if (!mailbox) { 1741219820Sjeff mailbox = mthca_alloc_mailbox(dev, GFP_KERNEL); 1742219820Sjeff if (!IS_ERR(mailbox)) { 1743219820Sjeff my_mailbox = 1; 1744219820Sjeff op_mod = 2; /* write outbox, any->reset */ 1745219820Sjeff } else 1746219820Sjeff mailbox = NULL; 1747219820Sjeff } 1748219820Sjeff 1749219820Sjeff err = mthca_cmd_box(dev, 0, mailbox ? mailbox->dma : 0, 1750219820Sjeff (!!is_ee << 24) | num, op_mod, 1751219820Sjeff op[cur][next], CMD_TIME_CLASS_C, status); 1752219820Sjeff 1753219820Sjeff if (0 && mailbox) { 1754219820Sjeff int i; 1755219820Sjeff mthca_dbg(dev, "Dumping QP context:\n"); 1756219820Sjeff printk(" %08x\n", be32_to_cpup(mailbox->buf)); 1757219820Sjeff for (i = 0; i < 0x100 / 4; ++i) { 1758219820Sjeff if (i % 8 == 0) 1759219820Sjeff printk("[%02x] ", i * 4); 1760219820Sjeff printk(" %08x", 1761219820Sjeff be32_to_cpu(((__be32 *) mailbox->buf)[i + 2])); 1762219820Sjeff if ((i + 1) % 8 == 0) 1763219820Sjeff printk("\n"); 1764219820Sjeff } 1765219820Sjeff } 1766219820Sjeff 1767219820Sjeff if (my_mailbox) 1768219820Sjeff mthca_free_mailbox(dev, mailbox); 1769219820Sjeff } else { 1770219820Sjeff if (0) { 1771219820Sjeff int i; 1772219820Sjeff mthca_dbg(dev, "Dumping QP context:\n"); 1773219820Sjeff printk(" opt param mask: %08x\n", be32_to_cpup(mailbox->buf)); 1774219820Sjeff for (i = 0; i < 0x100 / 4; ++i) { 1775219820Sjeff if (i % 8 == 0) 1776219820Sjeff printk(" [%02x] ", i * 4); 1777219820Sjeff printk(" %08x", 1778219820Sjeff be32_to_cpu(((__be32 *) mailbox->buf)[i + 2])); 1779219820Sjeff if ((i + 1) % 8 == 0) 1780219820Sjeff printk("\n"); 1781219820Sjeff } 1782219820Sjeff } 1783219820Sjeff 1784219820Sjeff err = mthca_cmd(dev, mailbox->dma, optmask | (!!is_ee << 24) | num, 1785219820Sjeff op_mod, op[cur][next], CMD_TIME_CLASS_C, status); 1786219820Sjeff } 1787219820Sjeff 1788219820Sjeff return err; 1789219820Sjeff} 1790219820Sjeff 1791219820Sjeffint mthca_QUERY_QP(struct mthca_dev *dev, u32 num, int is_ee, 1792219820Sjeff struct mthca_mailbox *mailbox, u8 *status) 1793219820Sjeff{ 1794219820Sjeff return mthca_cmd_box(dev, 0, mailbox->dma, (!!is_ee << 24) | num, 0, 1795219820Sjeff CMD_QUERY_QPEE, CMD_TIME_CLASS_A, status); 1796219820Sjeff} 1797219820Sjeff 1798219820Sjeffint mthca_CONF_SPECIAL_QP(struct mthca_dev *dev, int type, u32 qpn, 1799219820Sjeff u8 *status) 1800219820Sjeff{ 1801219820Sjeff u8 op_mod; 1802219820Sjeff 1803219820Sjeff switch (type) { 1804219820Sjeff case IB_QPT_SMI: 1805219820Sjeff op_mod = 0; 1806219820Sjeff break; 1807219820Sjeff case IB_QPT_GSI: 1808219820Sjeff op_mod = 1; 1809219820Sjeff break; 1810219820Sjeff case IB_QPT_RAW_IPV6: 1811219820Sjeff op_mod = 2; 1812219820Sjeff break; 1813255932Salfred case IB_QPT_RAW_ETHERTYPE: 1814219820Sjeff op_mod = 3; 1815219820Sjeff break; 1816219820Sjeff default: 1817219820Sjeff return -EINVAL; 1818219820Sjeff } 1819219820Sjeff 1820219820Sjeff return mthca_cmd(dev, 0, qpn, op_mod, CMD_CONF_SPECIAL_QP, 1821219820Sjeff CMD_TIME_CLASS_B, status); 1822219820Sjeff} 1823219820Sjeff 1824219820Sjeffint mthca_MAD_IFC(struct mthca_dev *dev, int ignore_mkey, int ignore_bkey, 1825219820Sjeff int port, struct ib_wc *in_wc, struct ib_grh *in_grh, 1826219820Sjeff void *in_mad, void *response_mad, u8 *status) 1827219820Sjeff{ 1828219820Sjeff struct mthca_mailbox *inmailbox, *outmailbox; 1829219820Sjeff void *inbox; 1830219820Sjeff int err; 1831219820Sjeff u32 in_modifier = port; 1832219820Sjeff u8 op_modifier = 0; 1833219820Sjeff 1834219820Sjeff#define MAD_IFC_BOX_SIZE 0x400 1835219820Sjeff#define MAD_IFC_MY_QPN_OFFSET 0x100 1836219820Sjeff#define MAD_IFC_RQPN_OFFSET 0x108 1837219820Sjeff#define MAD_IFC_SL_OFFSET 0x10c 1838219820Sjeff#define MAD_IFC_G_PATH_OFFSET 0x10d 1839219820Sjeff#define MAD_IFC_RLID_OFFSET 0x10e 1840219820Sjeff#define MAD_IFC_PKEY_OFFSET 0x112 1841219820Sjeff#define MAD_IFC_GRH_OFFSET 0x140 1842219820Sjeff 1843219820Sjeff inmailbox = mthca_alloc_mailbox(dev, GFP_KERNEL); 1844219820Sjeff if (IS_ERR(inmailbox)) 1845219820Sjeff return PTR_ERR(inmailbox); 1846219820Sjeff inbox = inmailbox->buf; 1847219820Sjeff 1848219820Sjeff outmailbox = mthca_alloc_mailbox(dev, GFP_KERNEL); 1849219820Sjeff if (IS_ERR(outmailbox)) { 1850219820Sjeff mthca_free_mailbox(dev, inmailbox); 1851219820Sjeff return PTR_ERR(outmailbox); 1852219820Sjeff } 1853219820Sjeff 1854219820Sjeff memcpy(inbox, in_mad, 256); 1855219820Sjeff 1856219820Sjeff /* 1857219820Sjeff * Key check traps can't be generated unless we have in_wc to 1858219820Sjeff * tell us where to send the trap. 1859219820Sjeff */ 1860219820Sjeff if (ignore_mkey || !in_wc) 1861219820Sjeff op_modifier |= 0x1; 1862219820Sjeff if (ignore_bkey || !in_wc) 1863219820Sjeff op_modifier |= 0x2; 1864219820Sjeff 1865219820Sjeff if (in_wc) { 1866219820Sjeff u8 val; 1867219820Sjeff 1868219820Sjeff memset(inbox + 256, 0, 256); 1869219820Sjeff 1870219820Sjeff MTHCA_PUT(inbox, in_wc->qp->qp_num, MAD_IFC_MY_QPN_OFFSET); 1871219820Sjeff MTHCA_PUT(inbox, in_wc->src_qp, MAD_IFC_RQPN_OFFSET); 1872219820Sjeff 1873219820Sjeff val = in_wc->sl << 4; 1874219820Sjeff MTHCA_PUT(inbox, val, MAD_IFC_SL_OFFSET); 1875219820Sjeff 1876219820Sjeff val = in_wc->dlid_path_bits | 1877219820Sjeff (in_wc->wc_flags & IB_WC_GRH ? 0x80 : 0); 1878219820Sjeff MTHCA_PUT(inbox, val, MAD_IFC_G_PATH_OFFSET); 1879219820Sjeff 1880219820Sjeff MTHCA_PUT(inbox, in_wc->slid, MAD_IFC_RLID_OFFSET); 1881219820Sjeff MTHCA_PUT(inbox, in_wc->pkey_index, MAD_IFC_PKEY_OFFSET); 1882219820Sjeff 1883219820Sjeff if (in_grh) 1884219820Sjeff memcpy(inbox + MAD_IFC_GRH_OFFSET, in_grh, 40); 1885219820Sjeff 1886219820Sjeff op_modifier |= 0x4; 1887219820Sjeff 1888219820Sjeff in_modifier |= in_wc->slid << 16; 1889219820Sjeff } 1890219820Sjeff 1891219820Sjeff err = mthca_cmd_box(dev, inmailbox->dma, outmailbox->dma, 1892219820Sjeff in_modifier, op_modifier, 1893219820Sjeff CMD_MAD_IFC, CMD_TIME_CLASS_C, status); 1894219820Sjeff 1895219820Sjeff if (!err && !*status) 1896219820Sjeff memcpy(response_mad, outmailbox->buf, 256); 1897219820Sjeff 1898219820Sjeff mthca_free_mailbox(dev, inmailbox); 1899219820Sjeff mthca_free_mailbox(dev, outmailbox); 1900219820Sjeff return err; 1901219820Sjeff} 1902219820Sjeff 1903219820Sjeffint mthca_READ_MGM(struct mthca_dev *dev, int index, 1904219820Sjeff struct mthca_mailbox *mailbox, u8 *status) 1905219820Sjeff{ 1906219820Sjeff return mthca_cmd_box(dev, 0, mailbox->dma, index, 0, 1907219820Sjeff CMD_READ_MGM, CMD_TIME_CLASS_A, status); 1908219820Sjeff} 1909219820Sjeff 1910219820Sjeffint mthca_WRITE_MGM(struct mthca_dev *dev, int index, 1911219820Sjeff struct mthca_mailbox *mailbox, u8 *status) 1912219820Sjeff{ 1913219820Sjeff return mthca_cmd(dev, mailbox->dma, index, 0, CMD_WRITE_MGM, 1914219820Sjeff CMD_TIME_CLASS_A, status); 1915219820Sjeff} 1916219820Sjeff 1917219820Sjeffint mthca_MGID_HASH(struct mthca_dev *dev, struct mthca_mailbox *mailbox, 1918219820Sjeff u16 *hash, u8 *status) 1919219820Sjeff{ 1920219820Sjeff u64 imm; 1921219820Sjeff int err; 1922219820Sjeff 1923219820Sjeff err = mthca_cmd_imm(dev, mailbox->dma, &imm, 0, 0, CMD_MGID_HASH, 1924219820Sjeff CMD_TIME_CLASS_A, status); 1925219820Sjeff 1926219820Sjeff *hash = imm; 1927219820Sjeff return err; 1928219820Sjeff} 1929219820Sjeff 1930219820Sjeffint mthca_NOP(struct mthca_dev *dev, u8 *status) 1931219820Sjeff{ 1932219820Sjeff return mthca_cmd(dev, 0, 0x1f, 0, CMD_NOP, msecs_to_jiffies(100), status); 1933219820Sjeff} 1934