1198157Srrs/*- 2198157Srrs * Copyright (c) 2003-2009 RMI Corporation 3198157Srrs * All rights reserved. 4198157Srrs * 5198157Srrs * Redistribution and use in source and binary forms, with or without 6198157Srrs * modification, are permitted provided that the following conditions 7198157Srrs * are met: 8198157Srrs * 1. Redistributions of source code must retain the above copyright 9198157Srrs * notice, this list of conditions and the following disclaimer. 10198157Srrs * 2. Redistributions in binary form must reproduce the above copyright 11198157Srrs * notice, this list of conditions and the following disclaimer in the 12198157Srrs * documentation and/or other materials provided with the distribution. 13198157Srrs * 3. Neither the name of RMI Corporation, nor the names of its contributors, 14198157Srrs * may be used to endorse or promote products derived from this software 15198157Srrs * without specific prior written permission. 16198157Srrs * 17198157Srrs * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 18198157Srrs * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 19198157Srrs * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 20198157Srrs * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 21198157Srrs * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 22198157Srrs * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 23198157Srrs * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 24198157Srrs * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 25198157Srrs * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 26198157Srrs * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 27198157Srrs * SUCH DAMAGE. 28198157Srrs * 29212759Sjchandra * $FreeBSD$ 30198157Srrs * RMI_BSD */ 31198157Srrs#ifndef _RMI_RGE_H_ 32198157Srrs#define _RMI_RGE_H_ 33198157Srrs 34198157Srrs/* #define MAC_SPLIT_MODE */ 35198157Srrs 36198157Srrs#define MAC_SPACING 0x400 37198157Srrs#define XGMAC_SPACING 0x400 38198157Srrs 39198157Srrs/* PE-MCXMAC register and bit field definitions */ 40198157Srrs#define R_MAC_CONFIG_1 0x00 41198157Srrs#define O_MAC_CONFIG_1__srst 31 42198157Srrs#define O_MAC_CONFIG_1__simr 30 43198157Srrs#define O_MAC_CONFIG_1__hrrmc 18 44198157Srrs#define W_MAC_CONFIG_1__hrtmc 2 45198157Srrs#define O_MAC_CONFIG_1__hrrfn 16 46198157Srrs#define W_MAC_CONFIG_1__hrtfn 2 47198157Srrs#define O_MAC_CONFIG_1__intlb 8 48198157Srrs#define O_MAC_CONFIG_1__rxfc 5 49198157Srrs#define O_MAC_CONFIG_1__txfc 4 50198157Srrs#define O_MAC_CONFIG_1__srxen 3 51198157Srrs#define O_MAC_CONFIG_1__rxen 2 52198157Srrs#define O_MAC_CONFIG_1__stxen 1 53198157Srrs#define O_MAC_CONFIG_1__txen 0 54198157Srrs#define R_MAC_CONFIG_2 0x01 55198157Srrs#define O_MAC_CONFIG_2__prlen 12 56198157Srrs#define W_MAC_CONFIG_2__prlen 4 57198157Srrs#define O_MAC_CONFIG_2__speed 8 58198157Srrs#define W_MAC_CONFIG_2__speed 2 59198157Srrs#define O_MAC_CONFIG_2__hugen 5 60198157Srrs#define O_MAC_CONFIG_2__flchk 4 61198157Srrs#define O_MAC_CONFIG_2__crce 1 62198157Srrs#define O_MAC_CONFIG_2__fulld 0 63198157Srrs#define R_IPG_IFG 0x02 64198157Srrs#define O_IPG_IFG__ipgr1 24 65198157Srrs#define W_IPG_IFG__ipgr1 7 66198157Srrs#define O_IPG_IFG__ipgr2 16 67198157Srrs#define W_IPG_IFG__ipgr2 7 68198157Srrs#define O_IPG_IFG__mifg 8 69198157Srrs#define W_IPG_IFG__mifg 8 70198157Srrs#define O_IPG_IFG__ipgt 0 71198157Srrs#define W_IPG_IFG__ipgt 7 72198157Srrs#define R_HALF_DUPLEX 0x03 73198157Srrs#define O_HALF_DUPLEX__abebt 24 74198157Srrs#define W_HALF_DUPLEX__abebt 4 75198157Srrs#define O_HALF_DUPLEX__abebe 19 76198157Srrs#define O_HALF_DUPLEX__bpnb 18 77198157Srrs#define O_HALF_DUPLEX__nobo 17 78198157Srrs#define O_HALF_DUPLEX__edxsdfr 16 79198157Srrs#define O_HALF_DUPLEX__retry 12 80198157Srrs#define W_HALF_DUPLEX__retry 4 81198157Srrs#define O_HALF_DUPLEX__lcol 0 82198157Srrs#define W_HALF_DUPLEX__lcol 10 83198157Srrs#define R_MAXIMUM_FRAME_LENGTH 0x04 84198157Srrs#define O_MAXIMUM_FRAME_LENGTH__maxf 0 85198157Srrs#define W_MAXIMUM_FRAME_LENGTH__maxf 16 86198157Srrs#define R_TEST 0x07 87198157Srrs#define O_TEST__mbof 3 88198157Srrs#define O_TEST__rthdf 2 89198157Srrs#define O_TEST__tpause 1 90198157Srrs#define O_TEST__sstct 0 91198157Srrs#define R_MII_MGMT_CONFIG 0x08 92198157Srrs#define O_MII_MGMT_CONFIG__scinc 5 93198157Srrs#define O_MII_MGMT_CONFIG__spre 4 94198157Srrs#define O_MII_MGMT_CONFIG__clks 3 95198157Srrs#define W_MII_MGMT_CONFIG__clks 3 96198157Srrs#define R_MII_MGMT_COMMAND 0x09 97198157Srrs#define O_MII_MGMT_COMMAND__scan 1 98198157Srrs#define O_MII_MGMT_COMMAND__rstat 0 99198157Srrs#define R_MII_MGMT_ADDRESS 0x0A 100198157Srrs#define O_MII_MGMT_ADDRESS__fiad 8 101198157Srrs#define W_MII_MGMT_ADDRESS__fiad 5 102198157Srrs#define O_MII_MGMT_ADDRESS__fgad 5 103198157Srrs#define W_MII_MGMT_ADDRESS__fgad 0 104198157Srrs#define R_MII_MGMT_WRITE_DATA 0x0B 105198157Srrs#define O_MII_MGMT_WRITE_DATA__ctld 0 106198157Srrs#define W_MII_MGMT_WRITE_DATA__ctld 16 107198157Srrs#define R_MII_MGMT_STATUS 0x0C 108198157Srrs#define R_MII_MGMT_INDICATORS 0x0D 109198157Srrs#define O_MII_MGMT_INDICATORS__nvalid 2 110198157Srrs#define O_MII_MGMT_INDICATORS__scan 1 111198157Srrs#define O_MII_MGMT_INDICATORS__busy 0 112198157Srrs#define R_INTERFACE_CONTROL 0x0E 113198157Srrs#define O_INTERFACE_CONTROL__hrstint 31 114198157Srrs#define O_INTERFACE_CONTROL__tbimode 27 115198157Srrs#define O_INTERFACE_CONTROL__ghdmode 26 116198157Srrs#define O_INTERFACE_CONTROL__lhdmode 25 117198157Srrs#define O_INTERFACE_CONTROL__phymod 24 118198157Srrs#define O_INTERFACE_CONTROL__hrrmi 23 119198157Srrs#define O_INTERFACE_CONTROL__rspd 16 120198157Srrs#define O_INTERFACE_CONTROL__hr100 15 121198157Srrs#define O_INTERFACE_CONTROL__frcq 10 122198157Srrs#define O_INTERFACE_CONTROL__nocfr 9 123198157Srrs#define O_INTERFACE_CONTROL__dlfct 8 124198157Srrs#define O_INTERFACE_CONTROL__enjab 0 125198157Srrs#define R_INTERFACE_STATUS 0x0F 126198157Srrs#define O_INTERFACE_STATUS__xsdfr 9 127198157Srrs#define O_INTERFACE_STATUS__ssrr 8 128198157Srrs#define W_INTERFACE_STATUS__ssrr 5 129198157Srrs#define O_INTERFACE_STATUS__miilf 3 130198157Srrs#define O_INTERFACE_STATUS__locar 2 131198157Srrs#define O_INTERFACE_STATUS__sqerr 1 132198157Srrs#define O_INTERFACE_STATUS__jabber 0 133198157Srrs#define R_STATION_ADDRESS_LS 0x10 134198157Srrs#define R_STATION_ADDRESS_MS 0x11 135198157Srrs 136198157Srrs/* A-XGMAC register and bit field definitions */ 137198157Srrs#define R_XGMAC_CONFIG_0 0x00 138198157Srrs#define O_XGMAC_CONFIG_0__hstmacrst 31 139198157Srrs#define O_XGMAC_CONFIG_0__hstrstrctl 23 140198157Srrs#define O_XGMAC_CONFIG_0__hstrstrfn 22 141198157Srrs#define O_XGMAC_CONFIG_0__hstrsttctl 18 142198157Srrs#define O_XGMAC_CONFIG_0__hstrsttfn 17 143198157Srrs#define O_XGMAC_CONFIG_0__hstrstmiim 16 144198157Srrs#define O_XGMAC_CONFIG_0__hstloopback 8 145198157Srrs#define R_XGMAC_CONFIG_1 0x01 146198157Srrs#define O_XGMAC_CONFIG_1__hsttctlen 31 147198157Srrs#define O_XGMAC_CONFIG_1__hsttfen 30 148198157Srrs#define O_XGMAC_CONFIG_1__hstrctlen 29 149198157Srrs#define O_XGMAC_CONFIG_1__hstrfen 28 150198157Srrs#define O_XGMAC_CONFIG_1__tfen 26 151198157Srrs#define O_XGMAC_CONFIG_1__rfen 24 152198157Srrs#define O_XGMAC_CONFIG_1__hstrctlshrtp 12 153198157Srrs#define O_XGMAC_CONFIG_1__hstdlyfcstx 10 154198157Srrs#define W_XGMAC_CONFIG_1__hstdlyfcstx 2 155198157Srrs#define O_XGMAC_CONFIG_1__hstdlyfcsrx 8 156198157Srrs#define W_XGMAC_CONFIG_1__hstdlyfcsrx 2 157198157Srrs#define O_XGMAC_CONFIG_1__hstppen 7 158198157Srrs#define O_XGMAC_CONFIG_1__hstbytswp 6 159198157Srrs#define O_XGMAC_CONFIG_1__hstdrplt64 5 160198157Srrs#define O_XGMAC_CONFIG_1__hstprmscrx 4 161198157Srrs#define O_XGMAC_CONFIG_1__hstlenchk 3 162198157Srrs#define O_XGMAC_CONFIG_1__hstgenfcs 2 163198157Srrs#define O_XGMAC_CONFIG_1__hstpadmode 0 164198157Srrs#define W_XGMAC_CONFIG_1__hstpadmode 2 165198157Srrs#define R_XGMAC_CONFIG_2 0x02 166198157Srrs#define O_XGMAC_CONFIG_2__hsttctlfrcp 31 167198157Srrs#define O_XGMAC_CONFIG_2__hstmlnkflth 27 168198157Srrs#define O_XGMAC_CONFIG_2__hstalnkflth 26 169198157Srrs#define O_XGMAC_CONFIG_2__rflnkflt 24 170198157Srrs#define W_XGMAC_CONFIG_2__rflnkflt 2 171198157Srrs#define O_XGMAC_CONFIG_2__hstipgextmod 16 172198157Srrs#define W_XGMAC_CONFIG_2__hstipgextmod 5 173198157Srrs#define O_XGMAC_CONFIG_2__hstrctlfrcp 15 174198157Srrs#define O_XGMAC_CONFIG_2__hstipgexten 5 175198157Srrs#define O_XGMAC_CONFIG_2__hstmipgext 0 176198157Srrs#define W_XGMAC_CONFIG_2__hstmipgext 5 177198157Srrs#define R_XGMAC_CONFIG_3 0x03 178198157Srrs#define O_XGMAC_CONFIG_3__hstfltrfrm 31 179198157Srrs#define W_XGMAC_CONFIG_3__hstfltrfrm 16 180198157Srrs#define O_XGMAC_CONFIG_3__hstfltrfrmdc 15 181198157Srrs#define W_XGMAC_CONFIG_3__hstfltrfrmdc 16 182198157Srrs#define R_XGMAC_STATION_ADDRESS_LS 0x04 183198157Srrs#define O_XGMAC_STATION_ADDRESS_LS__hstmacadr0 0 184198157Srrs#define W_XGMAC_STATION_ADDRESS_LS__hstmacadr0 32 185198157Srrs#define R_XGMAC_STATION_ADDRESS_MS 0x05 186198157Srrs#define R_XGMAC_MAX_FRAME_LEN 0x08 187198157Srrs#define O_XGMAC_MAX_FRAME_LEN__hstmxfrmwctx 16 188198157Srrs#define W_XGMAC_MAX_FRAME_LEN__hstmxfrmwctx 14 189198157Srrs#define O_XGMAC_MAX_FRAME_LEN__hstmxfrmbcrx 0 190198157Srrs#define W_XGMAC_MAX_FRAME_LEN__hstmxfrmbcrx 16 191198157Srrs#define R_XGMAC_REV_LEVEL 0x0B 192198157Srrs#define O_XGMAC_REV_LEVEL__revlvl 0 193198157Srrs#define W_XGMAC_REV_LEVEL__revlvl 15 194198157Srrs#define R_XGMAC_MIIM_COMMAND 0x10 195198157Srrs#define O_XGMAC_MIIM_COMMAND__hstldcmd 3 196198157Srrs#define O_XGMAC_MIIM_COMMAND__hstmiimcmd 0 197198157Srrs#define W_XGMAC_MIIM_COMMAND__hstmiimcmd 3 198198157Srrs#define R_XGMAC_MIIM_FILED 0x11 199198157Srrs#define O_XGMAC_MIIM_FILED__hststfield 30 200198157Srrs#define W_XGMAC_MIIM_FILED__hststfield 2 201198157Srrs#define O_XGMAC_MIIM_FILED__hstopfield 28 202198157Srrs#define W_XGMAC_MIIM_FILED__hstopfield 2 203198157Srrs#define O_XGMAC_MIIM_FILED__hstphyadx 23 204198157Srrs#define W_XGMAC_MIIM_FILED__hstphyadx 5 205198157Srrs#define O_XGMAC_MIIM_FILED__hstregadx 18 206198157Srrs#define W_XGMAC_MIIM_FILED__hstregadx 5 207198157Srrs#define O_XGMAC_MIIM_FILED__hsttafield 16 208198157Srrs#define W_XGMAC_MIIM_FILED__hsttafield 2 209198157Srrs#define O_XGMAC_MIIM_FILED__miimrddat 0 210198157Srrs#define W_XGMAC_MIIM_FILED__miimrddat 16 211198157Srrs#define R_XGMAC_MIIM_CONFIG 0x12 212198157Srrs#define O_XGMAC_MIIM_CONFIG__hstnopram 7 213198157Srrs#define O_XGMAC_MIIM_CONFIG__hstclkdiv 0 214198157Srrs#define W_XGMAC_MIIM_CONFIG__hstclkdiv 7 215198157Srrs#define R_XGMAC_MIIM_LINK_FAIL_VECTOR 0x13 216198157Srrs#define O_XGMAC_MIIM_LINK_FAIL_VECTOR__miimlfvec 0 217198157Srrs#define W_XGMAC_MIIM_LINK_FAIL_VECTOR__miimlfvec 32 218198157Srrs#define R_XGMAC_MIIM_INDICATOR 0x14 219198157Srrs#define O_XGMAC_MIIM_INDICATOR__miimphylf 4 220198157Srrs#define O_XGMAC_MIIM_INDICATOR__miimmoncplt 3 221198157Srrs#define O_XGMAC_MIIM_INDICATOR__miimmonvld 2 222198157Srrs#define O_XGMAC_MIIM_INDICATOR__miimmon 1 223198157Srrs#define O_XGMAC_MIIM_INDICATOR__miimbusy 0 224198157Srrs 225198157Srrs/* Glue logic register and bit field definitions */ 226198157Srrs#define R_MAC_ADDR0 0x50 227198157Srrs#define R_MAC_ADDR1 0x52 228198157Srrs#define R_MAC_ADDR2 0x54 229198157Srrs#define R_MAC_ADDR3 0x56 230198157Srrs#define R_MAC_ADDR_MASK2 0x58 231198157Srrs#define R_MAC_ADDR_MASK3 0x5A 232198157Srrs#define R_MAC_FILTER_CONFIG 0x5C 233198157Srrs#define O_MAC_FILTER_CONFIG__BROADCAST_EN 10 234198157Srrs#define O_MAC_FILTER_CONFIG__PAUSE_FRAME_EN 9 235198157Srrs#define O_MAC_FILTER_CONFIG__ALL_MCAST_EN 8 236198157Srrs#define O_MAC_FILTER_CONFIG__ALL_UCAST_EN 7 237198157Srrs#define O_MAC_FILTER_CONFIG__HASH_MCAST_EN 6 238198157Srrs#define O_MAC_FILTER_CONFIG__HASH_UCAST_EN 5 239198157Srrs#define O_MAC_FILTER_CONFIG__ADDR_MATCH_DISC 4 240198157Srrs#define O_MAC_FILTER_CONFIG__MAC_ADDR3_VALID 3 241198157Srrs#define O_MAC_FILTER_CONFIG__MAC_ADDR2_VALID 2 242198157Srrs#define O_MAC_FILTER_CONFIG__MAC_ADDR1_VALID 1 243198157Srrs#define O_MAC_FILTER_CONFIG__MAC_ADDR0_VALID 0 244198157Srrs#define R_HASH_TABLE_VECTOR 0x30 245198157Srrs#define R_TX_CONTROL 0x0A0 246198157Srrs#define O_TX_CONTROL__Tx15Halt 31 247198157Srrs#define O_TX_CONTROL__Tx14Halt 30 248198157Srrs#define O_TX_CONTROL__Tx13Halt 29 249198157Srrs#define O_TX_CONTROL__Tx12Halt 28 250198157Srrs#define O_TX_CONTROL__Tx11Halt 27 251198157Srrs#define O_TX_CONTROL__Tx10Halt 26 252198157Srrs#define O_TX_CONTROL__Tx9Halt 25 253198157Srrs#define O_TX_CONTROL__Tx8Halt 24 254198157Srrs#define O_TX_CONTROL__Tx7Halt 23 255198157Srrs#define O_TX_CONTROL__Tx6Halt 22 256198157Srrs#define O_TX_CONTROL__Tx5Halt 21 257198157Srrs#define O_TX_CONTROL__Tx4Halt 20 258198157Srrs#define O_TX_CONTROL__Tx3Halt 19 259198157Srrs#define O_TX_CONTROL__Tx2Halt 18 260198157Srrs#define O_TX_CONTROL__Tx1Halt 17 261198157Srrs#define O_TX_CONTROL__Tx0Halt 16 262198157Srrs#define O_TX_CONTROL__TxIdle 15 263198157Srrs#define O_TX_CONTROL__TxEnable 14 264198157Srrs#define O_TX_CONTROL__TxThreshold 0 265198157Srrs#define W_TX_CONTROL__TxThreshold 14 266198157Srrs#define R_RX_CONTROL 0x0A1 267198157Srrs#define O_RX_CONTROL__RGMII 10 268198157Srrs#define O_RX_CONTROL__RxHalt 1 269198157Srrs#define O_RX_CONTROL__RxEnable 0 270198157Srrs#define R_DESC_PACK_CTRL 0x0A2 271198157Srrs#define O_DESC_PACK_CTRL__ByteOffset 17 272198157Srrs#define W_DESC_PACK_CTRL__ByteOffset 3 273198157Srrs#define O_DESC_PACK_CTRL__PrePadEnable 16 274198157Srrs#define O_DESC_PACK_CTRL__MaxEntry 14 275198157Srrs#define W_DESC_PACK_CTRL__MaxEntry 2 276198157Srrs#define O_DESC_PACK_CTRL__RegularSize 0 277198157Srrs#define W_DESC_PACK_CTRL__RegularSize 14 278198157Srrs#define R_STATCTRL 0x0A3 279198157Srrs#define O_STATCTRL__OverFlowEn 4 280198157Srrs#define O_STATCTRL__GIG 3 281198157Srrs#define O_STATCTRL__Sten 2 282198157Srrs#define O_STATCTRL__ClrCnt 1 283198157Srrs#define O_STATCTRL__AutoZ 0 284198157Srrs#define R_L2ALLOCCTRL 0x0A4 285198157Srrs#define O_L2ALLOCCTRL__TxL2Allocate 9 286198157Srrs#define W_L2ALLOCCTRL__TxL2Allocate 9 287198157Srrs#define O_L2ALLOCCTRL__RxL2Allocate 0 288198157Srrs#define W_L2ALLOCCTRL__RxL2Allocate 9 289198157Srrs#define R_INTMASK 0x0A5 290198157Srrs#define O_INTMASK__Spi4TxError 28 291198157Srrs#define O_INTMASK__Spi4RxError 27 292198157Srrs#define O_INTMASK__RGMIIHalfDupCollision 27 293198157Srrs#define O_INTMASK__Abort 26 294198157Srrs#define O_INTMASK__Underrun 25 295198157Srrs#define O_INTMASK__DiscardPacket 24 296198157Srrs#define O_INTMASK__AsyncFifoFull 23 297198157Srrs#define O_INTMASK__TagFull 22 298198157Srrs#define O_INTMASK__Class3Full 21 299198157Srrs#define O_INTMASK__C3EarlyFull 20 300198157Srrs#define O_INTMASK__Class2Full 19 301198157Srrs#define O_INTMASK__C2EarlyFull 18 302198157Srrs#define O_INTMASK__Class1Full 17 303198157Srrs#define O_INTMASK__C1EarlyFull 16 304198157Srrs#define O_INTMASK__Class0Full 15 305198157Srrs#define O_INTMASK__C0EarlyFull 14 306198157Srrs#define O_INTMASK__RxDataFull 13 307198157Srrs#define O_INTMASK__RxEarlyFull 12 308198157Srrs#define O_INTMASK__RFreeEmpty 9 309198157Srrs#define O_INTMASK__RFEarlyEmpty 8 310198157Srrs#define O_INTMASK__P2PSpillEcc 7 311198157Srrs#define O_INTMASK__FreeDescFull 5 312198157Srrs#define O_INTMASK__FreeEarlyFull 4 313198157Srrs#define O_INTMASK__TxFetchError 3 314198157Srrs#define O_INTMASK__StatCarry 2 315198157Srrs#define O_INTMASK__MDInt 1 316198157Srrs#define O_INTMASK__TxIllegal 0 317198157Srrs#define R_INTREG 0x0A6 318198157Srrs#define O_INTREG__Spi4TxError 28 319198157Srrs#define O_INTREG__Spi4RxError 27 320198157Srrs#define O_INTREG__RGMIIHalfDupCollision 27 321198157Srrs#define O_INTREG__Abort 26 322198157Srrs#define O_INTREG__Underrun 25 323198157Srrs#define O_INTREG__DiscardPacket 24 324198157Srrs#define O_INTREG__AsyncFifoFull 23 325198157Srrs#define O_INTREG__TagFull 22 326198157Srrs#define O_INTREG__Class3Full 21 327198157Srrs#define O_INTREG__C3EarlyFull 20 328198157Srrs#define O_INTREG__Class2Full 19 329198157Srrs#define O_INTREG__C2EarlyFull 18 330198157Srrs#define O_INTREG__Class1Full 17 331198157Srrs#define O_INTREG__C1EarlyFull 16 332198157Srrs#define O_INTREG__Class0Full 15 333198157Srrs#define O_INTREG__C0EarlyFull 14 334198157Srrs#define O_INTREG__RxDataFull 13 335198157Srrs#define O_INTREG__RxEarlyFull 12 336198157Srrs#define O_INTREG__RFreeEmpty 9 337198157Srrs#define O_INTREG__RFEarlyEmpty 8 338198157Srrs#define O_INTREG__P2PSpillEcc 7 339198157Srrs#define O_INTREG__FreeDescFull 5 340198157Srrs#define O_INTREG__FreeEarlyFull 4 341198157Srrs#define O_INTREG__TxFetchError 3 342198157Srrs#define O_INTREG__StatCarry 2 343198157Srrs#define O_INTREG__MDInt 1 344198157Srrs#define O_INTREG__TxIllegal 0 345198157Srrs#define R_TXRETRY 0x0A7 346198157Srrs#define O_TXRETRY__CollisionRetry 6 347198157Srrs#define O_TXRETRY__BusErrorRetry 5 348198157Srrs#define O_TXRETRY__UnderRunRetry 4 349198157Srrs#define O_TXRETRY__Retries 0 350198157Srrs#define W_TXRETRY__Retries 4 351198157Srrs#define R_CORECONTROL 0x0A8 352198157Srrs#define O_CORECONTROL__ErrorThread 4 353198157Srrs#define W_CORECONTROL__ErrorThread 7 354198157Srrs#define O_CORECONTROL__Shutdown 2 355198157Srrs#define O_CORECONTROL__Speed 0 356198157Srrs#define W_CORECONTROL__Speed 2 357198157Srrs#define R_BYTEOFFSET0 0x0A9 358198157Srrs#define R_BYTEOFFSET1 0x0AA 359198157Srrs#define R_L2TYPE_0 0x0F0 360198157Srrs#define O_L2TYPE__ExtraHdrProtoSize 26 361198157Srrs#define W_L2TYPE__ExtraHdrProtoSize 5 362198157Srrs#define O_L2TYPE__ExtraHdrProtoOffset 20 363198157Srrs#define W_L2TYPE__ExtraHdrProtoOffset 6 364198157Srrs#define O_L2TYPE__ExtraHeaderSize 14 365198157Srrs#define W_L2TYPE__ExtraHeaderSize 6 366198157Srrs#define O_L2TYPE__ProtoOffset 8 367198157Srrs#define W_L2TYPE__ProtoOffset 6 368198157Srrs#define O_L2TYPE__L2HdrOffset 2 369198157Srrs#define W_L2TYPE__L2HdrOffset 6 370198157Srrs#define O_L2TYPE__L2Proto 0 371198157Srrs#define W_L2TYPE__L2Proto 2 372198157Srrs#define R_L2TYPE_1 0xF0 373198157Srrs#define R_L2TYPE_2 0xF0 374198157Srrs#define R_L2TYPE_3 0xF0 375198157Srrs#define R_PARSERCONFIGREG 0x100 376198157Srrs#define O_PARSERCONFIGREG__CRCHashPoly 8 377198157Srrs#define W_PARSERCONFIGREG__CRCHashPoly 7 378198157Srrs#define O_PARSERCONFIGREG__PrePadOffset 4 379198157Srrs#define W_PARSERCONFIGREG__PrePadOffset 4 380198157Srrs#define O_PARSERCONFIGREG__UseCAM 2 381198157Srrs#define O_PARSERCONFIGREG__UseHASH 1 382198157Srrs#define O_PARSERCONFIGREG__UseProto 0 383198157Srrs#define R_L3CTABLE 0x140 384198157Srrs#define O_L3CTABLE__Offset0 25 385198157Srrs#define W_L3CTABLE__Offset0 7 386198157Srrs#define O_L3CTABLE__Len0 21 387198157Srrs#define W_L3CTABLE__Len0 4 388198157Srrs#define O_L3CTABLE__Offset1 14 389198157Srrs#define W_L3CTABLE__Offset1 7 390198157Srrs#define O_L3CTABLE__Len1 10 391198157Srrs#define W_L3CTABLE__Len1 4 392198157Srrs#define O_L3CTABLE__Offset2 4 393198157Srrs#define W_L3CTABLE__Offset2 6 394198157Srrs#define O_L3CTABLE__Len2 0 395198157Srrs#define W_L3CTABLE__Len2 4 396198157Srrs#define O_L3CTABLE__L3HdrOffset 26 397198157Srrs#define W_L3CTABLE__L3HdrOffset 6 398198157Srrs#define O_L3CTABLE__L4ProtoOffset 20 399198157Srrs#define W_L3CTABLE__L4ProtoOffset 6 400198157Srrs#define O_L3CTABLE__IPChksumCompute 19 401198157Srrs#define O_L3CTABLE__L4Classify 18 402198157Srrs#define O_L3CTABLE__L2Proto 16 403198157Srrs#define W_L3CTABLE__L2Proto 2 404198157Srrs#define O_L3CTABLE__L3ProtoKey 0 405198157Srrs#define W_L3CTABLE__L3ProtoKey 16 406198157Srrs#define R_L4CTABLE 0x160 407198157Srrs#define O_L4CTABLE__Offset0 21 408198157Srrs#define W_L4CTABLE__Offset0 6 409198157Srrs#define O_L4CTABLE__Len0 17 410198157Srrs#define W_L4CTABLE__Len0 4 411198157Srrs#define O_L4CTABLE__Offset1 11 412198157Srrs#define W_L4CTABLE__Offset1 6 413198157Srrs#define O_L4CTABLE__Len1 7 414198157Srrs#define W_L4CTABLE__Len1 4 415198157Srrs#define O_L4CTABLE__TCPChksumEnable 0 416198157Srrs#define R_CAM4X128TABLE 0x172 417198157Srrs#define O_CAM4X128TABLE__ClassId 7 418198157Srrs#define W_CAM4X128TABLE__ClassId 2 419198157Srrs#define O_CAM4X128TABLE__BucketId 1 420198157Srrs#define W_CAM4X128TABLE__BucketId 6 421198157Srrs#define O_CAM4X128TABLE__UseBucket 0 422198157Srrs#define R_CAM4X128KEY 0x180 423198157Srrs#define R_TRANSLATETABLE 0x1A0 424198157Srrs#define R_DMACR0 0x200 425198157Srrs#define O_DMACR0__Data0WrMaxCr 27 426198157Srrs#define W_DMACR0__Data0WrMaxCr 3 427198157Srrs#define O_DMACR0__Data0RdMaxCr 24 428198157Srrs#define W_DMACR0__Data0RdMaxCr 3 429198157Srrs#define O_DMACR0__Data1WrMaxCr 21 430198157Srrs#define W_DMACR0__Data1WrMaxCr 3 431198157Srrs#define O_DMACR0__Data1RdMaxCr 18 432198157Srrs#define W_DMACR0__Data1RdMaxCr 3 433198157Srrs#define O_DMACR0__Data2WrMaxCr 15 434198157Srrs#define W_DMACR0__Data2WrMaxCr 3 435198157Srrs#define O_DMACR0__Data2RdMaxCr 12 436198157Srrs#define W_DMACR0__Data2RdMaxCr 3 437198157Srrs#define O_DMACR0__Data3WrMaxCr 9 438198157Srrs#define W_DMACR0__Data3WrMaxCr 3 439198157Srrs#define O_DMACR0__Data3RdMaxCr 6 440198157Srrs#define W_DMACR0__Data3RdMaxCr 3 441198157Srrs#define O_DMACR0__Data4WrMaxCr 3 442198157Srrs#define W_DMACR0__Data4WrMaxCr 3 443198157Srrs#define O_DMACR0__Data4RdMaxCr 0 444198157Srrs#define W_DMACR0__Data4RdMaxCr 3 445198157Srrs#define R_DMACR1 0x201 446198157Srrs#define O_DMACR1__Data5WrMaxCr 27 447198157Srrs#define W_DMACR1__Data5WrMaxCr 3 448198157Srrs#define O_DMACR1__Data5RdMaxCr 24 449198157Srrs#define W_DMACR1__Data5RdMaxCr 3 450198157Srrs#define O_DMACR1__Data6WrMaxCr 21 451198157Srrs#define W_DMACR1__Data6WrMaxCr 3 452198157Srrs#define O_DMACR1__Data6RdMaxCr 18 453198157Srrs#define W_DMACR1__Data6RdMaxCr 3 454198157Srrs#define O_DMACR1__Data7WrMaxCr 15 455198157Srrs#define W_DMACR1__Data7WrMaxCr 3 456198157Srrs#define O_DMACR1__Data7RdMaxCr 12 457198157Srrs#define W_DMACR1__Data7RdMaxCr 3 458198157Srrs#define O_DMACR1__Data8WrMaxCr 9 459198157Srrs#define W_DMACR1__Data8WrMaxCr 3 460198157Srrs#define O_DMACR1__Data8RdMaxCr 6 461198157Srrs#define W_DMACR1__Data8RdMaxCr 3 462198157Srrs#define O_DMACR1__Data9WrMaxCr 3 463198157Srrs#define W_DMACR1__Data9WrMaxCr 3 464198157Srrs#define O_DMACR1__Data9RdMaxCr 0 465198157Srrs#define W_DMACR1__Data9RdMaxCr 3 466198157Srrs#define R_DMACR2 0x202 467198157Srrs#define O_DMACR2__Data10WrMaxCr 27 468198157Srrs#define W_DMACR2__Data10WrMaxCr 3 469198157Srrs#define O_DMACR2__Data10RdMaxCr 24 470198157Srrs#define W_DMACR2__Data10RdMaxCr 3 471198157Srrs#define O_DMACR2__Data11WrMaxCr 21 472198157Srrs#define W_DMACR2__Data11WrMaxCr 3 473198157Srrs#define O_DMACR2__Data11RdMaxCr 18 474198157Srrs#define W_DMACR2__Data11RdMaxCr 3 475198157Srrs#define O_DMACR2__Data12WrMaxCr 15 476198157Srrs#define W_DMACR2__Data12WrMaxCr 3 477198157Srrs#define O_DMACR2__Data12RdMaxCr 12 478198157Srrs#define W_DMACR2__Data12RdMaxCr 3 479198157Srrs#define O_DMACR2__Data13WrMaxCr 9 480198157Srrs#define W_DMACR2__Data13WrMaxCr 3 481198157Srrs#define O_DMACR2__Data13RdMaxCr 6 482198157Srrs#define W_DMACR2__Data13RdMaxCr 3 483198157Srrs#define O_DMACR2__Data14WrMaxCr 3 484198157Srrs#define W_DMACR2__Data14WrMaxCr 3 485198157Srrs#define O_DMACR2__Data14RdMaxCr 0 486198157Srrs#define W_DMACR2__Data14RdMaxCr 3 487198157Srrs#define R_DMACR3 0x203 488198157Srrs#define O_DMACR3__Data15WrMaxCr 27 489198157Srrs#define W_DMACR3__Data15WrMaxCr 3 490198157Srrs#define O_DMACR3__Data15RdMaxCr 24 491198157Srrs#define W_DMACR3__Data15RdMaxCr 3 492198157Srrs#define O_DMACR3__SpClassWrMaxCr 21 493198157Srrs#define W_DMACR3__SpClassWrMaxCr 3 494198157Srrs#define O_DMACR3__SpClassRdMaxCr 18 495198157Srrs#define W_DMACR3__SpClassRdMaxCr 3 496198157Srrs#define O_DMACR3__JumFrInWrMaxCr 15 497198157Srrs#define W_DMACR3__JumFrInWrMaxCr 3 498198157Srrs#define O_DMACR3__JumFrInRdMaxCr 12 499198157Srrs#define W_DMACR3__JumFrInRdMaxCr 3 500198157Srrs#define O_DMACR3__RegFrInWrMaxCr 9 501198157Srrs#define W_DMACR3__RegFrInWrMaxCr 3 502198157Srrs#define O_DMACR3__RegFrInRdMaxCr 6 503198157Srrs#define W_DMACR3__RegFrInRdMaxCr 3 504198157Srrs#define O_DMACR3__FrOutWrMaxCr 3 505198157Srrs#define W_DMACR3__FrOutWrMaxCr 3 506198157Srrs#define O_DMACR3__FrOutRdMaxCr 0 507198157Srrs#define W_DMACR3__FrOutRdMaxCr 3 508198157Srrs#define R_REG_FRIN_SPILL_MEM_START_0 0x204 509198157Srrs#define O_REG_FRIN_SPILL_MEM_START_0__RegFrInSpillMemStart0 0 510198157Srrs#define W_REG_FRIN_SPILL_MEM_START_0__RegFrInSpillMemStart0 32 511198157Srrs#define R_REG_FRIN_SPILL_MEM_START_1 0x205 512198157Srrs#define O_REG_FRIN_SPILL_MEM_START_1__RegFrInSpillMemStart1 0 513198157Srrs#define W_REG_FRIN_SPILL_MEM_START_1__RegFrInSpillMemStart1 3 514198157Srrs#define R_REG_FRIN_SPILL_MEM_SIZE 0x206 515198157Srrs#define O_REG_FRIN_SPILL_MEM_SIZE__RegFrInSpillMemSize 0 516198157Srrs#define W_REG_FRIN_SPILL_MEM_SIZE__RegFrInSpillMemSize 32 517198157Srrs#define R_FROUT_SPILL_MEM_START_0 0x207 518198157Srrs#define O_FROUT_SPILL_MEM_START_0__FrOutSpillMemStart0 0 519198157Srrs#define W_FROUT_SPILL_MEM_START_0__FrOutSpillMemStart0 32 520198157Srrs#define R_FROUT_SPILL_MEM_START_1 0x208 521198157Srrs#define O_FROUT_SPILL_MEM_START_1__FrOutSpillMemStart1 0 522198157Srrs#define W_FROUT_SPILL_MEM_START_1__FrOutSpillMemStart1 3 523198157Srrs#define R_FROUT_SPILL_MEM_SIZE 0x209 524198157Srrs#define O_FROUT_SPILL_MEM_SIZE__FrOutSpillMemSize 0 525198157Srrs#define W_FROUT_SPILL_MEM_SIZE__FrOutSpillMemSize 32 526198157Srrs#define R_CLASS0_SPILL_MEM_START_0 0x20A 527198157Srrs#define O_CLASS0_SPILL_MEM_START_0__Class0SpillMemStart0 0 528198157Srrs#define W_CLASS0_SPILL_MEM_START_0__Class0SpillMemStart0 32 529198157Srrs#define R_CLASS0_SPILL_MEM_START_1 0x20B 530198157Srrs#define O_CLASS0_SPILL_MEM_START_1__Class0SpillMemStart1 0 531198157Srrs#define W_CLASS0_SPILL_MEM_START_1__Class0SpillMemStart1 3 532198157Srrs#define R_CLASS0_SPILL_MEM_SIZE 0x20C 533198157Srrs#define O_CLASS0_SPILL_MEM_SIZE__Class0SpillMemSize 0 534198157Srrs#define W_CLASS0_SPILL_MEM_SIZE__Class0SpillMemSize 32 535198157Srrs#define R_JUMFRIN_SPILL_MEM_START_0 0x20D 536198157Srrs#define O_JUMFRIN_SPILL_MEM_START_0__JumFrInSpillMemStar0 0 537198157Srrs#define W_JUMFRIN_SPILL_MEM_START_0__JumFrInSpillMemStar0 32 538198157Srrs#define R_JUMFRIN_SPILL_MEM_START_1 0x20E 539198157Srrs#define O_JUMFRIN_SPILL_MEM_START_1__JumFrInSpillMemStart1 0 540198157Srrs#define W_JUMFRIN_SPILL_MEM_START_1__JumFrInSpillMemStart1 3 541198157Srrs#define R_JUMFRIN_SPILL_MEM_SIZE 0x20F 542198157Srrs#define O_JUMFRIN_SPILL_MEM_SIZE__JumFrInSpillMemSize 0 543198157Srrs#define W_JUMFRIN_SPILL_MEM_SIZE__JumFrInSpillMemSize 32 544198157Srrs#define R_CLASS1_SPILL_MEM_START_0 0x210 545198157Srrs#define O_CLASS1_SPILL_MEM_START_0__Class1SpillMemStart0 0 546198157Srrs#define W_CLASS1_SPILL_MEM_START_0__Class1SpillMemStart0 32 547198157Srrs#define R_CLASS1_SPILL_MEM_START_1 0x211 548198157Srrs#define O_CLASS1_SPILL_MEM_START_1__Class1SpillMemStart1 0 549198157Srrs#define W_CLASS1_SPILL_MEM_START_1__Class1SpillMemStart1 3 550198157Srrs#define R_CLASS1_SPILL_MEM_SIZE 0x212 551198157Srrs#define O_CLASS1_SPILL_MEM_SIZE__Class1SpillMemSize 0 552198157Srrs#define W_CLASS1_SPILL_MEM_SIZE__Class1SpillMemSize 32 553198157Srrs#define R_CLASS2_SPILL_MEM_START_0 0x213 554198157Srrs#define O_CLASS2_SPILL_MEM_START_0__Class2SpillMemStart0 0 555198157Srrs#define W_CLASS2_SPILL_MEM_START_0__Class2SpillMemStart0 32 556198157Srrs#define R_CLASS2_SPILL_MEM_START_1 0x214 557198157Srrs#define O_CLASS2_SPILL_MEM_START_1__Class2SpillMemStart1 0 558198157Srrs#define W_CLASS2_SPILL_MEM_START_1__Class2SpillMemStart1 3 559198157Srrs#define R_CLASS2_SPILL_MEM_SIZE 0x215 560198157Srrs#define O_CLASS2_SPILL_MEM_SIZE__Class2SpillMemSize 0 561198157Srrs#define W_CLASS2_SPILL_MEM_SIZE__Class2SpillMemSize 32 562198157Srrs#define R_CLASS3_SPILL_MEM_START_0 0x216 563198157Srrs#define O_CLASS3_SPILL_MEM_START_0__Class3SpillMemStart0 0 564198157Srrs#define W_CLASS3_SPILL_MEM_START_0__Class3SpillMemStart0 32 565198157Srrs#define R_CLASS3_SPILL_MEM_START_1 0x217 566198157Srrs#define O_CLASS3_SPILL_MEM_START_1__Class3SpillMemStart1 0 567198157Srrs#define W_CLASS3_SPILL_MEM_START_1__Class3SpillMemStart1 3 568198157Srrs#define R_CLASS3_SPILL_MEM_SIZE 0x218 569198157Srrs#define O_CLASS3_SPILL_MEM_SIZE__Class3SpillMemSize 0 570198157Srrs#define W_CLASS3_SPILL_MEM_SIZE__Class3SpillMemSize 32 571198157Srrs#define R_REG_FRIN1_SPILL_MEM_START_0 0x219 572198157Srrs#define R_REG_FRIN1_SPILL_MEM_START_1 0x21a 573198157Srrs#define R_REG_FRIN1_SPILL_MEM_SIZE 0x21b 574198157Srrs#define R_SPIHNGY0 0x219 575198157Srrs#define O_SPIHNGY0__EG_HNGY_THRESH_0 24 576198157Srrs#define W_SPIHNGY0__EG_HNGY_THRESH_0 7 577198157Srrs#define O_SPIHNGY0__EG_HNGY_THRESH_1 16 578198157Srrs#define W_SPIHNGY0__EG_HNGY_THRESH_1 7 579198157Srrs#define O_SPIHNGY0__EG_HNGY_THRESH_2 8 580198157Srrs#define W_SPIHNGY0__EG_HNGY_THRESH_2 7 581198157Srrs#define O_SPIHNGY0__EG_HNGY_THRESH_3 0 582198157Srrs#define W_SPIHNGY0__EG_HNGY_THRESH_3 7 583198157Srrs#define R_SPIHNGY1 0x21A 584198157Srrs#define O_SPIHNGY1__EG_HNGY_THRESH_4 24 585198157Srrs#define W_SPIHNGY1__EG_HNGY_THRESH_4 7 586198157Srrs#define O_SPIHNGY1__EG_HNGY_THRESH_5 16 587198157Srrs#define W_SPIHNGY1__EG_HNGY_THRESH_5 7 588198157Srrs#define O_SPIHNGY1__EG_HNGY_THRESH_6 8 589198157Srrs#define W_SPIHNGY1__EG_HNGY_THRESH_6 7 590198157Srrs#define O_SPIHNGY1__EG_HNGY_THRESH_7 0 591198157Srrs#define W_SPIHNGY1__EG_HNGY_THRESH_7 7 592198157Srrs#define R_SPIHNGY2 0x21B 593198157Srrs#define O_SPIHNGY2__EG_HNGY_THRESH_8 24 594198157Srrs#define W_SPIHNGY2__EG_HNGY_THRESH_8 7 595198157Srrs#define O_SPIHNGY2__EG_HNGY_THRESH_9 16 596198157Srrs#define W_SPIHNGY2__EG_HNGY_THRESH_9 7 597198157Srrs#define O_SPIHNGY2__EG_HNGY_THRESH_10 8 598198157Srrs#define W_SPIHNGY2__EG_HNGY_THRESH_10 7 599198157Srrs#define O_SPIHNGY2__EG_HNGY_THRESH_11 0 600198157Srrs#define W_SPIHNGY2__EG_HNGY_THRESH_11 7 601198157Srrs#define R_SPIHNGY3 0x21C 602198157Srrs#define O_SPIHNGY3__EG_HNGY_THRESH_12 24 603198157Srrs#define W_SPIHNGY3__EG_HNGY_THRESH_12 7 604198157Srrs#define O_SPIHNGY3__EG_HNGY_THRESH_13 16 605198157Srrs#define W_SPIHNGY3__EG_HNGY_THRESH_13 7 606198157Srrs#define O_SPIHNGY3__EG_HNGY_THRESH_14 8 607198157Srrs#define W_SPIHNGY3__EG_HNGY_THRESH_14 7 608198157Srrs#define O_SPIHNGY3__EG_HNGY_THRESH_15 0 609198157Srrs#define W_SPIHNGY3__EG_HNGY_THRESH_15 7 610198157Srrs#define R_SPISTRV0 0x21D 611198157Srrs#define O_SPISTRV0__EG_STRV_THRESH_0 24 612198157Srrs#define W_SPISTRV0__EG_STRV_THRESH_0 7 613198157Srrs#define O_SPISTRV0__EG_STRV_THRESH_1 16 614198157Srrs#define W_SPISTRV0__EG_STRV_THRESH_1 7 615198157Srrs#define O_SPISTRV0__EG_STRV_THRESH_2 8 616198157Srrs#define W_SPISTRV0__EG_STRV_THRESH_2 7 617198157Srrs#define O_SPISTRV0__EG_STRV_THRESH_3 0 618198157Srrs#define W_SPISTRV0__EG_STRV_THRESH_3 7 619198157Srrs#define R_SPISTRV1 0x21E 620198157Srrs#define O_SPISTRV1__EG_STRV_THRESH_4 24 621198157Srrs#define W_SPISTRV1__EG_STRV_THRESH_4 7 622198157Srrs#define O_SPISTRV1__EG_STRV_THRESH_5 16 623198157Srrs#define W_SPISTRV1__EG_STRV_THRESH_5 7 624198157Srrs#define O_SPISTRV1__EG_STRV_THRESH_6 8 625198157Srrs#define W_SPISTRV1__EG_STRV_THRESH_6 7 626198157Srrs#define O_SPISTRV1__EG_STRV_THRESH_7 0 627198157Srrs#define W_SPISTRV1__EG_STRV_THRESH_7 7 628198157Srrs#define R_SPISTRV2 0x21F 629198157Srrs#define O_SPISTRV2__EG_STRV_THRESH_8 24 630198157Srrs#define W_SPISTRV2__EG_STRV_THRESH_8 7 631198157Srrs#define O_SPISTRV2__EG_STRV_THRESH_9 16 632198157Srrs#define W_SPISTRV2__EG_STRV_THRESH_9 7 633198157Srrs#define O_SPISTRV2__EG_STRV_THRESH_10 8 634198157Srrs#define W_SPISTRV2__EG_STRV_THRESH_10 7 635198157Srrs#define O_SPISTRV2__EG_STRV_THRESH_11 0 636198157Srrs#define W_SPISTRV2__EG_STRV_THRESH_11 7 637198157Srrs#define R_SPISTRV3 0x220 638198157Srrs#define O_SPISTRV3__EG_STRV_THRESH_12 24 639198157Srrs#define W_SPISTRV3__EG_STRV_THRESH_12 7 640198157Srrs#define O_SPISTRV3__EG_STRV_THRESH_13 16 641198157Srrs#define W_SPISTRV3__EG_STRV_THRESH_13 7 642198157Srrs#define O_SPISTRV3__EG_STRV_THRESH_14 8 643198157Srrs#define W_SPISTRV3__EG_STRV_THRESH_14 7 644198157Srrs#define O_SPISTRV3__EG_STRV_THRESH_15 0 645198157Srrs#define W_SPISTRV3__EG_STRV_THRESH_15 7 646198157Srrs#define R_TXDATAFIFO0 0x221 647198157Srrs#define O_TXDATAFIFO0__Tx0DataFifoStart 24 648198157Srrs#define W_TXDATAFIFO0__Tx0DataFifoStart 7 649198157Srrs#define O_TXDATAFIFO0__Tx0DataFifoSize 16 650198157Srrs#define W_TXDATAFIFO0__Tx0DataFifoSize 7 651198157Srrs#define O_TXDATAFIFO0__Tx1DataFifoStart 8 652198157Srrs#define W_TXDATAFIFO0__Tx1DataFifoStart 7 653198157Srrs#define O_TXDATAFIFO0__Tx1DataFifoSize 0 654198157Srrs#define W_TXDATAFIFO0__Tx1DataFifoSize 7 655198157Srrs#define R_TXDATAFIFO1 0x222 656198157Srrs#define O_TXDATAFIFO1__Tx2DataFifoStart 24 657198157Srrs#define W_TXDATAFIFO1__Tx2DataFifoStart 7 658198157Srrs#define O_TXDATAFIFO1__Tx2DataFifoSize 16 659198157Srrs#define W_TXDATAFIFO1__Tx2DataFifoSize 7 660198157Srrs#define O_TXDATAFIFO1__Tx3DataFifoStart 8 661198157Srrs#define W_TXDATAFIFO1__Tx3DataFifoStart 7 662198157Srrs#define O_TXDATAFIFO1__Tx3DataFifoSize 0 663198157Srrs#define W_TXDATAFIFO1__Tx3DataFifoSize 7 664198157Srrs#define R_TXDATAFIFO2 0x223 665198157Srrs#define O_TXDATAFIFO2__Tx4DataFifoStart 24 666198157Srrs#define W_TXDATAFIFO2__Tx4DataFifoStart 7 667198157Srrs#define O_TXDATAFIFO2__Tx4DataFifoSize 16 668198157Srrs#define W_TXDATAFIFO2__Tx4DataFifoSize 7 669198157Srrs#define O_TXDATAFIFO2__Tx5DataFifoStart 8 670198157Srrs#define W_TXDATAFIFO2__Tx5DataFifoStart 7 671198157Srrs#define O_TXDATAFIFO2__Tx5DataFifoSize 0 672198157Srrs#define W_TXDATAFIFO2__Tx5DataFifoSize 7 673198157Srrs#define R_TXDATAFIFO3 0x224 674198157Srrs#define O_TXDATAFIFO3__Tx6DataFifoStart 24 675198157Srrs#define W_TXDATAFIFO3__Tx6DataFifoStart 7 676198157Srrs#define O_TXDATAFIFO3__Tx6DataFifoSize 16 677198157Srrs#define W_TXDATAFIFO3__Tx6DataFifoSize 7 678198157Srrs#define O_TXDATAFIFO3__Tx7DataFifoStart 8 679198157Srrs#define W_TXDATAFIFO3__Tx7DataFifoStart 7 680198157Srrs#define O_TXDATAFIFO3__Tx7DataFifoSize 0 681198157Srrs#define W_TXDATAFIFO3__Tx7DataFifoSize 7 682198157Srrs#define R_TXDATAFIFO4 0x225 683198157Srrs#define O_TXDATAFIFO4__Tx8DataFifoStart 24 684198157Srrs#define W_TXDATAFIFO4__Tx8DataFifoStart 7 685198157Srrs#define O_TXDATAFIFO4__Tx8DataFifoSize 16 686198157Srrs#define W_TXDATAFIFO4__Tx8DataFifoSize 7 687198157Srrs#define O_TXDATAFIFO4__Tx9DataFifoStart 8 688198157Srrs#define W_TXDATAFIFO4__Tx9DataFifoStart 7 689198157Srrs#define O_TXDATAFIFO4__Tx9DataFifoSize 0 690198157Srrs#define W_TXDATAFIFO4__Tx9DataFifoSize 7 691198157Srrs#define R_TXDATAFIFO5 0x226 692198157Srrs#define O_TXDATAFIFO5__Tx10DataFifoStart 24 693198157Srrs#define W_TXDATAFIFO5__Tx10DataFifoStart 7 694198157Srrs#define O_TXDATAFIFO5__Tx10DataFifoSize 16 695198157Srrs#define W_TXDATAFIFO5__Tx10DataFifoSize 7 696198157Srrs#define O_TXDATAFIFO5__Tx11DataFifoStart 8 697198157Srrs#define W_TXDATAFIFO5__Tx11DataFifoStart 7 698198157Srrs#define O_TXDATAFIFO5__Tx11DataFifoSize 0 699198157Srrs#define W_TXDATAFIFO5__Tx11DataFifoSize 7 700198157Srrs#define R_TXDATAFIFO6 0x227 701198157Srrs#define O_TXDATAFIFO6__Tx12DataFifoStart 24 702198157Srrs#define W_TXDATAFIFO6__Tx12DataFifoStart 7 703198157Srrs#define O_TXDATAFIFO6__Tx12DataFifoSize 16 704198157Srrs#define W_TXDATAFIFO6__Tx12DataFifoSize 7 705198157Srrs#define O_TXDATAFIFO6__Tx13DataFifoStart 8 706198157Srrs#define W_TXDATAFIFO6__Tx13DataFifoStart 7 707198157Srrs#define O_TXDATAFIFO6__Tx13DataFifoSize 0 708198157Srrs#define W_TXDATAFIFO6__Tx13DataFifoSize 7 709198157Srrs#define R_TXDATAFIFO7 0x228 710198157Srrs#define O_TXDATAFIFO7__Tx14DataFifoStart 24 711198157Srrs#define W_TXDATAFIFO7__Tx14DataFifoStart 7 712198157Srrs#define O_TXDATAFIFO7__Tx14DataFifoSize 16 713198157Srrs#define W_TXDATAFIFO7__Tx14DataFifoSize 7 714198157Srrs#define O_TXDATAFIFO7__Tx15DataFifoStart 8 715198157Srrs#define W_TXDATAFIFO7__Tx15DataFifoStart 7 716198157Srrs#define O_TXDATAFIFO7__Tx15DataFifoSize 0 717198157Srrs#define W_TXDATAFIFO7__Tx15DataFifoSize 7 718198157Srrs#define R_RXDATAFIFO0 0x229 719198157Srrs#define O_RXDATAFIFO0__Rx0DataFifoStart 24 720198157Srrs#define W_RXDATAFIFO0__Rx0DataFifoStart 7 721198157Srrs#define O_RXDATAFIFO0__Rx0DataFifoSize 16 722198157Srrs#define W_RXDATAFIFO0__Rx0DataFifoSize 7 723198157Srrs#define O_RXDATAFIFO0__Rx1DataFifoStart 8 724198157Srrs#define W_RXDATAFIFO0__Rx1DataFifoStart 7 725198157Srrs#define O_RXDATAFIFO0__Rx1DataFifoSize 0 726198157Srrs#define W_RXDATAFIFO0__Rx1DataFifoSize 7 727198157Srrs#define R_RXDATAFIFO1 0x22A 728198157Srrs#define O_RXDATAFIFO1__Rx2DataFifoStart 24 729198157Srrs#define W_RXDATAFIFO1__Rx2DataFifoStart 7 730198157Srrs#define O_RXDATAFIFO1__Rx2DataFifoSize 16 731198157Srrs#define W_RXDATAFIFO1__Rx2DataFifoSize 7 732198157Srrs#define O_RXDATAFIFO1__Rx3DataFifoStart 8 733198157Srrs#define W_RXDATAFIFO1__Rx3DataFifoStart 7 734198157Srrs#define O_RXDATAFIFO1__Rx3DataFifoSize 0 735198157Srrs#define W_RXDATAFIFO1__Rx3DataFifoSize 7 736198157Srrs#define R_RXDATAFIFO2 0x22B 737198157Srrs#define O_RXDATAFIFO2__Rx4DataFifoStart 24 738198157Srrs#define W_RXDATAFIFO2__Rx4DataFifoStart 7 739198157Srrs#define O_RXDATAFIFO2__Rx4DataFifoSize 16 740198157Srrs#define W_RXDATAFIFO2__Rx4DataFifoSize 7 741198157Srrs#define O_RXDATAFIFO2__Rx5DataFifoStart 8 742198157Srrs#define W_RXDATAFIFO2__Rx5DataFifoStart 7 743198157Srrs#define O_RXDATAFIFO2__Rx5DataFifoSize 0 744198157Srrs#define W_RXDATAFIFO2__Rx5DataFifoSize 7 745198157Srrs#define R_RXDATAFIFO3 0x22C 746198157Srrs#define O_RXDATAFIFO3__Rx6DataFifoStart 24 747198157Srrs#define W_RXDATAFIFO3__Rx6DataFifoStart 7 748198157Srrs#define O_RXDATAFIFO3__Rx6DataFifoSize 16 749198157Srrs#define W_RXDATAFIFO3__Rx6DataFifoSize 7 750198157Srrs#define O_RXDATAFIFO3__Rx7DataFifoStart 8 751198157Srrs#define W_RXDATAFIFO3__Rx7DataFifoStart 7 752198157Srrs#define O_RXDATAFIFO3__Rx7DataFifoSize 0 753198157Srrs#define W_RXDATAFIFO3__Rx7DataFifoSize 7 754198157Srrs#define R_RXDATAFIFO4 0x22D 755198157Srrs#define O_RXDATAFIFO4__Rx8DataFifoStart 24 756198157Srrs#define W_RXDATAFIFO4__Rx8DataFifoStart 7 757198157Srrs#define O_RXDATAFIFO4__Rx8DataFifoSize 16 758198157Srrs#define W_RXDATAFIFO4__Rx8DataFifoSize 7 759198157Srrs#define O_RXDATAFIFO4__Rx9DataFifoStart 8 760198157Srrs#define W_RXDATAFIFO4__Rx9DataFifoStart 7 761198157Srrs#define O_RXDATAFIFO4__Rx9DataFifoSize 0 762198157Srrs#define W_RXDATAFIFO4__Rx9DataFifoSize 7 763198157Srrs#define R_RXDATAFIFO5 0x22E 764198157Srrs#define O_RXDATAFIFO5__Rx10DataFifoStart 24 765198157Srrs#define W_RXDATAFIFO5__Rx10DataFifoStart 7 766198157Srrs#define O_RXDATAFIFO5__Rx10DataFifoSize 16 767198157Srrs#define W_RXDATAFIFO5__Rx10DataFifoSize 7 768198157Srrs#define O_RXDATAFIFO5__Rx11DataFifoStart 8 769198157Srrs#define W_RXDATAFIFO5__Rx11DataFifoStart 7 770198157Srrs#define O_RXDATAFIFO5__Rx11DataFifoSize 0 771198157Srrs#define W_RXDATAFIFO5__Rx11DataFifoSize 7 772198157Srrs#define R_RXDATAFIFO6 0x22F 773198157Srrs#define O_RXDATAFIFO6__Rx12DataFifoStart 24 774198157Srrs#define W_RXDATAFIFO6__Rx12DataFifoStart 7 775198157Srrs#define O_RXDATAFIFO6__Rx12DataFifoSize 16 776198157Srrs#define W_RXDATAFIFO6__Rx12DataFifoSize 7 777198157Srrs#define O_RXDATAFIFO6__Rx13DataFifoStart 8 778198157Srrs#define W_RXDATAFIFO6__Rx13DataFifoStart 7 779198157Srrs#define O_RXDATAFIFO6__Rx13DataFifoSize 0 780198157Srrs#define W_RXDATAFIFO6__Rx13DataFifoSize 7 781198157Srrs#define R_RXDATAFIFO7 0x230 782198157Srrs#define O_RXDATAFIFO7__Rx14DataFifoStart 24 783198157Srrs#define W_RXDATAFIFO7__Rx14DataFifoStart 7 784198157Srrs#define O_RXDATAFIFO7__Rx14DataFifoSize 16 785198157Srrs#define W_RXDATAFIFO7__Rx14DataFifoSize 7 786198157Srrs#define O_RXDATAFIFO7__Rx15DataFifoStart 8 787198157Srrs#define W_RXDATAFIFO7__Rx15DataFifoStart 7 788198157Srrs#define O_RXDATAFIFO7__Rx15DataFifoSize 0 789198157Srrs#define W_RXDATAFIFO7__Rx15DataFifoSize 7 790198157Srrs#define R_XGMACPADCALIBRATION 0x231 791198157Srrs#define R_FREEQCARVE 0x233 792198157Srrs#define R_SPI4STATICDELAY0 0x240 793198157Srrs#define O_SPI4STATICDELAY0__DataLine7 28 794198157Srrs#define W_SPI4STATICDELAY0__DataLine7 4 795198157Srrs#define O_SPI4STATICDELAY0__DataLine6 24 796198157Srrs#define W_SPI4STATICDELAY0__DataLine6 4 797198157Srrs#define O_SPI4STATICDELAY0__DataLine5 20 798198157Srrs#define W_SPI4STATICDELAY0__DataLine5 4 799198157Srrs#define O_SPI4STATICDELAY0__DataLine4 16 800198157Srrs#define W_SPI4STATICDELAY0__DataLine4 4 801198157Srrs#define O_SPI4STATICDELAY0__DataLine3 12 802198157Srrs#define W_SPI4STATICDELAY0__DataLine3 4 803198157Srrs#define O_SPI4STATICDELAY0__DataLine2 8 804198157Srrs#define W_SPI4STATICDELAY0__DataLine2 4 805198157Srrs#define O_SPI4STATICDELAY0__DataLine1 4 806198157Srrs#define W_SPI4STATICDELAY0__DataLine1 4 807198157Srrs#define O_SPI4STATICDELAY0__DataLine0 0 808198157Srrs#define W_SPI4STATICDELAY0__DataLine0 4 809198157Srrs#define R_SPI4STATICDELAY1 0x241 810198157Srrs#define O_SPI4STATICDELAY1__DataLine15 28 811198157Srrs#define W_SPI4STATICDELAY1__DataLine15 4 812198157Srrs#define O_SPI4STATICDELAY1__DataLine14 24 813198157Srrs#define W_SPI4STATICDELAY1__DataLine14 4 814198157Srrs#define O_SPI4STATICDELAY1__DataLine13 20 815198157Srrs#define W_SPI4STATICDELAY1__DataLine13 4 816198157Srrs#define O_SPI4STATICDELAY1__DataLine12 16 817198157Srrs#define W_SPI4STATICDELAY1__DataLine12 4 818198157Srrs#define O_SPI4STATICDELAY1__DataLine11 12 819198157Srrs#define W_SPI4STATICDELAY1__DataLine11 4 820198157Srrs#define O_SPI4STATICDELAY1__DataLine10 8 821198157Srrs#define W_SPI4STATICDELAY1__DataLine10 4 822198157Srrs#define O_SPI4STATICDELAY1__DataLine9 4 823198157Srrs#define W_SPI4STATICDELAY1__DataLine9 4 824198157Srrs#define O_SPI4STATICDELAY1__DataLine8 0 825198157Srrs#define W_SPI4STATICDELAY1__DataLine8 4 826198157Srrs#define R_SPI4STATICDELAY2 0x242 827198157Srrs#define O_SPI4STATICDELAY0__TxStat1 8 828198157Srrs#define W_SPI4STATICDELAY0__TxStat1 4 829198157Srrs#define O_SPI4STATICDELAY0__TxStat0 4 830198157Srrs#define W_SPI4STATICDELAY0__TxStat0 4 831198157Srrs#define O_SPI4STATICDELAY0__RxControl 0 832198157Srrs#define W_SPI4STATICDELAY0__RxControl 4 833198157Srrs#define R_SPI4CONTROL 0x243 834198157Srrs#define O_SPI4CONTROL__StaticDelay 2 835198157Srrs#define O_SPI4CONTROL__LVDS_LVTTL 1 836198157Srrs#define O_SPI4CONTROL__SPI4Enable 0 837198157Srrs#define R_CLASSWATERMARKS 0x244 838198157Srrs#define O_CLASSWATERMARKS__Class0Watermark 24 839198157Srrs#define W_CLASSWATERMARKS__Class0Watermark 5 840198157Srrs#define O_CLASSWATERMARKS__Class1Watermark 16 841198157Srrs#define W_CLASSWATERMARKS__Class1Watermark 5 842198157Srrs#define O_CLASSWATERMARKS__Class3Watermark 0 843198157Srrs#define W_CLASSWATERMARKS__Class3Watermark 5 844198157Srrs#define R_RXWATERMARKS1 0x245 845198157Srrs#define O_RXWATERMARKS__Rx0DataWatermark 24 846198157Srrs#define W_RXWATERMARKS__Rx0DataWatermark 7 847198157Srrs#define O_RXWATERMARKS__Rx1DataWatermark 16 848198157Srrs#define W_RXWATERMARKS__Rx1DataWatermark 7 849198157Srrs#define O_RXWATERMARKS__Rx3DataWatermark 0 850198157Srrs#define W_RXWATERMARKS__Rx3DataWatermark 7 851198157Srrs#define R_RXWATERMARKS2 0x246 852198157Srrs#define O_RXWATERMARKS__Rx4DataWatermark 24 853198157Srrs#define W_RXWATERMARKS__Rx4DataWatermark 7 854198157Srrs#define O_RXWATERMARKS__Rx5DataWatermark 16 855198157Srrs#define W_RXWATERMARKS__Rx5DataWatermark 7 856198157Srrs#define O_RXWATERMARKS__Rx6DataWatermark 8 857198157Srrs#define W_RXWATERMARKS__Rx6DataWatermark 7 858198157Srrs#define O_RXWATERMARKS__Rx7DataWatermark 0 859198157Srrs#define W_RXWATERMARKS__Rx7DataWatermark 7 860198157Srrs#define R_RXWATERMARKS3 0x247 861198157Srrs#define O_RXWATERMARKS__Rx8DataWatermark 24 862198157Srrs#define W_RXWATERMARKS__Rx8DataWatermark 7 863198157Srrs#define O_RXWATERMARKS__Rx9DataWatermark 16 864198157Srrs#define W_RXWATERMARKS__Rx9DataWatermark 7 865198157Srrs#define O_RXWATERMARKS__Rx10DataWatermark 8 866198157Srrs#define W_RXWATERMARKS__Rx10DataWatermark 7 867198157Srrs#define O_RXWATERMARKS__Rx11DataWatermark 0 868198157Srrs#define W_RXWATERMARKS__Rx11DataWatermark 7 869198157Srrs#define R_RXWATERMARKS4 0x248 870198157Srrs#define O_RXWATERMARKS__Rx12DataWatermark 24 871198157Srrs#define W_RXWATERMARKS__Rx12DataWatermark 7 872198157Srrs#define O_RXWATERMARKS__Rx13DataWatermark 16 873198157Srrs#define W_RXWATERMARKS__Rx13DataWatermark 7 874198157Srrs#define O_RXWATERMARKS__Rx14DataWatermark 8 875198157Srrs#define W_RXWATERMARKS__Rx14DataWatermark 7 876198157Srrs#define O_RXWATERMARKS__Rx15DataWatermark 0 877198157Srrs#define W_RXWATERMARKS__Rx15DataWatermark 7 878198157Srrs#define R_FREEWATERMARKS 0x249 879198157Srrs#define O_FREEWATERMARKS__FreeOutWatermark 16 880198157Srrs#define W_FREEWATERMARKS__FreeOutWatermark 16 881198157Srrs#define O_FREEWATERMARKS__JumFrWatermark 8 882198157Srrs#define W_FREEWATERMARKS__JumFrWatermark 7 883198157Srrs#define O_FREEWATERMARKS__RegFrWatermark 0 884198157Srrs#define W_FREEWATERMARKS__RegFrWatermark 7 885198157Srrs#define R_EGRESSFIFOCARVINGSLOTS 0x24a 886198157Srrs 887198157Srrs#define CTRL_RES0 0 888198157Srrs#define CTRL_RES1 1 889198157Srrs#define CTRL_REG_FREE 2 890198157Srrs#define CTRL_JUMBO_FREE 3 891198157Srrs#define CTRL_CONT 4 892198157Srrs#define CTRL_EOP 5 893198157Srrs#define CTRL_START 6 894198157Srrs#define CTRL_SNGL 7 895198157Srrs 896198157Srrs#define CTRL_B0_NOT_EOP 0 897198157Srrs#define CTRL_B0_EOP 1 898198157Srrs 899198157Srrs#define R_ROUND_ROBIN_TABLE 0 900198157Srrs#define R_PDE_CLASS_0 0x300 901198157Srrs#define R_PDE_CLASS_1 0x302 902198157Srrs#define R_PDE_CLASS_2 0x304 903198157Srrs#define R_PDE_CLASS_3 0x306 904198157Srrs 905198157Srrs#define R_MSG_TX_THRESHOLD 0x308 906198157Srrs 907198157Srrs#define R_GMAC_JFR0_BUCKET_SIZE 0x320 908198157Srrs#define R_GMAC_RFR0_BUCKET_SIZE 0x321 909198157Srrs#define R_GMAC_TX0_BUCKET_SIZE 0x322 910198157Srrs#define R_GMAC_TX1_BUCKET_SIZE 0x323 911198157Srrs#define R_GMAC_TX2_BUCKET_SIZE 0x324 912198157Srrs#define R_GMAC_TX3_BUCKET_SIZE 0x325 913198157Srrs#define R_GMAC_JFR1_BUCKET_SIZE 0x326 914198157Srrs#define R_GMAC_RFR1_BUCKET_SIZE 0x327 915198157Srrs 916198157Srrs#define R_XGS_TX0_BUCKET_SIZE 0x320 917198157Srrs#define R_XGS_TX1_BUCKET_SIZE 0x321 918198157Srrs#define R_XGS_TX2_BUCKET_SIZE 0x322 919198157Srrs#define R_XGS_TX3_BUCKET_SIZE 0x323 920198157Srrs#define R_XGS_TX4_BUCKET_SIZE 0x324 921198157Srrs#define R_XGS_TX5_BUCKET_SIZE 0x325 922198157Srrs#define R_XGS_TX6_BUCKET_SIZE 0x326 923198157Srrs#define R_XGS_TX7_BUCKET_SIZE 0x327 924198157Srrs#define R_XGS_TX8_BUCKET_SIZE 0x328 925198157Srrs#define R_XGS_TX9_BUCKET_SIZE 0x329 926198157Srrs#define R_XGS_TX10_BUCKET_SIZE 0x32A 927198157Srrs#define R_XGS_TX11_BUCKET_SIZE 0x32B 928198157Srrs#define R_XGS_TX12_BUCKET_SIZE 0x32C 929198157Srrs#define R_XGS_TX13_BUCKET_SIZE 0x32D 930198157Srrs#define R_XGS_TX14_BUCKET_SIZE 0x32E 931198157Srrs#define R_XGS_TX15_BUCKET_SIZE 0x32F 932198157Srrs#define R_XGS_JFR_BUCKET_SIZE 0x330 933198157Srrs#define R_XGS_RFR_BUCKET_SIZE 0x331 934198157Srrs 935198157Srrs#define R_CC_CPU0_0 0x380 936198157Srrs#define R_CC_CPU1_0 0x388 937198157Srrs#define R_CC_CPU2_0 0x390 938198157Srrs#define R_CC_CPU3_0 0x398 939198157Srrs#define R_CC_CPU4_0 0x3a0 940198157Srrs#define R_CC_CPU5_0 0x3a8 941198157Srrs#define R_CC_CPU6_0 0x3b0 942198157Srrs#define R_CC_CPU7_0 0x3b8 943198157Srrs 944198608Srrstypedef enum { 945198608Srrs xlr_mac_speed_10, xlr_mac_speed_100, 946198608Srrs xlr_mac_speed_1000, xlr_mac_speed_rsvd 947198626Srrs} xlr_mac_speed_t; 948198608Srrs 949198608Srrstypedef enum { 950198608Srrs xlr_mac_duplex_auto, xlr_mac_duplex_half, 951198608Srrs xlr_mac_duplex_full 952198626Srrs} xlr_mac_duplex_t; 953198608Srrs 954198608Srrstypedef enum { 955198608Srrs xlr_mac_link_down, 956198608Srrs xlr_mac_link_up, 957198626Srrs} xlr_mac_link_t; 958198608Srrs 959198608Srrstypedef enum { 960198608Srrs xlr_mac_fc_auto, xlr_mac_fc_disabled, xlr_mac_fc_frame, 961198608Srrs xlr_mac_fc_collision, xlr_mac_fc_carrier 962198626Srrs} xlr_mac_fc_t; 963198608Srrs 964198608Srrs/* static int mac_frin_to_be_sent_thr[8]; */ 965198608Srrs 966198608Srrsenum { 967198608Srrs PORT_TX, 968198608Srrs PORT_TX_COMPLETE, 969198608Srrs PORT_STARTQ, 970198608Srrs PORT_STOPQ, 971198608Srrs PORT_START_DEV_STATE, 972198608Srrs PORT_STOP_DEV_STATE, 973198608Srrs}; 974198608Srrs 975198608Srrsstruct rge_softc_stats { 976212759Sjchandra unsigned int rx_frames; 977212759Sjchandra unsigned int tx_frames; 978212759Sjchandra unsigned int rx_packets; 979212759Sjchandra unsigned int rx_bytes; 980212759Sjchandra unsigned int tx_packets; 981212759Sjchandra unsigned int tx_bytes; 982198608Srrs}; 983198608Srrs 984198608Srrsstruct driver_data { 985198608Srrs 986198608Srrs /* 987198608Srrs * Let these be the first fields in this structure the structure is 988198608Srrs * cacheline aligned when allocated in init_etherdev 989198608Srrs */ 990198608Srrs struct fr_desc *frin_spill; 991198608Srrs struct fr_desc *frout_spill; 992198608Srrs union rx_tx_desc *class_0_spill; 993198608Srrs union rx_tx_desc *class_1_spill; 994198608Srrs union rx_tx_desc *class_2_spill; 995198608Srrs union rx_tx_desc *class_3_spill; 996198626Srrs int spill_configured; 997198608Srrs 998198608Srrs struct rge_softc *sc; /* pointer to freebsd device soft-pointer */ 999198608Srrs struct rge_softc_stats stats; 1000198626Srrs struct mtx lock; 1001198608Srrs 1002198626Srrs xlr_reg_t *mmio; 1003198626Srrs xlr_reg_t *mii_mmio; 1004198626Srrs xlr_reg_t *pcs_mmio; 1005198626Srrs xlr_reg_t *serdes_mmio; 1006198608Srrs 1007198626Srrs int txbucket; 1008198626Srrs int rfrbucket; 1009198608Srrs 1010198626Srrs int phy_oldbmsr; 1011198626Srrs int phy_oldanlpar; 1012198626Srrs int phy_oldk1stsr; 1013198626Srrs int phy_oldlinkstat; 1014198626Srrs unsigned char phys_addr[2]; 1015198608Srrs 1016198626Srrs xlr_mac_speed_t speed; /* current speed */ 1017198608Srrs xlr_mac_duplex_t duplex;/* current duplex */ 1018198626Srrs xlr_mac_link_t link; /* current link */ 1019198626Srrs xlr_mac_fc_t flow_ctrl; /* current flow control setting */ 1020198626Srrs int advertising; 1021198608Srrs 1022198626Srrs int id; 1023198626Srrs int type; 1024198626Srrs int mode; 1025198626Srrs int instance; 1026198626Srrs int phy_addr; 1027198626Srrs int frin_to_be_sent[8]; 1028198626Srrs int init_frin_desc; 1029198608Srrs}; 1030198608Srrs 1031198608Srrsstruct rge_softc { 1032198626Srrs int unit; 1033198626Srrs int irq; 1034198626Srrs unsigned char dev_addr[6]; 1035198626Srrs unsigned long base_addr; 1036198626Srrs unsigned long mem_end; 1037198626Srrs struct ifnet *rge_ifp; /* interface info */ 1038198626Srrs device_t rge_dev; 1039198626Srrs int mtu; 1040198626Srrs int flags; 1041198608Srrs struct driver_data priv; 1042198626Srrs struct mtx rge_mtx; 1043198626Srrs device_t rge_miibus; 1044198626Srrs struct mii_data rge_mii;/* MII/media information */ 1045198608Srrs bus_space_handle_t rge_bhandle; 1046198626Srrs bus_space_tag_t rge_btag; 1047198626Srrs void *rge_intrhand; 1048198626Srrs struct resource rge_irq; 1049198608Srrs struct resource *rge_res; 1050198626Srrs struct ifmedia rge_ifmedia; /* TBI media info */ 1051198626Srrs int rge_if_flags; 1052198626Srrs int rge_link; /* link state */ 1053198626Srrs int rge_link_evt; /* pending link event */ 1054198626Srrs struct callout rge_stat_ch; 1055198626Srrs void (*xmit) (struct ifnet *); 1056198626Srrs void (*stop) (struct rge_softc *); 1057198626Srrs int (*ioctl) (struct ifnet *, u_long, caddr_t); 1058198608Srrs struct rge_softc_stats *(*get_stats) (struct rge_softc *); 1059198608Srrs int active; 1060198608Srrs int link_up; 1061198608Srrs}; 1062198608Srrs 1063198157Srrsstruct size_1_desc { 1064198626Srrs uint64_t entry0; 1065198157Srrs}; 1066198157Srrs 1067198157Srrsstruct size_2_desc { 1068198626Srrs uint64_t entry0; 1069198626Srrs uint64_t entry1; 1070198157Srrs}; 1071198157Srrs 1072198157Srrsstruct size_3_desc { 1073198626Srrs uint64_t entry0; 1074198626Srrs uint64_t entry1; 1075198626Srrs uint64_t entry2; 1076198157Srrs}; 1077198157Srrs 1078198157Srrsstruct size_4_desc { 1079198626Srrs uint64_t entry0; 1080198626Srrs uint64_t entry1; 1081198626Srrs uint64_t entry2; 1082198626Srrs uint64_t entry3; 1083198157Srrs}; 1084198157Srrs 1085198157Srrsstruct fr_desc { 1086198157Srrs struct size_1_desc d1; 1087198157Srrs}; 1088198157Srrs 1089198157Srrsunion rx_tx_desc { 1090198157Srrs struct size_2_desc d2; 1091198157Srrs /* struct size_3_desc d3; */ 1092198157Srrs /* struct size_4_desc d4; */ 1093198157Srrs}; 1094198157Srrs 1095198157Srrs 1096198157Srrsextern unsigned char xlr_base_mac_addr[]; 1097198157Srrs 1098198157Srrs#endif 1099