cache.c revision 261277
1/* $NetBSD: cache.c,v 1.33 2005/12/24 23:24:01 perry Exp $ */ 2 3/*- 4 * Copyright 2001, 2002 Wasabi Systems, Inc. 5 * All rights reserved. 6 * 7 * Written by Jason R. Thorpe and Simon Burge for Wasabi Systems, Inc. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 3. All advertising materials mentioning features or use of this software 18 * must display the following acknowledgement: 19 * This product includes software developed for the NetBSD Project by 20 * Wasabi Systems, Inc. 21 * 4. The name of Wasabi Systems, Inc. may not be used to endorse 22 * or promote products derived from this software without specific prior 23 * written permission. 24 * 25 * THIS SOFTWARE IS PROVIDED BY WASABI SYSTEMS, INC. ``AS IS'' AND 26 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 27 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 28 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL WASABI SYSTEMS, INC 29 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 30 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 31 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 32 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 33 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 34 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 35 * POSSIBILITY OF SUCH DAMAGE. 36 */ 37 38/*- 39 * Copyright 2000, 2001 40 * Broadcom Corporation. All rights reserved. 41 * 42 * This software is furnished under license and may be used and copied only 43 * in accordance with the following terms and conditions. Subject to these 44 * conditions, you may download, copy, install, use, modify and distribute 45 * modified or unmodified copies of this software in source and/or binary 46 * form. No title or ownership is transferred hereby. 47 * 48 * 1) Any source code used, modified or distributed must reproduce and 49 * retain this copyright notice and list of conditions as they appear in 50 * the source file. 51 * 52 * 2) No right is granted to use any trade name, trademark, or logo of 53 * Broadcom Corporation. The "Broadcom Corporation" name may not be 54 * used to endorse or promote products derived from this software 55 * without the prior written permission of Broadcom Corporation. 56 * 57 * 3) THIS SOFTWARE IS PROVIDED "AS-IS" AND ANY EXPRESS OR IMPLIED 58 * WARRANTIES, INCLUDING BUT NOT LIMITED TO, ANY IMPLIED WARRANTIES OF 59 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, OR 60 * NON-INFRINGEMENT ARE DISCLAIMED. IN NO EVENT SHALL BROADCOM BE LIABLE 61 * FOR ANY DAMAGES WHATSOEVER, AND IN PARTICULAR, BROADCOM SHALL NOT BE 62 * LIABLE FOR DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 63 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 64 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR 65 * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, 66 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE 67 * OR OTHERWISE), EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 68 */ 69 70#include <sys/cdefs.h> 71__FBSDID("$FreeBSD: stable/10/sys/mips/mips/cache.c 261277 2014-01-29 22:01:42Z brooks $"); 72 73#include <sys/types.h> 74#include <sys/systm.h> 75 76#include <machine/cpuinfo.h> 77#include <machine/cache.h> 78 79struct mips_cache_ops mips_cache_ops; 80 81#if defined(MIPS_DISABLE_L1_CACHE) || defined(CPU_RMI) || defined(CPU_NLM) 82static void 83cache_noop(vm_offset_t va, vm_size_t size) 84{ 85} 86#endif 87 88void 89mips_config_cache(struct mips_cpuinfo * cpuinfo) 90{ 91 92 switch (cpuinfo->l1.ic_linesize) { 93 case 16: 94 mips_cache_ops.mco_icache_sync_all = mipsNN_icache_sync_all_16; 95 mips_cache_ops.mco_icache_sync_range = 96 mipsNN_icache_sync_range_16; 97 mips_cache_ops.mco_icache_sync_range_index = 98 mipsNN_icache_sync_range_index_16; 99 break; 100 case 32: 101 mips_cache_ops.mco_icache_sync_all = mipsNN_icache_sync_all_32; 102 mips_cache_ops.mco_icache_sync_range = 103 mipsNN_icache_sync_range_32; 104 mips_cache_ops.mco_icache_sync_range_index = 105 mipsNN_icache_sync_range_index_32; 106 break; 107#ifdef CPU_CNMIPS 108 case 128: 109 mips_cache_ops.mco_icache_sync_all = mipsNN_icache_sync_all_128; 110 mips_cache_ops.mco_icache_sync_range = 111 mipsNN_icache_sync_range_128; 112 mips_cache_ops.mco_icache_sync_range_index = 113 mipsNN_icache_sync_range_index_128; 114 break; 115#endif 116 117#ifdef MIPS_DISABLE_L1_CACHE 118 case 0: 119 mips_cache_ops.mco_icache_sync_all = (void (*)(void))cache_noop; 120 mips_cache_ops.mco_icache_sync_range = cache_noop; 121 mips_cache_ops.mco_icache_sync_range_index = cache_noop; 122 break; 123#endif 124 default: 125 panic("no Icache ops for %d byte lines", 126 cpuinfo->l1.ic_linesize); 127 } 128 129 switch (cpuinfo->l1.dc_linesize) { 130 case 16: 131 mips_cache_ops.mco_pdcache_wbinv_all = 132 mips_cache_ops.mco_intern_pdcache_wbinv_all = 133 mipsNN_pdcache_wbinv_all_16; 134 mips_cache_ops.mco_pdcache_wbinv_range = 135 mipsNN_pdcache_wbinv_range_16; 136 mips_cache_ops.mco_pdcache_wbinv_range_index = 137 mips_cache_ops.mco_intern_pdcache_wbinv_range_index = 138 mipsNN_pdcache_wbinv_range_index_16; 139 mips_cache_ops.mco_pdcache_inv_range = 140 mipsNN_pdcache_inv_range_16; 141 mips_cache_ops.mco_pdcache_wb_range = 142 mips_cache_ops.mco_intern_pdcache_wb_range = 143 mipsNN_pdcache_wb_range_16; 144 break; 145 case 32: 146 mips_cache_ops.mco_pdcache_wbinv_all = 147 mips_cache_ops.mco_intern_pdcache_wbinv_all = 148 mipsNN_pdcache_wbinv_all_32; 149#if defined(CPU_RMI) || defined(CPU_NLM) 150 mips_cache_ops.mco_pdcache_wbinv_range = cache_noop; 151#else 152 mips_cache_ops.mco_pdcache_wbinv_range = 153 mipsNN_pdcache_wbinv_range_32; 154#endif 155#if defined(CPU_RMI) || defined(CPU_NLM) 156 mips_cache_ops.mco_pdcache_wbinv_range_index = 157 mips_cache_ops.mco_intern_pdcache_wbinv_range_index = cache_noop; 158 mips_cache_ops.mco_pdcache_inv_range = cache_noop; 159#else 160 mips_cache_ops.mco_pdcache_wbinv_range_index = 161 mips_cache_ops.mco_intern_pdcache_wbinv_range_index = 162 mipsNN_pdcache_wbinv_range_index_32; 163 mips_cache_ops.mco_pdcache_inv_range = 164 mipsNN_pdcache_inv_range_32; 165#endif 166#if defined(CPU_RMI) || defined(CPU_NLM) 167 mips_cache_ops.mco_pdcache_wb_range = 168 mips_cache_ops.mco_intern_pdcache_wb_range = cache_noop; 169#else 170 mips_cache_ops.mco_pdcache_wb_range = 171 mips_cache_ops.mco_intern_pdcache_wb_range = 172 mipsNN_pdcache_wb_range_32; 173#endif 174 break; 175#ifdef CPU_CNMIPS 176 case 128: 177 mips_cache_ops.mco_pdcache_wbinv_all = 178 mips_cache_ops.mco_intern_pdcache_wbinv_all = 179 mipsNN_pdcache_wbinv_all_128; 180 mips_cache_ops.mco_pdcache_wbinv_range = 181 mipsNN_pdcache_wbinv_range_128; 182 mips_cache_ops.mco_pdcache_wbinv_range_index = 183 mips_cache_ops.mco_intern_pdcache_wbinv_range_index = 184 mipsNN_pdcache_wbinv_range_index_128; 185 mips_cache_ops.mco_pdcache_inv_range = 186 mipsNN_pdcache_inv_range_128; 187 mips_cache_ops.mco_pdcache_wb_range = 188 mips_cache_ops.mco_intern_pdcache_wb_range = 189 mipsNN_pdcache_wb_range_128; 190 break; 191#endif 192#ifdef MIPS_DISABLE_L1_CACHE 193 case 0: 194 mips_cache_ops.mco_pdcache_wbinv_all = 195 mips_cache_ops.mco_intern_pdcache_wbinv_all = 196 (void (*)(void))cache_noop; 197 mips_cache_ops.mco_pdcache_wbinv_range = cache_noop; 198 mips_cache_ops.mco_pdcache_wbinv_range_index = cache_noop; 199 mips_cache_ops.mco_intern_pdcache_wbinv_range_index = 200 cache_noop; 201 mips_cache_ops.mco_pdcache_inv_range = cache_noop; 202 mips_cache_ops.mco_pdcache_wb_range = cache_noop; 203 mips_cache_ops.mco_intern_pdcache_wb_range = cache_noop; 204 break; 205#endif 206 default: 207 panic("no Dcache ops for %d byte lines", 208 cpuinfo->l1.dc_linesize); 209 } 210 211 mipsNN_cache_init(cpuinfo); 212 213#if 0 214 if (mips_cpu_flags & 215 (CPU_MIPS_D_CACHE_COHERENT | CPU_MIPS_I_D_CACHE_COHERENT)) { 216#ifdef CACHE_DEBUG 217 printf(" Dcache is coherent\n"); 218#endif 219 mips_cache_ops.mco_pdcache_wbinv_all = 220 (void (*)(void))cache_noop; 221 mips_cache_ops.mco_pdcache_wbinv_range = cache_noop; 222 mips_cache_ops.mco_pdcache_wbinv_range_index = cache_noop; 223 mips_cache_ops.mco_pdcache_inv_range = cache_noop; 224 mips_cache_ops.mco_pdcache_wb_range = cache_noop; 225 } 226 if (mips_cpu_flags & CPU_MIPS_I_D_CACHE_COHERENT) { 227#ifdef CACHE_DEBUG 228 printf(" Icache is coherent against Dcache\n"); 229#endif 230 mips_cache_ops.mco_intern_pdcache_wbinv_all = 231 (void (*)(void))cache_noop; 232 mips_cache_ops.mco_intern_pdcache_wbinv_range_index = 233 cache_noop; 234 mips_cache_ops.mco_intern_pdcache_wb_range = cache_noop; 235 } 236#endif 237 238 /* Check that all cache ops are set up. */ 239 /* must have primary Icache */ 240 if (cpuinfo->l1.ic_size) { 241 242 if (!mips_cache_ops.mco_icache_sync_all) 243 panic("no icache_sync_all cache op"); 244 if (!mips_cache_ops.mco_icache_sync_range) 245 panic("no icache_sync_range cache op"); 246 if (!mips_cache_ops.mco_icache_sync_range_index) 247 panic("no icache_sync_range_index cache op"); 248 } 249 /* must have primary Dcache */ 250 if (cpuinfo->l1.dc_size) { 251 if (!mips_cache_ops.mco_pdcache_wbinv_all) 252 panic("no pdcache_wbinv_all"); 253 if (!mips_cache_ops.mco_pdcache_wbinv_range) 254 panic("no pdcache_wbinv_range"); 255 if (!mips_cache_ops.mco_pdcache_wbinv_range_index) 256 panic("no pdcache_wbinv_range_index"); 257 if (!mips_cache_ops.mco_pdcache_inv_range) 258 panic("no pdcache_inv_range"); 259 if (!mips_cache_ops.mco_pdcache_wb_range) 260 panic("no pdcache_wb_range"); 261 } 262 263 /* XXXMIPS: No secondary cache handlers yet */ 264#ifdef notyet 265 if (mips_sdcache_size) { 266 if (!mips_cache_ops.mco_sdcache_wbinv_all) 267 panic("no sdcache_wbinv_all"); 268 if (!mips_cache_ops.mco_sdcache_wbinv_range) 269 panic("no sdcache_wbinv_range"); 270 if (!mips_cache_ops.mco_sdcache_wbinv_range_index) 271 panic("no sdcache_wbinv_range_index"); 272 if (!mips_cache_ops.mco_sdcache_inv_range) 273 panic("no sdcache_inv_range"); 274 if (!mips_cache_ops.mco_sdcache_wb_range) 275 panic("no sdcache_wb_range"); 276 } 277#endif 278} 279