1178173Simp/*- 2178173Simp * Copyright (C) 2007 by Oleksandr Tymoshenko. All rights reserved. 3178173Simp * 4178173Simp * Redistribution and use in source and binary forms, with or without 5178173Simp * modification, are permitted provided that the following conditions 6178173Simp * are met: 7178173Simp * 1. Redistributions of source code must retain the above copyright 8178173Simp * notice, this list of conditions and the following disclaimer. 9178173Simp * 2. Redistributions in binary form must reproduce the above copyright 10178173Simp * notice, this list of conditions and the following disclaimer in the 11178173Simp * documentation and/or other materials provided with the distribution. 12178173Simp * 13178173Simp * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 14178173Simp * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 15178173Simp * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 16178173Simp * IN NO EVENT SHALL THE AUTHOR OR HIS RELATIVES BE LIABLE FOR ANY DIRECT, 17178173Simp * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 18178173Simp * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 19178173Simp * SERVICES; LOSS OF MIND, USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 20178173Simp * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, 21178173Simp * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING 22178173Simp * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 23178173Simp * THE POSSIBILITY OF SUCH DAMAGE. 24178173Simp * 25178173Simp * $FreeBSD$ 26178173Simp * 27178173Simp */ 28178173Simp#ifndef __IDTREG_H__ 29178173Simp#define __IDTREG_H__ 30178173Simp 31178173Simp/* Interrupt controller */ 32178173Simp#define IDT_BASE_ICU 0x18038000 33178173Simp#define ICU_IPEND2 0x00 34178173Simp#define ICU_ITEST2 0x04 35178173Simp#define ICU_IMASK2 0x08 36178173Simp#define ICU_IPEND3 0x0C 37178173Simp#define ICU_ITEST3 0x10 38178173Simp#define ICU_IMASK3 0x14 39178173Simp#define ICU_IPEND4 0x18 40178173Simp#define ICU_ITEST4 0x1c 41178173Simp#define ICU_IMASK4 0x20 42178173Simp#define ICU_IPEND5 0x24 43178173Simp#define ICU_ITEST5 0x28 44178173Simp#define ICU_IMASK5 0x2c 45178173Simp#define ICU_IPEND6 0x30 46178173Simp#define ICU_ITEST6 0x34 47178173Simp#define ICU_IMASK6 0x38 48178173Simp#define ICU_NMIPS 0x3c 49178173Simp 50178173Simp#define IDT_BASE_GPIO 0x18050000 51178173Simp#define GPIO_FUNC 0x00 52178173Simp#define GPIO_CFG 0x04 53178173Simp#define GPIO_DATA 0x08 54178173Simp#define GPIO_ILEVEL 0x0C 55178173Simp#define GPIO_ISTAT 0x10 56178173Simp#define GPIO_NMIEN 0x14 57178173Simp 58178173Simp#define IDT_BASE_UART0 0x18058000 59178173Simp 60178173Simp/* PCI controller */ 61178173Simp#define IDT_BASE_PCI 0x18080000 62178173Simp#define IDT_PCI_CNTL 0x00 63178173Simp#define IDT_PCI_CNTL_EN 0x001 64178173Simp#define IDT_PCI_CNTL_TNR 0x002 65178173Simp#define IDT_PCI_CNTL_SCE 0x004 66178173Simp#define IDT_PCI_CNTL_IEN 0x008 67178173Simp#define IDT_PCI_CNTL_AAA 0x010 68178173Simp#define IDT_PCI_CNTL_EAP 0x020 69178173Simp#define IDT_PCI_CNTL_IGM 0x200 70178173Simp#define IDT_PCI_STATUS 0x04 71178173Simp#define IDT_PCI_STATUS_RIP 0x20000 72178173Simp#define IDT_PCI_STATUS_MASK 0x08 73178173Simp#define IDT_PCI_CFG_ADDR 0x0C 74178173Simp#define IDT_PCI_CFG_DATA 0x10 75178173Simp/* LBA stuff */ 76178173Simp#define IDT_PCI_LBA0 0x14 77178173Simp#define IDT_PCI_LBA0_CNTL 0x18 78178173Simp#define IDT_PCI_LBA_MSI 0x01 79178173Simp#define IDT_PCI_LBA_SIZE_1MB (0x14 << 2) 80178173Simp#define IDT_PCI_LBA_SIZE_2MB (0x15 << 2) 81178173Simp#define IDT_PCI_LBA_SIZE_4MB (0x16 << 2) 82178173Simp#define IDT_PCI_LBA_SIZE_8MB (0x17 << 2) 83178173Simp#define IDT_PCI_LBA_SIZE_16MB (0x18 << 2) 84178173Simp#define IDT_PCI_LBA_SIZE_32MB (0x19 << 2) 85178173Simp#define IDT_PCI_LBA_SIZE_64MB (0x1A << 2) 86178173Simp#define IDT_PCI_LBA_SIZE_128MB (0x1B << 2) 87178173Simp#define IDT_PCI_LBA_SIZE_256MB (0x1C << 2) 88178173Simp#define IDT_PCI_LBA_FE 0x80 89178173Simp#define IDT_PCI_LBA_RT 0x100 90178173Simp#define IDT_PCI_LBA0_MAP 0x1C 91178173Simp#define IDT_PCI_LBA1 0x20 92178173Simp#define IDT_PCI_LBA1_CNTL 0x24 93178173Simp#define IDT_PCI_LBA1_MAP 0x28 94178173Simp#define IDT_PCI_LBA2 0x2C 95178173Simp#define IDT_PCI_LBA2_CNTL 0x30 96178173Simp#define IDT_PCI_LBA2_MAP 0x34 97178173Simp#define IDT_PCI_LBA3 0x38 98178173Simp#define IDT_PCI_LBA3_CNTL 0x3C 99178173Simp#define IDT_PCI_LBA3_MAP 0x40 100178173Simp/* decoupled registers */ 101178173Simp#define IDT_PCI_DAC 0x44 102178173Simp#define IDT_PCI_DAS 0x48 103178173Simp#define IDT_PCI_DASM 0x4C 104178173Simp 105178173Simp#define IDT_PCI_TC 0x5C 106178173Simp#define IDT_PCI_TC_RTIMER 0x10 107178173Simp#define IDT_PCI_TC_DTIMER 0x08 108178173Simp/* Messaging unit of PCI controller */ 109178173Simp#define IDT_PCI_IIC 0x8024 110178173Simp#define IDT_PCI_IIM 0x8028 111178173Simp#define IDT_PCI_OIC 0x8030 112178173Simp#define IDT_PCI_OIM 0x8034 113178173Simp 114178173Simp/* PCI-related stuff */ 115178173Simp#define IDT_PCIMEM0_BASE 0x50000000 116178173Simp#define IDT_PCIMEM0_SIZE 0x01000000 117178173Simp 118178173Simp#define IDT_PCIMEM1_BASE 0x60000000 119178173Simp#define IDT_PCIMEM1_SIZE 0x10000000 120178173Simp 121178173Simp#define IDT_PCIMEM2_BASE 0x18C00000 122178173Simp#define IDT_PCIMEM2_SIZE 0x00400000 123178173Simp 124178173Simp#define IDT_PCIMEM3_BASE 0x18800000 125178173Simp#define IDT_PCIMEM3_SIZE 0x00100000 126178173Simp 127178173Simp/* Interrupts-related stuff */ 128178173Simp#define IRQ_BASE 8 129178173Simp/* Convert <IPbit, irq_offset> pair to IRQ number */ 130178173Simp#define IP_IRQ(IPbit, offset) ((IPbit - 2) * 32 + (offset) + IRQ_BASE) 131178173Simp/* The last one available IRQ */ 132178173Simp#define IRQ_END IP_IRQ(6, 31) 133178173Simp#define ICU_GROUP_REG_OFFSET 0x0C 134178173Simp 135178173Simp#define ICU_IP(irq) (((irq) - IRQ_BASE) & 0x1f) 136178173Simp#define ICU_IP_BIT(irq) (1 << ICU_IP(irq)) 137178173Simp#define ICU_GROUP(irq) (((irq) - IRQ_BASE) >> 5) 138178173Simp 139178173Simp#define ICU_GROUP_MASK_REG(group) \ 140178173Simp (ICU_IMASK2 + ((((group) - 2) * ICU_GROUP_REG_OFFSET))) 141178173Simp#define ICU_GROUP_IPEND_REG(group) \ 142178173Simp (ICU_IPEND2 + ((((group) - 2) * ICU_GROUP_REG_OFFSET))) 143178173Simp 144178173Simp#define ICU_IRQ_MASK_REG(irq) \ 145178173Simp (ICU_IMASK2 + ((ICU_GROUP(irq) * ICU_GROUP_REG_OFFSET))) 146178173Simp#define ICU_IRQ_IPEND_REG(irq) \ 147178173Simp (ICU_IPEND2 + ((ICU_GROUP(irq) * ICU_GROUP_REG_OFFSET))) 148178173Simp 149178173Simp#define PCI_IRQ_BASE IP_IRQ(6, 4) 150178173Simp#define PCI_IRQ_END IP_IRQ(6, 7) 151178173Simp 152178173Simp#endif /* __IDTREG_H__ */ 153178173Simp 154