1232812Sjmallett/***********************license start*************** 2232812Sjmallett * Copyright (c) 2003-2010 Cavium Networks (support@cavium.com). All rights 3232812Sjmallett * reserved. 4232812Sjmallett * 5232812Sjmallett * 6232812Sjmallett * Redistribution and use in source and binary forms, with or without 7232812Sjmallett * modification, are permitted provided that the following conditions are 8232812Sjmallett * met: 9232812Sjmallett * 10232812Sjmallett * * Redistributions of source code must retain the above copyright 11232812Sjmallett * notice, this list of conditions and the following disclaimer. 12232812Sjmallett * 13232812Sjmallett * * Redistributions in binary form must reproduce the above 14232812Sjmallett * copyright notice, this list of conditions and the following 15232812Sjmallett * disclaimer in the documentation and/or other materials provided 16232812Sjmallett * with the distribution. 17232812Sjmallett 18232812Sjmallett * * Neither the name of Cavium Networks nor the names of 19232812Sjmallett * its contributors may be used to endorse or promote products 20232812Sjmallett * derived from this software without specific prior written 21232812Sjmallett * permission. 22232812Sjmallett 23232812Sjmallett * This Software, including technical data, may be subject to U.S. export control 24232812Sjmallett * laws, including the U.S. Export Administration Act and its associated 25232812Sjmallett * regulations, and may be subject to export or import regulations in other 26232812Sjmallett * countries. 27232812Sjmallett 28232812Sjmallett * TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS" 29232812Sjmallett * AND WITH ALL FAULTS AND CAVIUM NETWORKS MAKES NO PROMISES, REPRESENTATIONS OR 30232812Sjmallett * WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH RESPECT TO 31232812Sjmallett * THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY REPRESENTATION OR 32232812Sjmallett * DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT DEFECTS, AND CAVIUM 33232812Sjmallett * SPECIFICALLY DISCLAIMS ALL IMPLIED (IF ANY) WARRANTIES OF TITLE, 34232812Sjmallett * MERCHANTABILITY, NONINFRINGEMENT, FITNESS FOR A PARTICULAR PURPOSE, LACK OF 35232812Sjmallett * VIRUSES, ACCURACY OR COMPLETENESS, QUIET ENJOYMENT, QUIET POSSESSION OR 36232812Sjmallett * CORRESPONDENCE TO DESCRIPTION. THE ENTIRE RISK ARISING OUT OF USE OR 37232812Sjmallett * PERFORMANCE OF THE SOFTWARE LIES WITH YOU. 38232812Sjmallett ***********************license end**************************************/ 39232812Sjmallett 40232812Sjmallett#ifndef __OCTEON_IRQ_H__ 41232812Sjmallett#define __OCTEON_IRQ_H__ 42232812Sjmallett 43232812Sjmallett/* 44232812Sjmallett * $FreeBSD$ 45232812Sjmallett */ 46232812Sjmallett 47232812Sjmallett/** 48232812Sjmallett * Enumeration of Interrupt numbers 49232812Sjmallett */ 50232812Sjmalletttypedef enum 51232812Sjmallett{ 52232812Sjmallett /* 0 - 7 represent the 8 MIPS standard interrupt sources */ 53232812Sjmallett OCTEON_IRQ_SW0 = 0, 54232812Sjmallett OCTEON_IRQ_SW1 = 1, 55232812Sjmallett OCTEON_IRQ_CIU0 = 2, 56232812Sjmallett OCTEON_IRQ_CIU1 = 3, 57232812Sjmallett OCTEON_IRQ_4 = 4, 58232812Sjmallett OCTEON_IRQ_5 = 5, 59232812Sjmallett OCTEON_IRQ_6 = 6, 60232812Sjmallett OCTEON_IRQ_7 = 7, 61232812Sjmallett 62232812Sjmallett /* 8 - 71 represent the sources in CIU_INTX_EN0 */ 63232812Sjmallett OCTEON_IRQ_WORKQ0 = 8, 64232812Sjmallett OCTEON_IRQ_WORKQ1 = 9, 65232812Sjmallett OCTEON_IRQ_WORKQ2 = 10, 66232812Sjmallett OCTEON_IRQ_WORKQ3 = 11, 67232812Sjmallett OCTEON_IRQ_WORKQ4 = 12, 68232812Sjmallett OCTEON_IRQ_WORKQ5 = 13, 69232812Sjmallett OCTEON_IRQ_WORKQ6 = 14, 70232812Sjmallett OCTEON_IRQ_WORKQ7 = 15, 71232812Sjmallett OCTEON_IRQ_WORKQ8 = 16, 72232812Sjmallett OCTEON_IRQ_WORKQ9 = 17, 73232812Sjmallett OCTEON_IRQ_WORKQ10 = 18, 74232812Sjmallett OCTEON_IRQ_WORKQ11 = 19, 75232812Sjmallett OCTEON_IRQ_WORKQ12 = 20, 76232812Sjmallett OCTEON_IRQ_WORKQ13 = 21, 77232812Sjmallett OCTEON_IRQ_WORKQ14 = 22, 78232812Sjmallett OCTEON_IRQ_WORKQ15 = 23, 79232812Sjmallett OCTEON_IRQ_GPIO0 = 24, 80232812Sjmallett OCTEON_IRQ_GPIO1 = 25, 81232812Sjmallett OCTEON_IRQ_GPIO2 = 26, 82232812Sjmallett OCTEON_IRQ_GPIO3 = 27, 83232812Sjmallett OCTEON_IRQ_GPIO4 = 28, 84232812Sjmallett OCTEON_IRQ_GPIO5 = 29, 85232812Sjmallett OCTEON_IRQ_GPIO6 = 30, 86232812Sjmallett OCTEON_IRQ_GPIO7 = 31, 87232812Sjmallett OCTEON_IRQ_GPIO8 = 32, 88232812Sjmallett OCTEON_IRQ_GPIO9 = 33, 89232812Sjmallett OCTEON_IRQ_GPIO10 = 34, 90232812Sjmallett OCTEON_IRQ_GPIO11 = 35, 91232812Sjmallett OCTEON_IRQ_GPIO12 = 36, 92232812Sjmallett OCTEON_IRQ_GPIO13 = 37, 93232812Sjmallett OCTEON_IRQ_GPIO14 = 38, 94232812Sjmallett OCTEON_IRQ_GPIO15 = 39, 95232812Sjmallett OCTEON_IRQ_MBOX0 = 40, 96232812Sjmallett OCTEON_IRQ_MBOX1 = 41, 97232812Sjmallett OCTEON_IRQ_UART0 = 42, 98232812Sjmallett OCTEON_IRQ_UART1 = 43, 99232812Sjmallett OCTEON_IRQ_PCI_INT0 = 44, 100232812Sjmallett OCTEON_IRQ_PCI_INT1 = 45, 101232812Sjmallett OCTEON_IRQ_PCI_INT2 = 46, 102232812Sjmallett OCTEON_IRQ_PCI_INT3 = 47, 103232812Sjmallett OCTEON_IRQ_PCI_MSI0 = 48, 104232812Sjmallett OCTEON_IRQ_PCI_MSI1 = 49, 105232812Sjmallett OCTEON_IRQ_PCI_MSI2 = 50, 106232812Sjmallett OCTEON_IRQ_PCI_MSI3 = 51, 107232812Sjmallett OCTEON_IRQ_RESERVED44 = 52, 108232812Sjmallett OCTEON_IRQ_TWSI = 53, 109232812Sjmallett OCTEON_IRQ_RML = 54, 110232812Sjmallett OCTEON_IRQ_TRACE = 55, 111232812Sjmallett OCTEON_IRQ_GMX_DRP0 = 56, 112232812Sjmallett OCTEON_IRQ_GMX_DRP1 = 57, /* Doesn't apply on CN52XX or CN63XX */ 113232812Sjmallett OCTEON_IRQ_IPD_DRP = 58, 114232812Sjmallett OCTEON_IRQ_KEY_ZERO = 59, /* Doesn't apply on CN52XX or CN63XX */ 115232812Sjmallett OCTEON_IRQ_TIMER0 = 60, 116232812Sjmallett OCTEON_IRQ_TIMER1 = 61, 117232812Sjmallett OCTEON_IRQ_TIMER2 = 62, 118232812Sjmallett OCTEON_IRQ_TIMER3 = 63, 119232812Sjmallett OCTEON_IRQ_USB0 = 64, /* Doesn't apply on CN38XX or CN58XX */ 120232812Sjmallett OCTEON_IRQ_PCM = 65, /* Doesn't apply on CN52XX or CN63XX */ 121232812Sjmallett OCTEON_IRQ_MPI = 66, /* Doesn't apply on CN52XX or CN63XX */ 122232812Sjmallett OCTEON_IRQ_TWSI2 = 67, /* Added in CN56XX */ 123232812Sjmallett OCTEON_IRQ_POWIQ = 68, /* Added in CN56XX */ 124232812Sjmallett OCTEON_IRQ_IPDPPTHR = 69, /* Added in CN56XX */ 125232812Sjmallett OCTEON_IRQ_MII = 70, /* Added in CN56XX */ 126232812Sjmallett OCTEON_IRQ_BOOTDMA = 71, /* Added in CN56XX */ 127232812Sjmallett 128232812Sjmallett /* 72 - 135 represent the sources in CIU_INTX_EN1 */ 129232812Sjmallett OCTEON_IRQ_WDOG0 = 72, 130232812Sjmallett OCTEON_IRQ_WDOG1 = 73, 131232812Sjmallett OCTEON_IRQ_WDOG2 = 74, 132232812Sjmallett OCTEON_IRQ_WDOG3 = 75, 133232812Sjmallett OCTEON_IRQ_WDOG4 = 76, 134232812Sjmallett OCTEON_IRQ_WDOG5 = 77, 135232812Sjmallett OCTEON_IRQ_WDOG6 = 78, 136232812Sjmallett OCTEON_IRQ_WDOG7 = 79, 137232812Sjmallett OCTEON_IRQ_WDOG8 = 80, 138232812Sjmallett OCTEON_IRQ_WDOG9 = 81, 139232812Sjmallett OCTEON_IRQ_WDOG10= 82, 140232812Sjmallett OCTEON_IRQ_WDOG11= 83, 141232812Sjmallett OCTEON_IRQ_WDOG12= 84, 142232812Sjmallett OCTEON_IRQ_WDOG13= 85, 143232812Sjmallett OCTEON_IRQ_WDOG14= 86, 144232812Sjmallett OCTEON_IRQ_WDOG15= 87, 145232812Sjmallett OCTEON_IRQ_UART2 = 88, /* Added in CN52XX */ 146232812Sjmallett OCTEON_IRQ_USB1 = 89, /* Added in CN52XX */ 147232812Sjmallett OCTEON_IRQ_MII1 = 90, /* Added in CN52XX */ 148232812Sjmallett OCTEON_IRQ_NAND = 91, /* Added in CN52XX */ 149232812Sjmallett OCTEON_IRQ_MIO = 92, /* Added in CN63XX */ 150232812Sjmallett OCTEON_IRQ_IOB = 93, /* Added in CN63XX */ 151232812Sjmallett OCTEON_IRQ_FPA = 94, /* Added in CN63XX */ 152232812Sjmallett OCTEON_IRQ_POW = 95, /* Added in CN63XX */ 153232812Sjmallett OCTEON_IRQ_L2C = 96, /* Added in CN63XX */ 154232812Sjmallett OCTEON_IRQ_IPD = 97, /* Added in CN63XX */ 155232812Sjmallett OCTEON_IRQ_PIP = 98, /* Added in CN63XX */ 156232812Sjmallett OCTEON_IRQ_PKO = 99, /* Added in CN63XX */ 157232812Sjmallett OCTEON_IRQ_ZIP = 100, /* Added in CN63XX */ 158232812Sjmallett OCTEON_IRQ_TIM = 101, /* Added in CN63XX */ 159232812Sjmallett OCTEON_IRQ_RAD = 102, /* Added in CN63XX */ 160232812Sjmallett OCTEON_IRQ_KEY = 103, /* Added in CN63XX */ 161232812Sjmallett OCTEON_IRQ_DFA = 104, /* Added in CN63XX */ 162232812Sjmallett OCTEON_IRQ_USB = 105, /* Added in CN63XX */ 163232812Sjmallett OCTEON_IRQ_SLI = 106, /* Added in CN63XX */ 164232812Sjmallett OCTEON_IRQ_DPI = 107, /* Added in CN63XX */ 165232812Sjmallett OCTEON_IRQ_AGX0 = 108, /* Added in CN63XX */ 166232812Sjmallett /* 109 - 117 are reserved */ 167232812Sjmallett OCTEON_IRQ_AGL = 118, /* Added in CN63XX */ 168232812Sjmallett OCTEON_IRQ_PTP = 119, /* Added in CN63XX */ 169232812Sjmallett OCTEON_IRQ_PEM0 = 120, /* Added in CN63XX */ 170232812Sjmallett OCTEON_IRQ_PEM1 = 121, /* Added in CN63XX */ 171232812Sjmallett OCTEON_IRQ_SRIO0 = 122, /* Added in CN63XX */ 172232812Sjmallett OCTEON_IRQ_SRIO1 = 123, /* Added in CN63XX */ 173232812Sjmallett OCTEON_IRQ_LMC0 = 124, /* Added in CN63XX */ 174232812Sjmallett /* Interrupts 125 - 127 are reserved */ 175232812Sjmallett OCTEON_IRQ_DFM = 128, /* Added in CN63XX */ 176232812Sjmallett /* Interrupts 129 - 135 are reserved */ 177232812Sjmallett} octeon_irq_t; 178232812Sjmallett 179233417Sgonzo#define OCTEON_PMC_IRQ OCTEON_IRQ_4 180233417Sgonzo 181232812Sjmallett#endif 182