138136Sdfr/*- 238136Sdfr * Copyright (c) 1990 The Regents of the University of California. 338136Sdfr * All rights reserved. 438136Sdfr * 538136Sdfr * This code is derived from software contributed to Berkeley by 638136Sdfr * William Jolitz. 738136Sdfr * 838136Sdfr * Redistribution and use in source and binary forms, with or without 938136Sdfr * modification, are permitted provided that the following conditions 1038136Sdfr * are met: 1138136Sdfr * 1. Redistributions of source code must retain the above copyright 1238136Sdfr * notice, this list of conditions and the following disclaimer. 1338136Sdfr * 2. Redistributions in binary form must reproduce the above copyright 1438136Sdfr * notice, this list of conditions and the following disclaimer in the 1538136Sdfr * documentation and/or other materials provided with the distribution. 1638136Sdfr * 4. Neither the name of the University nor the names of its contributors 1738136Sdfr * may be used to endorse or promote products derived from this software 1838136Sdfr * without specific prior written permission. 1938136Sdfr * 2038136Sdfr * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 2138136Sdfr * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 2238136Sdfr * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 2338136Sdfr * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 2438136Sdfr * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 2538136Sdfr * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 2638136Sdfr * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 2738136Sdfr * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 2838136Sdfr * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 2938136Sdfr * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 3038136Sdfr * SUCH DAMAGE. 3138136Sdfr * 3238136Sdfr * from: @(#)isa.h 5.7 (Berkeley) 5/9/91 3350477Speter * $FreeBSD$ 3438136Sdfr */ 3538136Sdfr 3638136Sdfr#ifdef PC98 37110231Snyan#error isareg.h is included from PC-9801 source 3838136Sdfr#endif 3938136Sdfr 4047613Sdfr#ifndef _ISA_ISA_H_ 4147613Sdfr#define _ISA_ISA_H_ 4238136Sdfr 4338136Sdfr/* BEWARE: Included in both assembler and C code */ 4438136Sdfr 4538136Sdfr/* 4638136Sdfr * ISA Bus conventions 4738136Sdfr */ 4838136Sdfr 4938136Sdfr/* 5038136Sdfr * Input / Output Port Assignments 5138136Sdfr */ 5238136Sdfr#ifndef IO_ISABEGIN 5338136Sdfr#define IO_ISABEGIN 0x000 /* 0x000 - Beginning of I/O Registers */ 5438136Sdfr 5538136Sdfr /* CPU Board */ 5638136Sdfr#define IO_ICU1 0x020 /* 8259A Interrupt Controller #1 */ 5738136Sdfr#define IO_PMP1 0x026 /* 82347 Power Management Peripheral */ 5838136Sdfr#define IO_KBD 0x060 /* 8042 Keyboard */ 5938136Sdfr#define IO_RTC 0x070 /* RTC */ 6038136Sdfr#define IO_NMI IO_RTC /* NMI Control */ 6138136Sdfr#define IO_ICU2 0x0A0 /* 8259A Interrupt Controller #2 */ 6238136Sdfr 6338136Sdfr /* Cards */ 6438136Sdfr /* 0x100 - 0x16F Open */ 6538136Sdfr 6638136Sdfr#define IO_WD2 0x170 /* Secondary Fixed Disk Controller */ 6738136Sdfr 6838136Sdfr#define IO_PMP2 0x178 /* 82347 Power Management Peripheral */ 6938136Sdfr 7038136Sdfr /* 0x17A - 0x1EF Open */ 7138136Sdfr 7238136Sdfr#define IO_WD1 0x1F0 /* Primary Fixed Disk Controller */ 7338136Sdfr#define IO_GAME 0x201 /* Game Controller */ 7438136Sdfr 7538136Sdfr /* 0x202 - 0x22A Open */ 7638136Sdfr 7738136Sdfr#define IO_ASC2 0x22B /* AmiScan addr.grp. 2 */ 7838136Sdfr 7938136Sdfr /* 0x230 - 0x26A Open */ 8038136Sdfr 8138136Sdfr#define IO_ASC3 0x26B /* AmiScan addr.grp. 3 */ 8238136Sdfr#define IO_GSC1 0x270 /* -- 0x27B! GeniScan GS-4500 addr.grp. 1 */ 8338136Sdfr#define IO_LPT2 0x278 /* Parallel Port #2 */ 8438136Sdfr 8538136Sdfr /* 0x280 - 0x2AA Open */ 8638136Sdfr 8738136Sdfr#define IO_ASC4 0x2AB /* AmiScan addr.grp. 4 */ 8838136Sdfr 8938136Sdfr /* 0x2B0 - 0x2DF Open */ 9038136Sdfr 9138136Sdfr#define IO_GSC2 0x2E0 /* GeniScan GS-4500 addr.grp. 2 */ 9238136Sdfr#define IO_COM4 0x2E8 /* COM4 i/o address */ 9338136Sdfr#define IO_ASC5 0x2EB /* AmiScan addr.grp. 5 */ 9438136Sdfr 9538136Sdfr /* 0x2F0 - 0x2F7 Open */ 9638136Sdfr 9738136Sdfr#define IO_COM2 0x2F8 /* COM2 i/o address */ 9838136Sdfr 9938136Sdfr /* 0x300 - 0x32A Open */ 10038136Sdfr 10138136Sdfr#define IO_ASC6 0x32B /* AmiScan addr.grp. 6 */ 10238136Sdfr#define IO_AHA0 0x330 /* adaptec 1542 default addr. */ 10338136Sdfr#define IO_BT0 0x330 /* bustek 742a default addr. */ 10438136Sdfr#define IO_UHA0 0x330 /* ultrastore 14f default addr. */ 10538136Sdfr#define IO_AHA1 0x334 /* adaptec 1542 default addr. */ 10638136Sdfr#define IO_BT1 0x334 /* bustek 742a default addr. */ 10738136Sdfr 10838136Sdfr /* 0x340 - 0x36A Open */ 10938136Sdfr 11038136Sdfr#define IO_ASC7 0x36B /* AmiScan addr.grp. 7 */ 11138136Sdfr#define IO_GSC3 0x370 /* GeniScan GS-4500 addr.grp. 3 */ 11238136Sdfr#define IO_FD2 0x370 /* secondary base i/o address */ 11338136Sdfr#define IO_LPT1 0x378 /* Parallel Port #1 */ 11438136Sdfr 11538136Sdfr /* 0x380 - 0x3AA Open */ 11638136Sdfr 11738136Sdfr#define IO_ASC8 0x3AB /* AmiScan addr.grp. 8 */ 11838136Sdfr#define IO_MDA 0x3B0 /* Monochome Adapter */ 11938136Sdfr#define IO_LPT3 0x3BC /* Monochome Adapter Printer Port */ 12038136Sdfr#define IO_VGA 0x3C0 /* E/VGA Ports */ 12138136Sdfr#define IO_CGA 0x3D0 /* CGA Ports */ 12238136Sdfr#define IO_GSC4 0x3E0 /* GeniScan GS-4500 addr.grp. 4 */ 12338136Sdfr#define IO_COM3 0x3E8 /* COM3 i/o address */ 12438136Sdfr#define IO_ASC1 0x3EB /* AmiScan addr.grp. 1 */ 12538136Sdfr#define IO_FD1 0x3F0 /* primary base i/o address */ 12638136Sdfr#define IO_COM1 0x3F8 /* COM1 i/o address */ 12738136Sdfr 12838136Sdfr#define IO_ISAEND 0x3FF /* End (actually Max) of I/O Regs */ 12938136Sdfr#endif /* !IO_ISABEGIN */ 13038136Sdfr 13138136Sdfr/* 13238136Sdfr * Input / Output Port Sizes - these are from several sources, and tend 13338136Sdfr * to be the larger of what was found. 13438136Sdfr */ 13538136Sdfr#ifndef IO_ISASIZES 13638136Sdfr#define IO_ISASIZES 13738136Sdfr 13838136Sdfr#define IO_ASCSIZE 5 /* AmiScan GI1904-based hand scanner */ 13942333Syokota#define IO_CGASIZE 12 /* CGA controllers */ 14038136Sdfr#define IO_EISASIZE 256 /* EISA controllers */ 14138136Sdfr#define IO_FDCSIZE 8 /* Nec765 floppy controllers */ 14238136Sdfr#define IO_GAMSIZE 16 /* AT compatible game controllers */ 14338136Sdfr#define IO_GSCSIZE 8 /* GeniScan GS-4500G hand scanner */ 14438136Sdfr#define IO_ICUSIZE 16 /* 8259A interrupt controllers */ 14538136Sdfr#define IO_KBDSIZE 16 /* 8042 Keyboard controllers */ 14660544Sdfr 14760544Sdfr/* The following line was changed to support more architectures (simpler 14860544Sdfr chipsets (like those for Alpha) only use 4, but more complex controllers 14960544Sdfr (usually modern i386's) can use an additional 4; the probe to see if 15060544Sdfr the additional 4 can be used by the specific chipset is now done in the ppc 15160544Sdfr code by ppc_probe()... */ 15260544Sdfr 15363403Sdfr#define IO_LPTSIZE_EXTENDED 8 /* "Extended" LPT controllers */ 15463403Sdfr#define IO_LPTSIZE_NORMAL 4 /* "Normal" LPT controllers */ 15560544Sdfr 15642333Syokota#define IO_MDASIZE 12 /* Monochrome display controllers */ 15738136Sdfr#define IO_PMPSIZE 2 /* 82347 power management peripheral */ 15842333Syokota#define IO_PSMSIZE 5 /* 8042 Keyboard controllers */ 15938136Sdfr#define IO_RTCSIZE 16 /* CMOS real time clock, NMI control */ 16038136Sdfr#define IO_TMRSIZE 16 /* 8253 programmable timers */ 16138136Sdfr#define IO_VGASIZE 16 /* VGA controllers */ 16238136Sdfr#define IO_WDCSIZE 8 /* WD compatible disk controllers */ 16338136Sdfr 16438136Sdfr#endif /* !IO_ISASIZES */ 16538136Sdfr 16638136Sdfr/* 16738136Sdfr * Input / Output Memory Physical Addresses 16838136Sdfr */ 16938136Sdfr#ifndef IOM_BEGIN 17038136Sdfr#define IOM_BEGIN 0x0A0000 /* Start of I/O Memory "hole" */ 17138136Sdfr#define IOM_END 0x100000 /* End of I/O Memory "hole" */ 17238136Sdfr#define IOM_SIZE (IOM_END - IOM_BEGIN) 17338136Sdfr#endif /* !IOM_BEGIN */ 17438136Sdfr 17538136Sdfr/* 17638136Sdfr * RAM Physical Address Space (ignoring the above mentioned "hole") 17738136Sdfr */ 17838136Sdfr#ifndef RAM_BEGIN 17938136Sdfr#define RAM_BEGIN 0x0000000 /* Start of RAM Memory */ 18038136Sdfr#define RAM_END 0x1000000 /* End of RAM Memory */ 18138136Sdfr#define RAM_SIZE (RAM_END - RAM_BEGIN) 18238136Sdfr#endif /* !RAM_BEGIN */ 18338136Sdfr 18447613Sdfr#endif /* !_ISA_ISA_H_ */ 185