166458Sdfr/*- 2170026Smarcel * Copyright (c) 2007 Marcel Moolenaar 366458Sdfr * Copyright (c) 2000 Doug Rabson 466458Sdfr * All rights reserved. 566458Sdfr * 666458Sdfr * Redistribution and use in source and binary forms, with or without 766458Sdfr * modification, are permitted provided that the following conditions 866458Sdfr * are met: 966458Sdfr * 1. Redistributions of source code must retain the above copyright 1066458Sdfr * notice, this list of conditions and the following disclaimer. 1166458Sdfr * 2. Redistributions in binary form must reproduce the above copyright 1266458Sdfr * notice, this list of conditions and the following disclaimer in the 1366458Sdfr * documentation and/or other materials provided with the distribution. 1466458Sdfr * 1566458Sdfr * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 1666458Sdfr * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 1766458Sdfr * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 1866458Sdfr * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 1966458Sdfr * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 2066458Sdfr * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 2166458Sdfr * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 2266458Sdfr * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 2366458Sdfr * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 2466458Sdfr * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 2566458Sdfr * SUCH DAMAGE. 2666458Sdfr * 27170026Smarcel * $FreeBSD$ 2866458Sdfr */ 2966458Sdfr 3066458Sdfr#ifndef _MACHINE_IA64_CPU_H_ 3166458Sdfr#define _MACHINE_IA64_CPU_H_ 3266458Sdfr 3366458Sdfr/* 34221271Smarcel * Local Interrupt ID. 35221271Smarcel */ 36221271Smarcel#define IA64_LID_GET_SAPIC_ID(x) ((u_int)((x) >> 16) & 0xffff) 37221271Smarcel#define IA64_LID_SET_SAPIC_ID(x) ((u_int)((x) & 0xffff) << 16) 38221271Smarcel 39221271Smarcel/* 40170026Smarcel * Definition of DCR bits. 41170026Smarcel */ 42170026Smarcel#define IA64_DCR_PP 0x0000000000000001 43170026Smarcel#define IA64_DCR_BE 0x0000000000000002 44170026Smarcel#define IA64_DCR_LC 0x0000000000000004 45170026Smarcel#define IA64_DCR_DM 0x0000000000000100 46170026Smarcel#define IA64_DCR_DP 0x0000000000000200 47170026Smarcel#define IA64_DCR_DK 0x0000000000000400 48170026Smarcel#define IA64_DCR_DX 0x0000000000000800 49170026Smarcel#define IA64_DCR_DR 0x0000000000001000 50170026Smarcel#define IA64_DCR_DA 0x0000000000002000 51170026Smarcel#define IA64_DCR_DD 0x0000000000004000 52170026Smarcel 53170026Smarcel#define IA64_DCR_DEFAULT \ 54170026Smarcel (IA64_DCR_DM | IA64_DCR_DP | IA64_DCR_DK | IA64_DCR_DX | \ 55170026Smarcel IA64_DCR_DR | IA64_DCR_DA | IA64_DCR_DD) 56170026Smarcel 57170026Smarcel/* 5866458Sdfr * Definition of PSR and IPSR bits. 5966458Sdfr */ 6066458Sdfr#define IA64_PSR_BE 0x0000000000000002 6166458Sdfr#define IA64_PSR_UP 0x0000000000000004 6266458Sdfr#define IA64_PSR_AC 0x0000000000000008 6366458Sdfr#define IA64_PSR_MFL 0x0000000000000010 6466458Sdfr#define IA64_PSR_MFH 0x0000000000000020 6566458Sdfr#define IA64_PSR_IC 0x0000000000002000 6666458Sdfr#define IA64_PSR_I 0x0000000000004000 6766458Sdfr#define IA64_PSR_PK 0x0000000000008000 6866458Sdfr#define IA64_PSR_DT 0x0000000000020000 6966458Sdfr#define IA64_PSR_DFL 0x0000000000040000 7066458Sdfr#define IA64_PSR_DFH 0x0000000000080000 7166458Sdfr#define IA64_PSR_SP 0x0000000000100000 7266458Sdfr#define IA64_PSR_PP 0x0000000000200000 7366458Sdfr#define IA64_PSR_DI 0x0000000000400000 7466458Sdfr#define IA64_PSR_SI 0x0000000000800000 7566458Sdfr#define IA64_PSR_DB 0x0000000001000000 7666458Sdfr#define IA64_PSR_LP 0x0000000002000000 7766458Sdfr#define IA64_PSR_TB 0x0000000004000000 7866458Sdfr#define IA64_PSR_RT 0x0000000008000000 7966458Sdfr#define IA64_PSR_CPL 0x0000000300000000 8066458Sdfr#define IA64_PSR_CPL_KERN 0x0000000000000000 8166458Sdfr#define IA64_PSR_CPL_1 0x0000000100000000 8266458Sdfr#define IA64_PSR_CPL_2 0x0000000200000000 8366458Sdfr#define IA64_PSR_CPL_USER 0x0000000300000000 8466458Sdfr#define IA64_PSR_IS 0x0000000400000000 8566458Sdfr#define IA64_PSR_MC 0x0000000800000000 8666458Sdfr#define IA64_PSR_IT 0x0000001000000000 8766458Sdfr#define IA64_PSR_ID 0x0000002000000000 8866458Sdfr#define IA64_PSR_DA 0x0000004000000000 8966458Sdfr#define IA64_PSR_DD 0x0000008000000000 9066458Sdfr#define IA64_PSR_SS 0x0000010000000000 9166458Sdfr#define IA64_PSR_RI 0x0000060000000000 9266458Sdfr#define IA64_PSR_RI_0 0x0000000000000000 9366458Sdfr#define IA64_PSR_RI_1 0x0000020000000000 9466458Sdfr#define IA64_PSR_RI_2 0x0000040000000000 9566458Sdfr#define IA64_PSR_ED 0x0000080000000000 9666458Sdfr#define IA64_PSR_BN 0x0000100000000000 9766458Sdfr#define IA64_PSR_IA 0x0000200000000000 9866458Sdfr 9966458Sdfr/* 10066458Sdfr * Definition of ISR bits. 10166458Sdfr */ 10266458Sdfr#define IA64_ISR_CODE 0x000000000000ffff 10366458Sdfr#define IA64_ISR_VECTOR 0x0000000000ff0000 10466458Sdfr#define IA64_ISR_X 0x0000000100000000 10566458Sdfr#define IA64_ISR_W 0x0000000200000000 10666458Sdfr#define IA64_ISR_R 0x0000000400000000 10766458Sdfr#define IA64_ISR_NA 0x0000000800000000 10866458Sdfr#define IA64_ISR_SP 0x0000001000000000 10966458Sdfr#define IA64_ISR_RS 0x0000002000000000 11066458Sdfr#define IA64_ISR_IR 0x0000004000000000 11166458Sdfr#define IA64_ISR_NI 0x0000008000000000 11266458Sdfr#define IA64_ISR_SO 0x0000010000000000 11366458Sdfr#define IA64_ISR_EI 0x0000060000000000 11466458Sdfr#define IA64_ISR_EI_0 0x0000000000000000 11566458Sdfr#define IA64_ISR_EI_1 0x0000020000000000 11666458Sdfr#define IA64_ISR_EI_2 0x0000040000000000 11766458Sdfr#define IA64_ISR_ED 0x0000080000000000 11866458Sdfr 11966458Sdfr/* 12066458Sdfr * Vector numbers for various ia64 interrupts. 12166458Sdfr */ 12266458Sdfr#define IA64_VEC_VHPT 0 12366458Sdfr#define IA64_VEC_ITLB 1 12466458Sdfr#define IA64_VEC_DTLB 2 12566458Sdfr#define IA64_VEC_ALT_ITLB 3 12666458Sdfr#define IA64_VEC_ALT_DTLB 4 12766458Sdfr#define IA64_VEC_NESTED_DTLB 5 12866458Sdfr#define IA64_VEC_IKEY_MISS 6 12966458Sdfr#define IA64_VEC_DKEY_MISS 7 13066458Sdfr#define IA64_VEC_DIRTY_BIT 8 13166458Sdfr#define IA64_VEC_INST_ACCESS 9 13266458Sdfr#define IA64_VEC_DATA_ACCESS 10 13366458Sdfr#define IA64_VEC_BREAK 11 13466458Sdfr#define IA64_VEC_EXT_INTR 12 13566458Sdfr#define IA64_VEC_PAGE_NOT_PRESENT 20 13666458Sdfr#define IA64_VEC_KEY_PERMISSION 21 13766458Sdfr#define IA64_VEC_INST_ACCESS_RIGHTS 22 13866458Sdfr#define IA64_VEC_DATA_ACCESS_RIGHTS 23 13966458Sdfr#define IA64_VEC_GENERAL_EXCEPTION 24 14066458Sdfr#define IA64_VEC_DISABLED_FP 25 14166458Sdfr#define IA64_VEC_NAT_CONSUMPTION 26 14266458Sdfr#define IA64_VEC_SPECULATION 27 14366458Sdfr#define IA64_VEC_DEBUG 29 14466458Sdfr#define IA64_VEC_UNALIGNED_REFERENCE 30 14566458Sdfr#define IA64_VEC_UNSUPP_DATA_REFERENCE 31 14666458Sdfr#define IA64_VEC_FLOATING_POINT_FAULT 32 14766458Sdfr#define IA64_VEC_FLOATING_POINT_TRAP 33 14866458Sdfr#define IA64_VEC_LOWER_PRIVILEGE_TRANSFER 34 14966458Sdfr#define IA64_VEC_TAKEN_BRANCH_TRAP 35 15066458Sdfr#define IA64_VEC_SINGLE_STEP_TRAP 36 15166458Sdfr#define IA64_VEC_IA32_EXCEPTION 45 15266458Sdfr#define IA64_VEC_IA32_INTERCEPT 46 15366458Sdfr#define IA64_VEC_IA32_INTERRUPT 47 15466458Sdfr 15566458Sdfr/* 15694373Sdfr * IA-32 exceptions. 15794373Sdfr */ 15894373Sdfr#define IA32_EXCEPTION_DIVIDE 0 15994373Sdfr#define IA32_EXCEPTION_DEBUG 1 16094373Sdfr#define IA32_EXCEPTION_BREAK 3 16194373Sdfr#define IA32_EXCEPTION_OVERFLOW 4 16294373Sdfr#define IA32_EXCEPTION_BOUND 5 16394373Sdfr#define IA32_EXCEPTION_DNA 7 16494373Sdfr#define IA32_EXCEPTION_NOT_PRESENT 11 16594373Sdfr#define IA32_EXCEPTION_STACK_FAULT 12 16694373Sdfr#define IA32_EXCEPTION_GPFAULT 13 16794373Sdfr#define IA32_EXCEPTION_FPERROR 16 16894373Sdfr#define IA32_EXCEPTION_ALIGNMENT_CHECK 17 16994373Sdfr#define IA32_EXCEPTION_STREAMING_SIMD 19 17094373Sdfr 17194373Sdfr#define IA32_INTERCEPT_INSTRUCTION 0 17294373Sdfr#define IA32_INTERCEPT_GATE 1 17394373Sdfr#define IA32_INTERCEPT_SYSTEM_FLAG 2 17494373Sdfr#define IA32_INTERCEPT_LOCK 4 17594373Sdfr 17667522Sdfr#ifndef LOCORE 17767522Sdfr 17866458Sdfr/* 17966458Sdfr * Various special ia64 instructions. 18066458Sdfr */ 18166458Sdfr 18266458Sdfr/* 18366458Sdfr * Memory Fence. 18466458Sdfr */ 18566458Sdfrstatic __inline void 18666458Sdfria64_mf(void) 18766458Sdfr{ 18866458Sdfr __asm __volatile("mf"); 18966458Sdfr} 19066458Sdfr 19183510Sdfrstatic __inline void 19283510Sdfria64_mf_a(void) 19383510Sdfr{ 19483510Sdfr __asm __volatile("mf.a"); 19583510Sdfr} 19683510Sdfr 19766458Sdfr/* 19883766Sdfr * Flush Cache. 19983766Sdfr */ 20083766Sdfrstatic __inline void 201208283Smarcelia64_fc(uint64_t va) 20283766Sdfr{ 20383766Sdfr __asm __volatile("fc %0" :: "r"(va)); 20483766Sdfr} 20583766Sdfr 206180354Smarcelstatic __inline void 207208283Smarcelia64_fc_i(uint64_t va) 208180354Smarcel{ 209180354Smarcel __asm __volatile("fc.i %0" :: "r"(va)); 210180354Smarcel} 211180354Smarcel 21283766Sdfr/* 21392271Sdfr * Sync instruction stream. 21492271Sdfr */ 21592271Sdfrstatic __inline void 21692271Sdfria64_sync_i(void) 21792271Sdfr{ 21892271Sdfr __asm __volatile("sync.i"); 21992271Sdfr} 22092271Sdfr 22192271Sdfr/* 22266458Sdfr * Calculate address in VHPT for va. 22366458Sdfr */ 224208283Smarcelstatic __inline uint64_t 225208283Smarcelia64_thash(uint64_t va) 22666458Sdfr{ 227208283Smarcel uint64_t result; 22866458Sdfr __asm __volatile("thash %0=%1" : "=r" (result) : "r" (va)); 22966458Sdfr return result; 23066458Sdfr} 23166458Sdfr 23266458Sdfr/* 23366458Sdfr * Calculate VHPT tag for va. 23466458Sdfr */ 235208283Smarcelstatic __inline uint64_t 236208283Smarcelia64_ttag(uint64_t va) 23766458Sdfr{ 238208283Smarcel uint64_t result; 23966458Sdfr __asm __volatile("ttag %0=%1" : "=r" (result) : "r" (va)); 24066458Sdfr return result; 24166458Sdfr} 24266458Sdfr 24366458Sdfr/* 24466458Sdfr * Convert virtual address to physical. 24566458Sdfr */ 246208283Smarcelstatic __inline uint64_t 247208283Smarcelia64_tpa(uint64_t va) 24866458Sdfr{ 249208283Smarcel uint64_t result; 25066458Sdfr __asm __volatile("tpa %0=%1" : "=r" (result) : "r" (va)); 25166458Sdfr return result; 25266458Sdfr} 25366458Sdfr 25466458Sdfr/* 25566937Sdfr * Generate a ptc.e instruction. 25666937Sdfr */ 25766937Sdfrstatic __inline void 258208283Smarcelia64_ptc_e(uint64_t v) 25966937Sdfr{ 260148804Smarcel __asm __volatile("ptc.e %0;; srlz.i;;" :: "r"(v)); 26166937Sdfr} 26266937Sdfr 26366937Sdfr/* 26466937Sdfr * Generate a ptc.g instruction. 26566937Sdfr */ 26666937Sdfrstatic __inline void 267208283Smarcelia64_ptc_g(uint64_t va, uint64_t log2size) 26866937Sdfr{ 269223170Smarcel __asm __volatile("ptc.g %0,%1;;" :: "r"(va), "r"(log2size)); 27066937Sdfr} 27166937Sdfr 27266937Sdfr/* 27366937Sdfr * Generate a ptc.ga instruction. 27466937Sdfr */ 27566937Sdfrstatic __inline void 276208283Smarcelia64_ptc_ga(uint64_t va, uint64_t log2size) 27766937Sdfr{ 278223170Smarcel __asm __volatile("ptc.ga %0,%1;;" :: "r"(va), "r"(log2size)); 27966937Sdfr} 28066937Sdfr 28166937Sdfr/* 28266937Sdfr * Generate a ptc.l instruction. 28366937Sdfr */ 28466937Sdfrstatic __inline void 285208283Smarcelia64_ptc_l(uint64_t va, uint64_t log2size) 28666937Sdfr{ 287148804Smarcel __asm __volatile("ptc.l %0,%1;; srlz.i;;" :: "r"(va), "r"(log2size)); 28866937Sdfr} 28966937Sdfr 29066937Sdfr/* 291223170Smarcel * Invalidate the ALAT on the local processor. 292223170Smarcel */ 293223170Smarcelstatic __inline void 294223170Smarcelia64_invala(void) 295223170Smarcel{ 296223170Smarcel __asm __volatile("invala;;"); 297223170Smarcel} 298223170Smarcel 299223170Smarcel/* 300200051Smarcel * Unordered memory load. 301200051Smarcel */ 302200051Smarcel 303200051Smarcelstatic __inline uint8_t 304200051Smarcelia64_ld1(uint8_t *p) 305200051Smarcel{ 306200051Smarcel uint8_t v; 307200051Smarcel 308200051Smarcel __asm __volatile("ld1 %0=[%1];;" : "=r"(v) : "r"(p)); 309200051Smarcel return (v); 310200051Smarcel} 311200051Smarcel 312200051Smarcelstatic __inline uint16_t 313200051Smarcelia64_ld2(uint16_t *p) 314200051Smarcel{ 315200051Smarcel uint16_t v; 316200051Smarcel 317200051Smarcel __asm __volatile("ld2 %0=[%1];;" : "=r"(v) : "r"(p)); 318200051Smarcel return (v); 319200051Smarcel} 320200051Smarcel 321200051Smarcelstatic __inline uint32_t 322200051Smarcelia64_ld4(uint32_t *p) 323200051Smarcel{ 324200051Smarcel uint32_t v; 325200051Smarcel 326200051Smarcel __asm __volatile("ld4 %0=[%1];;" : "=r"(v) : "r"(p)); 327200051Smarcel return (v); 328200051Smarcel} 329200051Smarcel 330200051Smarcelstatic __inline uint64_t 331200051Smarcelia64_ld8(uint64_t *p) 332200051Smarcel{ 333200051Smarcel uint64_t v; 334200051Smarcel 335200051Smarcel __asm __volatile("ld8 %0=[%1];;" : "=r"(v) : "r"(p)); 336200051Smarcel return (v); 337200051Smarcel} 338200051Smarcel 339200051Smarcel/* 340200051Smarcel * Unordered memory store. 341200051Smarcel */ 342200051Smarcel 343200051Smarcelstatic __inline void 344200051Smarcelia64_st1(uint8_t *p, uint8_t v) 345200051Smarcel{ 346200051Smarcel __asm __volatile("st1 [%0]=%1;;" :: "r"(p), "r"(v)); 347200051Smarcel} 348200051Smarcel 349200051Smarcelstatic __inline void 350200051Smarcelia64_st2(uint16_t *p, uint16_t v) 351200051Smarcel{ 352200051Smarcel __asm __volatile("st2 [%0]=%1;;" :: "r"(p), "r"(v)); 353200051Smarcel} 354200051Smarcel 355200051Smarcelstatic __inline void 356200051Smarcelia64_st4(uint32_t *p, uint32_t v) 357200051Smarcel{ 358200051Smarcel __asm __volatile("st4 [%0]=%1;;" :: "r"(p), "r"(v)); 359200051Smarcel} 360200051Smarcel 361200051Smarcelstatic __inline void 362200051Smarcelia64_st8(uint64_t *p, uint64_t v) 363200051Smarcel{ 364200051Smarcel __asm __volatile("st8 [%0]=%1;;" :: "r"(p), "r"(v)); 365200051Smarcel} 366200051Smarcel 367200051Smarcel/* 36872895Sjhb * Read the value of psr. 36972895Sjhb */ 370208283Smarcelstatic __inline uint64_t 37172895Sjhbia64_get_psr(void) 37272895Sjhb{ 373208283Smarcel uint64_t result; 37472895Sjhb __asm __volatile("mov %0=psr;;" : "=r" (result)); 37572895Sjhb return result; 37672895Sjhb} 37772895Sjhb 37872895Sjhb/* 37994271Sdfr * Define accessors for application registers. 38085282Sdfr */ 38185282Sdfr 38294271Sdfr#define IA64_AR(name) \ 38394271Sdfr \ 384208283Smarcelstatic __inline uint64_t \ 38594271Sdfria64_get_##name(void) \ 38694271Sdfr{ \ 387208283Smarcel uint64_t result; \ 38894271Sdfr __asm __volatile("mov %0=ar." #name : "=r" (result)); \ 38994271Sdfr return result; \ 39094271Sdfr} \ 39194271Sdfr \ 39294271Sdfrstatic __inline void \ 393208283Smarcelia64_set_##name(uint64_t v) \ 39494271Sdfr{ \ 395118934Smarcel __asm __volatile("mov ar." #name "=%0;;" :: "r" (v)); \ 39666633Sdfr} 39766633Sdfr 39894271SdfrIA64_AR(k0) 39994271SdfrIA64_AR(k1) 40094271SdfrIA64_AR(k2) 40194271SdfrIA64_AR(k3) 40294271SdfrIA64_AR(k4) 40394271SdfrIA64_AR(k5) 40494271SdfrIA64_AR(k6) 40594271SdfrIA64_AR(k7) 40666633Sdfr 40794271SdfrIA64_AR(rsc) 40894271SdfrIA64_AR(bsp) 40994271SdfrIA64_AR(bspstore) 41094271SdfrIA64_AR(rnat) 41166633Sdfr 41294271SdfrIA64_AR(fcr) 41366633Sdfr 41494271SdfrIA64_AR(eflag) 41594271SdfrIA64_AR(csd) 41694271SdfrIA64_AR(ssd) 41794271SdfrIA64_AR(cflg) 41894271SdfrIA64_AR(fsr) 41994271SdfrIA64_AR(fir) 42094271SdfrIA64_AR(fdr) 42166633Sdfr 42294271SdfrIA64_AR(ccv) 42366633Sdfr 42494271SdfrIA64_AR(unat) 42566633Sdfr 42694271SdfrIA64_AR(fpsr) 42766633Sdfr 42894271SdfrIA64_AR(itc) 42966633Sdfr 43094271SdfrIA64_AR(pfs) 43194271SdfrIA64_AR(lc) 43294271SdfrIA64_AR(ec) 43366633Sdfr 43466633Sdfr/* 43594271Sdfr * Define accessors for control registers. 43666633Sdfr */ 43766633Sdfr 43894271Sdfr#define IA64_CR(name) \ 43994271Sdfr \ 440208283Smarcelstatic __inline uint64_t \ 44194271Sdfria64_get_##name(void) \ 44294271Sdfr{ \ 443208283Smarcel uint64_t result; \ 44494271Sdfr __asm __volatile("mov %0=cr." #name : "=r" (result)); \ 44594271Sdfr return result; \ 44694271Sdfr} \ 44794271Sdfr \ 44894271Sdfrstatic __inline void \ 449208283Smarcelia64_set_##name(uint64_t v) \ 45094271Sdfr{ \ 451118934Smarcel __asm __volatile("mov cr." #name "=%0;;" :: "r" (v)); \ 45266633Sdfr} 45366633Sdfr 45494271SdfrIA64_CR(dcr) 45594271SdfrIA64_CR(itm) 45694271SdfrIA64_CR(iva) 45766633Sdfr 45894271SdfrIA64_CR(pta) 45966633Sdfr 46094271SdfrIA64_CR(ipsr) 46194271SdfrIA64_CR(isr) 46266633Sdfr 46394271SdfrIA64_CR(iip) 46494271SdfrIA64_CR(ifa) 46594271SdfrIA64_CR(itir) 46694271SdfrIA64_CR(iipa) 46794271SdfrIA64_CR(ifs) 46894271SdfrIA64_CR(iim) 46994271SdfrIA64_CR(iha) 47066633Sdfr 47194271SdfrIA64_CR(lid) 47294271SdfrIA64_CR(ivr) 47394271SdfrIA64_CR(tpr) 47494271SdfrIA64_CR(eoi) 47594271SdfrIA64_CR(irr0) 47694271SdfrIA64_CR(irr1) 47794271SdfrIA64_CR(irr2) 47894271SdfrIA64_CR(irr3) 47994271SdfrIA64_CR(itv) 48094271SdfrIA64_CR(pmv) 48194271SdfrIA64_CR(cmcv) 48266458Sdfr 48394271SdfrIA64_CR(lrr0) 48494271SdfrIA64_CR(lrr1) 48566486Sdfr 48666486Sdfr/* 48766486Sdfr * Write a region register. 48866486Sdfr */ 48966486Sdfrstatic __inline void 490208283Smarcelia64_set_rr(uint64_t rrbase, uint64_t v) 49166458Sdfr{ 492171735Smarcel __asm __volatile("mov rr[%0]=%1" 49385356Sdfr :: "r"(rrbase), "r"(v) : "memory"); 49466458Sdfr} 49566458Sdfr 49683622Sdfr/* 49783622Sdfr * Read a CPUID register. 49883622Sdfr */ 499208283Smarcelstatic __inline uint64_t 50083622Sdfria64_get_cpuid(int i) 50183622Sdfr{ 502208283Smarcel uint64_t result; 50383622Sdfr __asm __volatile("mov %0=cpuid[%1]" 50483622Sdfr : "=r" (result) : "r"(i)); 50583622Sdfr return result; 50683622Sdfr} 50783622Sdfr 508117499Smarcelstatic __inline void 509117499Smarcelia64_disable_highfp(void) 510117499Smarcel{ 511117499Smarcel __asm __volatile("ssm psr.dfh;; srlz.d"); 512117499Smarcel} 51367522Sdfr 514117499Smarcelstatic __inline void 515117499Smarcelia64_enable_highfp(void) 516117499Smarcel{ 517117499Smarcel __asm __volatile("rsm psr.dfh;; srlz.d"); 518117499Smarcel} 519117499Smarcel 520221889Smarcel/* 521221889Smarcel * Avoid inline functions for the following so that they still work 522221889Smarcel * correctly when inlining is not enabled (e.g. -O0). Function calls 523221889Smarcel * need data serialization after setting psr, which results in a 524221889Smarcel * hazard. 525221889Smarcel */ 526221889Smarcel#define ia64_srlz_d() __asm __volatile("srlz.d") 527221889Smarcel#define ia64_srlz_i() __asm __volatile("srlz.i;;") 528171718Smarcel 529117499Smarcel#endif /* !LOCORE */ 530117499Smarcel 53166458Sdfr#endif /* _MACHINE_IA64_CPU_H_ */ 53266458Sdfr 533