mp_machdep.c revision 265606
1/*- 2 * Copyright (c) 1996, by Steve Passe 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. The name of the developer may NOT be used to endorse or promote products 11 * derived from this software without specific prior written permission. 12 * 13 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 14 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 15 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 16 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 17 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 18 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 19 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 20 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 21 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 22 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 23 * SUCH DAMAGE. 24 */ 25 26#include <sys/cdefs.h> 27__FBSDID("$FreeBSD: stable/10/sys/i386/i386/mp_machdep.c 265606 2014-05-07 20:28:27Z scottl $"); 28 29#include "opt_apic.h" 30#include "opt_cpu.h" 31#include "opt_kstack_pages.h" 32#include "opt_pmap.h" 33#include "opt_sched.h" 34#include "opt_smp.h" 35 36#if !defined(lint) 37#if !defined(SMP) 38#error How did you get here? 39#endif 40 41#ifndef DEV_APIC 42#error The apic device is required for SMP, add "device apic" to your config file. 43#endif 44#if defined(CPU_DISABLE_CMPXCHG) && !defined(COMPILING_LINT) 45#error SMP not supported with CPU_DISABLE_CMPXCHG 46#endif 47#endif /* not lint */ 48 49#include <sys/param.h> 50#include <sys/systm.h> 51#include <sys/bus.h> 52#include <sys/cons.h> /* cngetc() */ 53#include <sys/cpuset.h> 54#ifdef GPROF 55#include <sys/gmon.h> 56#endif 57#include <sys/kernel.h> 58#include <sys/ktr.h> 59#include <sys/lock.h> 60#include <sys/malloc.h> 61#include <sys/memrange.h> 62#include <sys/mutex.h> 63#include <sys/pcpu.h> 64#include <sys/proc.h> 65#include <sys/sched.h> 66#include <sys/smp.h> 67#include <sys/sysctl.h> 68 69#include <vm/vm.h> 70#include <vm/vm_param.h> 71#include <vm/pmap.h> 72#include <vm/vm_kern.h> 73#include <vm/vm_extern.h> 74 75#include <x86/apicreg.h> 76#include <machine/clock.h> 77#include <machine/cputypes.h> 78#include <x86/mca.h> 79#include <machine/md_var.h> 80#include <machine/pcb.h> 81#include <machine/psl.h> 82#include <machine/smp.h> 83#include <machine/specialreg.h> 84#include <machine/cpu.h> 85 86#define WARMBOOT_TARGET 0 87#define WARMBOOT_OFF (KERNBASE + 0x0467) 88#define WARMBOOT_SEG (KERNBASE + 0x0469) 89 90#define CMOS_REG (0x70) 91#define CMOS_DATA (0x71) 92#define BIOS_RESET (0x0f) 93#define BIOS_WARM (0x0a) 94 95/* 96 * this code MUST be enabled here and in mpboot.s. 97 * it follows the very early stages of AP boot by placing values in CMOS ram. 98 * it NORMALLY will never be needed and thus the primitive method for enabling. 99 * 100#define CHECK_POINTS 101 */ 102 103#if defined(CHECK_POINTS) && !defined(PC98) 104#define CHECK_READ(A) (outb(CMOS_REG, (A)), inb(CMOS_DATA)) 105#define CHECK_WRITE(A,D) (outb(CMOS_REG, (A)), outb(CMOS_DATA, (D))) 106 107#define CHECK_INIT(D); \ 108 CHECK_WRITE(0x34, (D)); \ 109 CHECK_WRITE(0x35, (D)); \ 110 CHECK_WRITE(0x36, (D)); \ 111 CHECK_WRITE(0x37, (D)); \ 112 CHECK_WRITE(0x38, (D)); \ 113 CHECK_WRITE(0x39, (D)); 114 115#define CHECK_PRINT(S); \ 116 printf("%s: %d, %d, %d, %d, %d, %d\n", \ 117 (S), \ 118 CHECK_READ(0x34), \ 119 CHECK_READ(0x35), \ 120 CHECK_READ(0x36), \ 121 CHECK_READ(0x37), \ 122 CHECK_READ(0x38), \ 123 CHECK_READ(0x39)); 124 125#else /* CHECK_POINTS */ 126 127#define CHECK_INIT(D) 128#define CHECK_PRINT(S) 129#define CHECK_WRITE(A, D) 130 131#endif /* CHECK_POINTS */ 132 133/* lock region used by kernel profiling */ 134int mcount_lock; 135 136int mp_naps; /* # of Applications processors */ 137int boot_cpu_id = -1; /* designated BSP */ 138 139extern struct pcpu __pcpu[]; 140 141/* AP uses this during bootstrap. Do not staticize. */ 142char *bootSTK; 143static int bootAP; 144 145/* Free these after use */ 146void *bootstacks[MAXCPU]; 147static void *dpcpu; 148 149struct pcb stoppcbs[MAXCPU]; 150struct pcb **susppcbs = NULL; 151 152/* Variables needed for SMP tlb shootdown. */ 153vm_offset_t smp_tlb_addr1; 154vm_offset_t smp_tlb_addr2; 155volatile int smp_tlb_wait; 156 157#ifdef COUNT_IPIS 158/* Interrupt counts. */ 159static u_long *ipi_preempt_counts[MAXCPU]; 160static u_long *ipi_ast_counts[MAXCPU]; 161u_long *ipi_invltlb_counts[MAXCPU]; 162u_long *ipi_invlrng_counts[MAXCPU]; 163u_long *ipi_invlpg_counts[MAXCPU]; 164u_long *ipi_invlcache_counts[MAXCPU]; 165u_long *ipi_rendezvous_counts[MAXCPU]; 166u_long *ipi_lazypmap_counts[MAXCPU]; 167static u_long *ipi_hardclock_counts[MAXCPU]; 168#endif 169 170/* Default cpu_ops implementation. */ 171struct cpu_ops cpu_ops = { 172 .ipi_vectored = lapic_ipi_vectored 173}; 174 175/* 176 * Local data and functions. 177 */ 178 179static volatile cpuset_t ipi_nmi_pending; 180 181/* used to hold the AP's until we are ready to release them */ 182static struct mtx ap_boot_mtx; 183 184/* Set to 1 once we're ready to let the APs out of the pen. */ 185static volatile int aps_ready = 0; 186 187/* 188 * Store data from cpu_add() until later in the boot when we actually setup 189 * the APs. 190 */ 191struct cpu_info { 192 int cpu_present:1; 193 int cpu_bsp:1; 194 int cpu_disabled:1; 195 int cpu_hyperthread:1; 196} static cpu_info[MAX_APIC_ID + 1]; 197int cpu_apic_ids[MAXCPU]; 198int apic_cpuids[MAX_APIC_ID + 1]; 199 200/* Holds pending bitmap based IPIs per CPU */ 201volatile u_int cpu_ipi_pending[MAXCPU]; 202 203static u_int boot_address; 204static int cpu_logical; /* logical cpus per core */ 205static int cpu_cores; /* cores per package */ 206 207static void assign_cpu_ids(void); 208static void install_ap_tramp(void); 209static void set_interrupt_apic_ids(void); 210static int start_all_aps(void); 211static int start_ap(int apic_id); 212static void release_aps(void *dummy); 213 214static u_int hyperthreading_cpus; /* logical cpus sharing L1 cache */ 215static int hyperthreading_allowed = 1; 216 217static void 218mem_range_AP_init(void) 219{ 220 if (mem_range_softc.mr_op && mem_range_softc.mr_op->initAP) 221 mem_range_softc.mr_op->initAP(&mem_range_softc); 222} 223 224static void 225topo_probe_amd(void) 226{ 227 int core_id_bits; 228 int id; 229 230 /* AMD processors do not support HTT. */ 231 cpu_logical = 1; 232 233 if ((amd_feature2 & AMDID2_CMP) == 0) { 234 cpu_cores = 1; 235 return; 236 } 237 238 core_id_bits = (cpu_procinfo2 & AMDID_COREID_SIZE) >> 239 AMDID_COREID_SIZE_SHIFT; 240 if (core_id_bits == 0) { 241 cpu_cores = (cpu_procinfo2 & AMDID_CMP_CORES) + 1; 242 return; 243 } 244 245 /* Fam 10h and newer should get here. */ 246 for (id = 0; id <= MAX_APIC_ID; id++) { 247 /* Check logical CPU availability. */ 248 if (!cpu_info[id].cpu_present || cpu_info[id].cpu_disabled) 249 continue; 250 /* Check if logical CPU has the same package ID. */ 251 if ((id >> core_id_bits) != (boot_cpu_id >> core_id_bits)) 252 continue; 253 cpu_cores++; 254 } 255} 256 257/* 258 * Round up to the next power of two, if necessary, and then 259 * take log2. 260 * Returns -1 if argument is zero. 261 */ 262static __inline int 263mask_width(u_int x) 264{ 265 266 return (fls(x << (1 - powerof2(x))) - 1); 267} 268 269static void 270topo_probe_0x4(void) 271{ 272 u_int p[4]; 273 int pkg_id_bits; 274 int core_id_bits; 275 int max_cores; 276 int max_logical; 277 int id; 278 279 /* Both zero and one here mean one logical processor per package. */ 280 max_logical = (cpu_feature & CPUID_HTT) != 0 ? 281 (cpu_procinfo & CPUID_HTT_CORES) >> 16 : 1; 282 if (max_logical <= 1) 283 return; 284 285 /* 286 * Because of uniformity assumption we examine only 287 * those logical processors that belong to the same 288 * package as BSP. Further, we count number of 289 * logical processors that belong to the same core 290 * as BSP thus deducing number of threads per core. 291 */ 292 if (cpu_high >= 0x4) { 293 cpuid_count(0x04, 0, p); 294 max_cores = ((p[0] >> 26) & 0x3f) + 1; 295 } else 296 max_cores = 1; 297 core_id_bits = mask_width(max_logical/max_cores); 298 if (core_id_bits < 0) 299 return; 300 pkg_id_bits = core_id_bits + mask_width(max_cores); 301 302 for (id = 0; id <= MAX_APIC_ID; id++) { 303 /* Check logical CPU availability. */ 304 if (!cpu_info[id].cpu_present || cpu_info[id].cpu_disabled) 305 continue; 306 /* Check if logical CPU has the same package ID. */ 307 if ((id >> pkg_id_bits) != (boot_cpu_id >> pkg_id_bits)) 308 continue; 309 cpu_cores++; 310 /* Check if logical CPU has the same package and core IDs. */ 311 if ((id >> core_id_bits) == (boot_cpu_id >> core_id_bits)) 312 cpu_logical++; 313 } 314 315 KASSERT(cpu_cores >= 1 && cpu_logical >= 1, 316 ("topo_probe_0x4 couldn't find BSP")); 317 318 cpu_cores /= cpu_logical; 319 hyperthreading_cpus = cpu_logical; 320} 321 322static void 323topo_probe_0xb(void) 324{ 325 u_int p[4]; 326 int bits; 327 int cnt; 328 int i; 329 int logical; 330 int type; 331 int x; 332 333 /* We only support three levels for now. */ 334 for (i = 0; i < 3; i++) { 335 cpuid_count(0x0b, i, p); 336 337 /* Fall back if CPU leaf 11 doesn't really exist. */ 338 if (i == 0 && p[1] == 0) { 339 topo_probe_0x4(); 340 return; 341 } 342 343 bits = p[0] & 0x1f; 344 logical = p[1] &= 0xffff; 345 type = (p[2] >> 8) & 0xff; 346 if (type == 0 || logical == 0) 347 break; 348 /* 349 * Because of uniformity assumption we examine only 350 * those logical processors that belong to the same 351 * package as BSP. 352 */ 353 for (cnt = 0, x = 0; x <= MAX_APIC_ID; x++) { 354 if (!cpu_info[x].cpu_present || 355 cpu_info[x].cpu_disabled) 356 continue; 357 if (x >> bits == boot_cpu_id >> bits) 358 cnt++; 359 } 360 if (type == CPUID_TYPE_SMT) 361 cpu_logical = cnt; 362 else if (type == CPUID_TYPE_CORE) 363 cpu_cores = cnt; 364 } 365 if (cpu_logical == 0) 366 cpu_logical = 1; 367 cpu_cores /= cpu_logical; 368} 369 370/* 371 * Both topology discovery code and code that consumes topology 372 * information assume top-down uniformity of the topology. 373 * That is, all physical packages must be identical and each 374 * core in a package must have the same number of threads. 375 * Topology information is queried only on BSP, on which this 376 * code runs and for which it can query CPUID information. 377 * Then topology is extrapolated on all packages using the 378 * uniformity assumption. 379 */ 380static void 381topo_probe(void) 382{ 383 static int cpu_topo_probed = 0; 384 385 if (cpu_topo_probed) 386 return; 387 388 CPU_ZERO(&logical_cpus_mask); 389 if (mp_ncpus <= 1) 390 cpu_cores = cpu_logical = 1; 391 else if (cpu_vendor_id == CPU_VENDOR_AMD) 392 topo_probe_amd(); 393 else if (cpu_vendor_id == CPU_VENDOR_INTEL) { 394 /* 395 * See Intel(R) 64 Architecture Processor 396 * Topology Enumeration article for details. 397 * 398 * Note that 0x1 <= cpu_high < 4 case should be 399 * compatible with topo_probe_0x4() logic when 400 * CPUID.1:EBX[23:16] > 0 (cpu_cores will be 1) 401 * or it should trigger the fallback otherwise. 402 */ 403 if (cpu_high >= 0xb) 404 topo_probe_0xb(); 405 else if (cpu_high >= 0x1) 406 topo_probe_0x4(); 407 } 408 409 /* 410 * Fallback: assume each logical CPU is in separate 411 * physical package. That is, no multi-core, no SMT. 412 */ 413 if (cpu_cores == 0 || cpu_logical == 0) 414 cpu_cores = cpu_logical = 1; 415 cpu_topo_probed = 1; 416} 417 418struct cpu_group * 419cpu_topo(void) 420{ 421 int cg_flags; 422 423 /* 424 * Determine whether any threading flags are 425 * necessry. 426 */ 427 topo_probe(); 428 if (cpu_logical > 1 && hyperthreading_cpus) 429 cg_flags = CG_FLAG_HTT; 430 else if (cpu_logical > 1) 431 cg_flags = CG_FLAG_SMT; 432 else 433 cg_flags = 0; 434 if (mp_ncpus % (cpu_cores * cpu_logical) != 0) { 435 printf("WARNING: Non-uniform processors.\n"); 436 printf("WARNING: Using suboptimal topology.\n"); 437 return (smp_topo_none()); 438 } 439 /* 440 * No multi-core or hyper-threaded. 441 */ 442 if (cpu_logical * cpu_cores == 1) 443 return (smp_topo_none()); 444 /* 445 * Only HTT no multi-core. 446 */ 447 if (cpu_logical > 1 && cpu_cores == 1) 448 return (smp_topo_1level(CG_SHARE_L1, cpu_logical, cg_flags)); 449 /* 450 * Only multi-core no HTT. 451 */ 452 if (cpu_cores > 1 && cpu_logical == 1) 453 return (smp_topo_1level(CG_SHARE_L2, cpu_cores, cg_flags)); 454 /* 455 * Both HTT and multi-core. 456 */ 457 return (smp_topo_2level(CG_SHARE_L2, cpu_cores, 458 CG_SHARE_L1, cpu_logical, cg_flags)); 459} 460 461 462/* 463 * Calculate usable address in base memory for AP trampoline code. 464 */ 465u_int 466mp_bootaddress(u_int basemem) 467{ 468 469 boot_address = trunc_page(basemem); /* round down to 4k boundary */ 470 if ((basemem - boot_address) < bootMP_size) 471 boot_address -= PAGE_SIZE; /* not enough, lower by 4k */ 472 473 return boot_address; 474} 475 476void 477cpu_add(u_int apic_id, char boot_cpu) 478{ 479 480 if (apic_id > MAX_APIC_ID) { 481 panic("SMP: APIC ID %d too high", apic_id); 482 return; 483 } 484 KASSERT(cpu_info[apic_id].cpu_present == 0, ("CPU %d added twice", 485 apic_id)); 486 cpu_info[apic_id].cpu_present = 1; 487 if (boot_cpu) { 488 KASSERT(boot_cpu_id == -1, 489 ("CPU %d claims to be BSP, but CPU %d already is", apic_id, 490 boot_cpu_id)); 491 boot_cpu_id = apic_id; 492 cpu_info[apic_id].cpu_bsp = 1; 493 } 494 if (mp_ncpus < MAXCPU) { 495 mp_ncpus++; 496 mp_maxid = mp_ncpus - 1; 497 } 498 if (bootverbose) 499 printf("SMP: Added CPU %d (%s)\n", apic_id, boot_cpu ? "BSP" : 500 "AP"); 501} 502 503void 504cpu_mp_setmaxid(void) 505{ 506 507 /* 508 * mp_maxid should be already set by calls to cpu_add(). 509 * Just sanity check its value here. 510 */ 511 if (mp_ncpus == 0) 512 KASSERT(mp_maxid == 0, 513 ("%s: mp_ncpus is zero, but mp_maxid is not", __func__)); 514 else if (mp_ncpus == 1) 515 mp_maxid = 0; 516 else 517 KASSERT(mp_maxid >= mp_ncpus - 1, 518 ("%s: counters out of sync: max %d, count %d", __func__, 519 mp_maxid, mp_ncpus)); 520} 521 522int 523cpu_mp_probe(void) 524{ 525 526 /* 527 * Always record BSP in CPU map so that the mbuf init code works 528 * correctly. 529 */ 530 CPU_SETOF(0, &all_cpus); 531 if (mp_ncpus == 0) { 532 /* 533 * No CPUs were found, so this must be a UP system. Setup 534 * the variables to represent a system with a single CPU 535 * with an id of 0. 536 */ 537 mp_ncpus = 1; 538 return (0); 539 } 540 541 /* At least one CPU was found. */ 542 if (mp_ncpus == 1) { 543 /* 544 * One CPU was found, so this must be a UP system with 545 * an I/O APIC. 546 */ 547 mp_maxid = 0; 548 return (0); 549 } 550 551 /* At least two CPUs were found. */ 552 return (1); 553} 554 555/* 556 * Initialize the IPI handlers and start up the AP's. 557 */ 558void 559cpu_mp_start(void) 560{ 561 int i; 562 563 /* Initialize the logical ID to APIC ID table. */ 564 for (i = 0; i < MAXCPU; i++) { 565 cpu_apic_ids[i] = -1; 566 cpu_ipi_pending[i] = 0; 567 } 568 569 /* Install an inter-CPU IPI for TLB invalidation */ 570 setidt(IPI_INVLTLB, IDTVEC(invltlb), 571 SDT_SYS386IGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL)); 572 setidt(IPI_INVLPG, IDTVEC(invlpg), 573 SDT_SYS386IGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL)); 574 setidt(IPI_INVLRNG, IDTVEC(invlrng), 575 SDT_SYS386IGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL)); 576 577 /* Install an inter-CPU IPI for cache invalidation. */ 578 setidt(IPI_INVLCACHE, IDTVEC(invlcache), 579 SDT_SYS386IGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL)); 580 581 /* Install an inter-CPU IPI for lazy pmap release */ 582 setidt(IPI_LAZYPMAP, IDTVEC(lazypmap), 583 SDT_SYS386IGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL)); 584 585 /* Install an inter-CPU IPI for all-CPU rendezvous */ 586 setidt(IPI_RENDEZVOUS, IDTVEC(rendezvous), 587 SDT_SYS386IGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL)); 588 589 /* Install generic inter-CPU IPI handler */ 590 setidt(IPI_BITMAP_VECTOR, IDTVEC(ipi_intr_bitmap_handler), 591 SDT_SYS386IGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL)); 592 593 /* Install an inter-CPU IPI for CPU stop/restart */ 594 setidt(IPI_STOP, IDTVEC(cpustop), 595 SDT_SYS386IGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL)); 596 597 /* Install an inter-CPU IPI for CPU suspend/resume */ 598 setidt(IPI_SUSPEND, IDTVEC(cpususpend), 599 SDT_SYS386IGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL)); 600 601 /* Set boot_cpu_id if needed. */ 602 if (boot_cpu_id == -1) { 603 boot_cpu_id = PCPU_GET(apic_id); 604 cpu_info[boot_cpu_id].cpu_bsp = 1; 605 } else 606 KASSERT(boot_cpu_id == PCPU_GET(apic_id), 607 ("BSP's APIC ID doesn't match boot_cpu_id")); 608 609 /* Probe logical/physical core configuration. */ 610 topo_probe(); 611 612 assign_cpu_ids(); 613 614 /* Start each Application Processor */ 615 start_all_aps(); 616 617 set_interrupt_apic_ids(); 618} 619 620 621/* 622 * Print various information about the SMP system hardware and setup. 623 */ 624void 625cpu_mp_announce(void) 626{ 627 const char *hyperthread; 628 int i; 629 630 printf("FreeBSD/SMP: %d package(s) x %d core(s)", 631 mp_ncpus / (cpu_cores * cpu_logical), cpu_cores); 632 if (hyperthreading_cpus > 1) 633 printf(" x %d HTT threads", cpu_logical); 634 else if (cpu_logical > 1) 635 printf(" x %d SMT threads", cpu_logical); 636 printf("\n"); 637 638 /* List active CPUs first. */ 639 printf(" cpu0 (BSP): APIC ID: %2d\n", boot_cpu_id); 640 for (i = 1; i < mp_ncpus; i++) { 641 if (cpu_info[cpu_apic_ids[i]].cpu_hyperthread) 642 hyperthread = "/HT"; 643 else 644 hyperthread = ""; 645 printf(" cpu%d (AP%s): APIC ID: %2d\n", i, hyperthread, 646 cpu_apic_ids[i]); 647 } 648 649 /* List disabled CPUs last. */ 650 for (i = 0; i <= MAX_APIC_ID; i++) { 651 if (!cpu_info[i].cpu_present || !cpu_info[i].cpu_disabled) 652 continue; 653 if (cpu_info[i].cpu_hyperthread) 654 hyperthread = "/HT"; 655 else 656 hyperthread = ""; 657 printf(" cpu (AP%s): APIC ID: %2d (disabled)\n", hyperthread, 658 i); 659 } 660} 661 662/* 663 * AP CPU's call this to initialize themselves. 664 */ 665void 666init_secondary(void) 667{ 668 struct pcpu *pc; 669 vm_offset_t addr; 670 int gsel_tss; 671 int x, myid; 672 u_int cpuid, cr0; 673 674 /* bootAP is set in start_ap() to our ID. */ 675 myid = bootAP; 676 677 /* Get per-cpu data */ 678 pc = &__pcpu[myid]; 679 680 /* prime data page for it to use */ 681 pcpu_init(pc, myid, sizeof(struct pcpu)); 682 dpcpu_init(dpcpu, myid); 683 pc->pc_apic_id = cpu_apic_ids[myid]; 684 pc->pc_prvspace = pc; 685 pc->pc_curthread = 0; 686 687 gdt_segs[GPRIV_SEL].ssd_base = (int) pc; 688 gdt_segs[GPROC0_SEL].ssd_base = (int) &pc->pc_common_tss; 689 690 for (x = 0; x < NGDT; x++) { 691 ssdtosd(&gdt_segs[x], &gdt[myid * NGDT + x].sd); 692 } 693 694 r_gdt.rd_limit = NGDT * sizeof(gdt[0]) - 1; 695 r_gdt.rd_base = (int) &gdt[myid * NGDT]; 696 lgdt(&r_gdt); /* does magic intra-segment return */ 697 698 lidt(&r_idt); 699 700 lldt(_default_ldt); 701 PCPU_SET(currentldt, _default_ldt); 702 703 gsel_tss = GSEL(GPROC0_SEL, SEL_KPL); 704 gdt[myid * NGDT + GPROC0_SEL].sd.sd_type = SDT_SYS386TSS; 705 PCPU_SET(common_tss.tss_esp0, 0); /* not used until after switch */ 706 PCPU_SET(common_tss.tss_ss0, GSEL(GDATA_SEL, SEL_KPL)); 707 PCPU_SET(common_tss.tss_ioopt, (sizeof (struct i386tss)) << 16); 708 PCPU_SET(tss_gdt, &gdt[myid * NGDT + GPROC0_SEL].sd); 709 PCPU_SET(common_tssd, *PCPU_GET(tss_gdt)); 710 ltr(gsel_tss); 711 712 PCPU_SET(fsgs_gdt, &gdt[myid * NGDT + GUFS_SEL].sd); 713 714 /* 715 * Set to a known state: 716 * Set by mpboot.s: CR0_PG, CR0_PE 717 * Set by cpu_setregs: CR0_NE, CR0_MP, CR0_TS, CR0_WP, CR0_AM 718 */ 719 cr0 = rcr0(); 720 cr0 &= ~(CR0_CD | CR0_NW | CR0_EM); 721 load_cr0(cr0); 722 CHECK_WRITE(0x38, 5); 723 724 /* Disable local APIC just to be sure. */ 725 lapic_disable(); 726 727 /* signal our startup to the BSP. */ 728 mp_naps++; 729 CHECK_WRITE(0x39, 6); 730 731 /* Spin until the BSP releases the AP's. */ 732 while (!aps_ready) 733 ia32_pause(); 734 735 /* BSP may have changed PTD while we were waiting */ 736 invltlb(); 737 for (addr = 0; addr < NKPT * NBPDR - 1; addr += PAGE_SIZE) 738 invlpg(addr); 739 740#if defined(I586_CPU) && !defined(NO_F00F_HACK) 741 lidt(&r_idt); 742#endif 743 744 /* Initialize the PAT MSR if present. */ 745 pmap_init_pat(); 746 747 /* set up CPU registers and state */ 748 cpu_setregs(); 749 750 /* set up FPU state on the AP */ 751 npxinit(); 752 753 /* set up SSE registers */ 754 enable_sse(); 755 756 if (cpu_ops.cpu_init) 757 cpu_ops.cpu_init(); 758 759#ifdef PAE 760 /* Enable the PTE no-execute bit. */ 761 if ((amd_feature & AMDID_NX) != 0) { 762 uint64_t msr; 763 764 msr = rdmsr(MSR_EFER) | EFER_NXE; 765 wrmsr(MSR_EFER, msr); 766 } 767#endif 768 769 /* A quick check from sanity claus */ 770 cpuid = PCPU_GET(cpuid); 771 if (PCPU_GET(apic_id) != lapic_id()) { 772 printf("SMP: cpuid = %d\n", cpuid); 773 printf("SMP: actual apic_id = %d\n", lapic_id()); 774 printf("SMP: correct apic_id = %d\n", PCPU_GET(apic_id)); 775 panic("cpuid mismatch! boom!!"); 776 } 777 778 /* Initialize curthread. */ 779 KASSERT(PCPU_GET(idlethread) != NULL, ("no idle thread")); 780 PCPU_SET(curthread, PCPU_GET(idlethread)); 781 782 mca_init(); 783 784 mtx_lock_spin(&ap_boot_mtx); 785 786 /* Init local apic for irq's */ 787 lapic_setup(1); 788 789 /* Set memory range attributes for this CPU to match the BSP */ 790 mem_range_AP_init(); 791 792 smp_cpus++; 793 794 CTR1(KTR_SMP, "SMP: AP CPU #%d Launched", cpuid); 795 printf("SMP: AP CPU #%d Launched!\n", cpuid); 796 797 /* Determine if we are a logical CPU. */ 798 /* XXX Calculation depends on cpu_logical being a power of 2, e.g. 2 */ 799 if (cpu_logical > 1 && PCPU_GET(apic_id) % cpu_logical != 0) 800 CPU_SET(cpuid, &logical_cpus_mask); 801 802 if (bootverbose) 803 lapic_dump("AP"); 804 805 if (smp_cpus == mp_ncpus) { 806 /* enable IPI's, tlb shootdown, freezes etc */ 807 atomic_store_rel_int(&smp_started, 1); 808 } 809 810 mtx_unlock_spin(&ap_boot_mtx); 811 812 /* Wait until all the AP's are up. */ 813 while (smp_started == 0) 814 ia32_pause(); 815 816 /* Start per-CPU event timers. */ 817 cpu_initclocks_ap(); 818 819 /* Enter the scheduler. */ 820 sched_throw(NULL); 821 822 panic("scheduler returned us to %s", __func__); 823 /* NOTREACHED */ 824} 825 826/******************************************************************* 827 * local functions and data 828 */ 829 830/* 831 * We tell the I/O APIC code about all the CPUs we want to receive 832 * interrupts. If we don't want certain CPUs to receive IRQs we 833 * can simply not tell the I/O APIC code about them in this function. 834 * We also do not tell it about the BSP since it tells itself about 835 * the BSP internally to work with UP kernels and on UP machines. 836 */ 837static void 838set_interrupt_apic_ids(void) 839{ 840 u_int i, apic_id; 841 842 for (i = 0; i < MAXCPU; i++) { 843 apic_id = cpu_apic_ids[i]; 844 if (apic_id == -1) 845 continue; 846 if (cpu_info[apic_id].cpu_bsp) 847 continue; 848 if (cpu_info[apic_id].cpu_disabled) 849 continue; 850 851 /* Don't let hyperthreads service interrupts. */ 852 if (hyperthreading_cpus > 1 && 853 apic_id % hyperthreading_cpus != 0) 854 continue; 855 856 intr_add_cpu(i); 857 } 858} 859 860/* 861 * Assign logical CPU IDs to local APICs. 862 */ 863static void 864assign_cpu_ids(void) 865{ 866 u_int i; 867 868 TUNABLE_INT_FETCH("machdep.hyperthreading_allowed", 869 &hyperthreading_allowed); 870 871 /* Check for explicitly disabled CPUs. */ 872 for (i = 0; i <= MAX_APIC_ID; i++) { 873 if (!cpu_info[i].cpu_present || cpu_info[i].cpu_bsp) 874 continue; 875 876 if (hyperthreading_cpus > 1 && i % hyperthreading_cpus != 0) { 877 cpu_info[i].cpu_hyperthread = 1; 878 879 /* 880 * Don't use HT CPU if it has been disabled by a 881 * tunable. 882 */ 883 if (hyperthreading_allowed == 0) { 884 cpu_info[i].cpu_disabled = 1; 885 continue; 886 } 887 } 888 889 /* Don't use this CPU if it has been disabled by a tunable. */ 890 if (resource_disabled("lapic", i)) { 891 cpu_info[i].cpu_disabled = 1; 892 continue; 893 } 894 } 895 896 if (hyperthreading_allowed == 0 && hyperthreading_cpus > 1) { 897 hyperthreading_cpus = 0; 898 cpu_logical = 1; 899 } 900 901 /* 902 * Assign CPU IDs to local APIC IDs and disable any CPUs 903 * beyond MAXCPU. CPU 0 is always assigned to the BSP. 904 * 905 * To minimize confusion for userland, we attempt to number 906 * CPUs such that all threads and cores in a package are 907 * grouped together. For now we assume that the BSP is always 908 * the first thread in a package and just start adding APs 909 * starting with the BSP's APIC ID. 910 */ 911 mp_ncpus = 1; 912 cpu_apic_ids[0] = boot_cpu_id; 913 apic_cpuids[boot_cpu_id] = 0; 914 for (i = boot_cpu_id + 1; i != boot_cpu_id; 915 i == MAX_APIC_ID ? i = 0 : i++) { 916 if (!cpu_info[i].cpu_present || cpu_info[i].cpu_bsp || 917 cpu_info[i].cpu_disabled) 918 continue; 919 920 if (mp_ncpus < MAXCPU) { 921 cpu_apic_ids[mp_ncpus] = i; 922 apic_cpuids[i] = mp_ncpus; 923 mp_ncpus++; 924 } else 925 cpu_info[i].cpu_disabled = 1; 926 } 927 KASSERT(mp_maxid >= mp_ncpus - 1, 928 ("%s: counters out of sync: max %d, count %d", __func__, mp_maxid, 929 mp_ncpus)); 930} 931 932/* 933 * start each AP in our list 934 */ 935/* Lowest 1MB is already mapped: don't touch*/ 936#define TMPMAP_START 1 937static int 938start_all_aps(void) 939{ 940#ifndef PC98 941 u_char mpbiosreason; 942#endif 943 u_int32_t mpbioswarmvec; 944 int apic_id, cpu, i; 945 946 mtx_init(&ap_boot_mtx, "ap boot", NULL, MTX_SPIN); 947 948 /* install the AP 1st level boot code */ 949 install_ap_tramp(); 950 951 /* save the current value of the warm-start vector */ 952 mpbioswarmvec = *((u_int32_t *) WARMBOOT_OFF); 953#ifndef PC98 954 outb(CMOS_REG, BIOS_RESET); 955 mpbiosreason = inb(CMOS_DATA); 956#endif 957 958 /* set up temporary P==V mapping for AP boot */ 959 /* XXX this is a hack, we should boot the AP on its own stack/PTD */ 960 for (i = TMPMAP_START; i < NKPT; i++) 961 PTD[i] = PTD[KPTDI + i]; 962 invltlb(); 963 964 /* start each AP */ 965 for (cpu = 1; cpu < mp_ncpus; cpu++) { 966 apic_id = cpu_apic_ids[cpu]; 967 968 /* allocate and set up a boot stack data page */ 969 bootstacks[cpu] = 970 (char *)kmem_malloc(kernel_arena, KSTACK_PAGES * PAGE_SIZE, 971 M_WAITOK | M_ZERO); 972 dpcpu = (void *)kmem_malloc(kernel_arena, DPCPU_SIZE, 973 M_WAITOK | M_ZERO); 974 /* setup a vector to our boot code */ 975 *((volatile u_short *) WARMBOOT_OFF) = WARMBOOT_TARGET; 976 *((volatile u_short *) WARMBOOT_SEG) = (boot_address >> 4); 977#ifndef PC98 978 outb(CMOS_REG, BIOS_RESET); 979 outb(CMOS_DATA, BIOS_WARM); /* 'warm-start' */ 980#endif 981 982 bootSTK = (char *)bootstacks[cpu] + KSTACK_PAGES * PAGE_SIZE - 4; 983 bootAP = cpu; 984 985 /* attempt to start the Application Processor */ 986 CHECK_INIT(99); /* setup checkpoints */ 987 if (!start_ap(apic_id)) { 988 printf("AP #%d (PHY# %d) failed!\n", cpu, apic_id); 989 CHECK_PRINT("trace"); /* show checkpoints */ 990 /* better panic as the AP may be running loose */ 991 printf("panic y/n? [y] "); 992 if (cngetc() != 'n') 993 panic("bye-bye"); 994 } 995 CHECK_PRINT("trace"); /* show checkpoints */ 996 997 CPU_SET(cpu, &all_cpus); /* record AP in CPU map */ 998 } 999 1000 /* restore the warmstart vector */ 1001 *(u_int32_t *) WARMBOOT_OFF = mpbioswarmvec; 1002 1003#ifndef PC98 1004 outb(CMOS_REG, BIOS_RESET); 1005 outb(CMOS_DATA, mpbiosreason); 1006#endif 1007 1008 /* Undo V==P hack from above */ 1009 for (i = TMPMAP_START; i < NKPT; i++) 1010 PTD[i] = 0; 1011 pmap_invalidate_range(kernel_pmap, 0, NKPT * NBPDR - 1); 1012 1013 /* number of APs actually started */ 1014 return mp_naps; 1015} 1016 1017/* 1018 * load the 1st level AP boot code into base memory. 1019 */ 1020 1021/* targets for relocation */ 1022extern void bigJump(void); 1023extern void bootCodeSeg(void); 1024extern void bootDataSeg(void); 1025extern void MPentry(void); 1026extern u_int MP_GDT; 1027extern u_int mp_gdtbase; 1028 1029static void 1030install_ap_tramp(void) 1031{ 1032 int x; 1033 int size = *(int *) ((u_long) & bootMP_size); 1034 vm_offset_t va = boot_address + KERNBASE; 1035 u_char *src = (u_char *) ((u_long) bootMP); 1036 u_char *dst = (u_char *) va; 1037 u_int boot_base = (u_int) bootMP; 1038 u_int8_t *dst8; 1039 u_int16_t *dst16; 1040 u_int32_t *dst32; 1041 1042 KASSERT (size <= PAGE_SIZE, 1043 ("'size' do not fit into PAGE_SIZE, as expected.")); 1044 pmap_kenter(va, boot_address); 1045 pmap_invalidate_page (kernel_pmap, va); 1046 for (x = 0; x < size; ++x) 1047 *dst++ = *src++; 1048 1049 /* 1050 * modify addresses in code we just moved to basemem. unfortunately we 1051 * need fairly detailed info about mpboot.s for this to work. changes 1052 * to mpboot.s might require changes here. 1053 */ 1054 1055 /* boot code is located in KERNEL space */ 1056 dst = (u_char *) va; 1057 1058 /* modify the lgdt arg */ 1059 dst32 = (u_int32_t *) (dst + ((u_int) & mp_gdtbase - boot_base)); 1060 *dst32 = boot_address + ((u_int) & MP_GDT - boot_base); 1061 1062 /* modify the ljmp target for MPentry() */ 1063 dst32 = (u_int32_t *) (dst + ((u_int) bigJump - boot_base) + 1); 1064 *dst32 = ((u_int) MPentry - KERNBASE); 1065 1066 /* modify the target for boot code segment */ 1067 dst16 = (u_int16_t *) (dst + ((u_int) bootCodeSeg - boot_base)); 1068 dst8 = (u_int8_t *) (dst16 + 1); 1069 *dst16 = (u_int) boot_address & 0xffff; 1070 *dst8 = ((u_int) boot_address >> 16) & 0xff; 1071 1072 /* modify the target for boot data segment */ 1073 dst16 = (u_int16_t *) (dst + ((u_int) bootDataSeg - boot_base)); 1074 dst8 = (u_int8_t *) (dst16 + 1); 1075 *dst16 = (u_int) boot_address & 0xffff; 1076 *dst8 = ((u_int) boot_address >> 16) & 0xff; 1077} 1078 1079/* 1080 * This function starts the AP (application processor) identified 1081 * by the APIC ID 'physicalCpu'. It does quite a "song and dance" 1082 * to accomplish this. This is necessary because of the nuances 1083 * of the different hardware we might encounter. It isn't pretty, 1084 * but it seems to work. 1085 */ 1086static int 1087start_ap(int apic_id) 1088{ 1089 int vector, ms; 1090 int cpus; 1091 1092 /* calculate the vector */ 1093 vector = (boot_address >> 12) & 0xff; 1094 1095 /* used as a watchpoint to signal AP startup */ 1096 cpus = mp_naps; 1097 1098 ipi_startup(apic_id, vector); 1099 1100 /* Wait up to 5 seconds for it to start. */ 1101 for (ms = 0; ms < 5000; ms++) { 1102 if (mp_naps > cpus) 1103 return 1; /* return SUCCESS */ 1104 DELAY(1000); 1105 } 1106 return 0; /* return FAILURE */ 1107} 1108 1109#ifdef COUNT_XINVLTLB_HITS 1110u_int xhits_gbl[MAXCPU]; 1111u_int xhits_pg[MAXCPU]; 1112u_int xhits_rng[MAXCPU]; 1113static SYSCTL_NODE(_debug, OID_AUTO, xhits, CTLFLAG_RW, 0, ""); 1114SYSCTL_OPAQUE(_debug_xhits, OID_AUTO, global, CTLFLAG_RW, &xhits_gbl, 1115 sizeof(xhits_gbl), "IU", ""); 1116SYSCTL_OPAQUE(_debug_xhits, OID_AUTO, page, CTLFLAG_RW, &xhits_pg, 1117 sizeof(xhits_pg), "IU", ""); 1118SYSCTL_OPAQUE(_debug_xhits, OID_AUTO, range, CTLFLAG_RW, &xhits_rng, 1119 sizeof(xhits_rng), "IU", ""); 1120 1121u_int ipi_global; 1122u_int ipi_page; 1123u_int ipi_range; 1124u_int ipi_range_size; 1125SYSCTL_INT(_debug_xhits, OID_AUTO, ipi_global, CTLFLAG_RW, &ipi_global, 0, ""); 1126SYSCTL_INT(_debug_xhits, OID_AUTO, ipi_page, CTLFLAG_RW, &ipi_page, 0, ""); 1127SYSCTL_INT(_debug_xhits, OID_AUTO, ipi_range, CTLFLAG_RW, &ipi_range, 0, ""); 1128SYSCTL_INT(_debug_xhits, OID_AUTO, ipi_range_size, CTLFLAG_RW, &ipi_range_size, 1129 0, ""); 1130 1131u_int ipi_masked_global; 1132u_int ipi_masked_page; 1133u_int ipi_masked_range; 1134u_int ipi_masked_range_size; 1135SYSCTL_INT(_debug_xhits, OID_AUTO, ipi_masked_global, CTLFLAG_RW, 1136 &ipi_masked_global, 0, ""); 1137SYSCTL_INT(_debug_xhits, OID_AUTO, ipi_masked_page, CTLFLAG_RW, 1138 &ipi_masked_page, 0, ""); 1139SYSCTL_INT(_debug_xhits, OID_AUTO, ipi_masked_range, CTLFLAG_RW, 1140 &ipi_masked_range, 0, ""); 1141SYSCTL_INT(_debug_xhits, OID_AUTO, ipi_masked_range_size, CTLFLAG_RW, 1142 &ipi_masked_range_size, 0, ""); 1143#endif /* COUNT_XINVLTLB_HITS */ 1144 1145/* 1146 * Init and startup IPI. 1147 */ 1148void 1149ipi_startup(int apic_id, int vector) 1150{ 1151 1152 /* 1153 * first we do an INIT IPI: this INIT IPI might be run, resetting 1154 * and running the target CPU. OR this INIT IPI might be latched (P5 1155 * bug), CPU waiting for STARTUP IPI. OR this INIT IPI might be 1156 * ignored. 1157 */ 1158 lapic_ipi_raw(APIC_DEST_DESTFLD | APIC_TRIGMOD_EDGE | 1159 APIC_LEVEL_ASSERT | APIC_DESTMODE_PHY | APIC_DELMODE_INIT, apic_id); 1160 lapic_ipi_wait(-1); 1161 DELAY(10000); /* wait ~10mS */ 1162 1163 /* 1164 * next we do a STARTUP IPI: the previous INIT IPI might still be 1165 * latched, (P5 bug) this 1st STARTUP would then terminate 1166 * immediately, and the previously started INIT IPI would continue. OR 1167 * the previous INIT IPI has already run. and this STARTUP IPI will 1168 * run. OR the previous INIT IPI was ignored. and this STARTUP IPI 1169 * will run. 1170 */ 1171 lapic_ipi_raw(APIC_DEST_DESTFLD | APIC_TRIGMOD_EDGE | 1172 APIC_LEVEL_DEASSERT | APIC_DESTMODE_PHY | APIC_DELMODE_STARTUP | 1173 vector, apic_id); 1174 lapic_ipi_wait(-1); 1175 DELAY(200); /* wait ~200uS */ 1176 1177 /* 1178 * finally we do a 2nd STARTUP IPI: this 2nd STARTUP IPI should run IF 1179 * the previous STARTUP IPI was cancelled by a latched INIT IPI. OR 1180 * this STARTUP IPI will be ignored, as only ONE STARTUP IPI is 1181 * recognized after hardware RESET or INIT IPI. 1182 */ 1183 lapic_ipi_raw(APIC_DEST_DESTFLD | APIC_TRIGMOD_EDGE | 1184 APIC_LEVEL_DEASSERT | APIC_DESTMODE_PHY | APIC_DELMODE_STARTUP | 1185 vector, apic_id); 1186 lapic_ipi_wait(-1); 1187 DELAY(200); /* wait ~200uS */ 1188} 1189 1190/* 1191 * Send an IPI to specified CPU handling the bitmap logic. 1192 */ 1193static void 1194ipi_send_cpu(int cpu, u_int ipi) 1195{ 1196 u_int bitmap, old_pending, new_pending; 1197 1198 KASSERT(cpu_apic_ids[cpu] != -1, ("IPI to non-existent CPU %d", cpu)); 1199 1200 if (IPI_IS_BITMAPED(ipi)) { 1201 bitmap = 1 << ipi; 1202 ipi = IPI_BITMAP_VECTOR; 1203 do { 1204 old_pending = cpu_ipi_pending[cpu]; 1205 new_pending = old_pending | bitmap; 1206 } while (!atomic_cmpset_int(&cpu_ipi_pending[cpu], 1207 old_pending, new_pending)); 1208 if (old_pending) 1209 return; 1210 } 1211 cpu_ops.ipi_vectored(ipi, cpu_apic_ids[cpu]); 1212} 1213 1214/* 1215 * Flush the TLB on all other CPU's 1216 */ 1217static void 1218smp_tlb_shootdown(u_int vector, vm_offset_t addr1, vm_offset_t addr2) 1219{ 1220 u_int ncpu; 1221 1222 ncpu = mp_ncpus - 1; /* does not shootdown self */ 1223 if (ncpu < 1) 1224 return; /* no other cpus */ 1225 if (!(read_eflags() & PSL_I)) 1226 panic("%s: interrupts disabled", __func__); 1227 mtx_lock_spin(&smp_ipi_mtx); 1228 smp_tlb_addr1 = addr1; 1229 smp_tlb_addr2 = addr2; 1230 atomic_store_rel_int(&smp_tlb_wait, 0); 1231 ipi_all_but_self(vector); 1232 while (smp_tlb_wait < ncpu) 1233 ia32_pause(); 1234 mtx_unlock_spin(&smp_ipi_mtx); 1235} 1236 1237static void 1238smp_targeted_tlb_shootdown(cpuset_t mask, u_int vector, vm_offset_t addr1, vm_offset_t addr2) 1239{ 1240 int cpu, ncpu, othercpus; 1241 1242 othercpus = mp_ncpus - 1; 1243 if (CPU_ISFULLSET(&mask)) { 1244 if (othercpus < 1) 1245 return; 1246 } else { 1247 CPU_CLR(PCPU_GET(cpuid), &mask); 1248 if (CPU_EMPTY(&mask)) 1249 return; 1250 } 1251 if (!(read_eflags() & PSL_I)) 1252 panic("%s: interrupts disabled", __func__); 1253 mtx_lock_spin(&smp_ipi_mtx); 1254 smp_tlb_addr1 = addr1; 1255 smp_tlb_addr2 = addr2; 1256 atomic_store_rel_int(&smp_tlb_wait, 0); 1257 if (CPU_ISFULLSET(&mask)) { 1258 ncpu = othercpus; 1259 ipi_all_but_self(vector); 1260 } else { 1261 ncpu = 0; 1262 while ((cpu = CPU_FFS(&mask)) != 0) { 1263 cpu--; 1264 CPU_CLR(cpu, &mask); 1265 CTR3(KTR_SMP, "%s: cpu: %d ipi: %x", __func__, cpu, 1266 vector); 1267 ipi_send_cpu(cpu, vector); 1268 ncpu++; 1269 } 1270 } 1271 while (smp_tlb_wait < ncpu) 1272 ia32_pause(); 1273 mtx_unlock_spin(&smp_ipi_mtx); 1274} 1275 1276void 1277smp_cache_flush(void) 1278{ 1279 1280 if (smp_started) 1281 smp_tlb_shootdown(IPI_INVLCACHE, 0, 0); 1282} 1283 1284void 1285smp_invltlb(void) 1286{ 1287 1288 if (smp_started) { 1289 smp_tlb_shootdown(IPI_INVLTLB, 0, 0); 1290#ifdef COUNT_XINVLTLB_HITS 1291 ipi_global++; 1292#endif 1293 } 1294} 1295 1296void 1297smp_invlpg(vm_offset_t addr) 1298{ 1299 1300 if (smp_started) { 1301 smp_tlb_shootdown(IPI_INVLPG, addr, 0); 1302#ifdef COUNT_XINVLTLB_HITS 1303 ipi_page++; 1304#endif 1305 } 1306} 1307 1308void 1309smp_invlpg_range(vm_offset_t addr1, vm_offset_t addr2) 1310{ 1311 1312 if (smp_started) { 1313 smp_tlb_shootdown(IPI_INVLRNG, addr1, addr2); 1314#ifdef COUNT_XINVLTLB_HITS 1315 ipi_range++; 1316 ipi_range_size += (addr2 - addr1) / PAGE_SIZE; 1317#endif 1318 } 1319} 1320 1321void 1322smp_masked_invltlb(cpuset_t mask) 1323{ 1324 1325 if (smp_started) { 1326 smp_targeted_tlb_shootdown(mask, IPI_INVLTLB, 0, 0); 1327#ifdef COUNT_XINVLTLB_HITS 1328 ipi_masked_global++; 1329#endif 1330 } 1331} 1332 1333void 1334smp_masked_invlpg(cpuset_t mask, vm_offset_t addr) 1335{ 1336 1337 if (smp_started) { 1338 smp_targeted_tlb_shootdown(mask, IPI_INVLPG, addr, 0); 1339#ifdef COUNT_XINVLTLB_HITS 1340 ipi_masked_page++; 1341#endif 1342 } 1343} 1344 1345void 1346smp_masked_invlpg_range(cpuset_t mask, vm_offset_t addr1, vm_offset_t addr2) 1347{ 1348 1349 if (smp_started) { 1350 smp_targeted_tlb_shootdown(mask, IPI_INVLRNG, addr1, addr2); 1351#ifdef COUNT_XINVLTLB_HITS 1352 ipi_masked_range++; 1353 ipi_masked_range_size += (addr2 - addr1) / PAGE_SIZE; 1354#endif 1355 } 1356} 1357 1358void 1359ipi_bitmap_handler(struct trapframe frame) 1360{ 1361 struct trapframe *oldframe; 1362 struct thread *td; 1363 int cpu = PCPU_GET(cpuid); 1364 u_int ipi_bitmap; 1365 1366 critical_enter(); 1367 td = curthread; 1368 td->td_intr_nesting_level++; 1369 oldframe = td->td_intr_frame; 1370 td->td_intr_frame = &frame; 1371 ipi_bitmap = atomic_readandclear_int(&cpu_ipi_pending[cpu]); 1372 if (ipi_bitmap & (1 << IPI_PREEMPT)) { 1373#ifdef COUNT_IPIS 1374 (*ipi_preempt_counts[cpu])++; 1375#endif 1376 sched_preempt(td); 1377 } 1378 if (ipi_bitmap & (1 << IPI_AST)) { 1379#ifdef COUNT_IPIS 1380 (*ipi_ast_counts[cpu])++; 1381#endif 1382 /* Nothing to do for AST */ 1383 } 1384 if (ipi_bitmap & (1 << IPI_HARDCLOCK)) { 1385#ifdef COUNT_IPIS 1386 (*ipi_hardclock_counts[cpu])++; 1387#endif 1388 hardclockintr(); 1389 } 1390 td->td_intr_frame = oldframe; 1391 td->td_intr_nesting_level--; 1392 critical_exit(); 1393} 1394 1395/* 1396 * send an IPI to a set of cpus. 1397 */ 1398void 1399ipi_selected(cpuset_t cpus, u_int ipi) 1400{ 1401 int cpu; 1402 1403 /* 1404 * IPI_STOP_HARD maps to a NMI and the trap handler needs a bit 1405 * of help in order to understand what is the source. 1406 * Set the mask of receiving CPUs for this purpose. 1407 */ 1408 if (ipi == IPI_STOP_HARD) 1409 CPU_OR_ATOMIC(&ipi_nmi_pending, &cpus); 1410 1411 while ((cpu = CPU_FFS(&cpus)) != 0) { 1412 cpu--; 1413 CPU_CLR(cpu, &cpus); 1414 CTR3(KTR_SMP, "%s: cpu: %d ipi: %x", __func__, cpu, ipi); 1415 ipi_send_cpu(cpu, ipi); 1416 } 1417} 1418 1419/* 1420 * send an IPI to a specific CPU. 1421 */ 1422void 1423ipi_cpu(int cpu, u_int ipi) 1424{ 1425 1426 /* 1427 * IPI_STOP_HARD maps to a NMI and the trap handler needs a bit 1428 * of help in order to understand what is the source. 1429 * Set the mask of receiving CPUs for this purpose. 1430 */ 1431 if (ipi == IPI_STOP_HARD) 1432 CPU_SET_ATOMIC(cpu, &ipi_nmi_pending); 1433 1434 CTR3(KTR_SMP, "%s: cpu: %d ipi: %x", __func__, cpu, ipi); 1435 ipi_send_cpu(cpu, ipi); 1436} 1437 1438/* 1439 * send an IPI to all CPUs EXCEPT myself 1440 */ 1441void 1442ipi_all_but_self(u_int ipi) 1443{ 1444 cpuset_t other_cpus; 1445 1446 other_cpus = all_cpus; 1447 CPU_CLR(PCPU_GET(cpuid), &other_cpus); 1448 if (IPI_IS_BITMAPED(ipi)) { 1449 ipi_selected(other_cpus, ipi); 1450 return; 1451 } 1452 1453 /* 1454 * IPI_STOP_HARD maps to a NMI and the trap handler needs a bit 1455 * of help in order to understand what is the source. 1456 * Set the mask of receiving CPUs for this purpose. 1457 */ 1458 if (ipi == IPI_STOP_HARD) 1459 CPU_OR_ATOMIC(&ipi_nmi_pending, &other_cpus); 1460 1461 CTR2(KTR_SMP, "%s: ipi: %x", __func__, ipi); 1462 cpu_ops.ipi_vectored(ipi, APIC_IPI_DEST_OTHERS); 1463} 1464 1465int 1466ipi_nmi_handler() 1467{ 1468 u_int cpuid; 1469 1470 /* 1471 * As long as there is not a simple way to know about a NMI's 1472 * source, if the bitmask for the current CPU is present in 1473 * the global pending bitword an IPI_STOP_HARD has been issued 1474 * and should be handled. 1475 */ 1476 cpuid = PCPU_GET(cpuid); 1477 if (!CPU_ISSET(cpuid, &ipi_nmi_pending)) 1478 return (1); 1479 1480 CPU_CLR_ATOMIC(cpuid, &ipi_nmi_pending); 1481 cpustop_handler(); 1482 return (0); 1483} 1484 1485/* 1486 * Handle an IPI_STOP by saving our current context and spinning until we 1487 * are resumed. 1488 */ 1489void 1490cpustop_handler(void) 1491{ 1492 u_int cpu; 1493 1494 cpu = PCPU_GET(cpuid); 1495 1496 savectx(&stoppcbs[cpu]); 1497 1498 /* Indicate that we are stopped */ 1499 CPU_SET_ATOMIC(cpu, &stopped_cpus); 1500 1501 /* Wait for restart */ 1502 while (!CPU_ISSET(cpu, &started_cpus)) 1503 ia32_pause(); 1504 1505 CPU_CLR_ATOMIC(cpu, &started_cpus); 1506 CPU_CLR_ATOMIC(cpu, &stopped_cpus); 1507 1508 if (cpu == 0 && cpustop_restartfunc != NULL) { 1509 cpustop_restartfunc(); 1510 cpustop_restartfunc = NULL; 1511 } 1512} 1513 1514/* 1515 * Handle an IPI_SUSPEND by saving our current context and spinning until we 1516 * are resumed. 1517 */ 1518void 1519cpususpend_handler(void) 1520{ 1521 u_int cpu; 1522 1523 mtx_assert(&smp_ipi_mtx, MA_NOTOWNED); 1524 1525 cpu = PCPU_GET(cpuid); 1526 if (savectx(susppcbs[cpu])) { 1527 wbinvd(); 1528 CPU_SET_ATOMIC(cpu, &suspended_cpus); 1529 } else { 1530 pmap_init_pat(); 1531 PCPU_SET(switchtime, 0); 1532 PCPU_SET(switchticks, ticks); 1533 1534 /* Indicate that we are resumed */ 1535 CPU_CLR_ATOMIC(cpu, &suspended_cpus); 1536 } 1537 1538 /* Wait for resume */ 1539 while (!CPU_ISSET(cpu, &started_cpus)) 1540 ia32_pause(); 1541 1542 if (cpu_ops.cpu_resume) 1543 cpu_ops.cpu_resume(); 1544 1545 /* Resume MCA and local APIC */ 1546 mca_resume(); 1547 lapic_setup(0); 1548 1549 /* Indicate that we are resumed */ 1550 CPU_CLR_ATOMIC(cpu, &suspended_cpus); 1551 CPU_CLR_ATOMIC(cpu, &started_cpus); 1552} 1553 1554/* 1555 * Handlers for TLB related IPIs 1556 */ 1557void 1558invltlb_handler(void) 1559{ 1560 uint64_t cr3; 1561#ifdef COUNT_XINVLTLB_HITS 1562 xhits_gbl[PCPU_GET(cpuid)]++; 1563#endif /* COUNT_XINVLTLB_HITS */ 1564#ifdef COUNT_IPIS 1565 (*ipi_invltlb_counts[PCPU_GET(cpuid)])++; 1566#endif /* COUNT_IPIS */ 1567 1568 cr3 = rcr3(); 1569 load_cr3(cr3); 1570 atomic_add_int(&smp_tlb_wait, 1); 1571} 1572 1573void 1574invlpg_handler(void) 1575{ 1576#ifdef COUNT_XINVLTLB_HITS 1577 xhits_pg[PCPU_GET(cpuid)]++; 1578#endif /* COUNT_XINVLTLB_HITS */ 1579#ifdef COUNT_IPIS 1580 (*ipi_invlpg_counts[PCPU_GET(cpuid)])++; 1581#endif /* COUNT_IPIS */ 1582 1583 invlpg(smp_tlb_addr1); 1584 1585 atomic_add_int(&smp_tlb_wait, 1); 1586} 1587 1588void 1589invlrng_handler(void) 1590{ 1591 vm_offset_t addr; 1592#ifdef COUNT_XINVLTLB_HITS 1593 xhits_rng[PCPU_GET(cpuid)]++; 1594#endif /* COUNT_XINVLTLB_HITS */ 1595#ifdef COUNT_IPIS 1596 (*ipi_invlrng_counts[PCPU_GET(cpuid)])++; 1597#endif /* COUNT_IPIS */ 1598 1599 addr = smp_tlb_addr1; 1600 do { 1601 invlpg(addr); 1602 addr += PAGE_SIZE; 1603 } while (addr < smp_tlb_addr2); 1604 1605 atomic_add_int(&smp_tlb_wait, 1); 1606} 1607 1608void 1609invlcache_handler(void) 1610{ 1611#ifdef COUNT_IPIS 1612 (*ipi_invlcache_counts[PCPU_GET(cpuid)])++; 1613#endif /* COUNT_IPIS */ 1614 1615 wbinvd(); 1616 atomic_add_int(&smp_tlb_wait, 1); 1617} 1618 1619/* 1620 * This is called once the rest of the system is up and running and we're 1621 * ready to let the AP's out of the pen. 1622 */ 1623static void 1624release_aps(void *dummy __unused) 1625{ 1626 1627 if (mp_ncpus == 1) 1628 return; 1629 atomic_store_rel_int(&aps_ready, 1); 1630 while (smp_started == 0) 1631 ia32_pause(); 1632} 1633SYSINIT(start_aps, SI_SUB_SMP, SI_ORDER_FIRST, release_aps, NULL); 1634 1635#ifdef COUNT_IPIS 1636/* 1637 * Setup interrupt counters for IPI handlers. 1638 */ 1639static void 1640mp_ipi_intrcnt(void *dummy) 1641{ 1642 char buf[64]; 1643 int i; 1644 1645 CPU_FOREACH(i) { 1646 snprintf(buf, sizeof(buf), "cpu%d:invltlb", i); 1647 intrcnt_add(buf, &ipi_invltlb_counts[i]); 1648 snprintf(buf, sizeof(buf), "cpu%d:invlrng", i); 1649 intrcnt_add(buf, &ipi_invlrng_counts[i]); 1650 snprintf(buf, sizeof(buf), "cpu%d:invlpg", i); 1651 intrcnt_add(buf, &ipi_invlpg_counts[i]); 1652 snprintf(buf, sizeof(buf), "cpu%d:invlcache", i); 1653 intrcnt_add(buf, &ipi_invlcache_counts[i]); 1654 snprintf(buf, sizeof(buf), "cpu%d:preempt", i); 1655 intrcnt_add(buf, &ipi_preempt_counts[i]); 1656 snprintf(buf, sizeof(buf), "cpu%d:ast", i); 1657 intrcnt_add(buf, &ipi_ast_counts[i]); 1658 snprintf(buf, sizeof(buf), "cpu%d:rendezvous", i); 1659 intrcnt_add(buf, &ipi_rendezvous_counts[i]); 1660 snprintf(buf, sizeof(buf), "cpu%d:lazypmap", i); 1661 intrcnt_add(buf, &ipi_lazypmap_counts[i]); 1662 snprintf(buf, sizeof(buf), "cpu%d:hardclock", i); 1663 intrcnt_add(buf, &ipi_hardclock_counts[i]); 1664 } 1665} 1666SYSINIT(mp_ipi_intrcnt, SI_SUB_INTR, SI_ORDER_MIDDLE, mp_ipi_intrcnt, NULL); 1667#endif 1668