1262569Simp/* 2262569Simp * Copyright (c) 2012-2013 Hisilicon Limited. 3262569Simp * Copyright (c) 2012-2013 Linaro Limited. 4262569Simp * 5262569Simp * Author: Haojian Zhuang <haojian.zhuang@linaro.org> 6262569Simp * Xin Li <li.xin@linaro.org> 7262569Simp * 8262569Simp * This program is free software; you can redistribute it and/or modify 9262569Simp * it under the terms of the GNU General Public License as published by 10262569Simp * the Free Software Foundation; either version 2 of the License, or 11262569Simp * (at your option) any later version. 12262569Simp * 13262569Simp * This program is distributed in the hope that it will be useful, 14262569Simp * but WITHOUT ANY WARRANTY; without even the implied warranty of 15262569Simp * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 16262569Simp * GNU General Public License for more details. 17262569Simp * 18262569Simp * You should have received a copy of the GNU General Public License along 19262569Simp * with this program; if not, write to the Free Software Foundation, Inc., 20262569Simp * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. 21262569Simp * 22262569Simp */ 23262569Simp 24262569Simp#ifndef __DTS_HI3620_CLOCK_H 25262569Simp#define __DTS_HI3620_CLOCK_H 26262569Simp 27262569Simp#define HI3620_NONE_CLOCK 0 28262569Simp 29262569Simp/* fixed rate & fixed factor clocks */ 30262569Simp#define HI3620_OSC32K 1 31262569Simp#define HI3620_OSC26M 2 32262569Simp#define HI3620_PCLK 3 33262569Simp#define HI3620_PLL_ARM0 4 34262569Simp#define HI3620_PLL_ARM1 5 35262569Simp#define HI3620_PLL_PERI 6 36262569Simp#define HI3620_PLL_USB 7 37262569Simp#define HI3620_PLL_HDMI 8 38262569Simp#define HI3620_PLL_GPU 9 39262569Simp#define HI3620_RCLK_TCXO 10 40262569Simp#define HI3620_RCLK_CFGAXI 11 41262569Simp#define HI3620_RCLK_PICO 12 42262569Simp 43262569Simp/* mux clocks */ 44262569Simp#define HI3620_TIMER0_MUX 32 45262569Simp#define HI3620_TIMER1_MUX 33 46262569Simp#define HI3620_TIMER2_MUX 34 47262569Simp#define HI3620_TIMER3_MUX 35 48262569Simp#define HI3620_TIMER4_MUX 36 49262569Simp#define HI3620_TIMER5_MUX 37 50262569Simp#define HI3620_TIMER6_MUX 38 51262569Simp#define HI3620_TIMER7_MUX 39 52262569Simp#define HI3620_TIMER8_MUX 40 53262569Simp#define HI3620_TIMER9_MUX 41 54262569Simp#define HI3620_UART0_MUX 42 55262569Simp#define HI3620_UART1_MUX 43 56262569Simp#define HI3620_UART2_MUX 44 57262569Simp#define HI3620_UART3_MUX 45 58262569Simp#define HI3620_UART4_MUX 46 59262569Simp#define HI3620_SPI0_MUX 47 60262569Simp#define HI3620_SPI1_MUX 48 61262569Simp#define HI3620_SPI2_MUX 49 62262569Simp#define HI3620_SAXI_MUX 50 63262569Simp#define HI3620_PWM0_MUX 51 64262569Simp#define HI3620_PWM1_MUX 52 65262569Simp#define HI3620_SD_MUX 53 66262569Simp#define HI3620_MMC1_MUX 54 67262569Simp#define HI3620_MMC1_MUX2 55 68262569Simp#define HI3620_G2D_MUX 56 69262569Simp#define HI3620_VENC_MUX 57 70262569Simp#define HI3620_VDEC_MUX 58 71262569Simp#define HI3620_VPP_MUX 59 72262569Simp#define HI3620_EDC0_MUX 60 73262569Simp#define HI3620_LDI0_MUX 61 74262569Simp#define HI3620_EDC1_MUX 62 75262569Simp#define HI3620_LDI1_MUX 63 76262569Simp#define HI3620_RCLK_HSIC 64 77262569Simp#define HI3620_MMC2_MUX 65 78262569Simp#define HI3620_MMC3_MUX 66 79262569Simp 80262569Simp/* divider clocks */ 81262569Simp#define HI3620_SHAREAXI_DIV 128 82262569Simp#define HI3620_CFGAXI_DIV 129 83262569Simp#define HI3620_SD_DIV 130 84262569Simp#define HI3620_MMC1_DIV 131 85262569Simp#define HI3620_HSIC_DIV 132 86262569Simp#define HI3620_MMC2_DIV 133 87262569Simp#define HI3620_MMC3_DIV 134 88262569Simp 89262569Simp/* gate clocks */ 90262569Simp#define HI3620_TIMERCLK01 160 91262569Simp#define HI3620_TIMER_RCLK01 161 92262569Simp#define HI3620_TIMERCLK23 162 93262569Simp#define HI3620_TIMER_RCLK23 163 94262569Simp#define HI3620_TIMERCLK45 164 95262569Simp#define HI3620_TIMERCLK67 165 96262569Simp#define HI3620_TIMERCLK89 166 97262569Simp#define HI3620_RTCCLK 167 98262569Simp#define HI3620_KPC_CLK 168 99262569Simp#define HI3620_GPIOCLK0 169 100262569Simp#define HI3620_GPIOCLK1 170 101262569Simp#define HI3620_GPIOCLK2 171 102262569Simp#define HI3620_GPIOCLK3 172 103262569Simp#define HI3620_GPIOCLK4 173 104262569Simp#define HI3620_GPIOCLK5 174 105262569Simp#define HI3620_GPIOCLK6 175 106262569Simp#define HI3620_GPIOCLK7 176 107262569Simp#define HI3620_GPIOCLK8 177 108262569Simp#define HI3620_GPIOCLK9 178 109262569Simp#define HI3620_GPIOCLK10 179 110262569Simp#define HI3620_GPIOCLK11 180 111262569Simp#define HI3620_GPIOCLK12 181 112262569Simp#define HI3620_GPIOCLK13 182 113262569Simp#define HI3620_GPIOCLK14 183 114262569Simp#define HI3620_GPIOCLK15 184 115262569Simp#define HI3620_GPIOCLK16 185 116262569Simp#define HI3620_GPIOCLK17 186 117262569Simp#define HI3620_GPIOCLK18 187 118262569Simp#define HI3620_GPIOCLK19 188 119262569Simp#define HI3620_GPIOCLK20 189 120262569Simp#define HI3620_GPIOCLK21 190 121262569Simp#define HI3620_DPHY0_CLK 191 122262569Simp#define HI3620_DPHY1_CLK 192 123262569Simp#define HI3620_DPHY2_CLK 193 124262569Simp#define HI3620_USBPHY_CLK 194 125262569Simp#define HI3620_ACP_CLK 195 126262569Simp#define HI3620_PWMCLK0 196 127262569Simp#define HI3620_PWMCLK1 197 128262569Simp#define HI3620_UARTCLK0 198 129262569Simp#define HI3620_UARTCLK1 199 130262569Simp#define HI3620_UARTCLK2 200 131262569Simp#define HI3620_UARTCLK3 201 132262569Simp#define HI3620_UARTCLK4 202 133262569Simp#define HI3620_SPICLK0 203 134262569Simp#define HI3620_SPICLK1 204 135262569Simp#define HI3620_SPICLK2 205 136262569Simp#define HI3620_I2CCLK0 206 137262569Simp#define HI3620_I2CCLK1 207 138262569Simp#define HI3620_I2CCLK2 208 139262569Simp#define HI3620_I2CCLK3 209 140262569Simp#define HI3620_SCI_CLK 210 141262569Simp#define HI3620_DDRC_PER_CLK 211 142262569Simp#define HI3620_DMAC_CLK 212 143262569Simp#define HI3620_USB2DVC_CLK 213 144262569Simp#define HI3620_SD_CLK 214 145262569Simp#define HI3620_MMC_CLK1 215 146262569Simp#define HI3620_MMC_CLK2 216 147262569Simp#define HI3620_MMC_CLK3 217 148262569Simp#define HI3620_MCU_CLK 218 149262569Simp 150273712Sian#define HI3620_SD_CIUCLK 0 151273712Sian#define HI3620_MMC_CIUCLK1 1 152273712Sian#define HI3620_MMC_CIUCLK2 2 153273712Sian#define HI3620_MMC_CIUCLK3 3 154273712Sian 155262569Simp#define HI3620_NR_CLKS 219 156262569Simp 157262569Simp#endif /* __DTS_HI3620_CLOCK_H */ 158