wm8650.dtsi revision 284090 
1/*
2 * wm8650.dtsi - Device tree file for Wondermedia WM8650 SoC
3 *
4 * Copyright (C) 2012 Tony Prisk <linux@prisktech.co.nz>
5 *
6 * Licensed under GPLv2 or later
7 */
8
9/include/ "skeleton.dtsi"
10
11/ {
12	compatible = "wm,wm8650";
13
14	cpus {
15		#address-cells = <0>;
16		#size-cells = <0>;
17
18		cpu {
19			device_type = "cpu";
20			compatible = "arm,arm926ej-s";
21		};
22	};
23
24 	aliases {
25		serial0 = &uart0;
26		serial1 = &uart1;
27	};
28
29	soc {
30		#address-cells = <1>;
31		#size-cells = <1>;
32		compatible = "simple-bus";
33		ranges;
34		interrupt-parent = <&intc0>;
35
36		intc0: interrupt-controller@d8140000 {
37			compatible = "via,vt8500-intc";
38			interrupt-controller;
39			reg = <0xd8140000 0x10000>;
40			#interrupt-cells = <1>;
41		};
42
43		/* Secondary IC cascaded to intc0 */
44		intc1: interrupt-controller@d8150000 {
45			compatible = "via,vt8500-intc";
46			interrupt-controller;
47			#interrupt-cells = <1>;
48			reg = <0xD8150000 0x10000>;
49			interrupts = <56 57 58 59 60 61 62 63>;
50		};
51
52		pinctrl: pinctrl@d8110000 {
53			compatible = "wm,wm8650-pinctrl";
54			reg = <0xd8110000 0x10000>;
55			interrupt-controller;
56			#interrupt-cells = <2>;
57			gpio-controller;
58			#gpio-cells = <2>;
59		};
60
61		pmc@d8130000 {
62			compatible = "via,vt8500-pmc";
63			reg = <0xd8130000 0x1000>;
64
65			clocks {
66				#address-cells = <1>;
67				#size-cells = <0>;
68
69				ref25: ref25M {
70					#clock-cells = <0>;
71					compatible = "fixed-clock";
72					clock-frequency = <25000000>;
73				};
74
75				ref24: ref24M {
76					#clock-cells = <0>;
77					compatible = "fixed-clock";
78					clock-frequency = <24000000>;
79				};
80
81				plla: plla {
82					#clock-cells = <0>;
83					compatible = "wm,wm8650-pll-clock";
84					clocks = <&ref25>;
85					reg = <0x200>;
86				};
87
88				pllb: pllb {
89					#clock-cells = <0>;
90					compatible = "wm,wm8650-pll-clock";
91					clocks = <&ref25>;
92					reg = <0x204>;
93				};
94
95				pllc: pllc {
96					#clock-cells = <0>;
97					compatible = "wm,wm8650-pll-clock";
98					clocks = <&ref25>;
99					reg = <0x208>;
100				};
101
102				plld: plld {
103					#clock-cells = <0>;
104					compatible = "wm,wm8650-pll-clock";
105					clocks = <&ref25>;
106					reg = <0x20c>;
107				};
108
109				plle: plle {
110					#clock-cells = <0>;
111					compatible = "wm,wm8650-pll-clock";
112					clocks = <&ref25>;
113					reg = <0x210>;
114				};
115
116				clkarm: arm {
117					#clock-cells = <0>;
118					compatible = "via,vt8500-device-clock";
119					clocks = <&plla>;
120					divisor-reg = <0x300>;
121				};
122
123				clkahb: ahb {
124					#clock-cells = <0>;
125					compatible = "via,vt8500-device-clock";
126					clocks = <&pllb>;
127					divisor-reg = <0x304>;
128				};
129
130				clkapb: apb {
131					#clock-cells = <0>;
132					compatible = "via,vt8500-device-clock";
133					clocks = <&pllb>;
134					divisor-reg = <0x320>;
135				};
136
137				clkddr: ddr {
138					#clock-cells = <0>;
139					compatible = "via,vt8500-device-clock";
140					clocks = <&plld>;
141					divisor-reg = <0x310>;
142				};
143
144				clkuart0: uart0 {
145 					#clock-cells = <0>;
146 					compatible = "via,vt8500-device-clock";
147					clocks = <&ref24>;
148					enable-reg = <0x250>;
149					enable-bit = <1>;
150 				};
151
152				clkuart1: uart1 {
153					#clock-cells = <0>;
154					compatible = "via,vt8500-device-clock";
155					clocks = <&ref24>;
156					enable-reg = <0x250>;
157					enable-bit = <2>;
158				};
159
160				clksdhc: sdhc {
161					#clock-cells = <0>;
162					compatible = "via,vt8500-device-clock";
163					clocks = <&pllb>;
164					divisor-reg = <0x328>;
165					divisor-mask = <0x3f>;
166					enable-reg = <0x254>;
167					enable-bit = <18>;
168				};
169			};
170		};
171
172		timer@d8130100 {
173			compatible = "via,vt8500-timer";
174			reg = <0xd8130100 0x28>;
175			interrupts = <36>;
176		};
177
178		ehci@d8007900 {
179			compatible = "via,vt8500-ehci";
180			reg = <0xd8007900 0x200>;
181			interrupts = <43>;
182		};
183
184		uhci@d8007b00 {
185			compatible = "platform-uhci";
186			reg = <0xd8007b00 0x200>;
187			interrupts = <43>;
188		};
189
190		fb: fb@d8050800 {
191			compatible = "wm,wm8505-fb";
192			reg = <0xd8050800 0x200>;
193		};
194
195		ge_rops@d8050400 {
196			compatible = "wm,prizm-ge-rops";
197			reg = <0xd8050400 0x100>;
198		};
199
200		uart0: serial@d8200000 {
201			compatible = "via,vt8500-uart";
202			reg = <0xd8200000 0x1040>;
203			interrupts = <32>;
204			clocks = <&clkuart0>;
205			status = "disabled";
206		};
207
208		uart1: serial@d82b0000 {
209			compatible = "via,vt8500-uart";
210			reg = <0xd82b0000 0x1040>;
211			interrupts = <33>;
212			clocks = <&clkuart1>;
213			status = "disabled";
214		};
215
216		rtc@d8100000 {
217			compatible = "via,vt8500-rtc";
218			reg = <0xd8100000 0x10000>;
219			interrupts = <48>;
220		};
221
222		ethernet@d8004000 {
223			compatible = "via,vt8500-rhine";
224			reg = <0xd8004000 0x100>;
225			interrupts = <10>;
226		};
227	};
228};
229