vexpress-v2p-ca5s.dts revision 284090 
1/*
2 * ARM Ltd. Versatile Express
3 *
4 * CoreTile Express A5x2
5 * Cortex-A5 MPCore (V2P-CA5s)
6 *
7 * HBI-0225B
8 */
9
10/dts-v1/;
11
12/ {
13	model = "V2P-CA5s";
14	arm,hbi = <0x225>;
15	arm,vexpress,site = <0xf>;
16	compatible = "arm,vexpress,v2p-ca5s", "arm,vexpress";
17	interrupt-parent = <&gic>;
18	#address-cells = <1>;
19	#size-cells = <1>;
20
21	chosen { };
22
23	aliases {
24		serial0 = &v2m_serial0;
25		serial1 = &v2m_serial1;
26		serial2 = &v2m_serial2;
27		serial3 = &v2m_serial3;
28		i2c0 = &v2m_i2c_dvi;
29		i2c1 = &v2m_i2c_pcie;
30	};
31
32	cpus {
33		#address-cells = <1>;
34		#size-cells = <0>;
35
36		cpu@0 {
37			device_type = "cpu";
38			compatible = "arm,cortex-a5";
39			reg = <0>;
40			next-level-cache = <&L2>;
41		};
42
43		cpu@1 {
44			device_type = "cpu";
45			compatible = "arm,cortex-a5";
46			reg = <1>;
47			next-level-cache = <&L2>;
48		};
49	};
50
51	memory@80000000 {
52		device_type = "memory";
53		reg = <0x80000000 0x40000000>;
54	};
55
56	hdlcd@2a110000 {
57		compatible = "arm,hdlcd";
58		reg = <0x2a110000 0x1000>;
59		interrupts = <0 85 4>;
60		clocks = <&oscclk3>;
61		clock-names = "pxlclk";
62	};
63
64	memory-controller@2a150000 {
65		compatible = "arm,pl341", "arm,primecell";
66		reg = <0x2a150000 0x1000>;
67		clocks = <&oscclk1>;
68		clock-names = "apb_pclk";
69	};
70
71	memory-controller@2a190000 {
72		compatible = "arm,pl354", "arm,primecell";
73		reg = <0x2a190000 0x1000>;
74		interrupts = <0 86 4>,
75			     <0 87 4>;
76		clocks = <&oscclk1>;
77		clock-names = "apb_pclk";
78	};
79
80	scu@2c000000 {
81		compatible = "arm,cortex-a5-scu";
82		reg = <0x2c000000 0x58>;
83	};
84
85	timer@2c000600 {
86		compatible = "arm,cortex-a5-twd-timer";
87		reg = <0x2c000600 0x20>;
88		interrupts = <1 13 0x304>;
89	};
90
91	timer@2c000200 {
92		compatible = "arm,cortex-a5-global-timer",
93		             "arm,cortex-a9-global-timer";
94		reg = <0x2c000200 0x20>;
95		interrupts = <1 11 0x304>;
96		clocks = <&oscclk0>;
97	};
98
99	watchdog@2c000620 {
100		compatible = "arm,cortex-a5-twd-wdt";
101		reg = <0x2c000620 0x20>;
102		interrupts = <1 14 0x304>;
103	};
104
105	gic: interrupt-controller@2c001000 {
106		compatible = "arm,cortex-a5-gic", "arm,cortex-a9-gic";
107		#interrupt-cells = <3>;
108		#address-cells = <0>;
109		interrupt-controller;
110		reg = <0x2c001000 0x1000>,
111		      <0x2c000100 0x100>;
112	};
113
114	L2: cache-controller@2c0f0000 {
115		compatible = "arm,pl310-cache";
116		reg = <0x2c0f0000 0x1000>;
117		interrupts = <0 84 4>;
118		cache-level = <2>;
119	};
120
121	pmu {
122		compatible = "arm,cortex-a5-pmu";
123		interrupts = <0 68 4>,
124			     <0 69 4>;
125	};
126
127	dcc {
128		compatible = "arm,vexpress,config-bus";
129		arm,vexpress,config-bridge = <&v2m_sysreg>;
130
131		oscclk0: osc@0 {
132			/* CPU and internal AXI reference clock */
133			compatible = "arm,vexpress-osc";
134			arm,vexpress-sysreg,func = <1 0>;
135			freq-range = <50000000 100000000>;
136			#clock-cells = <0>;
137			clock-output-names = "oscclk0";
138		};
139
140		oscclk1: osc@1 {
141			/* Multiplexed AXI master clock */
142			compatible = "arm,vexpress-osc";
143			arm,vexpress-sysreg,func = <1 1>;
144			freq-range = <5000000 50000000>;
145			#clock-cells = <0>;
146			clock-output-names = "oscclk1";
147		};
148
149		osc@2 {
150			/* DDR2 */
151			compatible = "arm,vexpress-osc";
152			arm,vexpress-sysreg,func = <1 2>;
153			freq-range = <80000000 120000000>;
154			#clock-cells = <0>;
155			clock-output-names = "oscclk2";
156		};
157
158		oscclk3: osc@3 {
159			/* HDLCD */
160			compatible = "arm,vexpress-osc";
161			arm,vexpress-sysreg,func = <1 3>;
162			freq-range = <23750000 165000000>;
163			#clock-cells = <0>;
164			clock-output-names = "oscclk3";
165		};
166
167		osc@4 {
168			/* Test chip gate configuration */
169			compatible = "arm,vexpress-osc";
170			arm,vexpress-sysreg,func = <1 4>;
171			freq-range = <80000000 80000000>;
172			#clock-cells = <0>;
173			clock-output-names = "oscclk4";
174		};
175
176		smbclk: osc@5 {
177			/* SMB clock */
178			compatible = "arm,vexpress-osc";
179			arm,vexpress-sysreg,func = <1 5>;
180			freq-range = <25000000 60000000>;
181			#clock-cells = <0>;
182			clock-output-names = "oscclk5";
183		};
184
185		temp@0 {
186			/* DCC internal operating temperature */
187			compatible = "arm,vexpress-temp";
188			arm,vexpress-sysreg,func = <4 0>;
189			label = "DCC";
190		};
191	};
192
193	smb {
194		compatible = "simple-bus";
195
196		#address-cells = <2>;
197		#size-cells = <1>;
198		ranges = <0 0 0x08000000 0x04000000>,
199			 <1 0 0x14000000 0x04000000>,
200			 <2 0 0x18000000 0x04000000>,
201			 <3 0 0x1c000000 0x04000000>,
202			 <4 0 0x0c000000 0x04000000>,
203			 <5 0 0x10000000 0x04000000>;
204
205		#interrupt-cells = <1>;
206		interrupt-map-mask = <0 0 63>;
207		interrupt-map = <0 0  0 &gic 0  0 4>,
208				<0 0  1 &gic 0  1 4>,
209				<0 0  2 &gic 0  2 4>,
210				<0 0  3 &gic 0  3 4>,
211				<0 0  4 &gic 0  4 4>,
212				<0 0  5 &gic 0  5 4>,
213				<0 0  6 &gic 0  6 4>,
214				<0 0  7 &gic 0  7 4>,
215				<0 0  8 &gic 0  8 4>,
216				<0 0  9 &gic 0  9 4>,
217				<0 0 10 &gic 0 10 4>,
218				<0 0 11 &gic 0 11 4>,
219				<0 0 12 &gic 0 12 4>,
220				<0 0 13 &gic 0 13 4>,
221				<0 0 14 &gic 0 14 4>,
222				<0 0 15 &gic 0 15 4>,
223				<0 0 16 &gic 0 16 4>,
224				<0 0 17 &gic 0 17 4>,
225				<0 0 18 &gic 0 18 4>,
226				<0 0 19 &gic 0 19 4>,
227				<0 0 20 &gic 0 20 4>,
228				<0 0 21 &gic 0 21 4>,
229				<0 0 22 &gic 0 22 4>,
230				<0 0 23 &gic 0 23 4>,
231				<0 0 24 &gic 0 24 4>,
232				<0 0 25 &gic 0 25 4>,
233				<0 0 26 &gic 0 26 4>,
234				<0 0 27 &gic 0 27 4>,
235				<0 0 28 &gic 0 28 4>,
236				<0 0 29 &gic 0 29 4>,
237				<0 0 30 &gic 0 30 4>,
238				<0 0 31 &gic 0 31 4>,
239				<0 0 32 &gic 0 32 4>,
240				<0 0 33 &gic 0 33 4>,
241				<0 0 34 &gic 0 34 4>,
242				<0 0 35 &gic 0 35 4>,
243				<0 0 36 &gic 0 36 4>,
244				<0 0 37 &gic 0 37 4>,
245				<0 0 38 &gic 0 38 4>,
246				<0 0 39 &gic 0 39 4>,
247				<0 0 40 &gic 0 40 4>,
248				<0 0 41 &gic 0 41 4>,
249				<0 0 42 &gic 0 42 4>;
250
251		/include/ "vexpress-v2m-rs1.dtsi"
252	};
253};
254