sun8i-a23.dtsi revision 284090
1/* 2 * Copyright 2014 Chen-Yu Tsai 3 * 4 * Chen-Yu Tsai <wens@csie.org> 5 * 6 * This file is dual-licensed: you can use it either under the terms 7 * of the GPL or the X11 license, at your option. Note that this dual 8 * licensing only applies to this file, and not this project as a 9 * whole. 10 * 11 * a) This file is free software; you can redistribute it and/or 12 * modify it under the terms of the GNU General Public License as 13 * published by the Free Software Foundation; either version 2 of the 14 * License, or (at your option) any later version. 15 * 16 * This file is distributed in the hope that it will be useful, 17 * but WITHOUT ANY WARRANTY; without even the implied warranty of 18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 19 * GNU General Public License for more details. 20 * 21 * You should have received a copy of the GNU General Public 22 * License along with this file; if not, write to the Free 23 * Software Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, 24 * MA 02110-1301 USA 25 * 26 * Or, alternatively, 27 * 28 * b) Permission is hereby granted, free of charge, to any person 29 * obtaining a copy of this software and associated documentation 30 * files (the "Software"), to deal in the Software without 31 * restriction, including without limitation the rights to use, 32 * copy, modify, merge, publish, distribute, sublicense, and/or 33 * sell copies of the Software, and to permit persons to whom the 34 * Software is furnished to do so, subject to the following 35 * conditions: 36 * 37 * The above copyright notice and this permission notice shall be 38 * included in all copies or substantial portions of the Software. 39 * 40 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 41 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES 42 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 43 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT 44 * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, 45 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 46 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 47 * OTHER DEALINGS IN THE SOFTWARE. 48 */ 49 50#include "skeleton.dtsi" 51 52#include <dt-bindings/interrupt-controller/arm-gic.h> 53 54#include <dt-bindings/pinctrl/sun4i-a10.h> 55 56/ { 57 interrupt-parent = <&gic>; 58 59 chosen { 60 #address-cells = <1>; 61 #size-cells = <1>; 62 ranges; 63 64 framebuffer@0 { 65 compatible = "allwinner,simple-framebuffer", 66 "simple-framebuffer"; 67 allwinner,pipeline = "de_be0-lcd0"; 68 clocks = <&pll6 0>; 69 status = "disabled"; 70 }; 71 }; 72 73 cpus { 74 #address-cells = <1>; 75 #size-cells = <0>; 76 77 cpu@0 { 78 compatible = "arm,cortex-a7"; 79 device_type = "cpu"; 80 reg = <0>; 81 }; 82 83 cpu@1 { 84 compatible = "arm,cortex-a7"; 85 device_type = "cpu"; 86 reg = <1>; 87 }; 88 }; 89 90 memory { 91 reg = <0x40000000 0x40000000>; 92 }; 93 94 clocks { 95 #address-cells = <1>; 96 #size-cells = <1>; 97 ranges; 98 99 osc24M: osc24M_clk { 100 #clock-cells = <0>; 101 compatible = "fixed-clock"; 102 clock-frequency = <24000000>; 103 clock-output-names = "osc24M"; 104 }; 105 106 osc32k: osc32k_clk { 107 #clock-cells = <0>; 108 compatible = "fixed-clock"; 109 clock-frequency = <32768>; 110 clock-output-names = "osc32k"; 111 }; 112 113 pll1: clk@01c20000 { 114 #clock-cells = <0>; 115 compatible = "allwinner,sun8i-a23-pll1-clk"; 116 reg = <0x01c20000 0x4>; 117 clocks = <&osc24M>; 118 clock-output-names = "pll1"; 119 }; 120 121 /* dummy clock until actually implemented */ 122 pll5: pll5_clk { 123 #clock-cells = <0>; 124 compatible = "fixed-clock"; 125 clock-frequency = <0>; 126 clock-output-names = "pll5"; 127 }; 128 129 pll6: clk@01c20028 { 130 #clock-cells = <1>; 131 compatible = "allwinner,sun6i-a31-pll6-clk"; 132 reg = <0x01c20028 0x4>; 133 clocks = <&osc24M>; 134 clock-output-names = "pll6", "pll6x2"; 135 }; 136 137 cpu: cpu_clk@01c20050 { 138 #clock-cells = <0>; 139 compatible = "allwinner,sun4i-a10-cpu-clk"; 140 reg = <0x01c20050 0x4>; 141 142 /* 143 * PLL1 is listed twice here. 144 * While it looks suspicious, it's actually documented 145 * that way both in the datasheet and in the code from 146 * Allwinner. 147 */ 148 clocks = <&osc32k>, <&osc24M>, <&pll1>, <&pll1>; 149 clock-output-names = "cpu"; 150 }; 151 152 axi: axi_clk@01c20050 { 153 #clock-cells = <0>; 154 compatible = "allwinner,sun8i-a23-axi-clk"; 155 reg = <0x01c20050 0x4>; 156 clocks = <&cpu>; 157 clock-output-names = "axi"; 158 }; 159 160 ahb1: ahb1_clk@01c20054 { 161 #clock-cells = <0>; 162 compatible = "allwinner,sun6i-a31-ahb1-clk"; 163 reg = <0x01c20054 0x4>; 164 clocks = <&osc32k>, <&osc24M>, <&axi>, <&pll6 0>; 165 clock-output-names = "ahb1"; 166 }; 167 168 apb1: apb1_clk@01c20054 { 169 #clock-cells = <0>; 170 compatible = "allwinner,sun4i-a10-apb0-clk"; 171 reg = <0x01c20054 0x4>; 172 clocks = <&ahb1>; 173 clock-output-names = "apb1"; 174 }; 175 176 ahb1_gates: clk@01c20060 { 177 #clock-cells = <1>; 178 compatible = "allwinner,sun8i-a23-ahb1-gates-clk"; 179 reg = <0x01c20060 0x8>; 180 clocks = <&ahb1>; 181 clock-output-names = "ahb1_mipidsi", "ahb1_dma", 182 "ahb1_mmc0", "ahb1_mmc1", "ahb1_mmc2", 183 "ahb1_nand", "ahb1_sdram", 184 "ahb1_hstimer", "ahb1_spi0", 185 "ahb1_spi1", "ahb1_otg", "ahb1_ehci", 186 "ahb1_ohci", "ahb1_ve", "ahb1_lcd", 187 "ahb1_csi", "ahb1_be", "ahb1_fe", 188 "ahb1_gpu", "ahb1_spinlock", 189 "ahb1_drc"; 190 }; 191 192 apb1_gates: clk@01c20068 { 193 #clock-cells = <1>; 194 compatible = "allwinner,sun8i-a23-apb1-gates-clk"; 195 reg = <0x01c20068 0x4>; 196 clocks = <&apb1>; 197 clock-output-names = "apb1_codec", "apb1_pio", 198 "apb1_daudio0", "apb1_daudio1"; 199 }; 200 201 apb2: clk@01c20058 { 202 #clock-cells = <0>; 203 compatible = "allwinner,sun4i-a10-apb1-clk"; 204 reg = <0x01c20058 0x4>; 205 clocks = <&osc32k>, <&osc24M>, <&pll6 0>, <&pll6 0>; 206 clock-output-names = "apb2"; 207 }; 208 209 apb2_gates: clk@01c2006c { 210 #clock-cells = <1>; 211 compatible = "allwinner,sun8i-a23-apb2-gates-clk"; 212 reg = <0x01c2006c 0x4>; 213 clocks = <&apb2>; 214 clock-output-names = "apb2_i2c0", "apb2_i2c1", 215 "apb2_i2c2", "apb2_uart0", 216 "apb2_uart1", "apb2_uart2", 217 "apb2_uart3", "apb2_uart4"; 218 }; 219 220 mmc0_clk: clk@01c20088 { 221 #clock-cells = <1>; 222 compatible = "allwinner,sun4i-a10-mmc-clk"; 223 reg = <0x01c20088 0x4>; 224 clocks = <&osc24M>, <&pll6 0>; 225 clock-output-names = "mmc0", 226 "mmc0_output", 227 "mmc0_sample"; 228 }; 229 230 mmc1_clk: clk@01c2008c { 231 #clock-cells = <1>; 232 compatible = "allwinner,sun4i-a10-mmc-clk"; 233 reg = <0x01c2008c 0x4>; 234 clocks = <&osc24M>, <&pll6 0>; 235 clock-output-names = "mmc1", 236 "mmc1_output", 237 "mmc1_sample"; 238 }; 239 240 mmc2_clk: clk@01c20090 { 241 #clock-cells = <1>; 242 compatible = "allwinner,sun4i-a10-mmc-clk"; 243 reg = <0x01c20090 0x4>; 244 clocks = <&osc24M>, <&pll6 0>; 245 clock-output-names = "mmc2", 246 "mmc2_output", 247 "mmc2_sample"; 248 }; 249 250 mbus_clk: clk@01c2015c { 251 #clock-cells = <0>; 252 compatible = "allwinner,sun8i-a23-mbus-clk"; 253 reg = <0x01c2015c 0x4>; 254 clocks = <&osc24M>, <&pll6 1>, <&pll5>; 255 clock-output-names = "mbus"; 256 }; 257 }; 258 259 soc@01c00000 { 260 compatible = "simple-bus"; 261 #address-cells = <1>; 262 #size-cells = <1>; 263 ranges; 264 265 dma: dma-controller@01c02000 { 266 compatible = "allwinner,sun8i-a23-dma"; 267 reg = <0x01c02000 0x1000>; 268 interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>; 269 clocks = <&ahb1_gates 6>; 270 resets = <&ahb1_rst 6>; 271 #dma-cells = <1>; 272 }; 273 274 mmc0: mmc@01c0f000 { 275 compatible = "allwinner,sun5i-a13-mmc"; 276 reg = <0x01c0f000 0x1000>; 277 clocks = <&ahb1_gates 8>, 278 <&mmc0_clk 0>, 279 <&mmc0_clk 1>, 280 <&mmc0_clk 2>; 281 clock-names = "ahb", 282 "mmc", 283 "output", 284 "sample"; 285 resets = <&ahb1_rst 8>; 286 reset-names = "ahb"; 287 interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>; 288 status = "disabled"; 289 }; 290 291 mmc1: mmc@01c10000 { 292 compatible = "allwinner,sun5i-a13-mmc"; 293 reg = <0x01c10000 0x1000>; 294 clocks = <&ahb1_gates 9>, 295 <&mmc1_clk 0>, 296 <&mmc1_clk 1>, 297 <&mmc1_clk 2>; 298 clock-names = "ahb", 299 "mmc", 300 "output", 301 "sample"; 302 resets = <&ahb1_rst 9>; 303 reset-names = "ahb"; 304 interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>; 305 status = "disabled"; 306 }; 307 308 mmc2: mmc@01c11000 { 309 compatible = "allwinner,sun5i-a13-mmc"; 310 reg = <0x01c11000 0x1000>; 311 clocks = <&ahb1_gates 10>, 312 <&mmc2_clk 0>, 313 <&mmc2_clk 1>, 314 <&mmc2_clk 2>; 315 clock-names = "ahb", 316 "mmc", 317 "output", 318 "sample"; 319 resets = <&ahb1_rst 10>; 320 reset-names = "ahb"; 321 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>; 322 status = "disabled"; 323 }; 324 325 pio: pinctrl@01c20800 { 326 compatible = "allwinner,sun8i-a23-pinctrl"; 327 reg = <0x01c20800 0x400>; 328 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>, 329 <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>, 330 <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>; 331 clocks = <&apb1_gates 5>; 332 gpio-controller; 333 interrupt-controller; 334 #address-cells = <1>; 335 #size-cells = <0>; 336 #gpio-cells = <3>; 337 338 uart0_pins_a: uart0@0 { 339 allwinner,pins = "PF2", "PF4"; 340 allwinner,function = "uart0"; 341 allwinner,drive = <SUN4I_PINCTRL_10_MA>; 342 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; 343 }; 344 345 mmc0_pins_a: mmc0@0 { 346 allwinner,pins = "PF0","PF1","PF2","PF3","PF4","PF5"; 347 allwinner,function = "mmc0"; 348 allwinner,drive = <SUN4I_PINCTRL_30_MA>; 349 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; 350 }; 351 352 mmc1_pins_a: mmc1@0 { 353 allwinner,pins = "PG0","PG1","PG2","PG3","PG4","PG5"; 354 allwinner,function = "mmc1"; 355 allwinner,drive = <SUN4I_PINCTRL_30_MA>; 356 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; 357 }; 358 359 i2c0_pins_a: i2c0@0 { 360 allwinner,pins = "PH2", "PH3"; 361 allwinner,function = "i2c0"; 362 allwinner,drive = <SUN4I_PINCTRL_10_MA>; 363 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; 364 }; 365 366 i2c1_pins_a: i2c1@0 { 367 allwinner,pins = "PH4", "PH5"; 368 allwinner,function = "i2c1"; 369 allwinner,drive = <SUN4I_PINCTRL_10_MA>; 370 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; 371 }; 372 373 i2c2_pins_a: i2c2@0 { 374 allwinner,pins = "PE12", "PE13"; 375 allwinner,function = "i2c2"; 376 allwinner,drive = <SUN4I_PINCTRL_10_MA>; 377 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; 378 }; 379 }; 380 381 ahb1_rst: reset@01c202c0 { 382 #reset-cells = <1>; 383 compatible = "allwinner,sun6i-a31-clock-reset"; 384 reg = <0x01c202c0 0xc>; 385 }; 386 387 apb1_rst: reset@01c202d0 { 388 #reset-cells = <1>; 389 compatible = "allwinner,sun6i-a31-clock-reset"; 390 reg = <0x01c202d0 0x4>; 391 }; 392 393 apb2_rst: reset@01c202d8 { 394 #reset-cells = <1>; 395 compatible = "allwinner,sun6i-a31-clock-reset"; 396 reg = <0x01c202d8 0x4>; 397 }; 398 399 timer@01c20c00 { 400 compatible = "allwinner,sun4i-a10-timer"; 401 reg = <0x01c20c00 0xa0>; 402 interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>, 403 <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>; 404 clocks = <&osc24M>; 405 }; 406 407 wdt0: watchdog@01c20ca0 { 408 compatible = "allwinner,sun6i-a31-wdt"; 409 reg = <0x01c20ca0 0x20>; 410 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>; 411 }; 412 413 lradc: lradc@01c22800 { 414 compatible = "allwinner,sun4i-a10-lradc-keys"; 415 reg = <0x01c22800 0x100>; 416 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>; 417 status = "disabled"; 418 }; 419 420 uart0: serial@01c28000 { 421 compatible = "snps,dw-apb-uart"; 422 reg = <0x01c28000 0x400>; 423 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>; 424 reg-shift = <2>; 425 reg-io-width = <4>; 426 clocks = <&apb2_gates 16>; 427 resets = <&apb2_rst 16>; 428 dmas = <&dma 6>, <&dma 6>; 429 dma-names = "rx", "tx"; 430 status = "disabled"; 431 }; 432 433 uart1: serial@01c28400 { 434 compatible = "snps,dw-apb-uart"; 435 reg = <0x01c28400 0x400>; 436 interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>; 437 reg-shift = <2>; 438 reg-io-width = <4>; 439 clocks = <&apb2_gates 17>; 440 resets = <&apb2_rst 17>; 441 dmas = <&dma 7>, <&dma 7>; 442 dma-names = "rx", "tx"; 443 status = "disabled"; 444 }; 445 446 uart2: serial@01c28800 { 447 compatible = "snps,dw-apb-uart"; 448 reg = <0x01c28800 0x400>; 449 interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>; 450 reg-shift = <2>; 451 reg-io-width = <4>; 452 clocks = <&apb2_gates 18>; 453 resets = <&apb2_rst 18>; 454 dmas = <&dma 8>, <&dma 8>; 455 dma-names = "rx", "tx"; 456 status = "disabled"; 457 }; 458 459 uart3: serial@01c28c00 { 460 compatible = "snps,dw-apb-uart"; 461 reg = <0x01c28c00 0x400>; 462 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>; 463 reg-shift = <2>; 464 reg-io-width = <4>; 465 clocks = <&apb2_gates 19>; 466 resets = <&apb2_rst 19>; 467 dmas = <&dma 9>, <&dma 9>; 468 dma-names = "rx", "tx"; 469 status = "disabled"; 470 }; 471 472 uart4: serial@01c29000 { 473 compatible = "snps,dw-apb-uart"; 474 reg = <0x01c29000 0x400>; 475 interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>; 476 reg-shift = <2>; 477 reg-io-width = <4>; 478 clocks = <&apb2_gates 20>; 479 resets = <&apb2_rst 20>; 480 dmas = <&dma 10>, <&dma 10>; 481 dma-names = "rx", "tx"; 482 status = "disabled"; 483 }; 484 485 i2c0: i2c@01c2ac00 { 486 compatible = "allwinner,sun6i-a31-i2c"; 487 reg = <0x01c2ac00 0x400>; 488 interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>; 489 clocks = <&apb2_gates 0>; 490 resets = <&apb2_rst 0>; 491 status = "disabled"; 492 #address-cells = <1>; 493 #size-cells = <0>; 494 }; 495 496 i2c1: i2c@01c2b000 { 497 compatible = "allwinner,sun6i-a31-i2c"; 498 reg = <0x01c2b000 0x400>; 499 interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>; 500 clocks = <&apb2_gates 1>; 501 resets = <&apb2_rst 1>; 502 status = "disabled"; 503 #address-cells = <1>; 504 #size-cells = <0>; 505 }; 506 507 i2c2: i2c@01c2b400 { 508 compatible = "allwinner,sun6i-a31-i2c"; 509 reg = <0x01c2b400 0x400>; 510 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>; 511 clocks = <&apb2_gates 2>; 512 resets = <&apb2_rst 2>; 513 status = "disabled"; 514 #address-cells = <1>; 515 #size-cells = <0>; 516 }; 517 518 gic: interrupt-controller@01c81000 { 519 compatible = "arm,cortex-a7-gic", "arm,cortex-a15-gic"; 520 reg = <0x01c81000 0x1000>, 521 <0x01c82000 0x1000>, 522 <0x01c84000 0x2000>, 523 <0x01c86000 0x2000>; 524 interrupt-controller; 525 #interrupt-cells = <3>; 526 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; 527 }; 528 529 rtc: rtc@01f00000 { 530 compatible = "allwinner,sun6i-a31-rtc"; 531 reg = <0x01f00000 0x54>; 532 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>, 533 <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>; 534 }; 535 536 prcm@01f01400 { 537 compatible = "allwinner,sun8i-a23-prcm"; 538 reg = <0x01f01400 0x200>; 539 540 ar100: ar100_clk { 541 compatible = "fixed-factor-clock"; 542 #clock-cells = <0>; 543 clock-div = <1>; 544 clock-mult = <1>; 545 clocks = <&osc24M>; 546 clock-output-names = "ar100"; 547 }; 548 549 ahb0: ahb0_clk { 550 compatible = "fixed-factor-clock"; 551 #clock-cells = <0>; 552 clock-div = <1>; 553 clock-mult = <1>; 554 clocks = <&ar100>; 555 clock-output-names = "ahb0"; 556 }; 557 558 apb0: apb0_clk { 559 compatible = "allwinner,sun8i-a23-apb0-clk"; 560 #clock-cells = <0>; 561 clocks = <&ahb0>; 562 clock-output-names = "apb0"; 563 }; 564 565 apb0_gates: apb0_gates_clk { 566 compatible = "allwinner,sun8i-a23-apb0-gates-clk"; 567 #clock-cells = <1>; 568 clocks = <&apb0>; 569 clock-output-names = "apb0_pio", "apb0_timer", 570 "apb0_rsb", "apb0_uart", 571 "apb0_i2c"; 572 }; 573 574 apb0_rst: apb0_rst { 575 compatible = "allwinner,sun6i-a31-clock-reset"; 576 #reset-cells = <1>; 577 }; 578 }; 579 580 r_uart: serial@01f02800 { 581 compatible = "snps,dw-apb-uart"; 582 reg = <0x01f02800 0x400>; 583 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>; 584 reg-shift = <2>; 585 reg-io-width = <4>; 586 clocks = <&apb0_gates 4>; 587 resets = <&apb0_rst 4>; 588 status = "disabled"; 589 }; 590 591 r_pio: pinctrl@01f02c00 { 592 compatible = "allwinner,sun8i-a23-r-pinctrl"; 593 reg = <0x01f02c00 0x400>; 594 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>; 595 clocks = <&apb0_gates 0>; 596 resets = <&apb0_rst 0>; 597 gpio-controller; 598 interrupt-controller; 599 #address-cells = <1>; 600 #size-cells = <0>; 601 #gpio-cells = <3>; 602 603 r_uart_pins_a: r_uart@0 { 604 allwinner,pins = "PL2", "PL3"; 605 allwinner,function = "s_uart"; 606 allwinner,drive = <SUN4I_PINCTRL_10_MA>; 607 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; 608 }; 609 }; 610 }; 611}; 612