stih407-pinctrl.dtsi revision 284090 
1/*
2 * Copyright (C) 2014 STMicroelectronics Limited.
3 * Author: Giuseppe Cavallaro <peppe.cavallaro@st.com>
4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License version 2 as
7 * publishhed by the Free Software Foundation.
8 */
9#include "st-pincfg.h"
10#include <dt-bindings/interrupt-controller/arm-gic.h>
11/ {
12
13	aliases {
14		/* 0-5: PIO_SBC */
15		gpio0 = &pio0;
16		gpio1 = &pio1;
17		gpio2 = &pio2;
18		gpio3 = &pio3;
19		gpio4 = &pio4;
20		gpio5 = &pio5;
21		/* 10-19: PIO_FRONT0 */
22		gpio6 = &pio10;
23		gpio7 = &pio11;
24		gpio8 = &pio12;
25		gpio9 = &pio13;
26		gpio10 = &pio14;
27		gpio11 = &pio15;
28		gpio12 = &pio16;
29		gpio13 = &pio17;
30		gpio14 = &pio18;
31		gpio15 = &pio19;
32		/* 20: PIO_FRONT1 */
33		gpio16 = &pio20;
34		/* 30-35: PIO_REAR */
35		gpio17 = &pio30;
36		gpio18 = &pio31;
37		gpio19 = &pio32;
38		gpio20 = &pio33;
39		gpio21 = &pio34;
40		gpio22 = &pio35;
41		/* 40-42: PIO_FLASH */
42		gpio23 = &pio40;
43		gpio24 = &pio41;
44		gpio25 = &pio42;
45	};
46
47	soc {
48		pin-controller-sbc {
49			#address-cells = <1>;
50			#size-cells = <1>;
51			compatible = "st,stih407-sbc-pinctrl";
52			st,syscfg = <&syscfg_sbc>;
53			reg = <0x0961f080 0x4>;
54			reg-names = "irqmux";
55			interrupts = <GIC_SPI 188 IRQ_TYPE_NONE>;
56			interrupts-names = "irqmux";
57			ranges = <0 0x09610000 0x6000>;
58
59			pio0: gpio@09610000 {
60				gpio-controller;
61				#gpio-cells = <1>;
62				interrupt-controller;
63				#interrupt-cells = <2>;
64				reg = <0x0 0x100>;
65				st,bank-name = "PIO0";
66			};
67			pio1: gpio@09611000 {
68				gpio-controller;
69				#gpio-cells = <1>;
70				interrupt-controller;
71				#interrupt-cells = <2>;
72				reg = <0x1000 0x100>;
73				st,bank-name = "PIO1";
74			};
75			pio2: gpio@09612000 {
76				gpio-controller;
77				#gpio-cells = <1>;
78				interrupt-controller;
79				#interrupt-cells = <2>;
80				reg = <0x2000 0x100>;
81				st,bank-name = "PIO2";
82			};
83			pio3: gpio@09613000 {
84				gpio-controller;
85				#gpio-cells = <1>;
86				interrupt-controller;
87				#interrupt-cells = <2>;
88				reg = <0x3000 0x100>;
89				st,bank-name = "PIO3";
90			};
91			pio4: gpio@09614000 {
92				gpio-controller;
93				#gpio-cells = <1>;
94				interrupt-controller;
95				#interrupt-cells = <2>;
96				reg = <0x4000 0x100>;
97				st,bank-name = "PIO4";
98			};
99
100			pio5: gpio@09615000 {
101				gpio-controller;
102				#gpio-cells = <1>;
103				interrupt-controller;
104				#interrupt-cells = <2>;
105				reg = <0x5000 0x100>;
106				st,bank-name = "PIO5";
107			};
108
109			rc {
110				pinctrl_ir: ir0 {
111					st,pins {
112						ir = <&pio4 0 ALT2 IN>;
113					};
114				};
115			};
116
117			/* SBC_ASC0 - UART10 */
118			sbc_serial0 {
119				pinctrl_sbc_serial0: sbc_serial0-0 {
120					st,pins {
121						tx = <&pio3 4 ALT1 OUT>;
122						rx = <&pio3 5 ALT1 IN>;
123					};
124				};
125			};
126			/* SBC_ASC1 - UART11 */
127			sbc_serial1 {
128				pinctrl_sbc_serial1: sbc_serial1-0 {
129					st,pins {
130						tx = <&pio2 6 ALT3 OUT>;
131						rx = <&pio2 7 ALT3 IN>;
132					};
133				};
134			};
135
136			i2c10 {
137				pinctrl_i2c10_default: i2c10-default {
138					st,pins {
139						sda = <&pio4 6 ALT1 BIDIR>;
140						scl = <&pio4 5 ALT1 BIDIR>;
141					};
142				};
143			};
144
145			i2c11 {
146				pinctrl_i2c11_default: i2c11-default {
147					st,pins {
148						sda = <&pio5 1 ALT1 BIDIR>;
149						scl = <&pio5 0 ALT1 BIDIR>;
150					};
151				};
152			};
153
154			keyscan {
155				pinctrl_keyscan: keyscan {
156					st,pins {
157						keyin0 = <&pio4 0 ALT6 IN>;
158						keyin1 = <&pio4 5 ALT4 IN>;
159						keyin2 = <&pio0 4 ALT2 IN>;
160						keyin3 = <&pio2 6 ALT2 IN>;
161
162						keyout0 = <&pio4 6 ALT4 OUT>;
163						keyout1 = <&pio1 7 ALT2 OUT>;
164						keyout2 = <&pio0 6 ALT2 OUT>;
165						keyout3 = <&pio2 7 ALT2 OUT>;
166					};
167				};
168			};
169
170			gmac1 {
171				/*
172				 * Almost all the boards based on STiH407 SoC have an embedded
173				 * switch where the mdio/mdc have been used for managing the SMI
174				 * iface via I2C. For this reason these lines can be allocated
175				 * by using dedicated configuration (in case of there will be a
176				 * standard PHY transceiver on-board).
177				 */
178				pinctrl_rgmii1: rgmii1-0 {
179					st,pins {
180
181						txd0 = <&pio0 0 ALT1 OUT DE_IO 0 CLK_A>;
182						txd1 = <&pio0 1 ALT1 OUT DE_IO 0 CLK_A>;
183						txd2 = <&pio0 2 ALT1 OUT DE_IO 0 CLK_A>;
184						txd3 = <&pio0 3 ALT1 OUT DE_IO 0 CLK_A>;
185						txen = <&pio0 5 ALT1 OUT DE_IO 0 CLK_A>;
186						txclk = <&pio0 6 ALT1 IN NICLK 0 CLK_A>;
187						rxd0 = <&pio1 4 ALT1 IN DE_IO 0 CLK_A>;
188						rxd1 = <&pio1 5 ALT1 IN DE_IO 0 CLK_A>;
189						rxd2 = <&pio1 6 ALT1 IN DE_IO 0 CLK_A>;
190						rxd3 = <&pio1 7 ALT1 IN DE_IO 0 CLK_A>;
191						rxdv = <&pio2 0 ALT1 IN DE_IO 0 CLK_A>;
192						rxclk = <&pio2 2 ALT1 IN NICLK 500 CLK_A>;
193						clk125 = <&pio3 7 ALT4 IN NICLK 0 CLK_A>;
194						phyclk = <&pio2 3 ALT4 OUT NICLK 1750 CLK_B>;
195					};
196				};
197
198				pinctrl_rgmii1_mdio: rgmii1-mdio {
199					st,pins {
200						mdio = <&pio1 0 ALT1 OUT BYPASS 0>;
201						mdc = <&pio1 1 ALT1 OUT NICLK 0 CLK_A>;
202						mdint = <&pio1 3 ALT1 IN BYPASS 0>;
203					};
204				};
205
206				pinctrl_mii1: mii1 {
207					st,pins {
208						txd0 = <&pio0 0 ALT1 OUT SE_NICLK_IO 0 CLK_A>;
209						txd1 = <&pio0 1 ALT1 OUT SE_NICLK_IO 0 CLK_A>;
210						txd2 = <&pio0 2 ALT1 OUT SE_NICLK_IO 0 CLK_A>;
211						txd3 = <&pio0 3 ALT1 OUT SE_NICLK_IO 0 CLK_A>;
212						txer = <&pio0 4 ALT1 OUT SE_NICLK_IO 0 CLK_A>;
213						txen = <&pio0 5 ALT1 OUT SE_NICLK_IO 0 CLK_A>;
214						txclk = <&pio0 6 ALT1 IN NICLK 0 CLK_A>;
215						col = <&pio0 7 ALT1 IN BYPASS 1000>;
216
217						mdio = <&pio1 0 ALT1 OUT BYPASS 1500>;
218						mdc = <&pio1 1 ALT1 OUT NICLK 0 CLK_A>;
219						crs = <&pio1 2 ALT1 IN BYPASS 1000>;
220						mdint = <&pio1 3 ALT1 IN BYPASS 0>;
221						rxd0 = <&pio1 4 ALT1 IN SE_NICLK_IO 0 CLK_A>;
222						rxd1 = <&pio1 5 ALT1 IN SE_NICLK_IO 0 CLK_A>;
223						rxd2 = <&pio1 6 ALT1 IN SE_NICLK_IO 0 CLK_A>;
224						rxd3 = <&pio1 7 ALT1 IN SE_NICLK_IO 0 CLK_A>;
225
226						rxdv = <&pio2 0 ALT1 IN SE_NICLK_IO 0 CLK_A>;
227						rx_er = <&pio2 1 ALT1 IN SE_NICLK_IO 0 CLK_A>;
228						rxclk = <&pio2 2 ALT1 IN NICLK 0 CLK_A>;
229						phyclk = <&pio2 3 ALT1 OUT NICLK 0 CLK_A>;
230					};
231				};
232			};
233
234			pwm1 {
235				pinctrl_pwm1_chan0_default: pwm1-0-default {
236					st,pins {
237						pwm-out = <&pio3 0 ALT1 OUT>;
238					};
239				};
240				pinctrl_pwm1_chan1_default: pwm1-1-default {
241					st,pins {
242						pwm-out = <&pio4 4 ALT1 OUT>;
243					};
244				};
245				pinctrl_pwm1_chan2_default: pwm1-2-default {
246					st,pins {
247						pwm-out = <&pio4 6 ALT3 OUT>;
248					};
249				};
250				pinctrl_pwm1_chan3_default: pwm1-3-default {
251					st,pins {
252						pwm-out = <&pio4 7 ALT3 OUT>;
253					};
254				};
255			};
256		};
257
258		pin-controller-front0 {
259			#address-cells = <1>;
260			#size-cells = <1>;
261			compatible = "st,stih407-front-pinctrl";
262			st,syscfg = <&syscfg_front>;
263			reg = <0x0920f080 0x4>;
264			reg-names = "irqmux";
265			interrupts = <GIC_SPI 189 IRQ_TYPE_NONE>;
266			interrupts-names = "irqmux";
267			ranges = <0 0x09200000 0x10000>;
268
269			pio10: pio@09200000 {
270				gpio-controller;
271				#gpio-cells = <1>;
272				interrupt-controller;
273				#interrupt-cells = <2>;
274				reg = <0x0 0x100>;
275				st,bank-name = "PIO10";
276			};
277			pio11: pio@09201000 {
278				gpio-controller;
279				#gpio-cells = <1>;
280				interrupt-controller;
281				#interrupt-cells = <2>;
282				reg = <0x1000 0x100>;
283				st,bank-name = "PIO11";
284			};
285			pio12: pio@09202000 {
286				gpio-controller;
287				#gpio-cells = <1>;
288				interrupt-controller;
289				#interrupt-cells = <2>;
290				reg = <0x2000 0x100>;
291				st,bank-name = "PIO12";
292			};
293			pio13: pio@09203000 {
294				gpio-controller;
295				#gpio-cells = <1>;
296				interrupt-controller;
297				#interrupt-cells = <2>;
298				reg = <0x3000 0x100>;
299				st,bank-name = "PIO13";
300			};
301			pio14: pio@09204000 {
302				gpio-controller;
303				#gpio-cells = <1>;
304				interrupt-controller;
305				#interrupt-cells = <2>;
306				reg = <0x4000 0x100>;
307				st,bank-name = "PIO14";
308			};
309			pio15: pio@09205000 {
310				gpio-controller;
311				#gpio-cells = <1>;
312				interrupt-controller;
313				#interrupt-cells = <2>;
314				reg = <0x5000 0x100>;
315				st,bank-name = "PIO15";
316			};
317			pio16: pio@09206000 {
318				gpio-controller;
319				#gpio-cells = <1>;
320				interrupt-controller;
321				#interrupt-cells = <2>;
322				reg = <0x6000 0x100>;
323				st,bank-name = "PIO16";
324			};
325			pio17: pio@09207000 {
326				gpio-controller;
327				#gpio-cells = <1>;
328				interrupt-controller;
329				#interrupt-cells = <2>;
330				reg = <0x7000 0x100>;
331				st,bank-name = "PIO17";
332			};
333			pio18: pio@09208000 {
334				gpio-controller;
335				#gpio-cells = <1>;
336				interrupt-controller;
337				#interrupt-cells = <2>;
338				reg = <0x8000 0x100>;
339				st,bank-name = "PIO18";
340			};
341			pio19: pio@09209000 {
342				gpio-controller;
343				#gpio-cells = <1>;
344				interrupt-controller;
345				#interrupt-cells = <2>;
346				reg = <0x9000 0x100>;
347				st,bank-name = "PIO19";
348			};
349
350			/* Comms */
351			serial0 {
352				pinctrl_serial0: serial0-0 {
353					st,pins {
354						tx = <&pio17 0 ALT1 OUT>;
355						rx = <&pio17 1 ALT1 IN>;
356					};
357				};
358			};
359
360			serial1 {
361				pinctrl_serial1: serial1-0 {
362					st,pins {
363						tx = <&pio16 0 ALT1 OUT>;
364						rx = <&pio16 1 ALT1 IN>;
365					};
366				};
367			};
368
369			serial2 {
370				pinctrl_serial2: serial2-0 {
371					st,pins {
372						tx = <&pio15 0 ALT1 OUT>;
373						rx = <&pio15 1 ALT1 IN>;
374					};
375				};
376			};
377
378			mmc1 {
379				pinctrl_sd1: sd1-0 {
380					st,pins {
381						sd_clk = <&pio19 3 ALT5 BIDIR NICLK 0 CLK_B>;
382						sd_cmd = <&pio19 2 ALT5 BIDIR_PU BYPASS 0>;
383						sd_dat0 = <&pio19 4 ALT5 BIDIR_PU BYPASS 0>;
384						sd_dat1 = <&pio19 5 ALT5 BIDIR_PU BYPASS 0>;
385						sd_dat2 = <&pio19 6 ALT5 BIDIR_PU BYPASS 0>;
386						sd_dat3 = <&pio19 7 ALT5 BIDIR_PU BYPASS 0>;
387						sd_led = <&pio16 6 ALT6 OUT>;
388						sd_pwren = <&pio16 7 ALT6 OUT>;
389						sd_cd = <&pio19 0 ALT6 IN>;
390						sd_wp = <&pio19 1 ALT6 IN>;
391					};
392				};
393			};
394
395
396			i2c0 {
397				pinctrl_i2c0_default: i2c0-default {
398					st,pins {
399						sda = <&pio10 6 ALT2 BIDIR>;
400						scl = <&pio10 5 ALT2 BIDIR>;
401					};
402				};
403			};
404
405			i2c1 {
406				pinctrl_i2c1_default: i2c1-default {
407					st,pins {
408						sda = <&pio11 1 ALT2 BIDIR>;
409						scl = <&pio11 0 ALT2 BIDIR>;
410					};
411				};
412			};
413
414			i2c2 {
415				pinctrl_i2c2_default: i2c2-default {
416					st,pins {
417						sda = <&pio15 6 ALT2 BIDIR>;
418						scl = <&pio15 5 ALT2 BIDIR>;
419					};
420				};
421			};
422
423			i2c3 {
424				pinctrl_i2c3_default: i2c3-default {
425					st,pins {
426						sda = <&pio18 6 ALT1 BIDIR>;
427						scl = <&pio18 5 ALT1 BIDIR>;
428					};
429				};
430			};
431
432			spi0 {
433				pinctrl_spi0_default: spi0-default {
434					st,pins {
435						mtsr = <&pio12 6 ALT2 BIDIR>;
436						mrst = <&pio12 7 ALT2 BIDIR>;
437						scl = <&pio12 5 ALT2 BIDIR>;
438					};
439				};
440			};
441		};
442
443		pin-controller-front1 {
444			#address-cells = <1>;
445			#size-cells = <1>;
446			compatible = "st,stih407-front-pinctrl";
447			st,syscfg = <&syscfg_front>;
448			reg = <0x0921f080 0x4>;
449			reg-names = "irqmux";
450			interrupts = <GIC_SPI 190 IRQ_TYPE_NONE>;
451			interrupts-names = "irqmux";
452			ranges = <0 0x09210000 0x10000>;
453
454			pio20: pio@09210000 {
455				gpio-controller;
456				#gpio-cells = <1>;
457				interrupt-controller;
458				#interrupt-cells = <2>;
459				reg = <0x0 0x100>;
460				st,bank-name = "PIO20";
461			};
462		};
463
464		pin-controller-rear {
465			#address-cells = <1>;
466			#size-cells = <1>;
467			compatible = "st,stih407-rear-pinctrl";
468			st,syscfg = <&syscfg_rear>;
469			reg = <0x0922f080 0x4>;
470			reg-names = "irqmux";
471			interrupts = <GIC_SPI 191 IRQ_TYPE_NONE>;
472			interrupts-names = "irqmux";
473			ranges = <0 0x09220000 0x6000>;
474
475			pio30: gpio@09220000 {
476				gpio-controller;
477				#gpio-cells = <1>;
478				interrupt-controller;
479				#interrupt-cells = <2>;
480				reg = <0x0 0x100>;
481				st,bank-name = "PIO30";
482			};
483			pio31: gpio@09221000 {
484				gpio-controller;
485				#gpio-cells = <1>;
486				interrupt-controller;
487				#interrupt-cells = <2>;
488				reg = <0x1000 0x100>;
489				st,bank-name = "PIO31";
490			};
491			pio32: gpio@09222000 {
492				gpio-controller;
493				#gpio-cells = <1>;
494				interrupt-controller;
495				#interrupt-cells = <2>;
496				reg = <0x2000 0x100>;
497				st,bank-name = "PIO32";
498			};
499			pio33: gpio@09223000 {
500				gpio-controller;
501				#gpio-cells = <1>;
502				interrupt-controller;
503				#interrupt-cells = <2>;
504				reg = <0x3000 0x100>;
505				st,bank-name = "PIO33";
506			};
507			pio34: gpio@09224000 {
508				gpio-controller;
509				#gpio-cells = <1>;
510				interrupt-controller;
511				#interrupt-cells = <2>;
512				reg = <0x4000 0x100>;
513				st,bank-name = "PIO34";
514			};
515			pio35: gpio@09225000 {
516				gpio-controller;
517				#gpio-cells = <1>;
518				interrupt-controller;
519				#interrupt-cells = <2>;
520				reg = <0x5000 0x100>;
521				st,bank-name = "PIO35";
522			};
523
524			i2c4 {
525				pinctrl_i2c4_default: i2c4-default {
526					st,pins {
527						sda = <&pio30 1 ALT1 BIDIR>;
528						scl = <&pio30 0 ALT1 BIDIR>;
529					};
530				};
531			};
532
533			i2c5 {
534				pinctrl_i2c5_default: i2c5-default {
535					st,pins {
536						sda = <&pio34 4 ALT1 BIDIR>;
537						scl = <&pio34 3 ALT1 BIDIR>;
538					};
539				};
540			};
541
542			usb3 {
543				pinctrl_usb3: usb3-2 {
544					st,pins {
545						usb-oc-detect = <&pio35 4 ALT1 IN>;
546						usb-pwr-enable = <&pio35 5 ALT1 OUT>;
547						usb-vbus-valid = <&pio35 6 ALT1 IN>;
548					};
549				};
550			};
551
552			pwm0 {
553				pinctrl_pwm0_chan0_default: pwm0-0-default {
554					st,pins {
555						pwm-out = <&pio31 1 ALT1 OUT>;
556					};
557				};
558			};
559		};
560
561		pin-controller-flash {
562			#address-cells = <1>;
563			#size-cells = <1>;
564			compatible = "st,stih407-flash-pinctrl";
565			st,syscfg = <&syscfg_flash>;
566			reg = <0x0923f080 0x4>;
567			reg-names = "irqmux";
568			interrupts = <GIC_SPI 192 IRQ_TYPE_NONE>;
569			interrupts-names = "irqmux";
570			ranges = <0 0x09230000 0x3000>;
571
572			pio40: gpio@09230000 {
573				gpio-controller;
574				#gpio-cells = <1>;
575				interrupt-controller;
576				#interrupt-cells = <2>;
577				reg = <0 0x100>;
578				st,bank-name = "PIO40";
579			};
580			pio41: gpio@09231000 {
581				gpio-controller;
582				#gpio-cells = <1>;
583				interrupt-controller;
584				#interrupt-cells = <2>;
585				reg = <0x1000 0x100>;
586				st,bank-name = "PIO41";
587			};
588			pio42: gpio@09232000 {
589				gpio-controller;
590				#gpio-cells = <1>;
591				interrupt-controller;
592				#interrupt-cells = <2>;
593				reg = <0x2000 0x100>;
594				st,bank-name = "PIO42";
595			};
596
597			mmc0 {
598				pinctrl_mmc0: mmc0-0 {
599					st,pins {
600						emmc_clk = <&pio40 6 ALT1 BIDIR>;
601						emmc_cmd = <&pio40 7 ALT1 BIDIR_PU>;
602						emmc_d0 = <&pio41 0 ALT1 BIDIR_PU>;
603						emmc_d1 = <&pio41 1 ALT1 BIDIR_PU>;
604						emmc_d2 = <&pio41 2 ALT1 BIDIR_PU>;
605						emmc_d3 = <&pio41 3 ALT1 BIDIR_PU>;
606						emmc_d4 = <&pio41 4 ALT1 BIDIR_PU>;
607						emmc_d5 = <&pio41 5 ALT1 BIDIR_PU>;
608						emmc_d6 = <&pio41 6 ALT1 BIDIR_PU>;
609						emmc_d7 = <&pio41 7 ALT1 BIDIR_PU>;
610					};
611				};
612			};
613		};
614	};
615};
616