rk3xxx.dtsi revision 284090
1/* 2 * Copyright (c) 2013 MundoReader S.L. 3 * Author: Heiko Stuebner <heiko@sntech.de> 4 * 5 * This program is free software; you can redistribute it and/or modify 6 * it under the terms of the GNU General Public License as published by 7 * the Free Software Foundation; either version 2 of the License, or 8 * (at your option) any later version. 9 * 10 * This program is distributed in the hope that it will be useful, 11 * but WITHOUT ANY WARRANTY; without even the implied warranty of 12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 13 * GNU General Public License for more details. 14 */ 15 16#include <dt-bindings/interrupt-controller/irq.h> 17#include <dt-bindings/interrupt-controller/arm-gic.h> 18#include "skeleton.dtsi" 19 20/ { 21 interrupt-parent = <&gic>; 22 23 aliases { 24 i2c0 = &i2c0; 25 i2c1 = &i2c1; 26 i2c2 = &i2c2; 27 i2c3 = &i2c3; 28 i2c4 = &i2c4; 29 mshc0 = &emmc; 30 mshc1 = &mmc0; 31 mshc2 = &mmc1; 32 serial0 = &uart0; 33 serial1 = &uart1; 34 serial2 = &uart2; 35 serial3 = &uart3; 36 spi0 = &spi0; 37 spi1 = &spi1; 38 }; 39 40 amba { 41 compatible = "arm,amba-bus"; 42 #address-cells = <1>; 43 #size-cells = <1>; 44 ranges; 45 46 dmac1_s: dma-controller@20018000 { 47 compatible = "arm,pl330", "arm,primecell"; 48 reg = <0x20018000 0x4000>; 49 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>, 50 <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>; 51 #dma-cells = <1>; 52 clocks = <&cru ACLK_DMA1>; 53 clock-names = "apb_pclk"; 54 }; 55 56 dmac1_ns: dma-controller@2001c000 { 57 compatible = "arm,pl330", "arm,primecell"; 58 reg = <0x2001c000 0x4000>; 59 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>, 60 <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>; 61 #dma-cells = <1>; 62 clocks = <&cru ACLK_DMA1>; 63 clock-names = "apb_pclk"; 64 status = "disabled"; 65 }; 66 67 dmac2: dma-controller@20078000 { 68 compatible = "arm,pl330", "arm,primecell"; 69 reg = <0x20078000 0x4000>; 70 interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>, 71 <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>; 72 #dma-cells = <1>; 73 clocks = <&cru ACLK_DMA2>; 74 clock-names = "apb_pclk"; 75 }; 76 }; 77 78 xin24m: oscillator { 79 compatible = "fixed-clock"; 80 clock-frequency = <24000000>; 81 #clock-cells = <0>; 82 clock-output-names = "xin24m"; 83 }; 84 85 L2: l2-cache-controller@10138000 { 86 compatible = "arm,pl310-cache"; 87 reg = <0x10138000 0x1000>; 88 cache-unified; 89 cache-level = <2>; 90 }; 91 92 scu@1013c000 { 93 compatible = "arm,cortex-a9-scu"; 94 reg = <0x1013c000 0x100>; 95 }; 96 97 global_timer: global-timer@1013c200 { 98 compatible = "arm,cortex-a9-global-timer"; 99 reg = <0x1013c200 0x20>; 100 interrupts = <GIC_PPI 11 0x304>; 101 clocks = <&cru CORE_PERI>; 102 }; 103 104 local_timer: local-timer@1013c600 { 105 compatible = "arm,cortex-a9-twd-timer"; 106 reg = <0x1013c600 0x20>; 107 interrupts = <GIC_PPI 13 0x304>; 108 clocks = <&cru CORE_PERI>; 109 }; 110 111 gic: interrupt-controller@1013d000 { 112 compatible = "arm,cortex-a9-gic"; 113 interrupt-controller; 114 #interrupt-cells = <3>; 115 reg = <0x1013d000 0x1000>, 116 <0x1013c100 0x0100>; 117 }; 118 119 uart0: serial@10124000 { 120 compatible = "snps,dw-apb-uart"; 121 reg = <0x10124000 0x400>; 122 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>; 123 reg-shift = <2>; 124 reg-io-width = <1>; 125 clock-names = "baudclk", "apb_pclk"; 126 clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>; 127 status = "disabled"; 128 }; 129 130 uart1: serial@10126000 { 131 compatible = "snps,dw-apb-uart"; 132 reg = <0x10126000 0x400>; 133 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>; 134 reg-shift = <2>; 135 reg-io-width = <1>; 136 clock-names = "baudclk", "apb_pclk"; 137 clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>; 138 status = "disabled"; 139 }; 140 141 usb_otg: usb@10180000 { 142 compatible = "rockchip,rk3066-usb", "snps,dwc2"; 143 reg = <0x10180000 0x40000>; 144 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>; 145 clocks = <&cru HCLK_OTG0>; 146 clock-names = "otg"; 147 status = "disabled"; 148 }; 149 150 usb_host: usb@101c0000 { 151 compatible = "snps,dwc2"; 152 reg = <0x101c0000 0x40000>; 153 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>; 154 clocks = <&cru HCLK_OTG1>; 155 clock-names = "otg"; 156 status = "disabled"; 157 }; 158 159 emac: ethernet@10204000 { 160 compatible = "snps,arc-emac"; 161 reg = <0x10204000 0x3c>; 162 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>; 163 #address-cells = <1>; 164 #size-cells = <0>; 165 166 rockchip,grf = <&grf>; 167 168 clocks = <&cru HCLK_EMAC>, <&cru SCLK_MAC>; 169 clock-names = "hclk", "macref"; 170 max-speed = <100>; 171 phy-mode = "rmii"; 172 173 status = "disabled"; 174 }; 175 176 mmc0: dwmmc@10214000 { 177 compatible = "rockchip,rk2928-dw-mshc"; 178 reg = <0x10214000 0x1000>; 179 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>; 180 clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>; 181 clock-names = "biu", "ciu"; 182 fifo-depth = <256>; 183 status = "disabled"; 184 }; 185 186 mmc1: dwmmc@10218000 { 187 compatible = "rockchip,rk2928-dw-mshc"; 188 reg = <0x10218000 0x1000>; 189 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>; 190 clocks = <&cru HCLK_SDIO>, <&cru SCLK_SDIO>; 191 clock-names = "biu", "ciu"; 192 fifo-depth = <256>; 193 status = "disabled"; 194 }; 195 196 emmc: dwmmc@1021c000 { 197 compatible = "rockchip,rk2928-dw-mshc"; 198 reg = <0x1021c000 0x1000>; 199 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>; 200 clocks = <&cru HCLK_EMMC>, <&cru SCLK_EMMC>; 201 clock-names = "biu", "ciu"; 202 fifo-depth = <256>; 203 status = "disabled"; 204 }; 205 206 pmu: pmu@20004000 { 207 compatible = "rockchip,rk3066-pmu", "syscon"; 208 reg = <0x20004000 0x100>; 209 }; 210 211 grf: grf@20008000 { 212 compatible = "syscon"; 213 reg = <0x20008000 0x200>; 214 }; 215 216 i2c0: i2c@2002d000 { 217 compatible = "rockchip,rk3066-i2c"; 218 reg = <0x2002d000 0x1000>; 219 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>; 220 #address-cells = <1>; 221 #size-cells = <0>; 222 223 rockchip,grf = <&grf>; 224 225 clock-names = "i2c"; 226 clocks = <&cru PCLK_I2C0>; 227 228 status = "disabled"; 229 }; 230 231 i2c1: i2c@2002f000 { 232 compatible = "rockchip,rk3066-i2c"; 233 reg = <0x2002f000 0x1000>; 234 interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>; 235 #address-cells = <1>; 236 #size-cells = <0>; 237 238 rockchip,grf = <&grf>; 239 240 clocks = <&cru PCLK_I2C1>; 241 clock-names = "i2c"; 242 243 status = "disabled"; 244 }; 245 246 pwm0: pwm@20030000 { 247 compatible = "rockchip,rk2928-pwm"; 248 reg = <0x20030000 0x10>; 249 #pwm-cells = <2>; 250 clocks = <&cru PCLK_PWM01>; 251 status = "disabled"; 252 }; 253 254 pwm1: pwm@20030010 { 255 compatible = "rockchip,rk2928-pwm"; 256 reg = <0x20030010 0x10>; 257 #pwm-cells = <2>; 258 clocks = <&cru PCLK_PWM01>; 259 status = "disabled"; 260 }; 261 262 wdt: watchdog@2004c000 { 263 compatible = "snps,dw-wdt"; 264 reg = <0x2004c000 0x100>; 265 clocks = <&cru PCLK_WDT>; 266 interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>; 267 status = "disabled"; 268 }; 269 270 pwm2: pwm@20050020 { 271 compatible = "rockchip,rk2928-pwm"; 272 reg = <0x20050020 0x10>; 273 #pwm-cells = <2>; 274 clocks = <&cru PCLK_PWM23>; 275 status = "disabled"; 276 }; 277 278 pwm3: pwm@20050030 { 279 compatible = "rockchip,rk2928-pwm"; 280 reg = <0x20050030 0x10>; 281 #pwm-cells = <2>; 282 clocks = <&cru PCLK_PWM23>; 283 status = "disabled"; 284 }; 285 286 i2c2: i2c@20056000 { 287 compatible = "rockchip,rk3066-i2c"; 288 reg = <0x20056000 0x1000>; 289 interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>; 290 #address-cells = <1>; 291 #size-cells = <0>; 292 293 rockchip,grf = <&grf>; 294 295 clocks = <&cru PCLK_I2C2>; 296 clock-names = "i2c"; 297 298 status = "disabled"; 299 }; 300 301 i2c3: i2c@2005a000 { 302 compatible = "rockchip,rk3066-i2c"; 303 reg = <0x2005a000 0x1000>; 304 interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>; 305 #address-cells = <1>; 306 #size-cells = <0>; 307 308 rockchip,grf = <&grf>; 309 310 clocks = <&cru PCLK_I2C3>; 311 clock-names = "i2c"; 312 313 status = "disabled"; 314 }; 315 316 i2c4: i2c@2005e000 { 317 compatible = "rockchip,rk3066-i2c"; 318 reg = <0x2005e000 0x1000>; 319 interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>; 320 #address-cells = <1>; 321 #size-cells = <0>; 322 323 rockchip,grf = <&grf>; 324 325 clocks = <&cru PCLK_I2C4>; 326 clock-names = "i2c"; 327 328 status = "disabled"; 329 }; 330 331 uart2: serial@20064000 { 332 compatible = "snps,dw-apb-uart"; 333 reg = <0x20064000 0x400>; 334 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>; 335 reg-shift = <2>; 336 reg-io-width = <1>; 337 clock-names = "baudclk", "apb_pclk"; 338 clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>; 339 status = "disabled"; 340 }; 341 342 uart3: serial@20068000 { 343 compatible = "snps,dw-apb-uart"; 344 reg = <0x20068000 0x400>; 345 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>; 346 reg-shift = <2>; 347 reg-io-width = <1>; 348 clock-names = "baudclk", "apb_pclk"; 349 clocks = <&cru SCLK_UART3>, <&cru PCLK_UART3>; 350 status = "disabled"; 351 }; 352 353 saradc: saradc@2006c000 { 354 compatible = "rockchip,saradc"; 355 reg = <0x2006c000 0x100>; 356 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>; 357 #io-channel-cells = <1>; 358 clocks = <&cru SCLK_SARADC>, <&cru PCLK_SARADC>; 359 clock-names = "saradc", "apb_pclk"; 360 status = "disabled"; 361 }; 362 363 spi0: spi@20070000 { 364 compatible = "rockchip,rk3066-spi"; 365 clocks = <&cru SCLK_SPI0>, <&cru PCLK_SPI0>; 366 clock-names = "spiclk", "apb_pclk"; 367 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>; 368 reg = <0x20070000 0x1000>; 369 #address-cells = <1>; 370 #size-cells = <0>; 371 dmas = <&dmac2 10>, <&dmac2 11>; 372 dma-names = "tx", "rx"; 373 status = "disabled"; 374 }; 375 376 spi1: spi@20074000 { 377 compatible = "rockchip,rk3066-spi"; 378 clocks = <&cru SCLK_SPI1>, <&cru PCLK_SPI1>; 379 clock-names = "spiclk", "apb_pclk"; 380 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>; 381 reg = <0x20074000 0x1000>; 382 #address-cells = <1>; 383 #size-cells = <0>; 384 dmas = <&dmac2 12>, <&dmac2 13>; 385 dma-names = "tx", "rx"; 386 status = "disabled"; 387 }; 388}; 389