r8a7794.dtsi revision 284090
1/* 2 * Device Tree Source for the r8a7794 SoC 3 * 4 * Copyright (C) 2014 Renesas Electronics Corporation 5 * Copyright (C) 2014 Ulrich Hecht 6 * 7 * This file is licensed under the terms of the GNU General Public License 8 * version 2. This program is licensed "as is" without any warranty of any 9 * kind, whether express or implied. 10 */ 11 12#include <dt-bindings/clock/r8a7794-clock.h> 13#include <dt-bindings/interrupt-controller/arm-gic.h> 14#include <dt-bindings/interrupt-controller/irq.h> 15 16/ { 17 compatible = "renesas,r8a7794"; 18 interrupt-parent = <&gic>; 19 #address-cells = <2>; 20 #size-cells = <2>; 21 22 cpus { 23 #address-cells = <1>; 24 #size-cells = <0>; 25 26 cpu0: cpu@0 { 27 device_type = "cpu"; 28 compatible = "arm,cortex-a7"; 29 reg = <0>; 30 clock-frequency = <1000000000>; 31 }; 32 33 cpu1: cpu@1 { 34 device_type = "cpu"; 35 compatible = "arm,cortex-a7"; 36 reg = <1>; 37 clock-frequency = <1000000000>; 38 }; 39 }; 40 41 gic: interrupt-controller@f1001000 { 42 compatible = "arm,cortex-a7-gic"; 43 #interrupt-cells = <3>; 44 #address-cells = <0>; 45 interrupt-controller; 46 reg = <0 0xf1001000 0 0x1000>, 47 <0 0xf1002000 0 0x1000>, 48 <0 0xf1004000 0 0x2000>, 49 <0 0xf1006000 0 0x2000>; 50 interrupts = <1 9 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>; 51 }; 52 53 cmt0: timer@ffca0000 { 54 compatible = "renesas,cmt-48-gen2"; 55 reg = <0 0xffca0000 0 0x1004>; 56 interrupts = <0 142 IRQ_TYPE_LEVEL_HIGH>, 57 <0 143 IRQ_TYPE_LEVEL_HIGH>; 58 clocks = <&mstp1_clks R8A7794_CLK_CMT0>; 59 clock-names = "fck"; 60 61 renesas,channels-mask = <0x60>; 62 63 status = "disabled"; 64 }; 65 66 cmt1: timer@e6130000 { 67 compatible = "renesas,cmt-48-gen2"; 68 reg = <0 0xe6130000 0 0x1004>; 69 interrupts = <0 120 IRQ_TYPE_LEVEL_HIGH>, 70 <0 121 IRQ_TYPE_LEVEL_HIGH>, 71 <0 122 IRQ_TYPE_LEVEL_HIGH>, 72 <0 123 IRQ_TYPE_LEVEL_HIGH>, 73 <0 124 IRQ_TYPE_LEVEL_HIGH>, 74 <0 125 IRQ_TYPE_LEVEL_HIGH>, 75 <0 126 IRQ_TYPE_LEVEL_HIGH>, 76 <0 127 IRQ_TYPE_LEVEL_HIGH>; 77 clocks = <&mstp3_clks R8A7794_CLK_CMT1>; 78 clock-names = "fck"; 79 80 renesas,channels-mask = <0xff>; 81 82 status = "disabled"; 83 }; 84 85 timer { 86 compatible = "arm,armv7-timer"; 87 interrupts = <1 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>, 88 <1 14 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>, 89 <1 11 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>, 90 <1 10 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>; 91 }; 92 93 irqc0: interrupt-controller@e61c0000 { 94 compatible = "renesas,irqc-r8a7794", "renesas,irqc"; 95 #interrupt-cells = <2>; 96 interrupt-controller; 97 reg = <0 0xe61c0000 0 0x200>; 98 interrupts = <0 0 IRQ_TYPE_LEVEL_HIGH>, 99 <0 1 IRQ_TYPE_LEVEL_HIGH>, 100 <0 2 IRQ_TYPE_LEVEL_HIGH>, 101 <0 3 IRQ_TYPE_LEVEL_HIGH>, 102 <0 12 IRQ_TYPE_LEVEL_HIGH>, 103 <0 13 IRQ_TYPE_LEVEL_HIGH>, 104 <0 14 IRQ_TYPE_LEVEL_HIGH>, 105 <0 15 IRQ_TYPE_LEVEL_HIGH>, 106 <0 16 IRQ_TYPE_LEVEL_HIGH>, 107 <0 17 IRQ_TYPE_LEVEL_HIGH>; 108 }; 109 110 scifa0: serial@e6c40000 { 111 compatible = "renesas,scifa-r8a7794", "renesas,scifa"; 112 reg = <0 0xe6c40000 0 64>; 113 interrupts = <0 144 IRQ_TYPE_LEVEL_HIGH>; 114 clocks = <&mstp2_clks R8A7794_CLK_SCIFA0>; 115 clock-names = "sci_ick"; 116 status = "disabled"; 117 }; 118 119 scifa1: serial@e6c50000 { 120 compatible = "renesas,scifa-r8a7794", "renesas,scifa"; 121 reg = <0 0xe6c50000 0 64>; 122 interrupts = <0 145 IRQ_TYPE_LEVEL_HIGH>; 123 clocks = <&mstp2_clks R8A7794_CLK_SCIFA1>; 124 clock-names = "sci_ick"; 125 status = "disabled"; 126 }; 127 128 scifa2: serial@e6c60000 { 129 compatible = "renesas,scifa-r8a7794", "renesas,scifa"; 130 reg = <0 0xe6c60000 0 64>; 131 interrupts = <0 151 IRQ_TYPE_LEVEL_HIGH>; 132 clocks = <&mstp2_clks R8A7794_CLK_SCIFA2>; 133 clock-names = "sci_ick"; 134 status = "disabled"; 135 }; 136 137 scifa3: serial@e6c70000 { 138 compatible = "renesas,scifa-r8a7794", "renesas,scifa"; 139 reg = <0 0xe6c70000 0 64>; 140 interrupts = <0 29 IRQ_TYPE_LEVEL_HIGH>; 141 clocks = <&mstp11_clks R8A7794_CLK_SCIFA3>; 142 clock-names = "sci_ick"; 143 status = "disabled"; 144 }; 145 146 scifa4: serial@e6c78000 { 147 compatible = "renesas,scifa-r8a7794", "renesas,scifa"; 148 reg = <0 0xe6c78000 0 64>; 149 interrupts = <0 30 IRQ_TYPE_LEVEL_HIGH>; 150 clocks = <&mstp11_clks R8A7794_CLK_SCIFA4>; 151 clock-names = "sci_ick"; 152 status = "disabled"; 153 }; 154 155 scifa5: serial@e6c80000 { 156 compatible = "renesas,scifa-r8a7794", "renesas,scifa"; 157 reg = <0 0xe6c80000 0 64>; 158 interrupts = <0 31 IRQ_TYPE_LEVEL_HIGH>; 159 clocks = <&mstp11_clks R8A7794_CLK_SCIFA5>; 160 clock-names = "sci_ick"; 161 status = "disabled"; 162 }; 163 164 scifb0: serial@e6c20000 { 165 compatible = "renesas,scifb-r8a7794", "renesas,scifb"; 166 reg = <0 0xe6c20000 0 64>; 167 interrupts = <0 148 IRQ_TYPE_LEVEL_HIGH>; 168 clocks = <&mstp2_clks R8A7794_CLK_SCIFB0>; 169 clock-names = "sci_ick"; 170 status = "disabled"; 171 }; 172 173 scifb1: serial@e6c30000 { 174 compatible = "renesas,scifb-r8a7794", "renesas,scifb"; 175 reg = <0 0xe6c30000 0 64>; 176 interrupts = <0 149 IRQ_TYPE_LEVEL_HIGH>; 177 clocks = <&mstp2_clks R8A7794_CLK_SCIFB1>; 178 clock-names = "sci_ick"; 179 status = "disabled"; 180 }; 181 182 scifb2: serial@e6ce0000 { 183 compatible = "renesas,scifb-r8a7794", "renesas,scifb"; 184 reg = <0 0xe6ce0000 0 64>; 185 interrupts = <0 150 IRQ_TYPE_LEVEL_HIGH>; 186 clocks = <&mstp2_clks R8A7794_CLK_SCIFB2>; 187 clock-names = "sci_ick"; 188 status = "disabled"; 189 }; 190 191 scif0: serial@e6e60000 { 192 compatible = "renesas,scif-r8a7794", "renesas,scif"; 193 reg = <0 0xe6e60000 0 64>; 194 interrupts = <0 152 IRQ_TYPE_LEVEL_HIGH>; 195 clocks = <&mstp7_clks R8A7794_CLK_SCIF0>; 196 clock-names = "sci_ick"; 197 status = "disabled"; 198 }; 199 200 scif1: serial@e6e68000 { 201 compatible = "renesas,scif-r8a7794", "renesas,scif"; 202 reg = <0 0xe6e68000 0 64>; 203 interrupts = <0 153 IRQ_TYPE_LEVEL_HIGH>; 204 clocks = <&mstp7_clks R8A7794_CLK_SCIF1>; 205 clock-names = "sci_ick"; 206 status = "disabled"; 207 }; 208 209 scif2: serial@e6e58000 { 210 compatible = "renesas,scif-r8a7794", "renesas,scif"; 211 reg = <0 0xe6e58000 0 64>; 212 interrupts = <0 22 IRQ_TYPE_LEVEL_HIGH>; 213 clocks = <&mstp7_clks R8A7794_CLK_SCIF2>; 214 clock-names = "sci_ick"; 215 status = "disabled"; 216 }; 217 218 scif3: serial@e6ea8000 { 219 compatible = "renesas,scif-r8a7794", "renesas,scif"; 220 reg = <0 0xe6ea8000 0 64>; 221 interrupts = <0 23 IRQ_TYPE_LEVEL_HIGH>; 222 clocks = <&mstp7_clks R8A7794_CLK_SCIF3>; 223 clock-names = "sci_ick"; 224 status = "disabled"; 225 }; 226 227 scif4: serial@e6ee0000 { 228 compatible = "renesas,scif-r8a7794", "renesas,scif"; 229 reg = <0 0xe6ee0000 0 64>; 230 interrupts = <0 24 IRQ_TYPE_LEVEL_HIGH>; 231 clocks = <&mstp7_clks R8A7794_CLK_SCIF4>; 232 clock-names = "sci_ick"; 233 status = "disabled"; 234 }; 235 236 scif5: serial@e6ee8000 { 237 compatible = "renesas,scif-r8a7794", "renesas,scif"; 238 reg = <0 0xe6ee8000 0 64>; 239 interrupts = <0 25 IRQ_TYPE_LEVEL_HIGH>; 240 clocks = <&mstp7_clks R8A7794_CLK_SCIF5>; 241 clock-names = "sci_ick"; 242 status = "disabled"; 243 }; 244 245 hscif0: serial@e62c0000 { 246 compatible = "renesas,hscif-r8a7794", "renesas,hscif"; 247 reg = <0 0xe62c0000 0 96>; 248 interrupts = <0 154 IRQ_TYPE_LEVEL_HIGH>; 249 clocks = <&mstp7_clks R8A7794_CLK_HSCIF0>; 250 clock-names = "sci_ick"; 251 status = "disabled"; 252 }; 253 254 hscif1: serial@e62c8000 { 255 compatible = "renesas,hscif-r8a7794", "renesas,hscif"; 256 reg = <0 0xe62c8000 0 96>; 257 interrupts = <0 155 IRQ_TYPE_LEVEL_HIGH>; 258 clocks = <&mstp7_clks R8A7794_CLK_HSCIF1>; 259 clock-names = "sci_ick"; 260 status = "disabled"; 261 }; 262 263 hscif2: serial@e62d0000 { 264 compatible = "renesas,hscif-r8a7794", "renesas,hscif"; 265 reg = <0 0xe62d0000 0 96>; 266 interrupts = <0 21 IRQ_TYPE_LEVEL_HIGH>; 267 clocks = <&mstp7_clks R8A7794_CLK_HSCIF2>; 268 clock-names = "sci_ick"; 269 status = "disabled"; 270 }; 271 272 clocks { 273 #address-cells = <2>; 274 #size-cells = <2>; 275 ranges; 276 277 /* External root clock */ 278 extal_clk: extal_clk { 279 compatible = "fixed-clock"; 280 #clock-cells = <0>; 281 /* This value must be overriden by the board. */ 282 clock-frequency = <0>; 283 clock-output-names = "extal"; 284 }; 285 286 /* Special CPG clocks */ 287 cpg_clocks: cpg_clocks@e6150000 { 288 compatible = "renesas,r8a7794-cpg-clocks", 289 "renesas,rcar-gen2-cpg-clocks"; 290 reg = <0 0xe6150000 0 0x1000>; 291 clocks = <&extal_clk>; 292 #clock-cells = <1>; 293 clock-output-names = "main", "pll0", "pll1", "pll3", 294 "lb", "qspi", "sdh", "sd0", "z"; 295 }; 296 /* Variable factor clocks */ 297 sd1_clk: sd2_clk@e6150078 { 298 compatible = "renesas,r8a7794-div6-clock", "renesas,cpg-div6-clock"; 299 reg = <0 0xe6150078 0 4>; 300 clocks = <&pll1_div2_clk>; 301 #clock-cells = <0>; 302 clock-output-names = "sd1"; 303 }; 304 sd2_clk: sd3_clk@e615007c { 305 compatible = "renesas,r8a7794-div6-clock", "renesas,cpg-div6-clock"; 306 reg = <0 0xe615007c 0 4>; 307 clocks = <&pll1_div2_clk>; 308 #clock-cells = <0>; 309 clock-output-names = "sd2"; 310 }; 311 mmc0_clk: mmc0_clk@e6150240 { 312 compatible = "renesas,r8a7794-div6-clock", "renesas,cpg-div6-clock"; 313 reg = <0 0xe6150240 0 4>; 314 clocks = <&pll1_div2_clk>; 315 #clock-cells = <0>; 316 clock-output-names = "mmc0"; 317 }; 318 319 /* Fixed factor clocks */ 320 pll1_div2_clk: pll1_div2_clk { 321 compatible = "fixed-factor-clock"; 322 clocks = <&cpg_clocks R8A7794_CLK_PLL1>; 323 #clock-cells = <0>; 324 clock-div = <2>; 325 clock-mult = <1>; 326 clock-output-names = "pll1_div2"; 327 }; 328 zg_clk: zg_clk { 329 compatible = "fixed-factor-clock"; 330 clocks = <&cpg_clocks R8A7794_CLK_PLL1>; 331 #clock-cells = <0>; 332 clock-div = <6>; 333 clock-mult = <1>; 334 clock-output-names = "zg"; 335 }; 336 zx_clk: zx_clk { 337 compatible = "fixed-factor-clock"; 338 clocks = <&cpg_clocks R8A7794_CLK_PLL1>; 339 #clock-cells = <0>; 340 clock-div = <3>; 341 clock-mult = <1>; 342 clock-output-names = "zx"; 343 }; 344 zs_clk: zs_clk { 345 compatible = "fixed-factor-clock"; 346 clocks = <&cpg_clocks R8A7794_CLK_PLL1>; 347 #clock-cells = <0>; 348 clock-div = <6>; 349 clock-mult = <1>; 350 clock-output-names = "zs"; 351 }; 352 hp_clk: hp_clk { 353 compatible = "fixed-factor-clock"; 354 clocks = <&cpg_clocks R8A7794_CLK_PLL1>; 355 #clock-cells = <0>; 356 clock-div = <12>; 357 clock-mult = <1>; 358 clock-output-names = "hp"; 359 }; 360 i_clk: i_clk { 361 compatible = "fixed-factor-clock"; 362 clocks = <&cpg_clocks R8A7794_CLK_PLL1>; 363 #clock-cells = <0>; 364 clock-div = <2>; 365 clock-mult = <1>; 366 clock-output-names = "i"; 367 }; 368 b_clk: b_clk { 369 compatible = "fixed-factor-clock"; 370 clocks = <&cpg_clocks R8A7794_CLK_PLL1>; 371 #clock-cells = <0>; 372 clock-div = <12>; 373 clock-mult = <1>; 374 clock-output-names = "b"; 375 }; 376 p_clk: p_clk { 377 compatible = "fixed-factor-clock"; 378 clocks = <&cpg_clocks R8A7794_CLK_PLL1>; 379 #clock-cells = <0>; 380 clock-div = <24>; 381 clock-mult = <1>; 382 clock-output-names = "p"; 383 }; 384 cl_clk: cl_clk { 385 compatible = "fixed-factor-clock"; 386 clocks = <&cpg_clocks R8A7794_CLK_PLL1>; 387 #clock-cells = <0>; 388 clock-div = <48>; 389 clock-mult = <1>; 390 clock-output-names = "cl"; 391 }; 392 m2_clk: m2_clk { 393 compatible = "fixed-factor-clock"; 394 clocks = <&cpg_clocks R8A7794_CLK_PLL1>; 395 #clock-cells = <0>; 396 clock-div = <8>; 397 clock-mult = <1>; 398 clock-output-names = "m2"; 399 }; 400 imp_clk: imp_clk { 401 compatible = "fixed-factor-clock"; 402 clocks = <&cpg_clocks R8A7794_CLK_PLL1>; 403 #clock-cells = <0>; 404 clock-div = <4>; 405 clock-mult = <1>; 406 clock-output-names = "imp"; 407 }; 408 rclk_clk: rclk_clk { 409 compatible = "fixed-factor-clock"; 410 clocks = <&cpg_clocks R8A7794_CLK_PLL1>; 411 #clock-cells = <0>; 412 clock-div = <(48 * 1024)>; 413 clock-mult = <1>; 414 clock-output-names = "rclk"; 415 }; 416 oscclk_clk: oscclk_clk { 417 compatible = "fixed-factor-clock"; 418 clocks = <&cpg_clocks R8A7794_CLK_PLL1>; 419 #clock-cells = <0>; 420 clock-div = <(12 * 1024)>; 421 clock-mult = <1>; 422 clock-output-names = "oscclk"; 423 }; 424 zb3_clk: zb3_clk { 425 compatible = "fixed-factor-clock"; 426 clocks = <&cpg_clocks R8A7794_CLK_PLL3>; 427 #clock-cells = <0>; 428 clock-div = <4>; 429 clock-mult = <1>; 430 clock-output-names = "zb3"; 431 }; 432 zb3d2_clk: zb3d2_clk { 433 compatible = "fixed-factor-clock"; 434 clocks = <&cpg_clocks R8A7794_CLK_PLL3>; 435 #clock-cells = <0>; 436 clock-div = <8>; 437 clock-mult = <1>; 438 clock-output-names = "zb3d2"; 439 }; 440 ddr_clk: ddr_clk { 441 compatible = "fixed-factor-clock"; 442 clocks = <&cpg_clocks R8A7794_CLK_PLL3>; 443 #clock-cells = <0>; 444 clock-div = <8>; 445 clock-mult = <1>; 446 clock-output-names = "ddr"; 447 }; 448 mp_clk: mp_clk { 449 compatible = "fixed-factor-clock"; 450 clocks = <&pll1_div2_clk>; 451 #clock-cells = <0>; 452 clock-div = <15>; 453 clock-mult = <1>; 454 clock-output-names = "mp"; 455 }; 456 cp_clk: cp_clk { 457 compatible = "fixed-factor-clock"; 458 clocks = <&cpg_clocks R8A7794_CLK_PLL1>; 459 #clock-cells = <0>; 460 clock-div = <48>; 461 clock-mult = <1>; 462 clock-output-names = "cp"; 463 }; 464 465 acp_clk: acp_clk { 466 compatible = "fixed-factor-clock"; 467 clocks = <&extal_clk>; 468 #clock-cells = <0>; 469 clock-div = <2>; 470 clock-mult = <1>; 471 clock-output-names = "acp"; 472 }; 473 474 /* Gate clocks */ 475 mstp0_clks: mstp0_clks@e6150130 { 476 compatible = "renesas,r8a7794-mstp-clocks", "renesas,cpg-mstp-clocks"; 477 reg = <0 0xe6150130 0 4>, <0 0xe6150030 0 4>; 478 clocks = <&mp_clk>; 479 #clock-cells = <1>; 480 clock-indices = <R8A7794_CLK_MSIOF0>; 481 clock-output-names = "msiof0"; 482 }; 483 mstp1_clks: mstp1_clks@e6150134 { 484 compatible = "renesas,r8a7794-mstp-clocks", "renesas,cpg-mstp-clocks"; 485 reg = <0 0xe6150134 0 4>, <0 0xe6150038 0 4>; 486 clocks = <&zs_clk>, <&zs_clk>, <&p_clk>, <&zg_clk>, <&zs_clk>, 487 <&zs_clk>, <&p_clk>, <&p_clk>, <&rclk_clk>, <&cp_clk>, 488 <&zs_clk>, <&zs_clk>; 489 #clock-cells = <1>; 490 clock-indices = < 491 R8A7794_CLK_VCP0 R8A7794_CLK_VPC0 R8A7794_CLK_TMU1 492 R8A7794_CLK_3DG R8A7794_CLK_2DDMAC R8A7794_CLK_FDP1_0 493 R8A7794_CLK_TMU3 R8A7794_CLK_TMU2 R8A7794_CLK_CMT0 494 R8A7794_CLK_TMU0 R8A7794_CLK_VSP1_DU0 R8A7794_CLK_VSP1_S 495 >; 496 clock-output-names = 497 "vcp0", "vpc0", "tmu1", "3dg", "2ddmac", "fdp1-0", 498 "tmu3", "tmu2", "cmt0", "tmu0", "vsp1-du0", "vsps"; 499 }; 500 mstp2_clks: mstp2_clks@e6150138 { 501 compatible = "renesas,r8a7794-mstp-clocks", "renesas,cpg-mstp-clocks"; 502 reg = <0 0xe6150138 0 4>, <0 0xe6150040 0 4>; 503 clocks = <&mp_clk>, <&mp_clk>, <&mp_clk>, <&mp_clk>, <&mp_clk>, 504 <&mp_clk>, <&mp_clk>, <&mp_clk>, 505 <&zs_clk>, <&zs_clk>; 506 #clock-cells = <1>; 507 clock-indices = < 508 R8A7794_CLK_SCIFA2 R8A7794_CLK_SCIFA1 R8A7794_CLK_SCIFA0 509 R8A7794_CLK_MSIOF2 R8A7794_CLK_SCIFB0 R8A7794_CLK_SCIFB1 510 R8A7794_CLK_MSIOF1 R8A7794_CLK_SCIFB2 511 R8A7794_CLK_SYS_DMAC1 R8A7794_CLK_SYS_DMAC0 512 >; 513 clock-output-names = 514 "scifa2", "scifa1", "scifa0", "msiof2", "scifb0", 515 "scifb1", "msiof1", "scifb2", 516 "sys-dmac1", "sys-dmac0"; 517 }; 518 mstp3_clks: mstp3_clks@e615013c { 519 compatible = "renesas,r8a7794-mstp-clocks", "renesas,cpg-mstp-clocks"; 520 reg = <0 0xe615013c 0 4>, <0 0xe6150048 0 4>; 521 clocks = <&sd2_clk>, <&sd1_clk>, <&cpg_clocks R8A7794_CLK_SD0>, 522 <&mmc0_clk>, <&rclk_clk>, <&hp_clk>, <&hp_clk>; 523 #clock-cells = <1>; 524 clock-indices = < 525 R8A7794_CLK_SDHI2 R8A7794_CLK_SDHI1 R8A7794_CLK_SDHI0 526 R8A7794_CLK_MMCIF0 R8A7794_CLK_CMT1 527 R8A7794_CLK_USBDMAC0 R8A7794_CLK_USBDMAC1 528 >; 529 clock-output-names = 530 "sdhi2", "sdhi1", "sdhi0", 531 "mmcif0", "cmt1", "usbdmac0", "usbdmac1"; 532 }; 533 mstp7_clks: mstp7_clks@e615014c { 534 compatible = "renesas,r8a7794-mstp-clocks", "renesas,cpg-mstp-clocks"; 535 reg = <0 0xe615014c 0 4>, <0 0xe61501c4 0 4>; 536 clocks = <&mp_clk>, <&mp_clk>, 537 <&zs_clk>, <&p_clk>, <&p_clk>, <&zs_clk>, 538 <&zs_clk>, <&p_clk>, <&p_clk>, <&p_clk>, <&p_clk>; 539 #clock-cells = <1>; 540 clock-indices = < 541 R8A7794_CLK_EHCI R8A7794_CLK_HSUSB 542 R8A7794_CLK_HSCIF2 R8A7794_CLK_SCIF5 543 R8A7794_CLK_SCIF4 R8A7794_CLK_HSCIF1 R8A7794_CLK_HSCIF0 544 R8A7794_CLK_SCIF3 R8A7794_CLK_SCIF2 R8A7794_CLK_SCIF1 545 R8A7794_CLK_SCIF0 546 >; 547 clock-output-names = 548 "ehci", "hsusb", 549 "hscif2", "scif5", "scif4", "hscif1", "hscif0", 550 "scif3", "scif2", "scif1", "scif0"; 551 }; 552 mstp8_clks: mstp8_clks@e6150990 { 553 compatible = "renesas,r8a7794-mstp-clocks", "renesas,cpg-mstp-clocks"; 554 reg = <0 0xe6150990 0 4>, <0 0xe61509a0 0 4>; 555 clocks = <&zg_clk>, <&zg_clk>, <&p_clk>; 556 #clock-cells = <1>; 557 clock-indices = < 558 R8A7794_CLK_VIN1 R8A7794_CLK_VIN0 R8A7794_CLK_ETHER 559 >; 560 clock-output-names = 561 "vin1", "vin0", "ether"; 562 }; 563 mstp9_clks: mstp9_clks@e6150994 { 564 compatible = "renesas,r8a7794-mstp-clocks", "renesas,cpg-mstp-clocks"; 565 reg = <0 0xe6150994 0 4>, <0 0xe61509a4 0 4>; 566 clocks = <&cpg_clocks R8A7794_CLK_QSPI>, <&hp_clk>, <&hp_clk>, 567 <&hp_clk>, <&hp_clk>, <&hp_clk>, <&hp_clk>; 568 #clock-cells = <1>; 569 clock-indices = < 570 R8A7794_CLK_QSPI_MOD R8A7794_CLK_I2C5 R8A7794_CLK_I2C4 571 R8A7794_CLK_I2C3 R8A7794_CLK_I2C2 R8A7794_CLK_I2C1 572 R8A7794_CLK_I2C0 573 >; 574 clock-output-names = 575 "qspi_mod", "i2c5", "i2c4", "i2c3", "i2c2", "i2c1", "i2c0"; 576 }; 577 mstp11_clks: mstp11_clks@e615099c { 578 compatible = "renesas,r8a7794-mstp-clocks", "renesas,cpg-mstp-clocks"; 579 reg = <0 0xe615099c 0 4>, <0 0xe61509ac 0 4>; 580 clocks = <&mp_clk>, <&mp_clk>, <&mp_clk>; 581 #clock-cells = <1>; 582 clock-indices = < 583 R8A7794_CLK_SCIFA3 R8A7794_CLK_SCIFA4 R8A7794_CLK_SCIFA5 584 >; 585 clock-output-names = "scifa3", "scifa4", "scifa5"; 586 }; 587 }; 588}; 589