orion5x.dtsi revision 284090 
1/*
2 * Copyright (C) 2012 Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
3 *
4 * This file is licensed under the terms of the GNU General Public
5 * License version 2. This program is licensed "as is" without any
6 * warranty of any kind, whether express or implied.
7 */
8
9#include "skeleton.dtsi"
10
11#define MBUS_ID(target,attributes) (((target) << 24) | ((attributes) << 16))
12
13/ {
14	model = "Marvell Orion5x SoC";
15	compatible = "marvell,orion5x";
16	interrupt-parent = <&intc>;
17
18	aliases {
19		gpio0 = &gpio0;
20	};
21
22	soc {
23		#address-cells = <2>;
24		#size-cells = <1>;
25		controller = <&mbusc>;
26
27		devbus_bootcs: devbus-bootcs {
28			compatible = "marvell,orion-devbus";
29			reg = <MBUS_ID(0xf0, 0x01) 0x1046C 0x4>;
30			ranges = <0 MBUS_ID(0x01, 0x0f) 0 0xffffffff>;
31			#address-cells = <1>;
32			#size-cells = <1>;
33			clocks = <&core_clk 0>;
34			status = "disabled";
35		};
36
37		devbus_cs0: devbus-cs0 {
38			compatible = "marvell,orion-devbus";
39			reg = <MBUS_ID(0xf0, 0x01) 0x1045C 0x4>;
40			ranges = <0 MBUS_ID(0x01, 0x1e) 0 0xffffffff>;
41			#address-cells = <1>;
42			#size-cells = <1>;
43			clocks = <&core_clk 0>;
44			status = "disabled";
45		};
46
47		devbus_cs1: devbus-cs1 {
48			compatible = "marvell,orion-devbus";
49			reg = <MBUS_ID(0xf0, 0x01) 0x10460 0x4>;
50			ranges = <0 MBUS_ID(0x01, 0x1d) 0 0xffffffff>;
51			#address-cells = <1>;
52			#size-cells = <1>;
53			clocks = <&core_clk 0>;
54			status = "disabled";
55		};
56
57		devbus_cs2: devbus-cs2 {
58			compatible = "marvell,orion-devbus";
59			reg = <MBUS_ID(0xf0, 0x01) 0x10464 0x4>;
60			ranges = <0 MBUS_ID(0x01, 0x1b) 0 0xffffffff>;
61			#address-cells = <1>;
62			#size-cells = <1>;
63			clocks = <&core_clk 0>;
64			status = "disabled";
65		};
66
67		internal-regs {
68			compatible = "simple-bus";
69			#address-cells = <1>;
70			#size-cells = <1>;
71			ranges = <0 MBUS_ID(0xf0, 0x01) 0 0x100000>;
72
73			gpio0: gpio@10100 {
74				compatible = "marvell,orion-gpio";
75				#gpio-cells = <2>;
76				gpio-controller;
77				reg = <0x10100 0x40>;
78				ngpios = <32>;
79				interrupt-controller;
80				#interrupt-cells = <2>;
81				interrupts = <6>, <7>, <8>, <9>;
82			};
83
84			spi: spi@10600 {
85				compatible = "marvell,orion-spi";
86				#address-cells = <1>;
87				#size-cells = <0>;
88				cell-index = <0>;
89				reg = <0x10600 0x28>;
90				status = "disabled";
91			};
92
93			i2c: i2c@11000 {
94				compatible = "marvell,mv64xxx-i2c";
95				reg = <0x11000 0x20>;
96				#address-cells = <1>;
97				#size-cells = <0>;
98				interrupts = <5>;
99				clocks = <&core_clk 0>;
100				status = "disabled";
101			};
102
103			uart0: serial@12000 {
104				compatible = "ns16550a";
105				reg = <0x12000 0x100>;
106				reg-shift = <2>;
107				interrupts = <3>;
108				clocks = <&core_clk 0>;
109				status = "disabled";
110			};
111
112			uart1: serial@12100 {
113				compatible = "ns16550a";
114				reg = <0x12100 0x100>;
115				reg-shift = <2>;
116				interrupts = <4>;
117				clocks = <&core_clk 0>;
118				status = "disabled";
119			};
120
121			bridge_intc: bridge-interrupt-ctrl@20110 {
122				compatible = "marvell,orion-bridge-intc";
123				interrupt-controller;
124				#interrupt-cells = <1>;
125				reg = <0x20110 0x8>;
126				interrupts = <0>;
127				marvell,#interrupts = <4>;
128			};
129
130			intc: interrupt-controller@20200 {
131				compatible = "marvell,orion-intc";
132				interrupt-controller;
133				#interrupt-cells = <1>;
134				reg = <0x20200 0x08>;
135			};
136
137			timer: timer@20300 {
138				compatible = "marvell,orion-timer";
139				reg = <0x20300 0x20>;
140				interrupt-parent = <&bridge_intc>;
141				interrupts = <1>, <2>;
142				clocks = <&core_clk 0>;
143			};
144
145			wdt: wdt@20300 {
146				compatible = "marvell,orion-wdt";
147				reg = <0x20300 0x28>;
148				interrupt-parent = <&bridge_intc>;
149				interrupts = <3>;
150				status = "okay";
151			};
152
153			ehci0: ehci@50000 {
154				compatible = "marvell,orion-ehci";
155				reg = <0x50000 0x1000>;
156				interrupts = <17>;
157				status = "disabled";
158			};
159
160			xor: dma-controller@60900 {
161				compatible = "marvell,orion-xor";
162				reg = <0x60900 0x100
163				       0x60b00 0x100>;
164				status = "okay";
165
166				xor00 {
167				      interrupts = <30>;
168				      dmacap,memcpy;
169				      dmacap,xor;
170				};
171				xor01 {
172				      interrupts = <31>;
173				      dmacap,memcpy;
174				      dmacap,xor;
175				      dmacap,memset;
176				};
177			};
178
179			eth: ethernet-controller@72000 {
180				compatible = "marvell,orion-eth";
181				#address-cells = <1>;
182				#size-cells = <0>;
183				reg = <0x72000 0x4000>;
184				marvell,tx-checksum-limit = <1600>;
185				status = "disabled";
186
187				ethport: ethernet-port@0 {
188					compatible = "marvell,orion-eth-port";
189					reg = <0>;
190					interrupts = <21>;
191					/* overwrite MAC address in bootloader */
192					local-mac-address = [00 00 00 00 00 00];
193					/* set phy-handle property in board file */
194				};
195			};
196
197			mdio: mdio-bus@72004 {
198				compatible = "marvell,orion-mdio";
199				#address-cells = <1>;
200				#size-cells = <0>;
201				reg = <0x72004 0x84>;
202				interrupts = <22>;
203				status = "disabled";
204
205				/* add phy nodes in board file */
206			};
207
208			sata: sata@80000 {
209				compatible = "marvell,orion-sata";
210				reg = <0x80000 0x5000>;
211				interrupts = <29>;
212				status = "disabled";
213			};
214
215			ehci1: ehci@a0000 {
216				compatible = "marvell,orion-ehci";
217				reg = <0xa0000 0x1000>;
218				interrupts = <12>;
219				status = "disabled";
220			};
221		};
222
223		cesa: crypto@90000 {
224			compatible = "marvell,orion-crypto";
225			reg = <MBUS_ID(0xf0, 0x01) 0x90000 0x10000>,
226			      <MBUS_ID(0x09, 0x00) 0x0 0x800>;
227			reg-names = "regs", "sram";
228			interrupts = <28>;
229			status = "okay";
230		};
231	};
232};
233