omap3xxx-clocks.dtsi revision 284090
1/* 2 * Device Tree Source for OMAP3 clock data 3 * 4 * Copyright (C) 2013 Texas Instruments, Inc. 5 * 6 * This program is free software; you can redistribute it and/or modify 7 * it under the terms of the GNU General Public License version 2 as 8 * published by the Free Software Foundation. 9 */ 10&prm_clocks { 11 virt_16_8m_ck: virt_16_8m_ck { 12 #clock-cells = <0>; 13 compatible = "fixed-clock"; 14 clock-frequency = <16800000>; 15 }; 16 17 osc_sys_ck: osc_sys_ck { 18 #clock-cells = <0>; 19 compatible = "ti,mux-clock"; 20 clocks = <&virt_12m_ck>, <&virt_13m_ck>, <&virt_19200000_ck>, <&virt_26000000_ck>, <&virt_38_4m_ck>, <&virt_16_8m_ck>; 21 reg = <0x0d40>; 22 }; 23 24 sys_ck: sys_ck { 25 #clock-cells = <0>; 26 compatible = "ti,divider-clock"; 27 clocks = <&osc_sys_ck>; 28 ti,bit-shift = <6>; 29 ti,max-div = <3>; 30 reg = <0x1270>; 31 ti,index-starts-at-one; 32 }; 33 34 sys_clkout1: sys_clkout1 { 35 #clock-cells = <0>; 36 compatible = "ti,gate-clock"; 37 clocks = <&osc_sys_ck>; 38 reg = <0x0d70>; 39 ti,bit-shift = <7>; 40 }; 41 42 dpll3_x2_ck: dpll3_x2_ck { 43 #clock-cells = <0>; 44 compatible = "fixed-factor-clock"; 45 clocks = <&dpll3_ck>; 46 clock-mult = <2>; 47 clock-div = <1>; 48 }; 49 50 dpll3_m2x2_ck: dpll3_m2x2_ck { 51 #clock-cells = <0>; 52 compatible = "fixed-factor-clock"; 53 clocks = <&dpll3_m2_ck>; 54 clock-mult = <2>; 55 clock-div = <1>; 56 }; 57 58 dpll4_x2_ck: dpll4_x2_ck { 59 #clock-cells = <0>; 60 compatible = "fixed-factor-clock"; 61 clocks = <&dpll4_ck>; 62 clock-mult = <2>; 63 clock-div = <1>; 64 }; 65 66 corex2_fck: corex2_fck { 67 #clock-cells = <0>; 68 compatible = "fixed-factor-clock"; 69 clocks = <&dpll3_m2x2_ck>; 70 clock-mult = <1>; 71 clock-div = <1>; 72 }; 73 74 wkup_l4_ick: wkup_l4_ick { 75 #clock-cells = <0>; 76 compatible = "fixed-factor-clock"; 77 clocks = <&sys_ck>; 78 clock-mult = <1>; 79 clock-div = <1>; 80 }; 81}; 82&scrm_clocks { 83 mcbsp5_mux_fck: mcbsp5_mux_fck { 84 #clock-cells = <0>; 85 compatible = "ti,composite-mux-clock"; 86 clocks = <&core_96m_fck>, <&mcbsp_clks>; 87 ti,bit-shift = <4>; 88 reg = <0x02d8>; 89 }; 90 91 mcbsp5_fck: mcbsp5_fck { 92 #clock-cells = <0>; 93 compatible = "ti,composite-clock"; 94 clocks = <&mcbsp5_gate_fck>, <&mcbsp5_mux_fck>; 95 }; 96 97 mcbsp1_mux_fck: mcbsp1_mux_fck { 98 #clock-cells = <0>; 99 compatible = "ti,composite-mux-clock"; 100 clocks = <&core_96m_fck>, <&mcbsp_clks>; 101 ti,bit-shift = <2>; 102 reg = <0x0274>; 103 }; 104 105 mcbsp1_fck: mcbsp1_fck { 106 #clock-cells = <0>; 107 compatible = "ti,composite-clock"; 108 clocks = <&mcbsp1_gate_fck>, <&mcbsp1_mux_fck>; 109 }; 110 111 mcbsp2_mux_fck: mcbsp2_mux_fck { 112 #clock-cells = <0>; 113 compatible = "ti,composite-mux-clock"; 114 clocks = <&per_96m_fck>, <&mcbsp_clks>; 115 ti,bit-shift = <6>; 116 reg = <0x0274>; 117 }; 118 119 mcbsp2_fck: mcbsp2_fck { 120 #clock-cells = <0>; 121 compatible = "ti,composite-clock"; 122 clocks = <&mcbsp2_gate_fck>, <&mcbsp2_mux_fck>; 123 }; 124 125 mcbsp3_mux_fck: mcbsp3_mux_fck { 126 #clock-cells = <0>; 127 compatible = "ti,composite-mux-clock"; 128 clocks = <&per_96m_fck>, <&mcbsp_clks>; 129 reg = <0x02d8>; 130 }; 131 132 mcbsp3_fck: mcbsp3_fck { 133 #clock-cells = <0>; 134 compatible = "ti,composite-clock"; 135 clocks = <&mcbsp3_gate_fck>, <&mcbsp3_mux_fck>; 136 }; 137 138 mcbsp4_mux_fck: mcbsp4_mux_fck { 139 #clock-cells = <0>; 140 compatible = "ti,composite-mux-clock"; 141 clocks = <&per_96m_fck>, <&mcbsp_clks>; 142 ti,bit-shift = <2>; 143 reg = <0x02d8>; 144 }; 145 146 mcbsp4_fck: mcbsp4_fck { 147 #clock-cells = <0>; 148 compatible = "ti,composite-clock"; 149 clocks = <&mcbsp4_gate_fck>, <&mcbsp4_mux_fck>; 150 }; 151}; 152&cm_clocks { 153 dummy_apb_pclk: dummy_apb_pclk { 154 #clock-cells = <0>; 155 compatible = "fixed-clock"; 156 clock-frequency = <0x0>; 157 }; 158 159 omap_32k_fck: omap_32k_fck { 160 #clock-cells = <0>; 161 compatible = "fixed-clock"; 162 clock-frequency = <32768>; 163 }; 164 165 virt_12m_ck: virt_12m_ck { 166 #clock-cells = <0>; 167 compatible = "fixed-clock"; 168 clock-frequency = <12000000>; 169 }; 170 171 virt_13m_ck: virt_13m_ck { 172 #clock-cells = <0>; 173 compatible = "fixed-clock"; 174 clock-frequency = <13000000>; 175 }; 176 177 virt_19200000_ck: virt_19200000_ck { 178 #clock-cells = <0>; 179 compatible = "fixed-clock"; 180 clock-frequency = <19200000>; 181 }; 182 183 virt_26000000_ck: virt_26000000_ck { 184 #clock-cells = <0>; 185 compatible = "fixed-clock"; 186 clock-frequency = <26000000>; 187 }; 188 189 virt_38_4m_ck: virt_38_4m_ck { 190 #clock-cells = <0>; 191 compatible = "fixed-clock"; 192 clock-frequency = <38400000>; 193 }; 194 195 dpll4_ck: dpll4_ck { 196 #clock-cells = <0>; 197 compatible = "ti,omap3-dpll-per-clock"; 198 clocks = <&sys_ck>, <&sys_ck>; 199 reg = <0x0d00>, <0x0d20>, <0x0d44>, <0x0d30>; 200 }; 201 202 dpll4_m2_ck: dpll4_m2_ck { 203 #clock-cells = <0>; 204 compatible = "ti,divider-clock"; 205 clocks = <&dpll4_ck>; 206 ti,max-div = <63>; 207 reg = <0x0d48>; 208 ti,index-starts-at-one; 209 }; 210 211 dpll4_m2x2_mul_ck: dpll4_m2x2_mul_ck { 212 #clock-cells = <0>; 213 compatible = "fixed-factor-clock"; 214 clocks = <&dpll4_m2_ck>; 215 clock-mult = <2>; 216 clock-div = <1>; 217 }; 218 219 dpll4_m2x2_ck: dpll4_m2x2_ck { 220 #clock-cells = <0>; 221 compatible = "ti,gate-clock"; 222 clocks = <&dpll4_m2x2_mul_ck>; 223 ti,bit-shift = <0x1b>; 224 reg = <0x0d00>; 225 ti,set-bit-to-disable; 226 }; 227 228 omap_96m_alwon_fck: omap_96m_alwon_fck { 229 #clock-cells = <0>; 230 compatible = "fixed-factor-clock"; 231 clocks = <&dpll4_m2x2_ck>; 232 clock-mult = <1>; 233 clock-div = <1>; 234 }; 235 236 dpll3_ck: dpll3_ck { 237 #clock-cells = <0>; 238 compatible = "ti,omap3-dpll-core-clock"; 239 clocks = <&sys_ck>, <&sys_ck>; 240 reg = <0x0d00>, <0x0d20>, <0x0d40>, <0x0d30>; 241 }; 242 243 dpll3_m3_ck: dpll3_m3_ck { 244 #clock-cells = <0>; 245 compatible = "ti,divider-clock"; 246 clocks = <&dpll3_ck>; 247 ti,bit-shift = <16>; 248 ti,max-div = <31>; 249 reg = <0x1140>; 250 ti,index-starts-at-one; 251 }; 252 253 dpll3_m3x2_mul_ck: dpll3_m3x2_mul_ck { 254 #clock-cells = <0>; 255 compatible = "fixed-factor-clock"; 256 clocks = <&dpll3_m3_ck>; 257 clock-mult = <2>; 258 clock-div = <1>; 259 }; 260 261 dpll3_m3x2_ck: dpll3_m3x2_ck { 262 #clock-cells = <0>; 263 compatible = "ti,gate-clock"; 264 clocks = <&dpll3_m3x2_mul_ck>; 265 ti,bit-shift = <0xc>; 266 reg = <0x0d00>; 267 ti,set-bit-to-disable; 268 }; 269 270 emu_core_alwon_ck: emu_core_alwon_ck { 271 #clock-cells = <0>; 272 compatible = "fixed-factor-clock"; 273 clocks = <&dpll3_m3x2_ck>; 274 clock-mult = <1>; 275 clock-div = <1>; 276 }; 277 278 sys_altclk: sys_altclk { 279 #clock-cells = <0>; 280 compatible = "fixed-clock"; 281 clock-frequency = <0x0>; 282 }; 283 284 mcbsp_clks: mcbsp_clks { 285 #clock-cells = <0>; 286 compatible = "fixed-clock"; 287 clock-frequency = <0x0>; 288 }; 289 290 dpll3_m2_ck: dpll3_m2_ck { 291 #clock-cells = <0>; 292 compatible = "ti,divider-clock"; 293 clocks = <&dpll3_ck>; 294 ti,bit-shift = <27>; 295 ti,max-div = <31>; 296 reg = <0x0d40>; 297 ti,index-starts-at-one; 298 }; 299 300 core_ck: core_ck { 301 #clock-cells = <0>; 302 compatible = "fixed-factor-clock"; 303 clocks = <&dpll3_m2_ck>; 304 clock-mult = <1>; 305 clock-div = <1>; 306 }; 307 308 dpll1_fck: dpll1_fck { 309 #clock-cells = <0>; 310 compatible = "ti,divider-clock"; 311 clocks = <&core_ck>; 312 ti,bit-shift = <19>; 313 ti,max-div = <7>; 314 reg = <0x0940>; 315 ti,index-starts-at-one; 316 }; 317 318 dpll1_ck: dpll1_ck { 319 #clock-cells = <0>; 320 compatible = "ti,omap3-dpll-clock"; 321 clocks = <&sys_ck>, <&dpll1_fck>; 322 reg = <0x0904>, <0x0924>, <0x0940>, <0x0934>; 323 }; 324 325 dpll1_x2_ck: dpll1_x2_ck { 326 #clock-cells = <0>; 327 compatible = "fixed-factor-clock"; 328 clocks = <&dpll1_ck>; 329 clock-mult = <2>; 330 clock-div = <1>; 331 }; 332 333 dpll1_x2m2_ck: dpll1_x2m2_ck { 334 #clock-cells = <0>; 335 compatible = "ti,divider-clock"; 336 clocks = <&dpll1_x2_ck>; 337 ti,max-div = <31>; 338 reg = <0x0944>; 339 ti,index-starts-at-one; 340 }; 341 342 cm_96m_fck: cm_96m_fck { 343 #clock-cells = <0>; 344 compatible = "fixed-factor-clock"; 345 clocks = <&omap_96m_alwon_fck>; 346 clock-mult = <1>; 347 clock-div = <1>; 348 }; 349 350 omap_96m_fck: omap_96m_fck { 351 #clock-cells = <0>; 352 compatible = "ti,mux-clock"; 353 clocks = <&cm_96m_fck>, <&sys_ck>; 354 ti,bit-shift = <6>; 355 reg = <0x0d40>; 356 }; 357 358 dpll4_m3_ck: dpll4_m3_ck { 359 #clock-cells = <0>; 360 compatible = "ti,divider-clock"; 361 clocks = <&dpll4_ck>; 362 ti,bit-shift = <8>; 363 ti,max-div = <32>; 364 reg = <0x0e40>; 365 ti,index-starts-at-one; 366 }; 367 368 dpll4_m3x2_mul_ck: dpll4_m3x2_mul_ck { 369 #clock-cells = <0>; 370 compatible = "fixed-factor-clock"; 371 clocks = <&dpll4_m3_ck>; 372 clock-mult = <2>; 373 clock-div = <1>; 374 }; 375 376 dpll4_m3x2_ck: dpll4_m3x2_ck { 377 #clock-cells = <0>; 378 compatible = "ti,gate-clock"; 379 clocks = <&dpll4_m3x2_mul_ck>; 380 ti,bit-shift = <0x1c>; 381 reg = <0x0d00>; 382 ti,set-bit-to-disable; 383 }; 384 385 omap_54m_fck: omap_54m_fck { 386 #clock-cells = <0>; 387 compatible = "ti,mux-clock"; 388 clocks = <&dpll4_m3x2_ck>, <&sys_altclk>; 389 ti,bit-shift = <5>; 390 reg = <0x0d40>; 391 }; 392 393 cm_96m_d2_fck: cm_96m_d2_fck { 394 #clock-cells = <0>; 395 compatible = "fixed-factor-clock"; 396 clocks = <&cm_96m_fck>; 397 clock-mult = <1>; 398 clock-div = <2>; 399 }; 400 401 omap_48m_fck: omap_48m_fck { 402 #clock-cells = <0>; 403 compatible = "ti,mux-clock"; 404 clocks = <&cm_96m_d2_fck>, <&sys_altclk>; 405 ti,bit-shift = <3>; 406 reg = <0x0d40>; 407 }; 408 409 omap_12m_fck: omap_12m_fck { 410 #clock-cells = <0>; 411 compatible = "fixed-factor-clock"; 412 clocks = <&omap_48m_fck>; 413 clock-mult = <1>; 414 clock-div = <4>; 415 }; 416 417 dpll4_m4_ck: dpll4_m4_ck { 418 #clock-cells = <0>; 419 compatible = "ti,divider-clock"; 420 clocks = <&dpll4_ck>; 421 ti,max-div = <32>; 422 reg = <0x0e40>; 423 ti,index-starts-at-one; 424 }; 425 426 dpll4_m4x2_mul_ck: dpll4_m4x2_mul_ck { 427 #clock-cells = <0>; 428 compatible = "ti,fixed-factor-clock"; 429 clocks = <&dpll4_m4_ck>; 430 ti,clock-mult = <2>; 431 ti,clock-div = <1>; 432 ti,set-rate-parent; 433 }; 434 435 dpll4_m4x2_ck: dpll4_m4x2_ck { 436 #clock-cells = <0>; 437 compatible = "ti,gate-clock"; 438 clocks = <&dpll4_m4x2_mul_ck>; 439 ti,bit-shift = <0x1d>; 440 reg = <0x0d00>; 441 ti,set-bit-to-disable; 442 ti,set-rate-parent; 443 }; 444 445 dpll4_m5_ck: dpll4_m5_ck { 446 #clock-cells = <0>; 447 compatible = "ti,divider-clock"; 448 clocks = <&dpll4_ck>; 449 ti,max-div = <63>; 450 reg = <0x0f40>; 451 ti,index-starts-at-one; 452 }; 453 454 dpll4_m5x2_mul_ck: dpll4_m5x2_mul_ck { 455 #clock-cells = <0>; 456 compatible = "ti,fixed-factor-clock"; 457 clocks = <&dpll4_m5_ck>; 458 ti,clock-mult = <2>; 459 ti,clock-div = <1>; 460 ti,set-rate-parent; 461 }; 462 463 dpll4_m5x2_ck: dpll4_m5x2_ck { 464 #clock-cells = <0>; 465 compatible = "ti,gate-clock"; 466 clocks = <&dpll4_m5x2_mul_ck>; 467 ti,bit-shift = <0x1e>; 468 reg = <0x0d00>; 469 ti,set-bit-to-disable; 470 ti,set-rate-parent; 471 }; 472 473 dpll4_m6_ck: dpll4_m6_ck { 474 #clock-cells = <0>; 475 compatible = "ti,divider-clock"; 476 clocks = <&dpll4_ck>; 477 ti,bit-shift = <24>; 478 ti,max-div = <63>; 479 reg = <0x1140>; 480 ti,index-starts-at-one; 481 }; 482 483 dpll4_m6x2_mul_ck: dpll4_m6x2_mul_ck { 484 #clock-cells = <0>; 485 compatible = "fixed-factor-clock"; 486 clocks = <&dpll4_m6_ck>; 487 clock-mult = <2>; 488 clock-div = <1>; 489 }; 490 491 dpll4_m6x2_ck: dpll4_m6x2_ck { 492 #clock-cells = <0>; 493 compatible = "ti,gate-clock"; 494 clocks = <&dpll4_m6x2_mul_ck>; 495 ti,bit-shift = <0x1f>; 496 reg = <0x0d00>; 497 ti,set-bit-to-disable; 498 }; 499 500 emu_per_alwon_ck: emu_per_alwon_ck { 501 #clock-cells = <0>; 502 compatible = "fixed-factor-clock"; 503 clocks = <&dpll4_m6x2_ck>; 504 clock-mult = <1>; 505 clock-div = <1>; 506 }; 507 508 clkout2_src_gate_ck: clkout2_src_gate_ck { 509 #clock-cells = <0>; 510 compatible = "ti,composite-no-wait-gate-clock"; 511 clocks = <&core_ck>; 512 ti,bit-shift = <7>; 513 reg = <0x0d70>; 514 }; 515 516 clkout2_src_mux_ck: clkout2_src_mux_ck { 517 #clock-cells = <0>; 518 compatible = "ti,composite-mux-clock"; 519 clocks = <&core_ck>, <&sys_ck>, <&cm_96m_fck>, <&omap_54m_fck>; 520 reg = <0x0d70>; 521 }; 522 523 clkout2_src_ck: clkout2_src_ck { 524 #clock-cells = <0>; 525 compatible = "ti,composite-clock"; 526 clocks = <&clkout2_src_gate_ck>, <&clkout2_src_mux_ck>; 527 }; 528 529 sys_clkout2: sys_clkout2 { 530 #clock-cells = <0>; 531 compatible = "ti,divider-clock"; 532 clocks = <&clkout2_src_ck>; 533 ti,bit-shift = <3>; 534 ti,max-div = <64>; 535 reg = <0x0d70>; 536 ti,index-power-of-two; 537 }; 538 539 mpu_ck: mpu_ck { 540 #clock-cells = <0>; 541 compatible = "fixed-factor-clock"; 542 clocks = <&dpll1_x2m2_ck>; 543 clock-mult = <1>; 544 clock-div = <1>; 545 }; 546 547 arm_fck: arm_fck { 548 #clock-cells = <0>; 549 compatible = "ti,divider-clock"; 550 clocks = <&mpu_ck>; 551 reg = <0x0924>; 552 ti,max-div = <2>; 553 }; 554 555 emu_mpu_alwon_ck: emu_mpu_alwon_ck { 556 #clock-cells = <0>; 557 compatible = "fixed-factor-clock"; 558 clocks = <&mpu_ck>; 559 clock-mult = <1>; 560 clock-div = <1>; 561 }; 562 563 l3_ick: l3_ick { 564 #clock-cells = <0>; 565 compatible = "ti,divider-clock"; 566 clocks = <&core_ck>; 567 ti,max-div = <3>; 568 reg = <0x0a40>; 569 ti,index-starts-at-one; 570 }; 571 572 l4_ick: l4_ick { 573 #clock-cells = <0>; 574 compatible = "ti,divider-clock"; 575 clocks = <&l3_ick>; 576 ti,bit-shift = <2>; 577 ti,max-div = <3>; 578 reg = <0x0a40>; 579 ti,index-starts-at-one; 580 }; 581 582 rm_ick: rm_ick { 583 #clock-cells = <0>; 584 compatible = "ti,divider-clock"; 585 clocks = <&l4_ick>; 586 ti,bit-shift = <1>; 587 ti,max-div = <3>; 588 reg = <0x0c40>; 589 ti,index-starts-at-one; 590 }; 591 592 gpt10_gate_fck: gpt10_gate_fck { 593 #clock-cells = <0>; 594 compatible = "ti,composite-gate-clock"; 595 clocks = <&sys_ck>; 596 ti,bit-shift = <11>; 597 reg = <0x0a00>; 598 }; 599 600 gpt10_mux_fck: gpt10_mux_fck { 601 #clock-cells = <0>; 602 compatible = "ti,composite-mux-clock"; 603 clocks = <&omap_32k_fck>, <&sys_ck>; 604 ti,bit-shift = <6>; 605 reg = <0x0a40>; 606 }; 607 608 gpt10_fck: gpt10_fck { 609 #clock-cells = <0>; 610 compatible = "ti,composite-clock"; 611 clocks = <&gpt10_gate_fck>, <&gpt10_mux_fck>; 612 }; 613 614 gpt11_gate_fck: gpt11_gate_fck { 615 #clock-cells = <0>; 616 compatible = "ti,composite-gate-clock"; 617 clocks = <&sys_ck>; 618 ti,bit-shift = <12>; 619 reg = <0x0a00>; 620 }; 621 622 gpt11_mux_fck: gpt11_mux_fck { 623 #clock-cells = <0>; 624 compatible = "ti,composite-mux-clock"; 625 clocks = <&omap_32k_fck>, <&sys_ck>; 626 ti,bit-shift = <7>; 627 reg = <0x0a40>; 628 }; 629 630 gpt11_fck: gpt11_fck { 631 #clock-cells = <0>; 632 compatible = "ti,composite-clock"; 633 clocks = <&gpt11_gate_fck>, <&gpt11_mux_fck>; 634 }; 635 636 core_96m_fck: core_96m_fck { 637 #clock-cells = <0>; 638 compatible = "fixed-factor-clock"; 639 clocks = <&omap_96m_fck>; 640 clock-mult = <1>; 641 clock-div = <1>; 642 }; 643 644 mmchs2_fck: mmchs2_fck { 645 #clock-cells = <0>; 646 compatible = "ti,wait-gate-clock"; 647 clocks = <&core_96m_fck>; 648 reg = <0x0a00>; 649 ti,bit-shift = <25>; 650 }; 651 652 mmchs1_fck: mmchs1_fck { 653 #clock-cells = <0>; 654 compatible = "ti,wait-gate-clock"; 655 clocks = <&core_96m_fck>; 656 reg = <0x0a00>; 657 ti,bit-shift = <24>; 658 }; 659 660 i2c3_fck: i2c3_fck { 661 #clock-cells = <0>; 662 compatible = "ti,wait-gate-clock"; 663 clocks = <&core_96m_fck>; 664 reg = <0x0a00>; 665 ti,bit-shift = <17>; 666 }; 667 668 i2c2_fck: i2c2_fck { 669 #clock-cells = <0>; 670 compatible = "ti,wait-gate-clock"; 671 clocks = <&core_96m_fck>; 672 reg = <0x0a00>; 673 ti,bit-shift = <16>; 674 }; 675 676 i2c1_fck: i2c1_fck { 677 #clock-cells = <0>; 678 compatible = "ti,wait-gate-clock"; 679 clocks = <&core_96m_fck>; 680 reg = <0x0a00>; 681 ti,bit-shift = <15>; 682 }; 683 684 mcbsp5_gate_fck: mcbsp5_gate_fck { 685 #clock-cells = <0>; 686 compatible = "ti,composite-gate-clock"; 687 clocks = <&mcbsp_clks>; 688 ti,bit-shift = <10>; 689 reg = <0x0a00>; 690 }; 691 692 mcbsp1_gate_fck: mcbsp1_gate_fck { 693 #clock-cells = <0>; 694 compatible = "ti,composite-gate-clock"; 695 clocks = <&mcbsp_clks>; 696 ti,bit-shift = <9>; 697 reg = <0x0a00>; 698 }; 699 700 core_48m_fck: core_48m_fck { 701 #clock-cells = <0>; 702 compatible = "fixed-factor-clock"; 703 clocks = <&omap_48m_fck>; 704 clock-mult = <1>; 705 clock-div = <1>; 706 }; 707 708 mcspi4_fck: mcspi4_fck { 709 #clock-cells = <0>; 710 compatible = "ti,wait-gate-clock"; 711 clocks = <&core_48m_fck>; 712 reg = <0x0a00>; 713 ti,bit-shift = <21>; 714 }; 715 716 mcspi3_fck: mcspi3_fck { 717 #clock-cells = <0>; 718 compatible = "ti,wait-gate-clock"; 719 clocks = <&core_48m_fck>; 720 reg = <0x0a00>; 721 ti,bit-shift = <20>; 722 }; 723 724 mcspi2_fck: mcspi2_fck { 725 #clock-cells = <0>; 726 compatible = "ti,wait-gate-clock"; 727 clocks = <&core_48m_fck>; 728 reg = <0x0a00>; 729 ti,bit-shift = <19>; 730 }; 731 732 mcspi1_fck: mcspi1_fck { 733 #clock-cells = <0>; 734 compatible = "ti,wait-gate-clock"; 735 clocks = <&core_48m_fck>; 736 reg = <0x0a00>; 737 ti,bit-shift = <18>; 738 }; 739 740 uart2_fck: uart2_fck { 741 #clock-cells = <0>; 742 compatible = "ti,wait-gate-clock"; 743 clocks = <&core_48m_fck>; 744 reg = <0x0a00>; 745 ti,bit-shift = <14>; 746 }; 747 748 uart1_fck: uart1_fck { 749 #clock-cells = <0>; 750 compatible = "ti,wait-gate-clock"; 751 clocks = <&core_48m_fck>; 752 reg = <0x0a00>; 753 ti,bit-shift = <13>; 754 }; 755 756 core_12m_fck: core_12m_fck { 757 #clock-cells = <0>; 758 compatible = "fixed-factor-clock"; 759 clocks = <&omap_12m_fck>; 760 clock-mult = <1>; 761 clock-div = <1>; 762 }; 763 764 hdq_fck: hdq_fck { 765 #clock-cells = <0>; 766 compatible = "ti,wait-gate-clock"; 767 clocks = <&core_12m_fck>; 768 reg = <0x0a00>; 769 ti,bit-shift = <22>; 770 }; 771 772 core_l3_ick: core_l3_ick { 773 #clock-cells = <0>; 774 compatible = "fixed-factor-clock"; 775 clocks = <&l3_ick>; 776 clock-mult = <1>; 777 clock-div = <1>; 778 }; 779 780 sdrc_ick: sdrc_ick { 781 #clock-cells = <0>; 782 compatible = "ti,wait-gate-clock"; 783 clocks = <&core_l3_ick>; 784 reg = <0x0a10>; 785 ti,bit-shift = <1>; 786 }; 787 788 gpmc_fck: gpmc_fck { 789 #clock-cells = <0>; 790 compatible = "fixed-factor-clock"; 791 clocks = <&core_l3_ick>; 792 clock-mult = <1>; 793 clock-div = <1>; 794 }; 795 796 core_l4_ick: core_l4_ick { 797 #clock-cells = <0>; 798 compatible = "fixed-factor-clock"; 799 clocks = <&l4_ick>; 800 clock-mult = <1>; 801 clock-div = <1>; 802 }; 803 804 mmchs2_ick: mmchs2_ick { 805 #clock-cells = <0>; 806 compatible = "ti,omap3-interface-clock"; 807 clocks = <&core_l4_ick>; 808 reg = <0x0a10>; 809 ti,bit-shift = <25>; 810 }; 811 812 mmchs1_ick: mmchs1_ick { 813 #clock-cells = <0>; 814 compatible = "ti,omap3-interface-clock"; 815 clocks = <&core_l4_ick>; 816 reg = <0x0a10>; 817 ti,bit-shift = <24>; 818 }; 819 820 hdq_ick: hdq_ick { 821 #clock-cells = <0>; 822 compatible = "ti,omap3-interface-clock"; 823 clocks = <&core_l4_ick>; 824 reg = <0x0a10>; 825 ti,bit-shift = <22>; 826 }; 827 828 mcspi4_ick: mcspi4_ick { 829 #clock-cells = <0>; 830 compatible = "ti,omap3-interface-clock"; 831 clocks = <&core_l4_ick>; 832 reg = <0x0a10>; 833 ti,bit-shift = <21>; 834 }; 835 836 mcspi3_ick: mcspi3_ick { 837 #clock-cells = <0>; 838 compatible = "ti,omap3-interface-clock"; 839 clocks = <&core_l4_ick>; 840 reg = <0x0a10>; 841 ti,bit-shift = <20>; 842 }; 843 844 mcspi2_ick: mcspi2_ick { 845 #clock-cells = <0>; 846 compatible = "ti,omap3-interface-clock"; 847 clocks = <&core_l4_ick>; 848 reg = <0x0a10>; 849 ti,bit-shift = <19>; 850 }; 851 852 mcspi1_ick: mcspi1_ick { 853 #clock-cells = <0>; 854 compatible = "ti,omap3-interface-clock"; 855 clocks = <&core_l4_ick>; 856 reg = <0x0a10>; 857 ti,bit-shift = <18>; 858 }; 859 860 i2c3_ick: i2c3_ick { 861 #clock-cells = <0>; 862 compatible = "ti,omap3-interface-clock"; 863 clocks = <&core_l4_ick>; 864 reg = <0x0a10>; 865 ti,bit-shift = <17>; 866 }; 867 868 i2c2_ick: i2c2_ick { 869 #clock-cells = <0>; 870 compatible = "ti,omap3-interface-clock"; 871 clocks = <&core_l4_ick>; 872 reg = <0x0a10>; 873 ti,bit-shift = <16>; 874 }; 875 876 i2c1_ick: i2c1_ick { 877 #clock-cells = <0>; 878 compatible = "ti,omap3-interface-clock"; 879 clocks = <&core_l4_ick>; 880 reg = <0x0a10>; 881 ti,bit-shift = <15>; 882 }; 883 884 uart2_ick: uart2_ick { 885 #clock-cells = <0>; 886 compatible = "ti,omap3-interface-clock"; 887 clocks = <&core_l4_ick>; 888 reg = <0x0a10>; 889 ti,bit-shift = <14>; 890 }; 891 892 uart1_ick: uart1_ick { 893 #clock-cells = <0>; 894 compatible = "ti,omap3-interface-clock"; 895 clocks = <&core_l4_ick>; 896 reg = <0x0a10>; 897 ti,bit-shift = <13>; 898 }; 899 900 gpt11_ick: gpt11_ick { 901 #clock-cells = <0>; 902 compatible = "ti,omap3-interface-clock"; 903 clocks = <&core_l4_ick>; 904 reg = <0x0a10>; 905 ti,bit-shift = <12>; 906 }; 907 908 gpt10_ick: gpt10_ick { 909 #clock-cells = <0>; 910 compatible = "ti,omap3-interface-clock"; 911 clocks = <&core_l4_ick>; 912 reg = <0x0a10>; 913 ti,bit-shift = <11>; 914 }; 915 916 mcbsp5_ick: mcbsp5_ick { 917 #clock-cells = <0>; 918 compatible = "ti,omap3-interface-clock"; 919 clocks = <&core_l4_ick>; 920 reg = <0x0a10>; 921 ti,bit-shift = <10>; 922 }; 923 924 mcbsp1_ick: mcbsp1_ick { 925 #clock-cells = <0>; 926 compatible = "ti,omap3-interface-clock"; 927 clocks = <&core_l4_ick>; 928 reg = <0x0a10>; 929 ti,bit-shift = <9>; 930 }; 931 932 omapctrl_ick: omapctrl_ick { 933 #clock-cells = <0>; 934 compatible = "ti,omap3-interface-clock"; 935 clocks = <&core_l4_ick>; 936 reg = <0x0a10>; 937 ti,bit-shift = <6>; 938 }; 939 940 dss_tv_fck: dss_tv_fck { 941 #clock-cells = <0>; 942 compatible = "ti,gate-clock"; 943 clocks = <&omap_54m_fck>; 944 reg = <0x0e00>; 945 ti,bit-shift = <2>; 946 }; 947 948 dss_96m_fck: dss_96m_fck { 949 #clock-cells = <0>; 950 compatible = "ti,gate-clock"; 951 clocks = <&omap_96m_fck>; 952 reg = <0x0e00>; 953 ti,bit-shift = <2>; 954 }; 955 956 dss2_alwon_fck: dss2_alwon_fck { 957 #clock-cells = <0>; 958 compatible = "ti,gate-clock"; 959 clocks = <&sys_ck>; 960 reg = <0x0e00>; 961 ti,bit-shift = <1>; 962 }; 963 964 dummy_ck: dummy_ck { 965 #clock-cells = <0>; 966 compatible = "fixed-clock"; 967 clock-frequency = <0>; 968 }; 969 970 gpt1_gate_fck: gpt1_gate_fck { 971 #clock-cells = <0>; 972 compatible = "ti,composite-gate-clock"; 973 clocks = <&sys_ck>; 974 ti,bit-shift = <0>; 975 reg = <0x0c00>; 976 }; 977 978 gpt1_mux_fck: gpt1_mux_fck { 979 #clock-cells = <0>; 980 compatible = "ti,composite-mux-clock"; 981 clocks = <&omap_32k_fck>, <&sys_ck>; 982 reg = <0x0c40>; 983 }; 984 985 gpt1_fck: gpt1_fck { 986 #clock-cells = <0>; 987 compatible = "ti,composite-clock"; 988 clocks = <&gpt1_gate_fck>, <&gpt1_mux_fck>; 989 }; 990 991 aes2_ick: aes2_ick { 992 #clock-cells = <0>; 993 compatible = "ti,omap3-interface-clock"; 994 clocks = <&core_l4_ick>; 995 ti,bit-shift = <28>; 996 reg = <0x0a10>; 997 }; 998 999 wkup_32k_fck: wkup_32k_fck { 1000 #clock-cells = <0>; 1001 compatible = "fixed-factor-clock"; 1002 clocks = <&omap_32k_fck>; 1003 clock-mult = <1>; 1004 clock-div = <1>; 1005 }; 1006 1007 gpio1_dbck: gpio1_dbck { 1008 #clock-cells = <0>; 1009 compatible = "ti,gate-clock"; 1010 clocks = <&wkup_32k_fck>; 1011 reg = <0x0c00>; 1012 ti,bit-shift = <3>; 1013 }; 1014 1015 sha12_ick: sha12_ick { 1016 #clock-cells = <0>; 1017 compatible = "ti,omap3-interface-clock"; 1018 clocks = <&core_l4_ick>; 1019 reg = <0x0a10>; 1020 ti,bit-shift = <27>; 1021 }; 1022 1023 wdt2_fck: wdt2_fck { 1024 #clock-cells = <0>; 1025 compatible = "ti,wait-gate-clock"; 1026 clocks = <&wkup_32k_fck>; 1027 reg = <0x0c00>; 1028 ti,bit-shift = <5>; 1029 }; 1030 1031 wdt2_ick: wdt2_ick { 1032 #clock-cells = <0>; 1033 compatible = "ti,omap3-interface-clock"; 1034 clocks = <&wkup_l4_ick>; 1035 reg = <0x0c10>; 1036 ti,bit-shift = <5>; 1037 }; 1038 1039 wdt1_ick: wdt1_ick { 1040 #clock-cells = <0>; 1041 compatible = "ti,omap3-interface-clock"; 1042 clocks = <&wkup_l4_ick>; 1043 reg = <0x0c10>; 1044 ti,bit-shift = <4>; 1045 }; 1046 1047 gpio1_ick: gpio1_ick { 1048 #clock-cells = <0>; 1049 compatible = "ti,omap3-interface-clock"; 1050 clocks = <&wkup_l4_ick>; 1051 reg = <0x0c10>; 1052 ti,bit-shift = <3>; 1053 }; 1054 1055 omap_32ksync_ick: omap_32ksync_ick { 1056 #clock-cells = <0>; 1057 compatible = "ti,omap3-interface-clock"; 1058 clocks = <&wkup_l4_ick>; 1059 reg = <0x0c10>; 1060 ti,bit-shift = <2>; 1061 }; 1062 1063 gpt12_ick: gpt12_ick { 1064 #clock-cells = <0>; 1065 compatible = "ti,omap3-interface-clock"; 1066 clocks = <&wkup_l4_ick>; 1067 reg = <0x0c10>; 1068 ti,bit-shift = <1>; 1069 }; 1070 1071 gpt1_ick: gpt1_ick { 1072 #clock-cells = <0>; 1073 compatible = "ti,omap3-interface-clock"; 1074 clocks = <&wkup_l4_ick>; 1075 reg = <0x0c10>; 1076 ti,bit-shift = <0>; 1077 }; 1078 1079 per_96m_fck: per_96m_fck { 1080 #clock-cells = <0>; 1081 compatible = "fixed-factor-clock"; 1082 clocks = <&omap_96m_alwon_fck>; 1083 clock-mult = <1>; 1084 clock-div = <1>; 1085 }; 1086 1087 per_48m_fck: per_48m_fck { 1088 #clock-cells = <0>; 1089 compatible = "fixed-factor-clock"; 1090 clocks = <&omap_48m_fck>; 1091 clock-mult = <1>; 1092 clock-div = <1>; 1093 }; 1094 1095 uart3_fck: uart3_fck { 1096 #clock-cells = <0>; 1097 compatible = "ti,wait-gate-clock"; 1098 clocks = <&per_48m_fck>; 1099 reg = <0x1000>; 1100 ti,bit-shift = <11>; 1101 }; 1102 1103 gpt2_gate_fck: gpt2_gate_fck { 1104 #clock-cells = <0>; 1105 compatible = "ti,composite-gate-clock"; 1106 clocks = <&sys_ck>; 1107 ti,bit-shift = <3>; 1108 reg = <0x1000>; 1109 }; 1110 1111 gpt2_mux_fck: gpt2_mux_fck { 1112 #clock-cells = <0>; 1113 compatible = "ti,composite-mux-clock"; 1114 clocks = <&omap_32k_fck>, <&sys_ck>; 1115 reg = <0x1040>; 1116 }; 1117 1118 gpt2_fck: gpt2_fck { 1119 #clock-cells = <0>; 1120 compatible = "ti,composite-clock"; 1121 clocks = <&gpt2_gate_fck>, <&gpt2_mux_fck>; 1122 }; 1123 1124 gpt3_gate_fck: gpt3_gate_fck { 1125 #clock-cells = <0>; 1126 compatible = "ti,composite-gate-clock"; 1127 clocks = <&sys_ck>; 1128 ti,bit-shift = <4>; 1129 reg = <0x1000>; 1130 }; 1131 1132 gpt3_mux_fck: gpt3_mux_fck { 1133 #clock-cells = <0>; 1134 compatible = "ti,composite-mux-clock"; 1135 clocks = <&omap_32k_fck>, <&sys_ck>; 1136 ti,bit-shift = <1>; 1137 reg = <0x1040>; 1138 }; 1139 1140 gpt3_fck: gpt3_fck { 1141 #clock-cells = <0>; 1142 compatible = "ti,composite-clock"; 1143 clocks = <&gpt3_gate_fck>, <&gpt3_mux_fck>; 1144 }; 1145 1146 gpt4_gate_fck: gpt4_gate_fck { 1147 #clock-cells = <0>; 1148 compatible = "ti,composite-gate-clock"; 1149 clocks = <&sys_ck>; 1150 ti,bit-shift = <5>; 1151 reg = <0x1000>; 1152 }; 1153 1154 gpt4_mux_fck: gpt4_mux_fck { 1155 #clock-cells = <0>; 1156 compatible = "ti,composite-mux-clock"; 1157 clocks = <&omap_32k_fck>, <&sys_ck>; 1158 ti,bit-shift = <2>; 1159 reg = <0x1040>; 1160 }; 1161 1162 gpt4_fck: gpt4_fck { 1163 #clock-cells = <0>; 1164 compatible = "ti,composite-clock"; 1165 clocks = <&gpt4_gate_fck>, <&gpt4_mux_fck>; 1166 }; 1167 1168 gpt5_gate_fck: gpt5_gate_fck { 1169 #clock-cells = <0>; 1170 compatible = "ti,composite-gate-clock"; 1171 clocks = <&sys_ck>; 1172 ti,bit-shift = <6>; 1173 reg = <0x1000>; 1174 }; 1175 1176 gpt5_mux_fck: gpt5_mux_fck { 1177 #clock-cells = <0>; 1178 compatible = "ti,composite-mux-clock"; 1179 clocks = <&omap_32k_fck>, <&sys_ck>; 1180 ti,bit-shift = <3>; 1181 reg = <0x1040>; 1182 }; 1183 1184 gpt5_fck: gpt5_fck { 1185 #clock-cells = <0>; 1186 compatible = "ti,composite-clock"; 1187 clocks = <&gpt5_gate_fck>, <&gpt5_mux_fck>; 1188 }; 1189 1190 gpt6_gate_fck: gpt6_gate_fck { 1191 #clock-cells = <0>; 1192 compatible = "ti,composite-gate-clock"; 1193 clocks = <&sys_ck>; 1194 ti,bit-shift = <7>; 1195 reg = <0x1000>; 1196 }; 1197 1198 gpt6_mux_fck: gpt6_mux_fck { 1199 #clock-cells = <0>; 1200 compatible = "ti,composite-mux-clock"; 1201 clocks = <&omap_32k_fck>, <&sys_ck>; 1202 ti,bit-shift = <4>; 1203 reg = <0x1040>; 1204 }; 1205 1206 gpt6_fck: gpt6_fck { 1207 #clock-cells = <0>; 1208 compatible = "ti,composite-clock"; 1209 clocks = <&gpt6_gate_fck>, <&gpt6_mux_fck>; 1210 }; 1211 1212 gpt7_gate_fck: gpt7_gate_fck { 1213 #clock-cells = <0>; 1214 compatible = "ti,composite-gate-clock"; 1215 clocks = <&sys_ck>; 1216 ti,bit-shift = <8>; 1217 reg = <0x1000>; 1218 }; 1219 1220 gpt7_mux_fck: gpt7_mux_fck { 1221 #clock-cells = <0>; 1222 compatible = "ti,composite-mux-clock"; 1223 clocks = <&omap_32k_fck>, <&sys_ck>; 1224 ti,bit-shift = <5>; 1225 reg = <0x1040>; 1226 }; 1227 1228 gpt7_fck: gpt7_fck { 1229 #clock-cells = <0>; 1230 compatible = "ti,composite-clock"; 1231 clocks = <&gpt7_gate_fck>, <&gpt7_mux_fck>; 1232 }; 1233 1234 gpt8_gate_fck: gpt8_gate_fck { 1235 #clock-cells = <0>; 1236 compatible = "ti,composite-gate-clock"; 1237 clocks = <&sys_ck>; 1238 ti,bit-shift = <9>; 1239 reg = <0x1000>; 1240 }; 1241 1242 gpt8_mux_fck: gpt8_mux_fck { 1243 #clock-cells = <0>; 1244 compatible = "ti,composite-mux-clock"; 1245 clocks = <&omap_32k_fck>, <&sys_ck>; 1246 ti,bit-shift = <6>; 1247 reg = <0x1040>; 1248 }; 1249 1250 gpt8_fck: gpt8_fck { 1251 #clock-cells = <0>; 1252 compatible = "ti,composite-clock"; 1253 clocks = <&gpt8_gate_fck>, <&gpt8_mux_fck>; 1254 }; 1255 1256 gpt9_gate_fck: gpt9_gate_fck { 1257 #clock-cells = <0>; 1258 compatible = "ti,composite-gate-clock"; 1259 clocks = <&sys_ck>; 1260 ti,bit-shift = <10>; 1261 reg = <0x1000>; 1262 }; 1263 1264 gpt9_mux_fck: gpt9_mux_fck { 1265 #clock-cells = <0>; 1266 compatible = "ti,composite-mux-clock"; 1267 clocks = <&omap_32k_fck>, <&sys_ck>; 1268 ti,bit-shift = <7>; 1269 reg = <0x1040>; 1270 }; 1271 1272 gpt9_fck: gpt9_fck { 1273 #clock-cells = <0>; 1274 compatible = "ti,composite-clock"; 1275 clocks = <&gpt9_gate_fck>, <&gpt9_mux_fck>; 1276 }; 1277 1278 per_32k_alwon_fck: per_32k_alwon_fck { 1279 #clock-cells = <0>; 1280 compatible = "fixed-factor-clock"; 1281 clocks = <&omap_32k_fck>; 1282 clock-mult = <1>; 1283 clock-div = <1>; 1284 }; 1285 1286 gpio6_dbck: gpio6_dbck { 1287 #clock-cells = <0>; 1288 compatible = "ti,gate-clock"; 1289 clocks = <&per_32k_alwon_fck>; 1290 reg = <0x1000>; 1291 ti,bit-shift = <17>; 1292 }; 1293 1294 gpio5_dbck: gpio5_dbck { 1295 #clock-cells = <0>; 1296 compatible = "ti,gate-clock"; 1297 clocks = <&per_32k_alwon_fck>; 1298 reg = <0x1000>; 1299 ti,bit-shift = <16>; 1300 }; 1301 1302 gpio4_dbck: gpio4_dbck { 1303 #clock-cells = <0>; 1304 compatible = "ti,gate-clock"; 1305 clocks = <&per_32k_alwon_fck>; 1306 reg = <0x1000>; 1307 ti,bit-shift = <15>; 1308 }; 1309 1310 gpio3_dbck: gpio3_dbck { 1311 #clock-cells = <0>; 1312 compatible = "ti,gate-clock"; 1313 clocks = <&per_32k_alwon_fck>; 1314 reg = <0x1000>; 1315 ti,bit-shift = <14>; 1316 }; 1317 1318 gpio2_dbck: gpio2_dbck { 1319 #clock-cells = <0>; 1320 compatible = "ti,gate-clock"; 1321 clocks = <&per_32k_alwon_fck>; 1322 reg = <0x1000>; 1323 ti,bit-shift = <13>; 1324 }; 1325 1326 wdt3_fck: wdt3_fck { 1327 #clock-cells = <0>; 1328 compatible = "ti,wait-gate-clock"; 1329 clocks = <&per_32k_alwon_fck>; 1330 reg = <0x1000>; 1331 ti,bit-shift = <12>; 1332 }; 1333 1334 per_l4_ick: per_l4_ick { 1335 #clock-cells = <0>; 1336 compatible = "fixed-factor-clock"; 1337 clocks = <&l4_ick>; 1338 clock-mult = <1>; 1339 clock-div = <1>; 1340 }; 1341 1342 gpio6_ick: gpio6_ick { 1343 #clock-cells = <0>; 1344 compatible = "ti,omap3-interface-clock"; 1345 clocks = <&per_l4_ick>; 1346 reg = <0x1010>; 1347 ti,bit-shift = <17>; 1348 }; 1349 1350 gpio5_ick: gpio5_ick { 1351 #clock-cells = <0>; 1352 compatible = "ti,omap3-interface-clock"; 1353 clocks = <&per_l4_ick>; 1354 reg = <0x1010>; 1355 ti,bit-shift = <16>; 1356 }; 1357 1358 gpio4_ick: gpio4_ick { 1359 #clock-cells = <0>; 1360 compatible = "ti,omap3-interface-clock"; 1361 clocks = <&per_l4_ick>; 1362 reg = <0x1010>; 1363 ti,bit-shift = <15>; 1364 }; 1365 1366 gpio3_ick: gpio3_ick { 1367 #clock-cells = <0>; 1368 compatible = "ti,omap3-interface-clock"; 1369 clocks = <&per_l4_ick>; 1370 reg = <0x1010>; 1371 ti,bit-shift = <14>; 1372 }; 1373 1374 gpio2_ick: gpio2_ick { 1375 #clock-cells = <0>; 1376 compatible = "ti,omap3-interface-clock"; 1377 clocks = <&per_l4_ick>; 1378 reg = <0x1010>; 1379 ti,bit-shift = <13>; 1380 }; 1381 1382 wdt3_ick: wdt3_ick { 1383 #clock-cells = <0>; 1384 compatible = "ti,omap3-interface-clock"; 1385 clocks = <&per_l4_ick>; 1386 reg = <0x1010>; 1387 ti,bit-shift = <12>; 1388 }; 1389 1390 uart3_ick: uart3_ick { 1391 #clock-cells = <0>; 1392 compatible = "ti,omap3-interface-clock"; 1393 clocks = <&per_l4_ick>; 1394 reg = <0x1010>; 1395 ti,bit-shift = <11>; 1396 }; 1397 1398 uart4_ick: uart4_ick { 1399 #clock-cells = <0>; 1400 compatible = "ti,omap3-interface-clock"; 1401 clocks = <&per_l4_ick>; 1402 reg = <0x1010>; 1403 ti,bit-shift = <18>; 1404 }; 1405 1406 gpt9_ick: gpt9_ick { 1407 #clock-cells = <0>; 1408 compatible = "ti,omap3-interface-clock"; 1409 clocks = <&per_l4_ick>; 1410 reg = <0x1010>; 1411 ti,bit-shift = <10>; 1412 }; 1413 1414 gpt8_ick: gpt8_ick { 1415 #clock-cells = <0>; 1416 compatible = "ti,omap3-interface-clock"; 1417 clocks = <&per_l4_ick>; 1418 reg = <0x1010>; 1419 ti,bit-shift = <9>; 1420 }; 1421 1422 gpt7_ick: gpt7_ick { 1423 #clock-cells = <0>; 1424 compatible = "ti,omap3-interface-clock"; 1425 clocks = <&per_l4_ick>; 1426 reg = <0x1010>; 1427 ti,bit-shift = <8>; 1428 }; 1429 1430 gpt6_ick: gpt6_ick { 1431 #clock-cells = <0>; 1432 compatible = "ti,omap3-interface-clock"; 1433 clocks = <&per_l4_ick>; 1434 reg = <0x1010>; 1435 ti,bit-shift = <7>; 1436 }; 1437 1438 gpt5_ick: gpt5_ick { 1439 #clock-cells = <0>; 1440 compatible = "ti,omap3-interface-clock"; 1441 clocks = <&per_l4_ick>; 1442 reg = <0x1010>; 1443 ti,bit-shift = <6>; 1444 }; 1445 1446 gpt4_ick: gpt4_ick { 1447 #clock-cells = <0>; 1448 compatible = "ti,omap3-interface-clock"; 1449 clocks = <&per_l4_ick>; 1450 reg = <0x1010>; 1451 ti,bit-shift = <5>; 1452 }; 1453 1454 gpt3_ick: gpt3_ick { 1455 #clock-cells = <0>; 1456 compatible = "ti,omap3-interface-clock"; 1457 clocks = <&per_l4_ick>; 1458 reg = <0x1010>; 1459 ti,bit-shift = <4>; 1460 }; 1461 1462 gpt2_ick: gpt2_ick { 1463 #clock-cells = <0>; 1464 compatible = "ti,omap3-interface-clock"; 1465 clocks = <&per_l4_ick>; 1466 reg = <0x1010>; 1467 ti,bit-shift = <3>; 1468 }; 1469 1470 mcbsp2_ick: mcbsp2_ick { 1471 #clock-cells = <0>; 1472 compatible = "ti,omap3-interface-clock"; 1473 clocks = <&per_l4_ick>; 1474 reg = <0x1010>; 1475 ti,bit-shift = <0>; 1476 }; 1477 1478 mcbsp3_ick: mcbsp3_ick { 1479 #clock-cells = <0>; 1480 compatible = "ti,omap3-interface-clock"; 1481 clocks = <&per_l4_ick>; 1482 reg = <0x1010>; 1483 ti,bit-shift = <1>; 1484 }; 1485 1486 mcbsp4_ick: mcbsp4_ick { 1487 #clock-cells = <0>; 1488 compatible = "ti,omap3-interface-clock"; 1489 clocks = <&per_l4_ick>; 1490 reg = <0x1010>; 1491 ti,bit-shift = <2>; 1492 }; 1493 1494 mcbsp2_gate_fck: mcbsp2_gate_fck { 1495 #clock-cells = <0>; 1496 compatible = "ti,composite-gate-clock"; 1497 clocks = <&mcbsp_clks>; 1498 ti,bit-shift = <0>; 1499 reg = <0x1000>; 1500 }; 1501 1502 mcbsp3_gate_fck: mcbsp3_gate_fck { 1503 #clock-cells = <0>; 1504 compatible = "ti,composite-gate-clock"; 1505 clocks = <&mcbsp_clks>; 1506 ti,bit-shift = <1>; 1507 reg = <0x1000>; 1508 }; 1509 1510 mcbsp4_gate_fck: mcbsp4_gate_fck { 1511 #clock-cells = <0>; 1512 compatible = "ti,composite-gate-clock"; 1513 clocks = <&mcbsp_clks>; 1514 ti,bit-shift = <2>; 1515 reg = <0x1000>; 1516 }; 1517 1518 emu_src_mux_ck: emu_src_mux_ck { 1519 #clock-cells = <0>; 1520 compatible = "ti,mux-clock"; 1521 clocks = <&sys_ck>, <&emu_core_alwon_ck>, <&emu_per_alwon_ck>, <&emu_mpu_alwon_ck>; 1522 reg = <0x1140>; 1523 }; 1524 1525 emu_src_ck: emu_src_ck { 1526 #clock-cells = <0>; 1527 compatible = "ti,clkdm-gate-clock"; 1528 clocks = <&emu_src_mux_ck>; 1529 }; 1530 1531 pclk_fck: pclk_fck { 1532 #clock-cells = <0>; 1533 compatible = "ti,divider-clock"; 1534 clocks = <&emu_src_ck>; 1535 ti,bit-shift = <8>; 1536 ti,max-div = <7>; 1537 reg = <0x1140>; 1538 ti,index-starts-at-one; 1539 }; 1540 1541 pclkx2_fck: pclkx2_fck { 1542 #clock-cells = <0>; 1543 compatible = "ti,divider-clock"; 1544 clocks = <&emu_src_ck>; 1545 ti,bit-shift = <6>; 1546 ti,max-div = <3>; 1547 reg = <0x1140>; 1548 ti,index-starts-at-one; 1549 }; 1550 1551 atclk_fck: atclk_fck { 1552 #clock-cells = <0>; 1553 compatible = "ti,divider-clock"; 1554 clocks = <&emu_src_ck>; 1555 ti,bit-shift = <4>; 1556 ti,max-div = <3>; 1557 reg = <0x1140>; 1558 ti,index-starts-at-one; 1559 }; 1560 1561 traceclk_src_fck: traceclk_src_fck { 1562 #clock-cells = <0>; 1563 compatible = "ti,mux-clock"; 1564 clocks = <&sys_ck>, <&emu_core_alwon_ck>, <&emu_per_alwon_ck>, <&emu_mpu_alwon_ck>; 1565 ti,bit-shift = <2>; 1566 reg = <0x1140>; 1567 }; 1568 1569 traceclk_fck: traceclk_fck { 1570 #clock-cells = <0>; 1571 compatible = "ti,divider-clock"; 1572 clocks = <&traceclk_src_fck>; 1573 ti,bit-shift = <11>; 1574 ti,max-div = <7>; 1575 reg = <0x1140>; 1576 ti,index-starts-at-one; 1577 }; 1578 1579 secure_32k_fck: secure_32k_fck { 1580 #clock-cells = <0>; 1581 compatible = "fixed-clock"; 1582 clock-frequency = <32768>; 1583 }; 1584 1585 gpt12_fck: gpt12_fck { 1586 #clock-cells = <0>; 1587 compatible = "fixed-factor-clock"; 1588 clocks = <&secure_32k_fck>; 1589 clock-mult = <1>; 1590 clock-div = <1>; 1591 }; 1592 1593 wdt1_fck: wdt1_fck { 1594 #clock-cells = <0>; 1595 compatible = "fixed-factor-clock"; 1596 clocks = <&secure_32k_fck>; 1597 clock-mult = <1>; 1598 clock-div = <1>; 1599 }; 1600}; 1601 1602&cm_clockdomains { 1603 core_l3_clkdm: core_l3_clkdm { 1604 compatible = "ti,clockdomain"; 1605 clocks = <&sdrc_ick>; 1606 }; 1607 1608 dpll3_clkdm: dpll3_clkdm { 1609 compatible = "ti,clockdomain"; 1610 clocks = <&dpll3_ck>; 1611 }; 1612 1613 dpll1_clkdm: dpll1_clkdm { 1614 compatible = "ti,clockdomain"; 1615 clocks = <&dpll1_ck>; 1616 }; 1617 1618 per_clkdm: per_clkdm { 1619 compatible = "ti,clockdomain"; 1620 clocks = <&uart3_fck>, <&gpio6_dbck>, <&gpio5_dbck>, 1621 <&gpio4_dbck>, <&gpio3_dbck>, <&gpio2_dbck>, 1622 <&wdt3_fck>, <&gpio6_ick>, <&gpio5_ick>, <&gpio4_ick>, 1623 <&gpio3_ick>, <&gpio2_ick>, <&wdt3_ick>, <&uart3_ick>, 1624 <&uart4_ick>, <&gpt9_ick>, <&gpt8_ick>, <&gpt7_ick>, 1625 <&gpt6_ick>, <&gpt5_ick>, <&gpt4_ick>, <&gpt3_ick>, 1626 <&gpt2_ick>, <&mcbsp2_ick>, <&mcbsp3_ick>, 1627 <&mcbsp4_ick>; 1628 }; 1629 1630 emu_clkdm: emu_clkdm { 1631 compatible = "ti,clockdomain"; 1632 clocks = <&emu_src_ck>; 1633 }; 1634 1635 dpll4_clkdm: dpll4_clkdm { 1636 compatible = "ti,clockdomain"; 1637 clocks = <&dpll4_ck>; 1638 }; 1639 1640 wkup_clkdm: wkup_clkdm { 1641 compatible = "ti,clockdomain"; 1642 clocks = <&gpio1_dbck>, <&wdt2_fck>, <&wdt2_ick>, <&wdt1_ick>, 1643 <&gpio1_ick>, <&omap_32ksync_ick>, <&gpt12_ick>, 1644 <&gpt1_ick>; 1645 }; 1646 1647 dss_clkdm: dss_clkdm { 1648 compatible = "ti,clockdomain"; 1649 clocks = <&dss_tv_fck>, <&dss_96m_fck>, <&dss2_alwon_fck>; 1650 }; 1651 1652 core_l4_clkdm: core_l4_clkdm { 1653 compatible = "ti,clockdomain"; 1654 clocks = <&mmchs2_fck>, <&mmchs1_fck>, <&i2c3_fck>, <&i2c2_fck>, 1655 <&i2c1_fck>, <&mcspi4_fck>, <&mcspi3_fck>, 1656 <&mcspi2_fck>, <&mcspi1_fck>, <&uart2_fck>, 1657 <&uart1_fck>, <&hdq_fck>, <&mmchs2_ick>, <&mmchs1_ick>, 1658 <&hdq_ick>, <&mcspi4_ick>, <&mcspi3_ick>, 1659 <&mcspi2_ick>, <&mcspi1_ick>, <&i2c3_ick>, <&i2c2_ick>, 1660 <&i2c1_ick>, <&uart2_ick>, <&uart1_ick>, <&gpt11_ick>, 1661 <&gpt10_ick>, <&mcbsp5_ick>, <&mcbsp1_ick>, 1662 <&omapctrl_ick>, <&aes2_ick>, <&sha12_ick>; 1663 }; 1664}; 1665