ls1021a-qds.dts revision 284090 
1/*
2 * Copyright 2013-2014 Freescale Semiconductor, Inc.
3 *
4 * This file is dual-licensed: you can use it either under the terms
5 * of the GPL or the X11 license, at your option. Note that this dual
6 * licensing only applies to this file, and not this project as a
7 * whole.
8 *
9 *  a) This file is free software; you can redistribute it and/or
10 *     modify it under the terms of the GNU General Public License as
11 *     published by the Free Software Foundation; either version 2 of
12 *     the License, or (at your option) any later version.
13 *
14 *     This file is distributed in the hope that it will be useful,
15 *     but WITHOUT ANY WARRANTY; without even the implied warranty of
16 *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
17 *     GNU General Public License for more details.
18 *
19 *     You should have received a copy of the GNU General Public
20 *     License along with this file; if not, write to the Free
21 *     Software Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
22 *     MA 02110-1301 USA
23 *
24 * Or, alternatively,
25 *
26 *  b) Permission is hereby granted, free of charge, to any person
27 *     obtaining a copy of this software and associated documentation
28 *     files (the "Software"), to deal in the Software without
29 *     restriction, including without limitation the rights to use,
30 *     copy, modify, merge, publish, distribute, sublicense, and/or
31 *     sell copies of the Software, and to permit persons to whom the
32 *     Software is furnished to do so, subject to the following
33 *     conditions:
34 *
35 *     The above copyright notice and this permission notice shall be
36 *     included in all copies or substantial portions of the Software.
37 *
38 *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
39 *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
40 *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
41 *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
42 *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
43 *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
44 *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
45 *     OTHER DEALINGS IN THE SOFTWARE.
46 */
47
48/dts-v1/;
49#include "ls1021a.dtsi"
50
51/ {
52	model = "LS1021A QDS Board";
53
54	aliases {
55		enet0_rgmii_phy = &rgmii_phy1;
56		enet1_rgmii_phy = &rgmii_phy2;
57		enet2_rgmii_phy = &rgmii_phy3;
58		enet0_sgmii_phy = &sgmii_phy1c;
59		enet1_sgmii_phy = &sgmii_phy1d;
60	};
61};
62
63&dspi0 {
64	bus-num = <0>;
65	status = "okay";
66
67	dspiflash: at45db021d@0 {
68		#address-cells = <1>;
69		#size-cells = <1>;
70		compatible = "atmel,at45db021d", "atmel,at45", "atmel,dataflash";
71		spi-max-frequency = <16000000>;
72		spi-cpol;
73		spi-cpha;
74		reg = <0>;
75	};
76};
77
78&i2c0 {
79	status = "okay";
80
81	pca9547: mux@77 {
82		reg = <0x77>;
83		#address-cells = <1>;
84		#size-cells = <0>;
85
86		i2c@0 {
87			#address-cells = <1>;
88			#size-cells = <0>;
89			reg = <0x0>;
90
91			ds3232: rtc@68 {
92				compatible = "dallas,ds3232";
93				reg = <0x68>;
94				interrupts = <GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>;
95			};
96		};
97
98		i2c@2 {
99			#address-cells = <1>;
100			#size-cells = <0>;
101			reg = <0x2>;
102
103			ina220@40 {
104				compatible = "ti,ina220";
105				reg = <0x40>;
106				shunt-resistor = <1000>;
107			};
108
109			ina220@41 {
110				compatible = "ti,ina220";
111				reg = <0x41>;
112				shunt-resistor = <1000>;
113			};
114		};
115
116		i2c@3 {
117			#address-cells = <1>;
118			#size-cells = <0>;
119			reg = <0x3>;
120
121			eeprom@56 {
122				compatible = "atmel,24c512";
123				reg = <0x56>;
124			};
125
126			eeprom@57 {
127				compatible = "atmel,24c512";
128				reg = <0x57>;
129			};
130
131			adt7461a@4c {
132				compatible = "adi,adt7461a";
133				reg = <0x4c>;
134			};
135		};
136	};
137};
138
139&ifc {
140	#address-cells = <2>;
141	#size-cells = <1>;
142	/* NOR, NAND Flashes and FPGA on board */
143	ranges = <0x0 0x0 0x0 0x60000000 0x08000000
144		  0x2 0x0 0x0 0x7e800000 0x00010000
145		  0x3 0x0 0x0 0x7fb00000 0x00000100>;
146	status = "okay";
147
148	nor@0,0 {
149		#address-cells = <1>;
150		#size-cells = <1>;
151		compatible = "cfi-flash";
152		reg = <0x0 0x0 0x8000000>;
153		bank-width = <2>;
154		device-width = <1>;
155	};
156
157	fpga: board-control@3,0 {
158		#address-cells = <1>;
159		#size-cells = <1>;
160		compatible = "simple-bus";
161		reg = <0x3 0x0 0x0000100>;
162		bank-width = <1>;
163		device-width = <1>;
164		ranges = <0 3 0 0x100>;
165
166		mdio-mux-emi1 {
167			compatible = "mdio-mux-mmioreg";
168			mdio-parent-bus = <&mdio0>;
169			#address-cells = <1>;
170			#size-cells = <0>;
171			reg = <0x54 1>; /* BRDCFG4 */
172			mux-mask = <0xe0>; /* EMI1[2:0] */
173
174			/* Onboard PHYs */
175			ls1021amdio0: mdio@0 {
176				reg = <0>;
177				#address-cells = <1>;
178				#size-cells = <0>;
179				rgmii_phy1: ethernet-phy@1 {
180					reg = <0x1>;
181				};
182			};
183
184			ls1021amdio1: mdio@20 {
185				reg = <0x20>;
186				#address-cells = <1>;
187				#size-cells = <0>;
188				rgmii_phy2: ethernet-phy@2 {
189					reg = <0x2>;
190				};
191			};
192
193			ls1021amdio2: mdio@40 {
194				reg = <0x40>;
195				#address-cells = <1>;
196				#size-cells = <0>;
197				rgmii_phy3: ethernet-phy@3 {
198					reg = <0x3>;
199				};
200			};
201
202			ls1021amdio3: mdio@60 {
203				reg = <0x60>;
204				#address-cells = <1>;
205				#size-cells = <0>;
206				sgmii_phy1c: ethernet-phy@1c {
207					reg = <0x1c>;
208				};
209			};
210
211			ls1021amdio4: mdio@80 {
212				reg = <0x80>;
213				#address-cells = <1>;
214				#size-cells = <0>;
215				sgmii_phy1d: ethernet-phy@1d {
216					reg = <0x1d>;
217				};
218			};
219		};
220	};
221};
222
223&lpuart0 {
224	status = "okay";
225};
226
227&mdio0 {
228	tbi0: tbi-phy@8 {
229		reg = <0x8>;
230		device_type = "tbi-phy";
231	};
232};
233
234&uart0 {
235	status = "okay";
236};
237
238&uart1 {
239	status = "okay";
240};
241