imx31.dtsi revision 284090 
1/*
2 * Copyright 2012 Denis 'GNUtoo' Carikli <GNUtoo@no-log.org>
3 *
4 * The code contained herein is licensed under the GNU General Public
5 * License. You may obtain a copy of the GNU General Public License
6 * Version 2 or later at the following locations:
7 *
8 * http://www.opensource.org/licenses/gpl-license.html
9 * http://www.gnu.org/copyleft/gpl.html
10 */
11
12#include "skeleton.dtsi"
13
14/ {
15	aliases {
16		serial0 = &uart1;
17		serial1 = &uart2;
18		serial2 = &uart3;
19		serial3 = &uart4;
20		serial4 = &uart5;
21	};
22
23	cpus {
24		#address-cells = <0>;
25		#size-cells = <0>;
26
27		cpu {
28			compatible = "arm,arm1136";
29			device_type = "cpu";
30		};
31	};
32
33	avic: avic-interrupt-controller@60000000 {
34		compatible = "fsl,imx31-avic", "fsl,avic";
35		interrupt-controller;
36		#interrupt-cells = <1>;
37		reg = <0x60000000 0x100000>;
38	};
39
40	soc {
41		#address-cells = <1>;
42		#size-cells = <1>;
43		compatible = "simple-bus";
44		interrupt-parent = <&avic>;
45		ranges;
46
47		aips@43f00000 { /* AIPS1 */
48			compatible = "fsl,aips-bus", "simple-bus";
49			#address-cells = <1>;
50			#size-cells = <1>;
51			reg = <0x43f00000 0x100000>;
52			ranges;
53
54			uart1: serial@43f90000 {
55				compatible = "fsl,imx31-uart", "fsl,imx21-uart";
56				reg = <0x43f90000 0x4000>;
57				interrupts = <45>;
58				clocks = <&clks 10>, <&clks 30>;
59				clock-names = "ipg", "per";
60				status = "disabled";
61			};
62
63			uart2: serial@43f94000 {
64				compatible = "fsl,imx31-uart", "fsl,imx21-uart";
65				reg = <0x43f94000 0x4000>;
66				interrupts = <32>;
67				clocks = <&clks 10>, <&clks 31>;
68				clock-names = "ipg", "per";
69				status = "disabled";
70			};
71
72			uart4: serial@43fb0000 {
73				compatible = "fsl,imx31-uart", "fsl,imx21-uart";
74				reg = <0x43fb0000 0x4000>;
75				clocks = <&clks 10>, <&clks 49>;
76				clock-names = "ipg", "per";
77				interrupts = <46>;
78				status = "disabled";
79			};
80
81			uart5: serial@43fb4000 {
82				compatible = "fsl,imx31-uart", "fsl,imx21-uart";
83				reg = <0x43fb4000 0x4000>;
84				interrupts = <47>;
85				clocks = <&clks 10>, <&clks 50>;
86				clock-names = "ipg", "per";
87				status = "disabled";
88			};
89		};
90
91		spba@50000000 {
92			compatible = "fsl,spba-bus", "simple-bus";
93			#address-cells = <1>;
94			#size-cells = <1>;
95			reg = <0x50000000 0x100000>;
96			ranges;
97
98			uart3: serial@5000c000 {
99				compatible = "fsl,imx31-uart", "fsl,imx21-uart";
100				reg = <0x5000c000 0x4000>;
101				interrupts = <18>;
102				clocks = <&clks 10>, <&clks 48>;
103				clock-names = "ipg", "per";
104				status = "disabled";
105			};
106
107			iim: iim@5001c000 {
108				compatible = "fsl,imx31-iim", "fsl,imx27-iim";
109				reg = <0x5001c000 0x1000>;
110				interrupts = <19>;
111				clocks = <&clks 25>;
112			};
113
114			clks: ccm@53f80000{
115				compatible = "fsl,imx31-ccm";
116				reg = <0x53f80000 0x4000>;
117				interrupts = <0 31 0x04 0 53 0x04>;
118				#clock-cells = <1>;
119			};
120		};
121
122		aips@53f00000 { /* AIPS2 */
123			compatible = "fsl,aips-bus", "simple-bus";
124			#address-cells = <1>;
125			#size-cells = <1>;
126			reg = <0x53f00000 0x100000>;
127			ranges;
128
129			gpt: timer@53f90000 {
130				compatible = "fsl,imx31-gpt";
131				reg = <0x53f90000 0x4000>;
132				interrupts = <29>;
133				clocks = <&clks 10>, <&clks 22>;
134				clock-names = "ipg", "per";
135			};
136		};
137	};
138};
139