dra72-evm.dts revision 284090
1/* 2 * Copyright (C) 2014 Texas Instruments Incorporated - http://www.ti.com/ 3 * 4 * This program is free software; you can redistribute it and/or modify 5 * it under the terms of the GNU General Public License version 2 as 6 * published by the Free Software Foundation. 7 */ 8/dts-v1/; 9 10#include "dra72x.dtsi" 11#include <dt-bindings/gpio/gpio.h> 12 13/ { 14 model = "TI DRA722"; 15 compatible = "ti,dra72-evm", "ti,dra722", "ti,dra72", "ti,dra7"; 16 17 memory { 18 device_type = "memory"; 19 reg = <0x80000000 0x40000000>; /* 1024 MB */ 20 }; 21 22 evm_3v3: fixedregulator-evm_3v3 { 23 compatible = "regulator-fixed"; 24 regulator-name = "evm_3v3"; 25 regulator-min-microvolt = <3300000>; 26 regulator-max-microvolt = <3300000>; 27 }; 28 29 extcon_usb1: extcon_usb1 { 30 compatible = "linux,extcon-usb-gpio"; 31 id-gpio = <&pcf_gpio_21 1 GPIO_ACTIVE_HIGH>; 32 }; 33 34 extcon_usb2: extcon_usb2 { 35 compatible = "linux,extcon-usb-gpio"; 36 id-gpio = <&pcf_gpio_21 2 GPIO_ACTIVE_HIGH>; 37 }; 38}; 39 40&dra7_pmx_core { 41 i2c1_pins: pinmux_i2c1_pins { 42 pinctrl-single,pins = < 43 0x400 (PIN_INPUT | MUX_MODE0) /* i2c1_sda.i2c1_sda */ 44 0x404 (PIN_INPUT | MUX_MODE0) /* i2c1_scl.i2c1_scl */ 45 >; 46 }; 47 48 nand_default: nand_default { 49 pinctrl-single,pins = < 50 0x0 (PIN_INPUT | MUX_MODE0) /* gpmc_ad0 */ 51 0x4 (PIN_INPUT | MUX_MODE0) /* gpmc_ad1 */ 52 0x8 (PIN_INPUT | MUX_MODE0) /* gpmc_ad2 */ 53 0xc (PIN_INPUT | MUX_MODE0) /* gpmc_ad3 */ 54 0x10 (PIN_INPUT | MUX_MODE0) /* gpmc_ad4 */ 55 0x14 (PIN_INPUT | MUX_MODE0) /* gpmc_ad5 */ 56 0x18 (PIN_INPUT | MUX_MODE0) /* gpmc_ad6 */ 57 0x1c (PIN_INPUT | MUX_MODE0) /* gpmc_ad7 */ 58 0x20 (PIN_INPUT | MUX_MODE0) /* gpmc_ad8 */ 59 0x24 (PIN_INPUT | MUX_MODE0) /* gpmc_ad9 */ 60 0x28 (PIN_INPUT | MUX_MODE0) /* gpmc_ad10 */ 61 0x2c (PIN_INPUT | MUX_MODE0) /* gpmc_ad11 */ 62 0x30 (PIN_INPUT | MUX_MODE0) /* gpmc_ad12 */ 63 0x34 (PIN_INPUT | MUX_MODE0) /* gpmc_ad13 */ 64 0x38 (PIN_INPUT | MUX_MODE0) /* gpmc_ad14 */ 65 0x3c (PIN_INPUT | MUX_MODE0) /* gpmc_ad15 */ 66 0xb4 (PIN_OUTPUT | MUX_MODE0) /* gpmc_cs0 */ 67 0xc4 (PIN_OUTPUT | MUX_MODE0) /* gpmc_advn_ale */ 68 0xcc (PIN_OUTPUT | MUX_MODE0) /* gpmc_wen */ 69 0xc8 (PIN_OUTPUT | MUX_MODE0) /* gpmc_oen_ren */ 70 0xd0 (PIN_OUTPUT | MUX_MODE0) /* gpmc_ben0 */ 71 0xd8 (PIN_INPUT | MUX_MODE0) /* gpmc_wait0 */ 72 >; 73 }; 74 75 usb1_pins: pinmux_usb1_pins { 76 pinctrl-single,pins = < 77 0x280 (PIN_INPUT_SLEW | MUX_MODE0) /* usb1_drvvbus */ 78 >; 79 }; 80 81 usb2_pins: pinmux_usb2_pins { 82 pinctrl-single,pins = < 83 0x284 (PIN_INPUT_SLEW | MUX_MODE0) /* usb2_drvvbus */ 84 >; 85 }; 86 87 tps65917_pins_default: tps65917_pins_default { 88 pinctrl-single,pins = < 89 0x424 (PIN_INPUT_PULLUP | MUX_MODE1) /* wakeup3.sys_nirq1 */ 90 >; 91 }; 92 93 mmc1_pins_default: mmc1_pins_default { 94 pinctrl-single,pins = < 95 0x36c (PIN_INPUT | MUX_MODE14) /* mmc1sdcd.gpio219 */ 96 0x354 (PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_clk.clk */ 97 0x358 (PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_cmd.cmd */ 98 0x35c (PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat0.dat0 */ 99 0x360 (PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat1.dat1 */ 100 0x364 (PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat2.dat2 */ 101 0x368 (PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat3.dat3 */ 102 >; 103 }; 104 105 mmc2_pins_default: mmc2_pins_default { 106 pinctrl-single,pins = < 107 0x9c (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a23.mmc2_clk */ 108 0xb0 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_cs1.mmc2_cmd */ 109 0xa0 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a24.mmc2_dat0 */ 110 0xa4 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a25.mmc2_dat1 */ 111 0xa8 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a26.mmc2_dat2 */ 112 0xac (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a27.mmc2_dat3 */ 113 0x8c (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a19.mmc2_dat4 */ 114 0x90 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a20.mmc2_dat5 */ 115 0x94 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a21.mmc2_dat6 */ 116 0x98 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a22.mmc2_dat7 */ 117 >; 118 }; 119 120 dcan1_pins_default: dcan1_pins_default { 121 pinctrl-single,pins = < 122 0x3d0 (PIN_OUTPUT | MUX_MODE0) /* dcan1_tx */ 123 0x3d4 (MUX_MODE15) /* dcan1_rx.off */ 124 0x418 (PULL_DIS | MUX_MODE1) /* wakeup0.dcan1_rx */ 125 >; 126 }; 127 128 dcan1_pins_sleep: dcan1_pins_sleep { 129 pinctrl-single,pins = < 130 0x3d0 (MUX_MODE15) /* dcan1_tx.off */ 131 0x3d4 (MUX_MODE15) /* dcan1_rx.off */ 132 0x418 (MUX_MODE15) /* wakeup0.off */ 133 >; 134 }; 135 136 qspi1_pins: pinmux_qspi1_pins { 137 pinctrl-single,pins = < 138 0x74 (PIN_OUTPUT | MUX_MODE1) /* gpmc_a13.qspi1_rtclk */ 139 0x78 (PIN_INPUT | MUX_MODE1) /* gpmc_a14.qspi1_d3 */ 140 0x7c (PIN_INPUT | MUX_MODE1) /* gpmc_a15.qspi1_d2 */ 141 0x80 (PIN_INPUT | MUX_MODE1) /* gpmc_a16.qspi1_d1 */ 142 0x84 (PIN_INPUT | MUX_MODE1) /* gpmc_a17.qspi1_d0 */ 143 0x88 (PIN_OUTPUT | MUX_MODE1) /* qpmc_a18.qspi1_sclk */ 144 0xb8 (PIN_OUTPUT | MUX_MODE1) /* gpmc_cs2.qspi1_cs0 */ 145 >; 146 }; 147}; 148 149&i2c1 { 150 status = "okay"; 151 pinctrl-names = "default"; 152 pinctrl-0 = <&i2c1_pins>; 153 clock-frequency = <400000>; 154 155 tps65917: tps65917@58 { 156 compatible = "ti,tps65917"; 157 reg = <0x58>; 158 159 pinctrl-names = "default"; 160 pinctrl-0 = <&tps65917_pins_default>; 161 162 interrupts = <GIC_SPI 2 IRQ_TYPE_NONE>; /* IRQ_SYS_1N */ 163 interrupt-parent = <&gic>; 164 interrupt-controller; 165 #interrupt-cells = <2>; 166 167 ti,system-power-controller; 168 169 tps65917_pmic { 170 compatible = "ti,tps65917-pmic"; 171 172 regulators { 173 smps1_reg: smps1 { 174 /* VDD_MPU */ 175 regulator-name = "smps1"; 176 regulator-min-microvolt = <850000>; 177 regulator-max-microvolt = <1250000>; 178 regulator-always-on; 179 regulator-boot-on; 180 }; 181 182 smps2_reg: smps2 { 183 /* VDD_CORE */ 184 regulator-name = "smps2"; 185 regulator-min-microvolt = <850000>; 186 regulator-max-microvolt = <1060000>; 187 regulator-boot-on; 188 regulator-always-on; 189 }; 190 191 smps3_reg: smps3 { 192 /* VDD_GPU IVA DSPEVE */ 193 regulator-name = "smps3"; 194 regulator-min-microvolt = <850000>; 195 regulator-max-microvolt = <1250000>; 196 regulator-boot-on; 197 regulator-always-on; 198 }; 199 200 smps4_reg: smps4 { 201 /* VDDS1V8 */ 202 regulator-name = "smps4"; 203 regulator-min-microvolt = <1800000>; 204 regulator-max-microvolt = <1800000>; 205 regulator-always-on; 206 regulator-boot-on; 207 }; 208 209 smps5_reg: smps5 { 210 /* VDD_DDR */ 211 regulator-name = "smps5"; 212 regulator-min-microvolt = <1350000>; 213 regulator-max-microvolt = <1350000>; 214 regulator-boot-on; 215 regulator-always-on; 216 }; 217 218 ldo1_reg: ldo1 { 219 /* LDO1_OUT --> SDIO */ 220 regulator-name = "ldo1"; 221 regulator-min-microvolt = <1800000>; 222 regulator-max-microvolt = <3300000>; 223 regulator-boot-on; 224 }; 225 226 ldo2_reg: ldo2 { 227 /* LDO2_OUT --> TP1017 (UNUSED) */ 228 regulator-name = "ldo2"; 229 regulator-min-microvolt = <1800000>; 230 regulator-max-microvolt = <3300000>; 231 }; 232 233 ldo3_reg: ldo3 { 234 /* VDDA_1V8_PHY */ 235 regulator-name = "ldo3"; 236 regulator-min-microvolt = <1800000>; 237 regulator-max-microvolt = <1800000>; 238 regulator-boot-on; 239 regulator-always-on; 240 }; 241 242 ldo5_reg: ldo5 { 243 /* VDDA_1V8_PLL */ 244 regulator-name = "ldo5"; 245 regulator-min-microvolt = <1800000>; 246 regulator-max-microvolt = <1800000>; 247 regulator-always-on; 248 regulator-boot-on; 249 }; 250 251 ldo4_reg: ldo4 { 252 /* VDDA_3V_USB: VDDA_USBHS33 */ 253 regulator-name = "ldo4"; 254 regulator-min-microvolt = <3300000>; 255 regulator-max-microvolt = <3300000>; 256 regulator-boot-on; 257 }; 258 }; 259 }; 260 261 tps65917_power_button { 262 compatible = "ti,palmas-pwrbutton"; 263 interrupt-parent = <&tps65917>; 264 interrupts = <1 IRQ_TYPE_NONE>; 265 wakeup-source; 266 ti,palmas-long-press-seconds = <6>; 267 }; 268 }; 269 270 pcf_gpio_21: gpio@21 { 271 compatible = "ti,pcf8575"; 272 reg = <0x21>; 273 lines-initial-states = <0x1408>; 274 gpio-controller; 275 #gpio-cells = <2>; 276 interrupt-parent = <&gpio6>; 277 interrupts = <11 IRQ_TYPE_EDGE_FALLING>; 278 interrupt-controller; 279 #interrupt-cells = <2>; 280 }; 281}; 282 283&uart1 { 284 status = "okay"; 285}; 286 287&elm { 288 status = "okay"; 289}; 290 291&gpmc { 292 status = "okay"; 293 pinctrl-names = "default"; 294 pinctrl-0 = <&nand_default>; 295 ranges = <0 0 0 0x01000000>; /* minimum GPMC partition = 16MB */ 296 nand@0,0 { 297 /* To use NAND, DIP switch SW5 must be set like so: 298 * SW5.1 (NAND_SELn) = ON (LOW) 299 * SW5.9 (GPMC_WPN) = OFF (HIGH) 300 */ 301 reg = <0 0 4>; /* device IO registers */ 302 ti,nand-ecc-opt = "bch8"; 303 ti,elm-id = <&elm>; 304 nand-bus-width = <16>; 305 gpmc,device-width = <2>; 306 gpmc,sync-clk-ps = <0>; 307 gpmc,cs-on-ns = <0>; 308 gpmc,cs-rd-off-ns = <80>; 309 gpmc,cs-wr-off-ns = <80>; 310 gpmc,adv-on-ns = <0>; 311 gpmc,adv-rd-off-ns = <60>; 312 gpmc,adv-wr-off-ns = <60>; 313 gpmc,we-on-ns = <10>; 314 gpmc,we-off-ns = <50>; 315 gpmc,oe-on-ns = <4>; 316 gpmc,oe-off-ns = <40>; 317 gpmc,access-ns = <40>; 318 gpmc,wr-access-ns = <80>; 319 gpmc,rd-cycle-ns = <80>; 320 gpmc,wr-cycle-ns = <80>; 321 gpmc,bus-turnaround-ns = <0>; 322 gpmc,cycle2cycle-delay-ns = <0>; 323 gpmc,clk-activation-ns = <0>; 324 gpmc,wait-monitoring-ns = <0>; 325 gpmc,wr-data-mux-bus-ns = <0>; 326 /* MTD partition table */ 327 /* All SPL-* partitions are sized to minimal length 328 * which can be independently programmable. For 329 * NAND flash this is equal to size of erase-block */ 330 #address-cells = <1>; 331 #size-cells = <1>; 332 partition@0 { 333 label = "NAND.SPL"; 334 reg = <0x00000000 0x000020000>; 335 }; 336 partition@1 { 337 label = "NAND.SPL.backup1"; 338 reg = <0x00020000 0x00020000>; 339 }; 340 partition@2 { 341 label = "NAND.SPL.backup2"; 342 reg = <0x00040000 0x00020000>; 343 }; 344 partition@3 { 345 label = "NAND.SPL.backup3"; 346 reg = <0x00060000 0x00020000>; 347 }; 348 partition@4 { 349 label = "NAND.u-boot-spl-os"; 350 reg = <0x00080000 0x00040000>; 351 }; 352 partition@5 { 353 label = "NAND.u-boot"; 354 reg = <0x000c0000 0x00100000>; 355 }; 356 partition@6 { 357 label = "NAND.u-boot-env"; 358 reg = <0x001c0000 0x00020000>; 359 }; 360 partition@7 { 361 label = "NAND.u-boot-env.backup1"; 362 reg = <0x001e0000 0x00020000>; 363 }; 364 partition@8 { 365 label = "NAND.kernel"; 366 reg = <0x00200000 0x00800000>; 367 }; 368 partition@9 { 369 label = "NAND.file-system"; 370 reg = <0x00a00000 0x0f600000>; 371 }; 372 }; 373}; 374 375&usb2_phy1 { 376 phy-supply = <&ldo4_reg>; 377}; 378 379&usb2_phy2 { 380 phy-supply = <&ldo4_reg>; 381}; 382 383&omap_dwc3_1 { 384 extcon = <&extcon_usb1>; 385}; 386 387&omap_dwc3_2 { 388 extcon = <&extcon_usb2>; 389}; 390 391&usb1 { 392 dr_mode = "peripheral"; 393 pinctrl-names = "default"; 394 pinctrl-0 = <&usb1_pins>; 395}; 396 397&usb2 { 398 dr_mode = "host"; 399 pinctrl-names = "default"; 400 pinctrl-0 = <&usb2_pins>; 401}; 402 403&mmc1 { 404 status = "okay"; 405 pinctrl-names = "default"; 406 pinctrl-0 = <&mmc1_pins_default>; 407 408 vmmc-supply = <&ldo1_reg>; 409 bus-width = <4>; 410 /* 411 * SDCD signal is not being used here - using the fact that GPIO mode 412 * is a viable alternative 413 */ 414 cd-gpios = <&gpio6 27 0>; 415}; 416 417&mmc2 { 418 /* SW5-3 in ON position */ 419 status = "okay"; 420 pinctrl-names = "default"; 421 pinctrl-0 = <&mmc2_pins_default>; 422 423 vmmc-supply = <&evm_3v3>; 424 bus-width = <8>; 425 ti,non-removable; 426}; 427 428&dra7_pmx_core { 429 cpsw_default: cpsw_default { 430 pinctrl-single,pins = < 431 /* Slave 2 */ 432 0x198 (PIN_OUTPUT | MUX_MODE3) /* vin2a_d12.rgmii1_txc */ 433 0x19c (PIN_OUTPUT | MUX_MODE3) /* vin2a_d13.rgmii1_tctl */ 434 0x1a0 (PIN_OUTPUT | MUX_MODE3) /* vin2a_d14.rgmii1_td3 */ 435 0x1a4 (PIN_OUTPUT | MUX_MODE3) /* vin2a_d15.rgmii1_td2 */ 436 0x1a8 (PIN_OUTPUT | MUX_MODE3) /* vin2a_d16.rgmii1_td1 */ 437 0x1ac (PIN_OUTPUT | MUX_MODE3) /* vin2a_d17.rgmii1_td0 */ 438 0x1b0 (PIN_INPUT | MUX_MODE3) /* vin2a_d18.rgmii1_rclk */ 439 0x1b4 (PIN_INPUT | MUX_MODE3) /* vin2a_d19.rgmii1_rctl */ 440 0x1b8 (PIN_INPUT | MUX_MODE3) /* vin2a_d20.rgmii1_rd3 */ 441 0x1bc (PIN_INPUT | MUX_MODE3) /* vin2a_d21.rgmii1_rd2 */ 442 0x1c0 (PIN_INPUT | MUX_MODE3) /* vin2a_d22.rgmii1_rd1 */ 443 0x1c4 (PIN_INPUT | MUX_MODE3) /* vin2a_d23.rgmii1_rd0 */ 444 >; 445 446 }; 447 448 cpsw_sleep: cpsw_sleep { 449 pinctrl-single,pins = < 450 /* Slave 2 */ 451 0x198 (MUX_MODE15) 452 0x19c (MUX_MODE15) 453 0x1a0 (MUX_MODE15) 454 0x1a4 (MUX_MODE15) 455 0x1a8 (MUX_MODE15) 456 0x1ac (MUX_MODE15) 457 0x1b0 (MUX_MODE15) 458 0x1b4 (MUX_MODE15) 459 0x1b8 (MUX_MODE15) 460 0x1bc (MUX_MODE15) 461 0x1c0 (MUX_MODE15) 462 0x1c4 (MUX_MODE15) 463 >; 464 }; 465 466 davinci_mdio_default: davinci_mdio_default { 467 pinctrl-single,pins = < 468 /* MDIO */ 469 0x23c (PIN_OUTPUT_PULLUP | MUX_MODE0) /* mdio_d.mdio_d */ 470 0x240 (PIN_INPUT_PULLUP | MUX_MODE0) /* mdio_clk.mdio_clk */ 471 >; 472 }; 473 474 davinci_mdio_sleep: davinci_mdio_sleep { 475 pinctrl-single,pins = < 476 0x23c (MUX_MODE15) 477 0x240 (MUX_MODE15) 478 >; 479 }; 480}; 481 482&mac { 483 status = "okay"; 484 pinctrl-names = "default", "sleep"; 485 pinctrl-0 = <&cpsw_default>; 486 pinctrl-1 = <&cpsw_sleep>; 487}; 488 489&cpsw_emac1 { 490 phy_id = <&davinci_mdio>, <3>; 491 phy-mode = "rgmii"; 492}; 493 494&davinci_mdio { 495 pinctrl-names = "default", "sleep"; 496 pinctrl-0 = <&davinci_mdio_default>; 497 pinctrl-1 = <&davinci_mdio_sleep>; 498 active_slave = <1>; 499}; 500 501&dcan1 { 502 status = "ok"; 503 pinctrl-names = "default", "sleep"; 504 pinctrl-0 = <&dcan1_pins_default>; 505 pinctrl-1 = <&dcan1_pins_sleep>; 506}; 507 508&qspi { 509 status = "okay"; 510 pinctrl-names = "default"; 511 pinctrl-0 = <&qspi1_pins>; 512 513 spi-max-frequency = <48000000>; 514 m25p80@0 { 515 compatible = "s25fl256s1"; 516 spi-max-frequency = <48000000>; 517 reg = <0>; 518 spi-tx-bus-width = <1>; 519 spi-rx-bus-width = <4>; 520 spi-cpol; 521 spi-cpha; 522 #address-cells = <1>; 523 #size-cells = <1>; 524 525 /* MTD partition table. 526 * The ROM checks the first four physical blocks 527 * for a valid file to boot and the flash here is 528 * 64KiB block size. 529 */ 530 partition@0 { 531 label = "QSPI.SPL"; 532 reg = <0x00000000 0x000010000>; 533 }; 534 partition@1 { 535 label = "QSPI.SPL.backup1"; 536 reg = <0x00010000 0x00010000>; 537 }; 538 partition@2 { 539 label = "QSPI.SPL.backup2"; 540 reg = <0x00020000 0x00010000>; 541 }; 542 partition@3 { 543 label = "QSPI.SPL.backup3"; 544 reg = <0x00030000 0x00010000>; 545 }; 546 partition@4 { 547 label = "QSPI.u-boot"; 548 reg = <0x00040000 0x00100000>; 549 }; 550 partition@5 { 551 label = "QSPI.u-boot-spl-os"; 552 reg = <0x00140000 0x00080000>; 553 }; 554 partition@6 { 555 label = "QSPI.u-boot-env"; 556 reg = <0x001c0000 0x00010000>; 557 }; 558 partition@7 { 559 label = "QSPI.u-boot-env.backup1"; 560 reg = <0x001d0000 0x0010000>; 561 }; 562 partition@8 { 563 label = "QSPI.kernel"; 564 reg = <0x001e0000 0x0800000>; 565 }; 566 partition@9 { 567 label = "QSPI.file-system"; 568 reg = <0x009e0000 0x01620000>; 569 }; 570 }; 571}; 572