armada-xp-mv78260.dtsi revision 284090
1/* 2 * Device Tree Include file for Marvell Armada XP family SoC 3 * 4 * Copyright (C) 2012 Marvell 5 * 6 * Thomas Petazzoni <thomas.petazzoni@free-electrons.com> 7 * 8 * This file is dual-licensed: you can use it either under the terms 9 * of the GPL or the X11 license, at your option. Note that this dual 10 * licensing only applies to this file, and not this project as a 11 * whole. 12 * 13 * a) This file is free software; you can redistribute it and/or 14 * modify it under the terms of the GNU General Public License as 15 * published by the Free Software Foundation; either version 2 of the 16 * License, or (at your option) any later version. 17 * 18 * This file is distributed in the hope that it will be useful 19 * but WITHOUT ANY WARRANTY; without even the implied warranty of 20 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 21 * GNU General Public License for more details. 22 * 23 * Or, alternatively 24 * 25 * b) Permission is hereby granted, free of charge, to any person 26 * obtaining a copy of this software and associated documentation 27 * files (the "Software"), to deal in the Software without 28 * restriction, including without limitation the rights to use 29 * copy, modify, merge, publish, distribute, sublicense, and/or 30 * sell copies of the Software, and to permit persons to whom the 31 * Software is furnished to do so, subject to the following 32 * conditions: 33 * 34 * The above copyright notice and this permission notice shall be 35 * included in all copies or substantial portions of the Software. 36 * 37 * THE SOFTWARE IS PROVIDED , WITHOUT WARRANTY OF ANY KIND 38 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES 39 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 40 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT 41 * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY 42 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 43 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 44 * OTHER DEALINGS IN THE SOFTWARE. 45 * 46 * Contains definitions specific to the Armada XP MV78260 SoC that are not 47 * common to all Armada XP SoCs. 48 */ 49 50#include "armada-xp.dtsi" 51 52/ { 53 model = "Marvell Armada XP MV78260 SoC"; 54 compatible = "marvell,armadaxp-mv78260", "marvell,armadaxp", "marvell,armada-370-xp"; 55 56 aliases { 57 gpio0 = &gpio0; 58 gpio1 = &gpio1; 59 gpio2 = &gpio2; 60 eth3 = ð3; 61 }; 62 63 cpus { 64 #address-cells = <1>; 65 #size-cells = <0>; 66 enable-method = "marvell,armada-xp-smp"; 67 68 cpu@0 { 69 device_type = "cpu"; 70 compatible = "marvell,sheeva-v7"; 71 reg = <0>; 72 clocks = <&cpuclk 0>; 73 clock-latency = <1000000>; 74 }; 75 76 cpu@1 { 77 device_type = "cpu"; 78 compatible = "marvell,sheeva-v7"; 79 reg = <1>; 80 clocks = <&cpuclk 1>; 81 clock-latency = <1000000>; 82 }; 83 }; 84 85 soc { 86 /* 87 * MV78260 has 3 PCIe units Gen2.0: Two units can be 88 * configured as x4 or quad x1 lanes. One unit is 89 * x4 only. 90 */ 91 pcie-controller { 92 compatible = "marvell,armada-xp-pcie"; 93 status = "disabled"; 94 device_type = "pci"; 95 96 #address-cells = <3>; 97 #size-cells = <2>; 98 99 msi-parent = <&mpic>; 100 bus-range = <0x00 0xff>; 101 102 ranges = 103 <0x82000000 0 0x40000 MBUS_ID(0xf0, 0x01) 0x40000 0 0x00002000 /* Port 0.0 registers */ 104 0x82000000 0 0x42000 MBUS_ID(0xf0, 0x01) 0x42000 0 0x00002000 /* Port 2.0 registers */ 105 0x82000000 0 0x44000 MBUS_ID(0xf0, 0x01) 0x44000 0 0x00002000 /* Port 0.1 registers */ 106 0x82000000 0 0x48000 MBUS_ID(0xf0, 0x01) 0x48000 0 0x00002000 /* Port 0.2 registers */ 107 0x82000000 0 0x4c000 MBUS_ID(0xf0, 0x01) 0x4c000 0 0x00002000 /* Port 0.3 registers */ 108 0x82000000 0 0x80000 MBUS_ID(0xf0, 0x01) 0x80000 0 0x00002000 /* Port 1.0 registers */ 109 0x82000000 0 0x84000 MBUS_ID(0xf0, 0x01) 0x84000 0 0x00002000 /* Port 1.1 registers */ 110 0x82000000 0 0x88000 MBUS_ID(0xf0, 0x01) 0x88000 0 0x00002000 /* Port 1.2 registers */ 111 0x82000000 0 0x8c000 MBUS_ID(0xf0, 0x01) 0x8c000 0 0x00002000 /* Port 1.3 registers */ 112 0x82000000 0x1 0 MBUS_ID(0x04, 0xe8) 0 1 0 /* Port 0.0 MEM */ 113 0x81000000 0x1 0 MBUS_ID(0x04, 0xe0) 0 1 0 /* Port 0.0 IO */ 114 0x82000000 0x2 0 MBUS_ID(0x04, 0xd8) 0 1 0 /* Port 0.1 MEM */ 115 0x81000000 0x2 0 MBUS_ID(0x04, 0xd0) 0 1 0 /* Port 0.1 IO */ 116 0x82000000 0x3 0 MBUS_ID(0x04, 0xb8) 0 1 0 /* Port 0.2 MEM */ 117 0x81000000 0x3 0 MBUS_ID(0x04, 0xb0) 0 1 0 /* Port 0.2 IO */ 118 0x82000000 0x4 0 MBUS_ID(0x04, 0x78) 0 1 0 /* Port 0.3 MEM */ 119 0x81000000 0x4 0 MBUS_ID(0x04, 0x70) 0 1 0 /* Port 0.3 IO */ 120 121 0x82000000 0x5 0 MBUS_ID(0x08, 0xe8) 0 1 0 /* Port 1.0 MEM */ 122 0x81000000 0x5 0 MBUS_ID(0x08, 0xe0) 0 1 0 /* Port 1.0 IO */ 123 0x82000000 0x6 0 MBUS_ID(0x08, 0xd8) 0 1 0 /* Port 1.1 MEM */ 124 0x81000000 0x6 0 MBUS_ID(0x08, 0xd0) 0 1 0 /* Port 1.1 IO */ 125 0x82000000 0x7 0 MBUS_ID(0x08, 0xb8) 0 1 0 /* Port 1.2 MEM */ 126 0x81000000 0x7 0 MBUS_ID(0x08, 0xb0) 0 1 0 /* Port 1.2 IO */ 127 0x82000000 0x8 0 MBUS_ID(0x08, 0x78) 0 1 0 /* Port 1.3 MEM */ 128 0x81000000 0x8 0 MBUS_ID(0x08, 0x70) 0 1 0 /* Port 1.3 IO */ 129 130 0x82000000 0x9 0 MBUS_ID(0x04, 0xf8) 0 1 0 /* Port 2.0 MEM */ 131 0x81000000 0x9 0 MBUS_ID(0x04, 0xf0) 0 1 0 /* Port 2.0 IO */>; 132 133 pcie@1,0 { 134 device_type = "pci"; 135 assigned-addresses = <0x82000800 0 0x40000 0 0x2000>; 136 reg = <0x0800 0 0 0 0>; 137 #address-cells = <3>; 138 #size-cells = <2>; 139 #interrupt-cells = <1>; 140 ranges = <0x82000000 0 0 0x82000000 0x1 0 1 0 141 0x81000000 0 0 0x81000000 0x1 0 1 0>; 142 interrupt-map-mask = <0 0 0 0>; 143 interrupt-map = <0 0 0 0 &mpic 58>; 144 marvell,pcie-port = <0>; 145 marvell,pcie-lane = <0>; 146 clocks = <&gateclk 5>; 147 status = "disabled"; 148 }; 149 150 pcie@2,0 { 151 device_type = "pci"; 152 assigned-addresses = <0x82000800 0 0x44000 0 0x2000>; 153 reg = <0x1000 0 0 0 0>; 154 #address-cells = <3>; 155 #size-cells = <2>; 156 #interrupt-cells = <1>; 157 ranges = <0x82000000 0 0 0x82000000 0x2 0 1 0 158 0x81000000 0 0 0x81000000 0x2 0 1 0>; 159 interrupt-map-mask = <0 0 0 0>; 160 interrupt-map = <0 0 0 0 &mpic 59>; 161 marvell,pcie-port = <0>; 162 marvell,pcie-lane = <1>; 163 clocks = <&gateclk 6>; 164 status = "disabled"; 165 }; 166 167 pcie@3,0 { 168 device_type = "pci"; 169 assigned-addresses = <0x82000800 0 0x48000 0 0x2000>; 170 reg = <0x1800 0 0 0 0>; 171 #address-cells = <3>; 172 #size-cells = <2>; 173 #interrupt-cells = <1>; 174 ranges = <0x82000000 0 0 0x82000000 0x3 0 1 0 175 0x81000000 0 0 0x81000000 0x3 0 1 0>; 176 interrupt-map-mask = <0 0 0 0>; 177 interrupt-map = <0 0 0 0 &mpic 60>; 178 marvell,pcie-port = <0>; 179 marvell,pcie-lane = <2>; 180 clocks = <&gateclk 7>; 181 status = "disabled"; 182 }; 183 184 pcie@4,0 { 185 device_type = "pci"; 186 assigned-addresses = <0x82000800 0 0x4c000 0 0x2000>; 187 reg = <0x2000 0 0 0 0>; 188 #address-cells = <3>; 189 #size-cells = <2>; 190 #interrupt-cells = <1>; 191 ranges = <0x82000000 0 0 0x82000000 0x4 0 1 0 192 0x81000000 0 0 0x81000000 0x4 0 1 0>; 193 interrupt-map-mask = <0 0 0 0>; 194 interrupt-map = <0 0 0 0 &mpic 61>; 195 marvell,pcie-port = <0>; 196 marvell,pcie-lane = <3>; 197 clocks = <&gateclk 8>; 198 status = "disabled"; 199 }; 200 201 pcie@5,0 { 202 device_type = "pci"; 203 assigned-addresses = <0x82000800 0 0x80000 0 0x2000>; 204 reg = <0x2800 0 0 0 0>; 205 #address-cells = <3>; 206 #size-cells = <2>; 207 #interrupt-cells = <1>; 208 ranges = <0x82000000 0 0 0x82000000 0x5 0 1 0 209 0x81000000 0 0 0x81000000 0x5 0 1 0>; 210 interrupt-map-mask = <0 0 0 0>; 211 interrupt-map = <0 0 0 0 &mpic 62>; 212 marvell,pcie-port = <1>; 213 marvell,pcie-lane = <0>; 214 clocks = <&gateclk 9>; 215 status = "disabled"; 216 }; 217 218 pcie@6,0 { 219 device_type = "pci"; 220 assigned-addresses = <0x82000800 0 0x84000 0 0x2000>; 221 reg = <0x3000 0 0 0 0>; 222 #address-cells = <3>; 223 #size-cells = <2>; 224 #interrupt-cells = <1>; 225 ranges = <0x82000000 0 0 0x82000000 0x6 0 1 0 226 0x81000000 0 0 0x81000000 0x6 0 1 0>; 227 interrupt-map-mask = <0 0 0 0>; 228 interrupt-map = <0 0 0 0 &mpic 63>; 229 marvell,pcie-port = <1>; 230 marvell,pcie-lane = <1>; 231 clocks = <&gateclk 10>; 232 status = "disabled"; 233 }; 234 235 pcie@7,0 { 236 device_type = "pci"; 237 assigned-addresses = <0x82000800 0 0x88000 0 0x2000>; 238 reg = <0x3800 0 0 0 0>; 239 #address-cells = <3>; 240 #size-cells = <2>; 241 #interrupt-cells = <1>; 242 ranges = <0x82000000 0 0 0x82000000 0x7 0 1 0 243 0x81000000 0 0 0x81000000 0x7 0 1 0>; 244 interrupt-map-mask = <0 0 0 0>; 245 interrupt-map = <0 0 0 0 &mpic 64>; 246 marvell,pcie-port = <1>; 247 marvell,pcie-lane = <2>; 248 clocks = <&gateclk 11>; 249 status = "disabled"; 250 }; 251 252 pcie@8,0 { 253 device_type = "pci"; 254 assigned-addresses = <0x82000800 0 0x8c000 0 0x2000>; 255 reg = <0x4000 0 0 0 0>; 256 #address-cells = <3>; 257 #size-cells = <2>; 258 #interrupt-cells = <1>; 259 ranges = <0x82000000 0 0 0x82000000 0x8 0 1 0 260 0x81000000 0 0 0x81000000 0x8 0 1 0>; 261 interrupt-map-mask = <0 0 0 0>; 262 interrupt-map = <0 0 0 0 &mpic 65>; 263 marvell,pcie-port = <1>; 264 marvell,pcie-lane = <3>; 265 clocks = <&gateclk 12>; 266 status = "disabled"; 267 }; 268 269 pcie@9,0 { 270 device_type = "pci"; 271 assigned-addresses = <0x82000800 0 0x42000 0 0x2000>; 272 reg = <0x4800 0 0 0 0>; 273 #address-cells = <3>; 274 #size-cells = <2>; 275 #interrupt-cells = <1>; 276 ranges = <0x82000000 0 0 0x82000000 0x9 0 1 0 277 0x81000000 0 0 0x81000000 0x9 0 1 0>; 278 interrupt-map-mask = <0 0 0 0>; 279 interrupt-map = <0 0 0 0 &mpic 99>; 280 marvell,pcie-port = <2>; 281 marvell,pcie-lane = <0>; 282 clocks = <&gateclk 26>; 283 status = "disabled"; 284 }; 285 }; 286 287 internal-regs { 288 gpio0: gpio@18100 { 289 compatible = "marvell,orion-gpio"; 290 reg = <0x18100 0x40>; 291 ngpios = <32>; 292 gpio-controller; 293 #gpio-cells = <2>; 294 interrupt-controller; 295 #interrupt-cells = <2>; 296 interrupts = <82>, <83>, <84>, <85>; 297 }; 298 299 gpio1: gpio@18140 { 300 compatible = "marvell,orion-gpio"; 301 reg = <0x18140 0x40>; 302 ngpios = <32>; 303 gpio-controller; 304 #gpio-cells = <2>; 305 interrupt-controller; 306 #interrupt-cells = <2>; 307 interrupts = <87>, <88>, <89>, <90>; 308 }; 309 310 gpio2: gpio@18180 { 311 compatible = "marvell,orion-gpio"; 312 reg = <0x18180 0x40>; 313 ngpios = <3>; 314 gpio-controller; 315 #gpio-cells = <2>; 316 interrupt-controller; 317 #interrupt-cells = <2>; 318 interrupts = <91>; 319 }; 320 321 eth3: ethernet@34000 { 322 compatible = "marvell,armada-370-neta"; 323 reg = <0x34000 0x4000>; 324 interrupts = <14>; 325 clocks = <&gateclk 1>; 326 status = "disabled"; 327 }; 328 }; 329 }; 330}; 331 332&pinctrl { 333 compatible = "marvell,mv78260-pinctrl"; 334}; 335