1139825Simp/*- 241502Swpaul * Copyright (c) 1997, 1998 341502Swpaul * Bill Paul <wpaul@ctr.columbia.edu>. All rights reserved. 441502Swpaul * 541502Swpaul * Redistribution and use in source and binary forms, with or without 641502Swpaul * modification, are permitted provided that the following conditions 741502Swpaul * are met: 841502Swpaul * 1. Redistributions of source code must retain the above copyright 941502Swpaul * notice, this list of conditions and the following disclaimer. 1041502Swpaul * 2. Redistributions in binary form must reproduce the above copyright 1141502Swpaul * notice, this list of conditions and the following disclaimer in the 1241502Swpaul * documentation and/or other materials provided with the distribution. 1341502Swpaul * 3. All advertising materials mentioning features or use of this software 1441502Swpaul * must display the following acknowledgement: 1541502Swpaul * This product includes software developed by Bill Paul. 1641502Swpaul * 4. Neither the name of the author nor the names of any co-contributors 1741502Swpaul * may be used to endorse or promote products derived from this software 1841502Swpaul * without specific prior written permission. 1941502Swpaul * 2041502Swpaul * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 2141502Swpaul * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 2241502Swpaul * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 2341502Swpaul * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 2441502Swpaul * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 2541502Swpaul * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 2641502Swpaul * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 2741502Swpaul * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 2841502Swpaul * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 2941502Swpaul * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 3041502Swpaul * THE POSSIBILITY OF SUCH DAMAGE. 3141502Swpaul * 3250477Speter * $FreeBSD$ 3341502Swpaul */ 3441502Swpaul 3541502Swpaul/* 3641502Swpaul * Winbond register definitions. 3741502Swpaul */ 3841502Swpaul 3941502Swpaul#define WB_BUSCTL 0x00 /* bus control */ 4041502Swpaul#define WB_TXSTART 0x04 /* tx start demand */ 4141502Swpaul#define WB_RXSTART 0x08 /* rx start demand */ 4241502Swpaul#define WB_RXADDR 0x0C /* rx descriptor list start addr */ 4341502Swpaul#define WB_TXADDR 0x10 /* tx descriptor list start addr */ 4441502Swpaul#define WB_ISR 0x14 /* interrupt status register */ 4541502Swpaul#define WB_NETCFG 0x18 /* network config register */ 4641502Swpaul#define WB_IMR 0x1C /* interrupt mask */ 4741502Swpaul#define WB_FRAMESDISCARDED 0x20 /* # of discarded frames */ 4841502Swpaul#define WB_SIO 0x24 /* MII and ROM/EEPROM access */ 4941502Swpaul#define WB_BOOTROMADDR 0x28 5041502Swpaul#define WB_TIMER 0x2C /* general timer */ 5141502Swpaul#define WB_CURRXCTL 0x30 /* current RX descriptor */ 5241502Swpaul#define WB_CURRXBUF 0x34 /* current RX buffer */ 5341502Swpaul#define WB_MAR0 0x38 /* multicast filter 0 */ 5441502Swpaul#define WB_MAR1 0x3C /* multicast filter 1 */ 5541502Swpaul#define WB_NODE0 0x40 /* station address 0 */ 5641502Swpaul#define WB_NODE1 0x44 /* station address 1 */ 5741502Swpaul#define WB_BOOTROMSIZE 0x48 /* boot ROM size */ 5841502Swpaul#define WB_CURTXCTL 0x4C /* current TX descriptor */ 5941502Swpaul#define WB_CURTXBUF 0x50 /* current TX buffer */ 6041502Swpaul 6141502Swpaul/* 6241502Swpaul * Bus control bits. 6341502Swpaul */ 6441502Swpaul#define WB_BUSCTL_RESET 0x00000001 6541502Swpaul#define WB_BUSCTL_ARBITRATION 0x00000002 6641502Swpaul#define WB_BUSCTL_SKIPLEN 0x0000007C 6741502Swpaul#define WB_BUSCTL_BUF_BIGENDIAN 0x00000080 6841502Swpaul#define WB_BUSCTL_BURSTLEN 0x00003F00 6941502Swpaul#define WB_BUSCTL_CACHEALIGN 0x0000C000 7041502Swpaul#define WB_BUSCTL_DES_BIGENDIAN 0x00100000 7141502Swpaul#define WB_BUSCTL_WAIT 0x00200000 7250675Swpaul#define WB_BUSCTL_MUSTBEONE 0x00400000 7341502Swpaul 7441502Swpaul#define WB_SKIPLEN_1LONG 0x00000004 7541502Swpaul#define WB_SKIPLEN_2LONG 0x00000008 7641502Swpaul#define WB_SKIPLEN_3LONG 0x00000010 7741502Swpaul#define WB_SKIPLEN_4LONG 0x00000020 7841502Swpaul#define WB_SKIPLEN_5LONG 0x00000040 7941502Swpaul 8050675Swpaul#define WB_CACHEALIGN_NONE 0x00000000 8141502Swpaul#define WB_CACHEALIGN_8LONG 0x00004000 8241502Swpaul#define WB_CACHEALIGN_16LONG 0x00008000 8341502Swpaul#define WB_CACHEALIGN_32LONG 0x0000C000 8441502Swpaul 8541502Swpaul#define WB_BURSTLEN_USECA 0x00000000 8641502Swpaul#define WB_BURSTLEN_1LONG 0x00000100 8741502Swpaul#define WB_BURSTLEN_2LONG 0x00000200 8841502Swpaul#define WB_BURSTLEN_4LONG 0x00000400 8941502Swpaul#define WB_BURSTLEN_8LONG 0x00000800 9041502Swpaul#define WB_BURSTLEN_16LONG 0x00001000 9141502Swpaul#define WB_BURSTLEN_32LONG 0x00002000 9241502Swpaul 9341502Swpaul#define WB_BUSCTL_CONFIG (WB_CACHEALIGN_8LONG|WB_SKIPLEN_3LONG| \ 9441502Swpaul WB_BURSTLEN_8LONG) 9541502Swpaul 9641502Swpaul/* 9741502Swpaul * Interrupt status bits. 9841502Swpaul */ 9941502Swpaul#define WB_ISR_TX_OK 0x00000001 10041502Swpaul#define WB_ISR_TX_IDLE 0x00000002 10141502Swpaul#define WB_ISR_TX_NOBUF 0x00000004 10241502Swpaul#define WB_ISR_RX_EARLY 0x00000008 10341502Swpaul#define WB_ISR_RX_ERR 0x00000010 10441502Swpaul#define WB_ISR_TX_UNDERRUN 0x00000020 10541502Swpaul#define WB_ISR_RX_OK 0x00000040 10641502Swpaul#define WB_ISR_RX_NOBUF 0x00000080 10741502Swpaul#define WB_ISR_RX_IDLE 0x00000100 10841502Swpaul#define WB_ISR_TX_EARLY 0x00000400 10941502Swpaul#define WB_ISR_TIMER_EXPIRED 0x00000800 11041502Swpaul#define WB_ISR_BUS_ERR 0x00002000 11141502Swpaul#define WB_ISR_ABNORMAL 0x00008000 11241502Swpaul#define WB_ISR_NORMAL 0x00010000 11341502Swpaul#define WB_ISR_RX_STATE 0x000E0000 11441502Swpaul#define WB_ISR_TX_STATE 0x00700000 11541502Swpaul#define WB_ISR_BUSERRTYPE 0x03800000 11641502Swpaul 11741502Swpaul/* 11841502Swpaul * The RX_STATE and TX_STATE fields are not described anywhere in the 11941502Swpaul * Winbond datasheet, however it appears that the Winbond chip is an 12041502Swpaul * attempt at a DEC 'tulip' clone, hence the ISR register is identical 12141502Swpaul * to that of the tulip chip and we can steal the bit definitions from 12241502Swpaul * the tulip documentation. 12341502Swpaul */ 12441502Swpaul#define WB_RXSTATE_STOPPED 0x00000000 /* 000 - Stopped */ 12541502Swpaul#define WB_RXSTATE_FETCH 0x00020000 /* 001 - Fetching descriptor */ 12641502Swpaul#define WB_RXSTATE_ENDCHECK 0x00040000 /* 010 - check for rx end */ 12741502Swpaul#define WB_RXSTATE_WAIT 0x00060000 /* 011 - waiting for packet */ 12841502Swpaul#define WB_RXSTATE_SUSPEND 0x00080000 /* 100 - suspend rx */ 12941502Swpaul#define WB_RXSTATE_CLOSE 0x000A0000 /* 101 - close tx desc */ 13041502Swpaul#define WB_RXSTATE_FLUSH 0x000C0000 /* 110 - flush from FIFO */ 13141502Swpaul#define WB_RXSTATE_DEQUEUE 0x000E0000 /* 111 - dequeue from FIFO */ 13241502Swpaul 13341502Swpaul#define WB_TXSTATE_RESET 0x00000000 /* 000 - reset */ 13441502Swpaul#define WB_TXSTATE_FETCH 0x00100000 /* 001 - fetching descriptor */ 13541502Swpaul#define WB_TXSTATE_WAITEND 0x00200000 /* 010 - wait for tx end */ 13641502Swpaul#define WB_TXSTATE_READING 0x00300000 /* 011 - read and enqueue */ 13741502Swpaul#define WB_TXSTATE_RSVD 0x00400000 /* 100 - reserved */ 13841502Swpaul#define WB_TXSTATE_SETUP 0x00500000 /* 101 - setup packet */ 13941502Swpaul#define WB_TXSTATE_SUSPEND 0x00600000 /* 110 - suspend tx */ 14041502Swpaul#define WB_TXSTATE_CLOSE 0x00700000 /* 111 - close tx desc */ 14141502Swpaul 14241502Swpaul/* 14341502Swpaul * Network config bits. 14441502Swpaul */ 14541502Swpaul#define WB_NETCFG_RX_ON 0x00000002 14641502Swpaul#define WB_NETCFG_RX_ALLPHYS 0x00000008 14741502Swpaul#define WB_NETCFG_RX_MULTI 0x00000010 14841502Swpaul#define WB_NETCFG_RX_BROAD 0x00000020 14941502Swpaul#define WB_NETCFG_RX_RUNT 0x00000040 15041502Swpaul#define WB_NETCFG_RX_ERR 0x00000080 15141502Swpaul#define WB_NETCFG_FULLDUPLEX 0x00000200 15241502Swpaul#define WB_NETCFG_LOOPBACK 0x00000C00 15341502Swpaul#define WB_NETCFG_TX_ON 0x00002000 15441502Swpaul#define WB_NETCFG_TX_THRESH 0x001FC000 15541502Swpaul#define WB_NETCFG_RX_EARLYTHRSH 0x1FE00000 15641502Swpaul#define WB_NETCFG_100MBPS 0x20000000 15741502Swpaul#define WB_NETCFG_TX_EARLY_ON 0x40000000 15841502Swpaul#define WB_NETCFG_RX_EARLY_ON 0x80000000 15941502Swpaul 16041502Swpaul/* 16141502Swpaul * The tx threshold can be adjusted in increments of 32 bytes. 16241502Swpaul */ 16341502Swpaul#define WB_TXTHRESH(x) ((x >> 5) << 14) 16441502Swpaul#define WB_TXTHRESH_CHUNK 32 16542718Swpaul#define WB_TXTHRESH_INIT 0 /*72*/ 16641502Swpaul 16741502Swpaul/* 16841502Swpaul * Interrupt mask bits. 16941502Swpaul */ 17041502Swpaul#define WB_IMR_TX_OK 0x00000001 17141502Swpaul#define WB_IMR_TX_IDLE 0x00000002 17241502Swpaul#define WB_IMR_TX_NOBUF 0x00000004 17341502Swpaul#define WB_IMR_RX_EARLY 0x00000008 17441502Swpaul#define WB_IMR_RX_ERR 0x00000010 17541502Swpaul#define WB_IMR_TX_UNDERRUN 0x00000020 17641502Swpaul#define WB_IMR_RX_OK 0x00000040 17741502Swpaul#define WB_IMR_RX_NOBUF 0x00000080 17841502Swpaul#define WB_IMR_RX_IDLE 0x00000100 17941502Swpaul#define WB_IMR_TX_EARLY 0x00000400 18041502Swpaul#define WB_IMR_TIMER_EXPIRED 0x00000800 18141502Swpaul#define WB_IMR_BUS_ERR 0x00002000 18241502Swpaul#define WB_IMR_ABNORMAL 0x00008000 18341502Swpaul#define WB_IMR_NORMAL 0x00010000 18441502Swpaul 18541502Swpaul#define WB_INTRS \ 18641502Swpaul (WB_IMR_RX_OK|WB_IMR_TX_OK|WB_IMR_RX_NOBUF|WB_IMR_RX_ERR| \ 18741502Swpaul WB_IMR_TX_NOBUF|WB_IMR_TX_UNDERRUN|WB_IMR_BUS_ERR| \ 18841502Swpaul WB_IMR_ABNORMAL|WB_IMR_NORMAL|WB_IMR_TX_EARLY) 18941502Swpaul/* 19041502Swpaul * Serial I/O (EEPROM/ROM) bits. 19141502Swpaul */ 19241502Swpaul#define WB_SIO_EE_CS 0x00000001 /* EEPROM chip select */ 19341502Swpaul#define WB_SIO_EE_CLK 0x00000002 /* EEPROM clock */ 19441502Swpaul#define WB_SIO_EE_DATAIN 0x00000004 /* EEPROM data output */ 19541502Swpaul#define WB_SIO_EE_DATAOUT 0x00000008 /* EEPROM data input */ 19641502Swpaul#define WB_SIO_ROMDATA4 0x00000010 19741502Swpaul#define WB_SIO_ROMDATA5 0x00000020 19841502Swpaul#define WB_SIO_ROMDATA6 0x00000040 19941502Swpaul#define WB_SIO_ROMDATA7 0x00000080 20041502Swpaul#define WB_SIO_ROMCTL_WRITE 0x00000200 20141502Swpaul#define WB_SIO_ROMCTL_READ 0x00000400 20241502Swpaul#define WB_SIO_EESEL 0x00000800 20341502Swpaul#define WB_SIO_MII_CLK 0x00010000 /* MDIO clock */ 20441502Swpaul#define WB_SIO_MII_DATAIN 0x00020000 /* MDIO data out */ 20541502Swpaul#define WB_SIO_MII_DIR 0x00040000 /* MDIO dir */ 20641502Swpaul#define WB_SIO_MII_DATAOUT 0x00080000 /* MDIO data in */ 20741502Swpaul 20841502Swpaul#define WB_EECMD_WRITE 0x140 20941502Swpaul#define WB_EECMD_READ 0x180 21041502Swpaul#define WB_EECMD_ERASE 0x1c0 21141502Swpaul 21241502Swpaul/* 21341502Swpaul * Winbond TX/RX descriptor structure. 21441502Swpaul */ 21541502Swpaul 21641502Swpaulstruct wb_desc { 21741502Swpaul u_int32_t wb_status; 21841502Swpaul u_int32_t wb_ctl; 21941502Swpaul u_int32_t wb_ptr1; 22041502Swpaul u_int32_t wb_ptr2; 22141502Swpaul}; 22241502Swpaul 22341502Swpaul#define wb_data wb_ptr1 22441502Swpaul#define wb_next wb_ptr2 22541502Swpaul 22641502Swpaul#define WB_RXSTAT_CRCERR 0x00000002 22741502Swpaul#define WB_RXSTAT_DRIBBLE 0x00000004 22841502Swpaul#define WB_RXSTAT_MIIERR 0x00000008 22941502Swpaul#define WB_RXSTAT_LATEEVENT 0x00000040 23041502Swpaul#define WB_RXSTAT_GIANT 0x00000080 23141502Swpaul#define WB_RXSTAT_LASTFRAG 0x00000100 23241502Swpaul#define WB_RXSTAT_FIRSTFRAG 0x00000200 23341502Swpaul#define WB_RXSTAT_MULTICAST 0x00000400 23441502Swpaul#define WB_RXSTAT_RUNT 0x00000800 23541502Swpaul#define WB_RXSTAT_RXTYPE 0x00003000 23641502Swpaul#define WB_RXSTAT_RXERR 0x00008000 23741502Swpaul#define WB_RXSTAT_RXLEN 0x3FFF0000 23841502Swpaul#define WB_RXSTAT_RXCMP 0x40000000 23941502Swpaul#define WB_RXSTAT_OWN 0x80000000 24041502Swpaul 24141502Swpaul#define WB_RXBYTES(x) ((x & WB_RXSTAT_RXLEN) >> 16) 24241502Swpaul#define WB_RXSTAT (WB_RXSTAT_FIRSTFRAG|WB_RXSTAT_LASTFRAG|WB_RXSTAT_OWN) 24341502Swpaul 24441502Swpaul#define WB_RXCTL_BUFLEN1 0x00000FFF 24541502Swpaul#define WB_RXCTL_BUFLEN2 0x00FFF000 24641502Swpaul#define WB_RXCTL_RLINK 0x01000000 24741502Swpaul#define WB_RXCTL_RLAST 0x02000000 24841502Swpaul 24941502Swpaul#define WB_TXSTAT_DEFER 0x00000001 25041502Swpaul#define WB_TXSTAT_UNDERRUN 0x00000002 25141502Swpaul#define WB_TXSTAT_COLLCNT 0x00000078 25241502Swpaul#define WB_TXSTAT_SQE 0x00000080 25341502Swpaul#define WB_TXSTAT_ABORT 0x00000100 25441502Swpaul#define WB_TXSTAT_LATECOLL 0x00000200 25541502Swpaul#define WB_TXSTAT_NOCARRIER 0x00000400 25641502Swpaul#define WB_TXSTAT_CARRLOST 0x00000800 25741502Swpaul#define WB_TXSTAT_TXERR 0x00001000 25841502Swpaul#define WB_TXSTAT_OWN 0x80000000 25941502Swpaul 26041502Swpaul#define WB_TXCTL_BUFLEN1 0x000007FF 26141502Swpaul#define WB_TXCTL_BUFLEN2 0x003FF800 26241502Swpaul#define WB_TXCTL_PAD 0x00800000 26341502Swpaul#define WB_TXCTL_TLINK 0x01000000 26441502Swpaul#define WB_TXCTL_TLAST 0x02000000 26541502Swpaul#define WB_TXCTL_NOCRC 0x08000000 26641502Swpaul#define WB_TXCTL_FIRSTFRAG 0x20000000 26741502Swpaul#define WB_TXCTL_LASTFRAG 0x40000000 26841502Swpaul#define WB_TXCTL_FINT 0x80000000 26941502Swpaul 27041502Swpaul#define WB_MAXFRAGS 16 27141502Swpaul#define WB_RX_LIST_CNT 64 27246561Swpaul#define WB_TX_LIST_CNT 128 27341502Swpaul#define WB_MIN_FRAMELEN 60 27448745Swpaul#define ETHER_ALIGN 2 27541502Swpaul 27641502Swpaul/* 27741502Swpaul * A transmit 'super descriptor' is actually WB_MAXFRAGS regular 27841502Swpaul * descriptors clumped together. The idea here is to emulate the 27941502Swpaul * multi-fragment descriptor layout found in devices such as the 28041502Swpaul * Texas Instruments ThunderLAN and 3Com boomerang and cylone chips. 28141502Swpaul * The advantage to using this scheme is that it avoids buffer copies. 28241502Swpaul * The disadvantage is that there's a certain amount of overhead due 28341502Swpaul * to the fact that each 'fragment' is 16 bytes long. In my tests, 28441502Swpaul * this limits top speed to about 10.5MB/sec. It should be more like 28541502Swpaul * 11.5MB/sec. However, the upshot is that you can achieve better 28641502Swpaul * results on slower machines: a Pentium 200 can pump out packets at 28741502Swpaul * same speed as a PII 400. 28841502Swpaul */ 28941502Swpaulstruct wb_txdesc { 29041502Swpaul struct wb_desc wb_frag[WB_MAXFRAGS]; 29141502Swpaul}; 29241502Swpaul 29341502Swpaul#define WB_TXNEXT(x) x->wb_ptr->wb_frag[x->wb_lastdesc].wb_next 29441502Swpaul#define WB_TXSTATUS(x) x->wb_ptr->wb_frag[x->wb_lastdesc].wb_status 29541502Swpaul#define WB_TXCTL(x) x->wb_ptr->wb_frag[x->wb_lastdesc].wb_ctl 29641502Swpaul#define WB_TXDATA(x) x->wb_ptr->wb_frag[x->wb_lastdesc].wb_data 29741502Swpaul 29841502Swpaul#define WB_TXOWN(x) x->wb_ptr->wb_frag[0].wb_status 29941502Swpaul 30041502Swpaul#define WB_UNSENT 0x1234 30141502Swpaul 30250675Swpaul#define WB_BUFBYTES (1024 * sizeof(u_int32_t)) 30350675Swpaul 30450675Swpaulstruct wb_buf { 30550675Swpaul u_int32_t wb_data[1024]; 30650675Swpaul}; 30750675Swpaul 30841502Swpaulstruct wb_list_data { 30950675Swpaul struct wb_buf wb_rxbufs[WB_RX_LIST_CNT]; 31041502Swpaul struct wb_desc wb_rx_list[WB_RX_LIST_CNT]; 31141502Swpaul struct wb_txdesc wb_tx_list[WB_TX_LIST_CNT]; 31241502Swpaul}; 31341502Swpaul 31441502Swpaulstruct wb_chain { 31541502Swpaul struct wb_txdesc *wb_ptr; 31641502Swpaul struct mbuf *wb_mbuf; 31741502Swpaul struct wb_chain *wb_nextdesc; 31841502Swpaul u_int8_t wb_lastdesc; 31941502Swpaul}; 32041502Swpaul 32141502Swpaulstruct wb_chain_onefrag { 32241502Swpaul struct wb_desc *wb_ptr; 32341502Swpaul struct mbuf *wb_mbuf; 32450675Swpaul void *wb_buf; 32541502Swpaul struct wb_chain_onefrag *wb_nextdesc; 32641502Swpaul u_int8_t wb_rlast; 32741502Swpaul}; 32841502Swpaul 32941502Swpaulstruct wb_chain_data { 33041502Swpaul u_int8_t wb_pad[WB_MIN_FRAMELEN]; 33141502Swpaul struct wb_chain_onefrag wb_rx_chain[WB_RX_LIST_CNT]; 33241502Swpaul struct wb_chain wb_tx_chain[WB_TX_LIST_CNT]; 33341502Swpaul 33441502Swpaul struct wb_chain_onefrag *wb_rx_head; 33541502Swpaul 33641502Swpaul struct wb_chain *wb_tx_head; 33741502Swpaul struct wb_chain *wb_tx_tail; 33841502Swpaul struct wb_chain *wb_tx_free; 33941502Swpaul}; 34041502Swpaul 34141502Swpaulstruct wb_type { 34241502Swpaul u_int16_t wb_vid; 34341502Swpaul u_int16_t wb_did; 344226995Smarius const char *wb_name; 34541502Swpaul}; 34641502Swpaul 34741502Swpaulstruct wb_softc { 348147256Sbrooks struct ifnet *wb_ifp; /* interface info */ 349162317Sru device_t wb_dev; 35050675Swpaul device_t wb_miibus; 35149611Swpaul struct resource *wb_res; 35249611Swpaul struct resource *wb_irq; 35349611Swpaul void *wb_intrhand; 35449611Swpaul struct wb_type *wb_info; /* Winbond adapter info */ 35541502Swpaul u_int8_t wb_type; 35641502Swpaul u_int16_t wb_txthresh; 35750675Swpaul int wb_cachesize; 358199560Sjhb int wb_timer; 35941502Swpaul caddr_t wb_ldata_ptr; 36041502Swpaul struct wb_list_data *wb_ldata; 36141502Swpaul struct wb_chain_data wb_cdata; 362151774Sjhb struct callout wb_stat_callout; 36367087Swpaul struct mtx wb_mtx; 36441502Swpaul}; 36541502Swpaul 36672200Sbmilekic#define WB_LOCK(_sc) mtx_lock(&(_sc)->wb_mtx) 36772200Sbmilekic#define WB_UNLOCK(_sc) mtx_unlock(&(_sc)->wb_mtx) 368122689Ssam#define WB_LOCK_ASSERT(_sc) mtx_assert(&(_sc)->wb_mtx, MA_OWNED) 36967087Swpaul 37041502Swpaul/* 37141502Swpaul * register space access macros 37241502Swpaul */ 373199414Sjhb#define CSR_WRITE_4(sc, reg, val) bus_write_4(sc->wb_res, reg, val) 374199414Sjhb#define CSR_WRITE_2(sc, reg, val) bus_write_2(sc->wb_res, reg, val) 375199414Sjhb#define CSR_WRITE_1(sc, reg, val) bus_write_1(sc->wb_res, reg, val) 37641502Swpaul 377199414Sjhb#define CSR_READ_4(sc, reg) bus_read_4(sc->wb_res, reg) 378199414Sjhb#define CSR_READ_2(sc, reg) bus_read_2(sc->wb_res, reg) 379199414Sjhb#define CSR_READ_1(sc, reg) bus_read_1(sc->wb_res, reg) 38041502Swpaul 381226995Smarius#define CSR_BARRIER(sc, reg, length, flags) \ 382226995Smarius bus_barrier(sc->wb_res, reg, length, flags) 383226995Smarius 38441502Swpaul#define WB_TIMEOUT 1000 38541502Swpaul 38641502Swpaul/* 38741502Swpaul * General constants that are fun to know. 38841502Swpaul * 38941502Swpaul * Winbond PCI vendor ID 39041502Swpaul */ 39141502Swpaul#define WB_VENDORID 0x1050 39241502Swpaul 39341502Swpaul/* 39441502Swpaul * Winbond device IDs. 39541502Swpaul */ 39641502Swpaul#define WB_DEVICEID_840F 0x0840 39741502Swpaul 39841502Swpaul/* 39941502Swpaul * Compex vendor ID. 40041502Swpaul */ 40141502Swpaul#define CP_VENDORID 0x11F6 40241502Swpaul 40341502Swpaul/* 40441502Swpaul * Compex device IDs. 40541502Swpaul */ 40641502Swpaul#define CP_DEVICEID_RL100 0x2011 40741502Swpaul 40841502Swpaul/* 40941502Swpaul * PCI low memory base and low I/O base register, and 41050675Swpaul * other PCI registers. 41141502Swpaul */ 41241502Swpaul 41341502Swpaul#define WB_PCI_VENDOR_ID 0x00 41441502Swpaul#define WB_PCI_DEVICE_ID 0x02 41541502Swpaul#define WB_PCI_COMMAND 0x04 41641502Swpaul#define WB_PCI_STATUS 0x06 41741502Swpaul#define WB_PCI_CLASSCODE 0x09 41850675Swpaul#define WB_PCI_CACHELEN 0x0C 41941502Swpaul#define WB_PCI_LATENCY_TIMER 0x0D 42041502Swpaul#define WB_PCI_HEADER_TYPE 0x0E 42141502Swpaul#define WB_PCI_LOIO 0x10 42241502Swpaul#define WB_PCI_LOMEM 0x14 42341502Swpaul#define WB_PCI_BIOSROM 0x30 42441502Swpaul#define WB_PCI_INTLINE 0x3C 42541502Swpaul#define WB_PCI_INTPIN 0x3D 42641502Swpaul#define WB_PCI_MINGNT 0x3E 42741502Swpaul#define WB_PCI_MINLAT 0x0F 42841502Swpaul#define WB_PCI_RESETOPT 0x48 42941502Swpaul#define WB_PCI_EEPROM_DATA 0x4C 43041502Swpaul 43141502Swpaul/* power management registers */ 43241502Swpaul#define WB_PCI_CAPID 0xDC /* 8 bits */ 43341502Swpaul#define WB_PCI_NEXTPTR 0xDD /* 8 bits */ 43441502Swpaul#define WB_PCI_PWRMGMTCAP 0xDE /* 16 bits */ 43541502Swpaul#define WB_PCI_PWRMGMTCTRL 0xE0 /* 16 bits */ 43641502Swpaul 43741502Swpaul#define WB_PSTATE_MASK 0x0003 43841502Swpaul#define WB_PSTATE_D0 0x0000 43941502Swpaul#define WB_PSTATE_D1 0x0002 44041502Swpaul#define WB_PSTATE_D2 0x0002 44141502Swpaul#define WB_PSTATE_D3 0x0003 44241502Swpaul#define WB_PME_EN 0x0010 44341502Swpaul#define WB_PME_STATUS 0x8000 444