if_wb.c revision 72084
1/* 2 * Copyright (c) 1997, 1998 3 * Bill Paul <wpaul@ctr.columbia.edu>. All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 3. All advertising materials mentioning features or use of this software 14 * must display the following acknowledgement: 15 * This product includes software developed by Bill Paul. 16 * 4. Neither the name of the author nor the names of any co-contributors 17 * may be used to endorse or promote products derived from this software 18 * without specific prior written permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 21 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 30 * THE POSSIBILITY OF SUCH DAMAGE. 31 * 32 * $FreeBSD: head/sys/pci/if_wb.c 72084 2001-02-06 10:12:15Z phk $ 33 */ 34 35/* 36 * Winbond fast ethernet PCI NIC driver 37 * 38 * Supports various cheap network adapters based on the Winbond W89C840F 39 * fast ethernet controller chip. This includes adapters manufactured by 40 * Winbond itself and some made by Linksys. 41 * 42 * Written by Bill Paul <wpaul@ctr.columbia.edu> 43 * Electrical Engineering Department 44 * Columbia University, New York City 45 */ 46 47/* 48 * The Winbond W89C840F chip is a bus master; in some ways it resembles 49 * a DEC 'tulip' chip, only not as complicated. Unfortunately, it has 50 * one major difference which is that while the registers do many of 51 * the same things as a tulip adapter, the offsets are different: where 52 * tulip registers are typically spaced 8 bytes apart, the Winbond 53 * registers are spaced 4 bytes apart. The receiver filter is also 54 * programmed differently. 55 * 56 * Like the tulip, the Winbond chip uses small descriptors containing 57 * a status word, a control word and 32-bit areas that can either be used 58 * to point to two external data blocks, or to point to a single block 59 * and another descriptor in a linked list. Descriptors can be grouped 60 * together in blocks to form fixed length rings or can be chained 61 * together in linked lists. A single packet may be spread out over 62 * several descriptors if necessary. 63 * 64 * For the receive ring, this driver uses a linked list of descriptors, 65 * each pointing to a single mbuf cluster buffer, which us large enough 66 * to hold an entire packet. The link list is looped back to created a 67 * closed ring. 68 * 69 * For transmission, the driver creates a linked list of 'super descriptors' 70 * which each contain several individual descriptors linked toghether. 71 * Each 'super descriptor' contains WB_MAXFRAGS descriptors, which we 72 * abuse as fragment pointers. This allows us to use a buffer managment 73 * scheme very similar to that used in the ThunderLAN and Etherlink XL 74 * drivers. 75 * 76 * Autonegotiation is performed using the external PHY via the MII bus. 77 * The sample boards I have all use a Davicom PHY. 78 * 79 * Note: the author of the Linux driver for the Winbond chip alludes 80 * to some sort of flaw in the chip's design that seems to mandate some 81 * drastic workaround which signigicantly impairs transmit performance. 82 * I have no idea what he's on about: transmit performance with all 83 * three of my test boards seems fine. 84 */ 85 86#include "opt_bdg.h" 87 88#include <sys/param.h> 89#include <sys/systm.h> 90#include <sys/sockio.h> 91#include <sys/mbuf.h> 92#include <sys/malloc.h> 93#include <sys/kernel.h> 94#include <sys/socket.h> 95#include <sys/queue.h> 96 97#include <net/if.h> 98#include <net/if_arp.h> 99#include <net/ethernet.h> 100#include <net/if_dl.h> 101#include <net/if_media.h> 102 103#include <net/bpf.h> 104 105#include <vm/vm.h> /* for vtophys */ 106#include <vm/pmap.h> /* for vtophys */ 107#include <machine/bus_memio.h> 108#include <machine/bus_pio.h> 109#include <machine/bus.h> 110#include <machine/resource.h> 111#include <sys/bus.h> 112#include <sys/rman.h> 113 114#include <pci/pcireg.h> 115#include <pci/pcivar.h> 116 117#include <dev/mii/mii.h> 118#include <dev/mii/miivar.h> 119 120/* "controller miibus0" required. See GENERIC if you get errors here. */ 121#include "miibus_if.h" 122 123#define WB_USEIOSPACE 124 125#include <pci/if_wbreg.h> 126 127MODULE_DEPEND(wb, miibus, 1, 1, 1); 128 129#ifndef lint 130static const char rcsid[] = 131 "$FreeBSD: head/sys/pci/if_wb.c 72084 2001-02-06 10:12:15Z phk $"; 132#endif 133 134/* 135 * Various supported device vendors/types and their names. 136 */ 137static struct wb_type wb_devs[] = { 138 { WB_VENDORID, WB_DEVICEID_840F, 139 "Winbond W89C840F 10/100BaseTX" }, 140 { CP_VENDORID, CP_DEVICEID_RL100, 141 "Compex RL100-ATX 10/100baseTX" }, 142 { 0, 0, NULL } 143}; 144 145static int wb_probe __P((device_t)); 146static int wb_attach __P((device_t)); 147static int wb_detach __P((device_t)); 148 149static void wb_bfree __P((caddr_t, void *args)); 150static int wb_newbuf __P((struct wb_softc *, 151 struct wb_chain_onefrag *, 152 struct mbuf *)); 153static int wb_encap __P((struct wb_softc *, struct wb_chain *, 154 struct mbuf *)); 155 156static void wb_rxeof __P((struct wb_softc *)); 157static void wb_rxeoc __P((struct wb_softc *)); 158static void wb_txeof __P((struct wb_softc *)); 159static void wb_txeoc __P((struct wb_softc *)); 160static void wb_intr __P((void *)); 161static void wb_tick __P((void *)); 162static void wb_start __P((struct ifnet *)); 163static int wb_ioctl __P((struct ifnet *, u_long, caddr_t)); 164static void wb_init __P((void *)); 165static void wb_stop __P((struct wb_softc *)); 166static void wb_watchdog __P((struct ifnet *)); 167static void wb_shutdown __P((device_t)); 168static int wb_ifmedia_upd __P((struct ifnet *)); 169static void wb_ifmedia_sts __P((struct ifnet *, struct ifmediareq *)); 170 171static void wb_eeprom_putbyte __P((struct wb_softc *, int)); 172static void wb_eeprom_getword __P((struct wb_softc *, int, u_int16_t *)); 173static void wb_read_eeprom __P((struct wb_softc *, caddr_t, int, 174 int, int)); 175static void wb_mii_sync __P((struct wb_softc *)); 176static void wb_mii_send __P((struct wb_softc *, u_int32_t, int)); 177static int wb_mii_readreg __P((struct wb_softc *, struct wb_mii_frame *)); 178static int wb_mii_writereg __P((struct wb_softc *, struct wb_mii_frame *)); 179 180static void wb_setcfg __P((struct wb_softc *, u_int32_t)); 181static u_int8_t wb_calchash __P((caddr_t)); 182static void wb_setmulti __P((struct wb_softc *)); 183static void wb_reset __P((struct wb_softc *)); 184static void wb_fixmedia __P((struct wb_softc *)); 185static int wb_list_rx_init __P((struct wb_softc *)); 186static int wb_list_tx_init __P((struct wb_softc *)); 187 188static int wb_miibus_readreg __P((device_t, int, int)); 189static int wb_miibus_writereg __P((device_t, int, int, int)); 190static void wb_miibus_statchg __P((device_t)); 191 192#ifdef WB_USEIOSPACE 193#define WB_RES SYS_RES_IOPORT 194#define WB_RID WB_PCI_LOIO 195#else 196#define WB_RES SYS_RES_MEMORY 197#define WB_RID WB_PCI_LOMEM 198#endif 199 200static device_method_t wb_methods[] = { 201 /* Device interface */ 202 DEVMETHOD(device_probe, wb_probe), 203 DEVMETHOD(device_attach, wb_attach), 204 DEVMETHOD(device_detach, wb_detach), 205 DEVMETHOD(device_shutdown, wb_shutdown), 206 207 /* bus interface, for miibus */ 208 DEVMETHOD(bus_print_child, bus_generic_print_child), 209 DEVMETHOD(bus_driver_added, bus_generic_driver_added), 210 211 /* MII interface */ 212 DEVMETHOD(miibus_readreg, wb_miibus_readreg), 213 DEVMETHOD(miibus_writereg, wb_miibus_writereg), 214 DEVMETHOD(miibus_statchg, wb_miibus_statchg), 215 { 0, 0 } 216}; 217 218static driver_t wb_driver = { 219 "wb", 220 wb_methods, 221 sizeof(struct wb_softc) 222}; 223 224static devclass_t wb_devclass; 225 226DRIVER_MODULE(if_wb, pci, wb_driver, wb_devclass, 0, 0); 227DRIVER_MODULE(miibus, wb, miibus_driver, miibus_devclass, 0, 0); 228 229#define WB_SETBIT(sc, reg, x) \ 230 CSR_WRITE_4(sc, reg, \ 231 CSR_READ_4(sc, reg) | x) 232 233#define WB_CLRBIT(sc, reg, x) \ 234 CSR_WRITE_4(sc, reg, \ 235 CSR_READ_4(sc, reg) & ~x) 236 237#define SIO_SET(x) \ 238 CSR_WRITE_4(sc, WB_SIO, \ 239 CSR_READ_4(sc, WB_SIO) | x) 240 241#define SIO_CLR(x) \ 242 CSR_WRITE_4(sc, WB_SIO, \ 243 CSR_READ_4(sc, WB_SIO) & ~x) 244 245/* 246 * Send a read command and address to the EEPROM, check for ACK. 247 */ 248static void wb_eeprom_putbyte(sc, addr) 249 struct wb_softc *sc; 250 int addr; 251{ 252 register int d, i; 253 254 d = addr | WB_EECMD_READ; 255 256 /* 257 * Feed in each bit and stobe the clock. 258 */ 259 for (i = 0x400; i; i >>= 1) { 260 if (d & i) { 261 SIO_SET(WB_SIO_EE_DATAIN); 262 } else { 263 SIO_CLR(WB_SIO_EE_DATAIN); 264 } 265 DELAY(100); 266 SIO_SET(WB_SIO_EE_CLK); 267 DELAY(150); 268 SIO_CLR(WB_SIO_EE_CLK); 269 DELAY(100); 270 } 271 272 return; 273} 274 275/* 276 * Read a word of data stored in the EEPROM at address 'addr.' 277 */ 278static void wb_eeprom_getword(sc, addr, dest) 279 struct wb_softc *sc; 280 int addr; 281 u_int16_t *dest; 282{ 283 register int i; 284 u_int16_t word = 0; 285 286 /* Enter EEPROM access mode. */ 287 CSR_WRITE_4(sc, WB_SIO, WB_SIO_EESEL|WB_SIO_EE_CS); 288 289 /* 290 * Send address of word we want to read. 291 */ 292 wb_eeprom_putbyte(sc, addr); 293 294 CSR_WRITE_4(sc, WB_SIO, WB_SIO_EESEL|WB_SIO_EE_CS); 295 296 /* 297 * Start reading bits from EEPROM. 298 */ 299 for (i = 0x8000; i; i >>= 1) { 300 SIO_SET(WB_SIO_EE_CLK); 301 DELAY(100); 302 if (CSR_READ_4(sc, WB_SIO) & WB_SIO_EE_DATAOUT) 303 word |= i; 304 SIO_CLR(WB_SIO_EE_CLK); 305 DELAY(100); 306 } 307 308 /* Turn off EEPROM access mode. */ 309 CSR_WRITE_4(sc, WB_SIO, 0); 310 311 *dest = word; 312 313 return; 314} 315 316/* 317 * Read a sequence of words from the EEPROM. 318 */ 319static void wb_read_eeprom(sc, dest, off, cnt, swap) 320 struct wb_softc *sc; 321 caddr_t dest; 322 int off; 323 int cnt; 324 int swap; 325{ 326 int i; 327 u_int16_t word = 0, *ptr; 328 329 for (i = 0; i < cnt; i++) { 330 wb_eeprom_getword(sc, off + i, &word); 331 ptr = (u_int16_t *)(dest + (i * 2)); 332 if (swap) 333 *ptr = ntohs(word); 334 else 335 *ptr = word; 336 } 337 338 return; 339} 340 341/* 342 * Sync the PHYs by setting data bit and strobing the clock 32 times. 343 */ 344static void wb_mii_sync(sc) 345 struct wb_softc *sc; 346{ 347 register int i; 348 349 SIO_SET(WB_SIO_MII_DIR|WB_SIO_MII_DATAIN); 350 351 for (i = 0; i < 32; i++) { 352 SIO_SET(WB_SIO_MII_CLK); 353 DELAY(1); 354 SIO_CLR(WB_SIO_MII_CLK); 355 DELAY(1); 356 } 357 358 return; 359} 360 361/* 362 * Clock a series of bits through the MII. 363 */ 364static void wb_mii_send(sc, bits, cnt) 365 struct wb_softc *sc; 366 u_int32_t bits; 367 int cnt; 368{ 369 int i; 370 371 SIO_CLR(WB_SIO_MII_CLK); 372 373 for (i = (0x1 << (cnt - 1)); i; i >>= 1) { 374 if (bits & i) { 375 SIO_SET(WB_SIO_MII_DATAIN); 376 } else { 377 SIO_CLR(WB_SIO_MII_DATAIN); 378 } 379 DELAY(1); 380 SIO_CLR(WB_SIO_MII_CLK); 381 DELAY(1); 382 SIO_SET(WB_SIO_MII_CLK); 383 } 384} 385 386/* 387 * Read an PHY register through the MII. 388 */ 389static int wb_mii_readreg(sc, frame) 390 struct wb_softc *sc; 391 struct wb_mii_frame *frame; 392 393{ 394 int i, ack; 395 396 WB_LOCK(sc); 397 398 /* 399 * Set up frame for RX. 400 */ 401 frame->mii_stdelim = WB_MII_STARTDELIM; 402 frame->mii_opcode = WB_MII_READOP; 403 frame->mii_turnaround = 0; 404 frame->mii_data = 0; 405 406 CSR_WRITE_4(sc, WB_SIO, 0); 407 408 /* 409 * Turn on data xmit. 410 */ 411 SIO_SET(WB_SIO_MII_DIR); 412 413 wb_mii_sync(sc); 414 415 /* 416 * Send command/address info. 417 */ 418 wb_mii_send(sc, frame->mii_stdelim, 2); 419 wb_mii_send(sc, frame->mii_opcode, 2); 420 wb_mii_send(sc, frame->mii_phyaddr, 5); 421 wb_mii_send(sc, frame->mii_regaddr, 5); 422 423 /* Idle bit */ 424 SIO_CLR((WB_SIO_MII_CLK|WB_SIO_MII_DATAIN)); 425 DELAY(1); 426 SIO_SET(WB_SIO_MII_CLK); 427 DELAY(1); 428 429 /* Turn off xmit. */ 430 SIO_CLR(WB_SIO_MII_DIR); 431 /* Check for ack */ 432 SIO_CLR(WB_SIO_MII_CLK); 433 DELAY(1); 434 SIO_SET(WB_SIO_MII_CLK); 435 DELAY(1); 436 ack = CSR_READ_4(sc, WB_SIO) & WB_SIO_MII_DATAOUT; 437 SIO_CLR(WB_SIO_MII_CLK); 438 DELAY(1); 439 SIO_SET(WB_SIO_MII_CLK); 440 DELAY(1); 441 442 /* 443 * Now try reading data bits. If the ack failed, we still 444 * need to clock through 16 cycles to keep the PHY(s) in sync. 445 */ 446 if (ack) { 447 for(i = 0; i < 16; i++) { 448 SIO_CLR(WB_SIO_MII_CLK); 449 DELAY(1); 450 SIO_SET(WB_SIO_MII_CLK); 451 DELAY(1); 452 } 453 goto fail; 454 } 455 456 for (i = 0x8000; i; i >>= 1) { 457 SIO_CLR(WB_SIO_MII_CLK); 458 DELAY(1); 459 if (!ack) { 460 if (CSR_READ_4(sc, WB_SIO) & WB_SIO_MII_DATAOUT) 461 frame->mii_data |= i; 462 DELAY(1); 463 } 464 SIO_SET(WB_SIO_MII_CLK); 465 DELAY(1); 466 } 467 468fail: 469 470 SIO_CLR(WB_SIO_MII_CLK); 471 DELAY(1); 472 SIO_SET(WB_SIO_MII_CLK); 473 DELAY(1); 474 475 WB_UNLOCK(sc); 476 477 if (ack) 478 return(1); 479 return(0); 480} 481 482/* 483 * Write to a PHY register through the MII. 484 */ 485static int wb_mii_writereg(sc, frame) 486 struct wb_softc *sc; 487 struct wb_mii_frame *frame; 488 489{ 490 WB_LOCK(sc); 491 492 /* 493 * Set up frame for TX. 494 */ 495 496 frame->mii_stdelim = WB_MII_STARTDELIM; 497 frame->mii_opcode = WB_MII_WRITEOP; 498 frame->mii_turnaround = WB_MII_TURNAROUND; 499 500 /* 501 * Turn on data output. 502 */ 503 SIO_SET(WB_SIO_MII_DIR); 504 505 wb_mii_sync(sc); 506 507 wb_mii_send(sc, frame->mii_stdelim, 2); 508 wb_mii_send(sc, frame->mii_opcode, 2); 509 wb_mii_send(sc, frame->mii_phyaddr, 5); 510 wb_mii_send(sc, frame->mii_regaddr, 5); 511 wb_mii_send(sc, frame->mii_turnaround, 2); 512 wb_mii_send(sc, frame->mii_data, 16); 513 514 /* Idle bit. */ 515 SIO_SET(WB_SIO_MII_CLK); 516 DELAY(1); 517 SIO_CLR(WB_SIO_MII_CLK); 518 DELAY(1); 519 520 /* 521 * Turn off xmit. 522 */ 523 SIO_CLR(WB_SIO_MII_DIR); 524 525 WB_UNLOCK(sc); 526 527 return(0); 528} 529 530static int wb_miibus_readreg(dev, phy, reg) 531 device_t dev; 532 int phy, reg; 533{ 534 struct wb_softc *sc; 535 struct wb_mii_frame frame; 536 537 sc = device_get_softc(dev); 538 539 bzero((char *)&frame, sizeof(frame)); 540 541 frame.mii_phyaddr = phy; 542 frame.mii_regaddr = reg; 543 wb_mii_readreg(sc, &frame); 544 545 return(frame.mii_data); 546} 547 548static int wb_miibus_writereg(dev, phy, reg, data) 549 device_t dev; 550 int phy, reg, data; 551{ 552 struct wb_softc *sc; 553 struct wb_mii_frame frame; 554 555 sc = device_get_softc(dev); 556 557 bzero((char *)&frame, sizeof(frame)); 558 559 frame.mii_phyaddr = phy; 560 frame.mii_regaddr = reg; 561 frame.mii_data = data; 562 563 wb_mii_writereg(sc, &frame); 564 565 return(0); 566} 567 568static void wb_miibus_statchg(dev) 569 device_t dev; 570{ 571 struct wb_softc *sc; 572 struct mii_data *mii; 573 574 sc = device_get_softc(dev); 575 WB_LOCK(sc); 576 mii = device_get_softc(sc->wb_miibus); 577 wb_setcfg(sc, mii->mii_media_active); 578 WB_UNLOCK(sc); 579 580 return; 581} 582 583static u_int8_t wb_calchash(addr) 584 caddr_t addr; 585{ 586 u_int32_t crc, carry; 587 int i, j; 588 u_int8_t c; 589 590 /* Compute CRC for the address value. */ 591 crc = 0xFFFFFFFF; /* initial value */ 592 593 for (i = 0; i < 6; i++) { 594 c = *(addr + i); 595 for (j = 0; j < 8; j++) { 596 carry = ((crc & 0x80000000) ? 1 : 0) ^ (c & 0x01); 597 crc <<= 1; 598 c >>= 1; 599 if (carry) 600 crc = (crc ^ 0x04c11db6) | carry; 601 } 602 } 603 604 /* 605 * return the filter bit position 606 * Note: I arrived at the following nonsense 607 * through experimentation. It's not the usual way to 608 * generate the bit position but it's the only thing 609 * I could come up with that works. 610 */ 611 return(~(crc >> 26) & 0x0000003F); 612} 613 614/* 615 * Program the 64-bit multicast hash filter. 616 */ 617static void wb_setmulti(sc) 618 struct wb_softc *sc; 619{ 620 struct ifnet *ifp; 621 int h = 0; 622 u_int32_t hashes[2] = { 0, 0 }; 623 struct ifmultiaddr *ifma; 624 u_int32_t rxfilt; 625 int mcnt = 0; 626 627 ifp = &sc->arpcom.ac_if; 628 629 rxfilt = CSR_READ_4(sc, WB_NETCFG); 630 631 if (ifp->if_flags & IFF_ALLMULTI || ifp->if_flags & IFF_PROMISC) { 632 rxfilt |= WB_NETCFG_RX_MULTI; 633 CSR_WRITE_4(sc, WB_NETCFG, rxfilt); 634 CSR_WRITE_4(sc, WB_MAR0, 0xFFFFFFFF); 635 CSR_WRITE_4(sc, WB_MAR1, 0xFFFFFFFF); 636 return; 637 } 638 639 /* first, zot all the existing hash bits */ 640 CSR_WRITE_4(sc, WB_MAR0, 0); 641 CSR_WRITE_4(sc, WB_MAR1, 0); 642 643 /* now program new ones */ 644 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 645 if (ifma->ifma_addr->sa_family != AF_LINK) 646 continue; 647 h = wb_calchash(LLADDR((struct sockaddr_dl *)ifma->ifma_addr)); 648 if (h < 32) 649 hashes[0] |= (1 << h); 650 else 651 hashes[1] |= (1 << (h - 32)); 652 mcnt++; 653 } 654 655 if (mcnt) 656 rxfilt |= WB_NETCFG_RX_MULTI; 657 else 658 rxfilt &= ~WB_NETCFG_RX_MULTI; 659 660 CSR_WRITE_4(sc, WB_MAR0, hashes[0]); 661 CSR_WRITE_4(sc, WB_MAR1, hashes[1]); 662 CSR_WRITE_4(sc, WB_NETCFG, rxfilt); 663 664 return; 665} 666 667/* 668 * The Winbond manual states that in order to fiddle with the 669 * 'full-duplex' and '100Mbps' bits in the netconfig register, we 670 * first have to put the transmit and/or receive logic in the idle state. 671 */ 672static void wb_setcfg(sc, media) 673 struct wb_softc *sc; 674 u_int32_t media; 675{ 676 int i, restart = 0; 677 678 if (CSR_READ_4(sc, WB_NETCFG) & (WB_NETCFG_TX_ON|WB_NETCFG_RX_ON)) { 679 restart = 1; 680 WB_CLRBIT(sc, WB_NETCFG, (WB_NETCFG_TX_ON|WB_NETCFG_RX_ON)); 681 682 for (i = 0; i < WB_TIMEOUT; i++) { 683 DELAY(10); 684 if ((CSR_READ_4(sc, WB_ISR) & WB_ISR_TX_IDLE) && 685 (CSR_READ_4(sc, WB_ISR) & WB_ISR_RX_IDLE)) 686 break; 687 } 688 689 if (i == WB_TIMEOUT) 690 printf("wb%d: failed to force tx and " 691 "rx to idle state\n", sc->wb_unit); 692 } 693 694 if (IFM_SUBTYPE(media) == IFM_10_T) 695 WB_CLRBIT(sc, WB_NETCFG, WB_NETCFG_100MBPS); 696 else 697 WB_SETBIT(sc, WB_NETCFG, WB_NETCFG_100MBPS); 698 699 if ((media & IFM_GMASK) == IFM_FDX) 700 WB_SETBIT(sc, WB_NETCFG, WB_NETCFG_FULLDUPLEX); 701 else 702 WB_CLRBIT(sc, WB_NETCFG, WB_NETCFG_FULLDUPLEX); 703 704 if (restart) 705 WB_SETBIT(sc, WB_NETCFG, WB_NETCFG_TX_ON|WB_NETCFG_RX_ON); 706 707 return; 708} 709 710static void wb_reset(sc) 711 struct wb_softc *sc; 712{ 713 register int i; 714 struct mii_data *mii; 715 716 CSR_WRITE_4(sc, WB_NETCFG, 0); 717 CSR_WRITE_4(sc, WB_BUSCTL, 0); 718 CSR_WRITE_4(sc, WB_TXADDR, 0); 719 CSR_WRITE_4(sc, WB_RXADDR, 0); 720 721 WB_SETBIT(sc, WB_BUSCTL, WB_BUSCTL_RESET); 722 WB_SETBIT(sc, WB_BUSCTL, WB_BUSCTL_RESET); 723 724 for (i = 0; i < WB_TIMEOUT; i++) { 725 DELAY(10); 726 if (!(CSR_READ_4(sc, WB_BUSCTL) & WB_BUSCTL_RESET)) 727 break; 728 } 729 if (i == WB_TIMEOUT) 730 printf("wb%d: reset never completed!\n", sc->wb_unit); 731 732 /* Wait a little while for the chip to get its brains in order. */ 733 DELAY(1000); 734 735 if (sc->wb_miibus == NULL) 736 return; 737 738 mii = device_get_softc(sc->wb_miibus); 739 if (mii == NULL) 740 return; 741 742 if (mii->mii_instance) { 743 struct mii_softc *miisc; 744 LIST_FOREACH(miisc, &mii->mii_phys, mii_list) 745 mii_phy_reset(miisc); 746 } 747 748 return; 749} 750 751static void wb_fixmedia(sc) 752 struct wb_softc *sc; 753{ 754 struct mii_data *mii = NULL; 755 struct ifnet *ifp; 756 u_int32_t media; 757 758 if (sc->wb_miibus == NULL) 759 return; 760 761 mii = device_get_softc(sc->wb_miibus); 762 ifp = &sc->arpcom.ac_if; 763 764 mii_pollstat(mii); 765 if (IFM_SUBTYPE(mii->mii_media_active) == IFM_10_T) { 766 media = mii->mii_media_active & ~IFM_10_T; 767 media |= IFM_100_TX; 768 } else if (IFM_SUBTYPE(mii->mii_media_active) == IFM_100_TX) { 769 media = mii->mii_media_active & ~IFM_100_TX; 770 media |= IFM_10_T; 771 } else 772 return; 773 774 ifmedia_set(&mii->mii_media, media); 775 776 return; 777} 778 779/* 780 * Probe for a Winbond chip. Check the PCI vendor and device 781 * IDs against our list and return a device name if we find a match. 782 */ 783static int wb_probe(dev) 784 device_t dev; 785{ 786 struct wb_type *t; 787 788 t = wb_devs; 789 790 while(t->wb_name != NULL) { 791 if ((pci_get_vendor(dev) == t->wb_vid) && 792 (pci_get_device(dev) == t->wb_did)) { 793 device_set_desc(dev, t->wb_name); 794 return(0); 795 } 796 t++; 797 } 798 799 return(ENXIO); 800} 801 802/* 803 * Attach the interface. Allocate softc structures, do ifmedia 804 * setup and ethernet/BPF attach. 805 */ 806static int wb_attach(dev) 807 device_t dev; 808{ 809 u_char eaddr[ETHER_ADDR_LEN]; 810 u_int32_t command; 811 struct wb_softc *sc; 812 struct ifnet *ifp; 813 int unit, error = 0, rid; 814 815 sc = device_get_softc(dev); 816 unit = device_get_unit(dev); 817 818 mtx_init(&sc->wb_mtx, device_get_nameunit(dev), MTX_DEF | MTX_RECURSE); 819 WB_LOCK(sc); 820 821 /* 822 * Handle power management nonsense. 823 */ 824 825 command = pci_read_config(dev, WB_PCI_CAPID, 4) & 0x000000FF; 826 if (command == 0x01) { 827 828 command = pci_read_config(dev, WB_PCI_PWRMGMTCTRL, 4); 829 if (command & WB_PSTATE_MASK) { 830 u_int32_t iobase, membase, irq; 831 832 /* Save important PCI config data. */ 833 iobase = pci_read_config(dev, WB_PCI_LOIO, 4); 834 membase = pci_read_config(dev, WB_PCI_LOMEM, 4); 835 irq = pci_read_config(dev, WB_PCI_INTLINE, 4); 836 837 /* Reset the power state. */ 838 printf("wb%d: chip is in D%d power mode " 839 "-- setting to D0\n", unit, command & WB_PSTATE_MASK); 840 command &= 0xFFFFFFFC; 841 pci_write_config(dev, WB_PCI_PWRMGMTCTRL, command, 4); 842 843 /* Restore PCI config data. */ 844 pci_write_config(dev, WB_PCI_LOIO, iobase, 4); 845 pci_write_config(dev, WB_PCI_LOMEM, membase, 4); 846 pci_write_config(dev, WB_PCI_INTLINE, irq, 4); 847 } 848 } 849 850 /* 851 * Map control/status registers. 852 */ 853 command = pci_read_config(dev, PCIR_COMMAND, 4); 854 command |= (PCIM_CMD_PORTEN|PCIM_CMD_MEMEN|PCIM_CMD_BUSMASTEREN); 855 pci_write_config(dev, PCIR_COMMAND, command, 4); 856 command = pci_read_config(dev, PCIR_COMMAND, 4); 857 858#ifdef WB_USEIOSPACE 859 if (!(command & PCIM_CMD_PORTEN)) { 860 printf("wb%d: failed to enable I/O ports!\n", unit); 861 error = ENXIO; 862 goto fail; 863 } 864#else 865 if (!(command & PCIM_CMD_MEMEN)) { 866 printf("wb%d: failed to enable memory mapping!\n", unit); 867 error = ENXIO; 868 goto fail; 869 } 870#endif 871 872 rid = WB_RID; 873 sc->wb_res = bus_alloc_resource(dev, WB_RES, &rid, 874 0, ~0, 1, RF_ACTIVE); 875 876 if (sc->wb_res == NULL) { 877 printf("wb%d: couldn't map ports/memory\n", unit); 878 error = ENXIO; 879 goto fail; 880 } 881 882 sc->wb_btag = rman_get_bustag(sc->wb_res); 883 sc->wb_bhandle = rman_get_bushandle(sc->wb_res); 884 885 /* Allocate interrupt */ 886 rid = 0; 887 sc->wb_irq = bus_alloc_resource(dev, SYS_RES_IRQ, &rid, 0, ~0, 1, 888 RF_SHAREABLE | RF_ACTIVE); 889 890 if (sc->wb_irq == NULL) { 891 printf("wb%d: couldn't map interrupt\n", unit); 892 bus_release_resource(dev, WB_RES, WB_RID, sc->wb_res); 893 error = ENXIO; 894 goto fail; 895 } 896 897 error = bus_setup_intr(dev, sc->wb_irq, INTR_TYPE_NET, 898 wb_intr, sc, &sc->wb_intrhand); 899 900 if (error) { 901 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->wb_irq); 902 bus_release_resource(dev, WB_RES, WB_RID, sc->wb_res); 903 printf("wb%d: couldn't set up irq\n", unit); 904 goto fail; 905 } 906 907 /* Save the cache line size. */ 908 sc->wb_cachesize = pci_read_config(dev, WB_PCI_CACHELEN, 4) & 0xFF; 909 910 /* Reset the adapter. */ 911 wb_reset(sc); 912 913 /* 914 * Get station address from the EEPROM. 915 */ 916 wb_read_eeprom(sc, (caddr_t)&eaddr, 0, 3, 0); 917 918 /* 919 * A Winbond chip was detected. Inform the world. 920 */ 921 printf("wb%d: Ethernet address: %6D\n", unit, eaddr, ":"); 922 923 sc->wb_unit = unit; 924 bcopy(eaddr, (char *)&sc->arpcom.ac_enaddr, ETHER_ADDR_LEN); 925 926 sc->wb_ldata = contigmalloc(sizeof(struct wb_list_data) + 8, M_DEVBUF, 927 M_NOWAIT, 0, 0xffffffff, PAGE_SIZE, 0); 928 929 if (sc->wb_ldata == NULL) { 930 printf("wb%d: no memory for list buffers!\n", unit); 931 bus_teardown_intr(dev, sc->wb_irq, sc->wb_intrhand); 932 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->wb_irq); 933 bus_release_resource(dev, WB_RES, WB_RID, sc->wb_res); 934 error = ENXIO; 935 goto fail; 936 } 937 938 bzero(sc->wb_ldata, sizeof(struct wb_list_data)); 939 940 ifp = &sc->arpcom.ac_if; 941 ifp->if_softc = sc; 942 ifp->if_unit = unit; 943 ifp->if_name = "wb"; 944 ifp->if_mtu = ETHERMTU; 945 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 946 ifp->if_ioctl = wb_ioctl; 947 ifp->if_output = ether_output; 948 ifp->if_start = wb_start; 949 ifp->if_watchdog = wb_watchdog; 950 ifp->if_init = wb_init; 951 ifp->if_baudrate = 10000000; 952 ifp->if_snd.ifq_maxlen = WB_TX_LIST_CNT - 1; 953 954 /* 955 * Do MII setup. 956 */ 957 if (mii_phy_probe(dev, &sc->wb_miibus, 958 wb_ifmedia_upd, wb_ifmedia_sts)) { 959 bus_teardown_intr(dev, sc->wb_irq, sc->wb_intrhand); 960 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->wb_irq); 961 bus_release_resource(dev, WB_RES, WB_RID, sc->wb_res); 962 free(sc->wb_ldata_ptr, M_DEVBUF); 963 error = ENXIO; 964 goto fail; 965 } 966 967 /* 968 * Call MI attach routine. 969 */ 970 ether_ifattach(ifp, ETHER_BPF_SUPPORTED); 971 WB_UNLOCK(sc); 972 return(0); 973 974fail: 975 if (error) 976 device_delete_child(dev, sc->wb_miibus); 977 WB_UNLOCK(sc); 978 mtx_destroy(&sc->wb_mtx); 979 980 return(error); 981} 982 983static int wb_detach(dev) 984 device_t dev; 985{ 986 struct wb_softc *sc; 987 struct ifnet *ifp; 988 989 sc = device_get_softc(dev); 990 WB_LOCK(sc); 991 ifp = &sc->arpcom.ac_if; 992 993 wb_stop(sc); 994 ether_ifdetach(ifp, ETHER_BPF_SUPPORTED); 995 996 /* Delete any miibus and phy devices attached to this interface */ 997 bus_generic_detach(dev); 998 device_delete_child(dev, sc->wb_miibus); 999 1000 bus_teardown_intr(dev, sc->wb_irq, sc->wb_intrhand); 1001 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->wb_irq); 1002 bus_release_resource(dev, WB_RES, WB_RID, sc->wb_res); 1003 1004 free(sc->wb_ldata_ptr, M_DEVBUF); 1005 1006 WB_UNLOCK(sc); 1007 mtx_destroy(&sc->wb_mtx); 1008 1009 return(0); 1010} 1011 1012/* 1013 * Initialize the transmit descriptors. 1014 */ 1015static int wb_list_tx_init(sc) 1016 struct wb_softc *sc; 1017{ 1018 struct wb_chain_data *cd; 1019 struct wb_list_data *ld; 1020 int i; 1021 1022 cd = &sc->wb_cdata; 1023 ld = sc->wb_ldata; 1024 1025 for (i = 0; i < WB_TX_LIST_CNT; i++) { 1026 cd->wb_tx_chain[i].wb_ptr = &ld->wb_tx_list[i]; 1027 if (i == (WB_TX_LIST_CNT - 1)) { 1028 cd->wb_tx_chain[i].wb_nextdesc = 1029 &cd->wb_tx_chain[0]; 1030 } else { 1031 cd->wb_tx_chain[i].wb_nextdesc = 1032 &cd->wb_tx_chain[i + 1]; 1033 } 1034 } 1035 1036 cd->wb_tx_free = &cd->wb_tx_chain[0]; 1037 cd->wb_tx_tail = cd->wb_tx_head = NULL; 1038 1039 return(0); 1040} 1041 1042 1043/* 1044 * Initialize the RX descriptors and allocate mbufs for them. Note that 1045 * we arrange the descriptors in a closed ring, so that the last descriptor 1046 * points back to the first. 1047 */ 1048static int wb_list_rx_init(sc) 1049 struct wb_softc *sc; 1050{ 1051 struct wb_chain_data *cd; 1052 struct wb_list_data *ld; 1053 int i; 1054 1055 cd = &sc->wb_cdata; 1056 ld = sc->wb_ldata; 1057 1058 for (i = 0; i < WB_RX_LIST_CNT; i++) { 1059 cd->wb_rx_chain[i].wb_ptr = 1060 (struct wb_desc *)&ld->wb_rx_list[i]; 1061 cd->wb_rx_chain[i].wb_buf = (void *)&ld->wb_rxbufs[i]; 1062 if (wb_newbuf(sc, &cd->wb_rx_chain[i], NULL) == ENOBUFS) 1063 return(ENOBUFS); 1064 if (i == (WB_RX_LIST_CNT - 1)) { 1065 cd->wb_rx_chain[i].wb_nextdesc = &cd->wb_rx_chain[0]; 1066 ld->wb_rx_list[i].wb_next = 1067 vtophys(&ld->wb_rx_list[0]); 1068 } else { 1069 cd->wb_rx_chain[i].wb_nextdesc = 1070 &cd->wb_rx_chain[i + 1]; 1071 ld->wb_rx_list[i].wb_next = 1072 vtophys(&ld->wb_rx_list[i + 1]); 1073 } 1074 } 1075 1076 cd->wb_rx_head = &cd->wb_rx_chain[0]; 1077 1078 return(0); 1079} 1080 1081static void wb_bfree(buf, args) 1082 caddr_t buf; 1083 void *args; 1084{ 1085 return; 1086} 1087 1088/* 1089 * Initialize an RX descriptor and attach an MBUF cluster. 1090 */ 1091static int wb_newbuf(sc, c, m) 1092 struct wb_softc *sc; 1093 struct wb_chain_onefrag *c; 1094 struct mbuf *m; 1095{ 1096 struct mbuf *m_new = NULL; 1097 1098 if (m == NULL) { 1099 MGETHDR(m_new, M_DONTWAIT, MT_DATA); 1100 if (m_new == NULL) { 1101 printf("wb%d: no memory for rx " 1102 "list -- packet dropped!\n", sc->wb_unit); 1103 return(ENOBUFS); 1104 } 1105 m_new->m_data = c->wb_buf; 1106 m_new->m_pkthdr.len = m_new->m_len = WB_BUFBYTES; 1107 MEXTADD(m_new, c->wb_buf, WB_BUFBYTES, wb_bfree, NULL, 0, 1108 EXT_NET_DRV); 1109 } else { 1110 m_new = m; 1111 m_new->m_len = m_new->m_pkthdr.len = WB_BUFBYTES; 1112 m_new->m_data = m_new->m_ext.ext_buf; 1113 } 1114 1115 m_adj(m_new, sizeof(u_int64_t)); 1116 1117 c->wb_mbuf = m_new; 1118 c->wb_ptr->wb_data = vtophys(mtod(m_new, caddr_t)); 1119 c->wb_ptr->wb_ctl = WB_RXCTL_RLINK | 1536; 1120 c->wb_ptr->wb_status = WB_RXSTAT; 1121 1122 return(0); 1123} 1124 1125/* 1126 * A frame has been uploaded: pass the resulting mbuf chain up to 1127 * the higher level protocols. 1128 */ 1129static void wb_rxeof(sc) 1130 struct wb_softc *sc; 1131{ 1132 struct ether_header *eh; 1133 struct mbuf *m = NULL; 1134 struct ifnet *ifp; 1135 struct wb_chain_onefrag *cur_rx; 1136 int total_len = 0; 1137 u_int32_t rxstat; 1138 1139 ifp = &sc->arpcom.ac_if; 1140 1141 while(!((rxstat = sc->wb_cdata.wb_rx_head->wb_ptr->wb_status) & 1142 WB_RXSTAT_OWN)) { 1143 struct mbuf *m0 = NULL; 1144 1145 cur_rx = sc->wb_cdata.wb_rx_head; 1146 sc->wb_cdata.wb_rx_head = cur_rx->wb_nextdesc; 1147 1148 m = cur_rx->wb_mbuf; 1149 1150 if ((rxstat & WB_RXSTAT_MIIERR) || 1151 (WB_RXBYTES(cur_rx->wb_ptr->wb_status) < WB_MIN_FRAMELEN) || 1152 (WB_RXBYTES(cur_rx->wb_ptr->wb_status) > 1536) || 1153 !(rxstat & WB_RXSTAT_LASTFRAG) || 1154 !(rxstat & WB_RXSTAT_RXCMP)) { 1155 ifp->if_ierrors++; 1156 wb_newbuf(sc, cur_rx, m); 1157 printf("wb%x: receiver babbling: possible chip " 1158 "bug, forcing reset\n", sc->wb_unit); 1159 wb_fixmedia(sc); 1160 wb_reset(sc); 1161 wb_init(sc); 1162 return; 1163 } 1164 1165 if (rxstat & WB_RXSTAT_RXERR) { 1166 ifp->if_ierrors++; 1167 wb_newbuf(sc, cur_rx, m); 1168 break; 1169 } 1170 1171 /* No errors; receive the packet. */ 1172 total_len = WB_RXBYTES(cur_rx->wb_ptr->wb_status); 1173 1174 /* 1175 * XXX The Winbond chip includes the CRC with every 1176 * received frame, and there's no way to turn this 1177 * behavior off (at least, I can't find anything in 1178 * the manual that explains how to do it) so we have 1179 * to trim off the CRC manually. 1180 */ 1181 total_len -= ETHER_CRC_LEN; 1182 1183 m0 = m_devget(mtod(m, char *) - ETHER_ALIGN, 1184 total_len + ETHER_ALIGN, 0, ifp, NULL); 1185 wb_newbuf(sc, cur_rx, m); 1186 if (m0 == NULL) { 1187 ifp->if_ierrors++; 1188 break; 1189 } 1190 m_adj(m0, ETHER_ALIGN); 1191 m = m0; 1192 1193 ifp->if_ipackets++; 1194 eh = mtod(m, struct ether_header *); 1195 1196 /* Remove header from mbuf and pass it on. */ 1197 m_adj(m, sizeof(struct ether_header)); 1198 ether_input(ifp, eh, m); 1199 } 1200} 1201 1202void wb_rxeoc(sc) 1203 struct wb_softc *sc; 1204{ 1205 wb_rxeof(sc); 1206 1207 WB_CLRBIT(sc, WB_NETCFG, WB_NETCFG_RX_ON); 1208 CSR_WRITE_4(sc, WB_RXADDR, vtophys(&sc->wb_ldata->wb_rx_list[0])); 1209 WB_SETBIT(sc, WB_NETCFG, WB_NETCFG_RX_ON); 1210 if (CSR_READ_4(sc, WB_ISR) & WB_RXSTATE_SUSPEND) 1211 CSR_WRITE_4(sc, WB_RXSTART, 0xFFFFFFFF); 1212 1213 return; 1214} 1215 1216/* 1217 * A frame was downloaded to the chip. It's safe for us to clean up 1218 * the list buffers. 1219 */ 1220static void wb_txeof(sc) 1221 struct wb_softc *sc; 1222{ 1223 struct wb_chain *cur_tx; 1224 struct ifnet *ifp; 1225 1226 ifp = &sc->arpcom.ac_if; 1227 1228 /* Clear the timeout timer. */ 1229 ifp->if_timer = 0; 1230 1231 if (sc->wb_cdata.wb_tx_head == NULL) 1232 return; 1233 1234 /* 1235 * Go through our tx list and free mbufs for those 1236 * frames that have been transmitted. 1237 */ 1238 while(sc->wb_cdata.wb_tx_head->wb_mbuf != NULL) { 1239 u_int32_t txstat; 1240 1241 cur_tx = sc->wb_cdata.wb_tx_head; 1242 txstat = WB_TXSTATUS(cur_tx); 1243 1244 if ((txstat & WB_TXSTAT_OWN) || txstat == WB_UNSENT) 1245 break; 1246 1247 if (txstat & WB_TXSTAT_TXERR) { 1248 ifp->if_oerrors++; 1249 if (txstat & WB_TXSTAT_ABORT) 1250 ifp->if_collisions++; 1251 if (txstat & WB_TXSTAT_LATECOLL) 1252 ifp->if_collisions++; 1253 } 1254 1255 ifp->if_collisions += (txstat & WB_TXSTAT_COLLCNT) >> 3; 1256 1257 ifp->if_opackets++; 1258 m_freem(cur_tx->wb_mbuf); 1259 cur_tx->wb_mbuf = NULL; 1260 1261 if (sc->wb_cdata.wb_tx_head == sc->wb_cdata.wb_tx_tail) { 1262 sc->wb_cdata.wb_tx_head = NULL; 1263 sc->wb_cdata.wb_tx_tail = NULL; 1264 break; 1265 } 1266 1267 sc->wb_cdata.wb_tx_head = cur_tx->wb_nextdesc; 1268 } 1269 1270 return; 1271} 1272 1273/* 1274 * TX 'end of channel' interrupt handler. 1275 */ 1276static void wb_txeoc(sc) 1277 struct wb_softc *sc; 1278{ 1279 struct ifnet *ifp; 1280 1281 ifp = &sc->arpcom.ac_if; 1282 1283 ifp->if_timer = 0; 1284 1285 if (sc->wb_cdata.wb_tx_head == NULL) { 1286 ifp->if_flags &= ~IFF_OACTIVE; 1287 sc->wb_cdata.wb_tx_tail = NULL; 1288 } else { 1289 if (WB_TXOWN(sc->wb_cdata.wb_tx_head) == WB_UNSENT) { 1290 WB_TXOWN(sc->wb_cdata.wb_tx_head) = WB_TXSTAT_OWN; 1291 ifp->if_timer = 5; 1292 CSR_WRITE_4(sc, WB_TXSTART, 0xFFFFFFFF); 1293 } 1294 } 1295 1296 return; 1297} 1298 1299static void wb_intr(arg) 1300 void *arg; 1301{ 1302 struct wb_softc *sc; 1303 struct ifnet *ifp; 1304 u_int32_t status; 1305 1306 sc = arg; 1307 WB_LOCK(sc); 1308 ifp = &sc->arpcom.ac_if; 1309 1310 if (!(ifp->if_flags & IFF_UP)) { 1311 WB_UNLOCK(sc); 1312 return; 1313 } 1314 1315 /* Disable interrupts. */ 1316 CSR_WRITE_4(sc, WB_IMR, 0x00000000); 1317 1318 for (;;) { 1319 1320 status = CSR_READ_4(sc, WB_ISR); 1321 if (status) 1322 CSR_WRITE_4(sc, WB_ISR, status); 1323 1324 if ((status & WB_INTRS) == 0) 1325 break; 1326 1327 if ((status & WB_ISR_RX_NOBUF) || (status & WB_ISR_RX_ERR)) { 1328 ifp->if_ierrors++; 1329 wb_reset(sc); 1330 if (status & WB_ISR_RX_ERR) 1331 wb_fixmedia(sc); 1332 wb_init(sc); 1333 continue; 1334 } 1335 1336 if (status & WB_ISR_RX_OK) 1337 wb_rxeof(sc); 1338 1339 if (status & WB_ISR_RX_IDLE) 1340 wb_rxeoc(sc); 1341 1342 if (status & WB_ISR_TX_OK) 1343 wb_txeof(sc); 1344 1345 if (status & WB_ISR_TX_NOBUF) 1346 wb_txeoc(sc); 1347 1348 if (status & WB_ISR_TX_IDLE) { 1349 wb_txeof(sc); 1350 if (sc->wb_cdata.wb_tx_head != NULL) { 1351 WB_SETBIT(sc, WB_NETCFG, WB_NETCFG_TX_ON); 1352 CSR_WRITE_4(sc, WB_TXSTART, 0xFFFFFFFF); 1353 } 1354 } 1355 1356 if (status & WB_ISR_TX_UNDERRUN) { 1357 ifp->if_oerrors++; 1358 wb_txeof(sc); 1359 WB_CLRBIT(sc, WB_NETCFG, WB_NETCFG_TX_ON); 1360 /* Jack up TX threshold */ 1361 sc->wb_txthresh += WB_TXTHRESH_CHUNK; 1362 WB_CLRBIT(sc, WB_NETCFG, WB_NETCFG_TX_THRESH); 1363 WB_SETBIT(sc, WB_NETCFG, WB_TXTHRESH(sc->wb_txthresh)); 1364 WB_SETBIT(sc, WB_NETCFG, WB_NETCFG_TX_ON); 1365 } 1366 1367 if (status & WB_ISR_BUS_ERR) { 1368 wb_reset(sc); 1369 wb_init(sc); 1370 } 1371 1372 } 1373 1374 /* Re-enable interrupts. */ 1375 CSR_WRITE_4(sc, WB_IMR, WB_INTRS); 1376 1377 if (ifp->if_snd.ifq_head != NULL) { 1378 wb_start(ifp); 1379 } 1380 1381 WB_UNLOCK(sc); 1382 1383 return; 1384} 1385 1386static void wb_tick(xsc) 1387 void *xsc; 1388{ 1389 struct wb_softc *sc; 1390 struct mii_data *mii; 1391 1392 sc = xsc; 1393 WB_LOCK(sc); 1394 mii = device_get_softc(sc->wb_miibus); 1395 1396 mii_tick(mii); 1397 1398 sc->wb_stat_ch = timeout(wb_tick, sc, hz); 1399 1400 WB_UNLOCK(sc); 1401 1402 return; 1403} 1404 1405/* 1406 * Encapsulate an mbuf chain in a descriptor by coupling the mbuf data 1407 * pointers to the fragment pointers. 1408 */ 1409static int wb_encap(sc, c, m_head) 1410 struct wb_softc *sc; 1411 struct wb_chain *c; 1412 struct mbuf *m_head; 1413{ 1414 int frag = 0; 1415 struct wb_desc *f = NULL; 1416 int total_len; 1417 struct mbuf *m; 1418 1419 /* 1420 * Start packing the mbufs in this chain into 1421 * the fragment pointers. Stop when we run out 1422 * of fragments or hit the end of the mbuf chain. 1423 */ 1424 m = m_head; 1425 total_len = 0; 1426 1427 for (m = m_head, frag = 0; m != NULL; m = m->m_next) { 1428 if (m->m_len != 0) { 1429 if (frag == WB_MAXFRAGS) 1430 break; 1431 total_len += m->m_len; 1432 f = &c->wb_ptr->wb_frag[frag]; 1433 f->wb_ctl = WB_TXCTL_TLINK | m->m_len; 1434 if (frag == 0) { 1435 f->wb_ctl |= WB_TXCTL_FIRSTFRAG; 1436 f->wb_status = 0; 1437 } else 1438 f->wb_status = WB_TXSTAT_OWN; 1439 f->wb_next = vtophys(&c->wb_ptr->wb_frag[frag + 1]); 1440 f->wb_data = vtophys(mtod(m, vm_offset_t)); 1441 frag++; 1442 } 1443 } 1444 1445 /* 1446 * Handle special case: we used up all 16 fragments, 1447 * but we have more mbufs left in the chain. Copy the 1448 * data into an mbuf cluster. Note that we don't 1449 * bother clearing the values in the other fragment 1450 * pointers/counters; it wouldn't gain us anything, 1451 * and would waste cycles. 1452 */ 1453 if (m != NULL) { 1454 struct mbuf *m_new = NULL; 1455 1456 MGETHDR(m_new, M_DONTWAIT, MT_DATA); 1457 if (m_new == NULL) { 1458 printf("wb%d: no memory for tx list", sc->wb_unit); 1459 return(1); 1460 } 1461 if (m_head->m_pkthdr.len > MHLEN) { 1462 MCLGET(m_new, M_DONTWAIT); 1463 if (!(m_new->m_flags & M_EXT)) { 1464 m_freem(m_new); 1465 printf("wb%d: no memory for tx list", 1466 sc->wb_unit); 1467 return(1); 1468 } 1469 } 1470 m_copydata(m_head, 0, m_head->m_pkthdr.len, 1471 mtod(m_new, caddr_t)); 1472 m_new->m_pkthdr.len = m_new->m_len = m_head->m_pkthdr.len; 1473 m_freem(m_head); 1474 m_head = m_new; 1475 f = &c->wb_ptr->wb_frag[0]; 1476 f->wb_status = 0; 1477 f->wb_data = vtophys(mtod(m_new, caddr_t)); 1478 f->wb_ctl = total_len = m_new->m_len; 1479 f->wb_ctl |= WB_TXCTL_TLINK|WB_TXCTL_FIRSTFRAG; 1480 frag = 1; 1481 } 1482 1483 if (total_len < WB_MIN_FRAMELEN) { 1484 f = &c->wb_ptr->wb_frag[frag]; 1485 f->wb_ctl = WB_MIN_FRAMELEN - total_len; 1486 f->wb_data = vtophys(&sc->wb_cdata.wb_pad); 1487 f->wb_ctl |= WB_TXCTL_TLINK; 1488 f->wb_status = WB_TXSTAT_OWN; 1489 frag++; 1490 } 1491 1492 c->wb_mbuf = m_head; 1493 c->wb_lastdesc = frag - 1; 1494 WB_TXCTL(c) |= WB_TXCTL_LASTFRAG; 1495 WB_TXNEXT(c) = vtophys(&c->wb_nextdesc->wb_ptr->wb_frag[0]); 1496 1497 return(0); 1498} 1499 1500/* 1501 * Main transmit routine. To avoid having to do mbuf copies, we put pointers 1502 * to the mbuf data regions directly in the transmit lists. We also save a 1503 * copy of the pointers since the transmit list fragment pointers are 1504 * physical addresses. 1505 */ 1506 1507static void wb_start(ifp) 1508 struct ifnet *ifp; 1509{ 1510 struct wb_softc *sc; 1511 struct mbuf *m_head = NULL; 1512 struct wb_chain *cur_tx = NULL, *start_tx; 1513 1514 sc = ifp->if_softc; 1515 WB_LOCK(sc); 1516 1517 /* 1518 * Check for an available queue slot. If there are none, 1519 * punt. 1520 */ 1521 if (sc->wb_cdata.wb_tx_free->wb_mbuf != NULL) { 1522 ifp->if_flags |= IFF_OACTIVE; 1523 WB_UNLOCK(sc); 1524 return; 1525 } 1526 1527 start_tx = sc->wb_cdata.wb_tx_free; 1528 1529 while(sc->wb_cdata.wb_tx_free->wb_mbuf == NULL) { 1530 IF_DEQUEUE(&ifp->if_snd, m_head); 1531 if (m_head == NULL) 1532 break; 1533 1534 /* Pick a descriptor off the free list. */ 1535 cur_tx = sc->wb_cdata.wb_tx_free; 1536 sc->wb_cdata.wb_tx_free = cur_tx->wb_nextdesc; 1537 1538 /* Pack the data into the descriptor. */ 1539 wb_encap(sc, cur_tx, m_head); 1540 1541 if (cur_tx != start_tx) 1542 WB_TXOWN(cur_tx) = WB_TXSTAT_OWN; 1543 1544 /* 1545 * If there's a BPF listener, bounce a copy of this frame 1546 * to him. 1547 */ 1548 if (ifp->if_bpf) 1549 bpf_mtap(ifp, cur_tx->wb_mbuf); 1550 } 1551 1552 /* 1553 * If there are no packets queued, bail. 1554 */ 1555 if (cur_tx == NULL) { 1556 WB_UNLOCK(sc); 1557 return; 1558 } 1559 1560 /* 1561 * Place the request for the upload interrupt 1562 * in the last descriptor in the chain. This way, if 1563 * we're chaining several packets at once, we'll only 1564 * get an interupt once for the whole chain rather than 1565 * once for each packet. 1566 */ 1567 WB_TXCTL(cur_tx) |= WB_TXCTL_FINT; 1568 cur_tx->wb_ptr->wb_frag[0].wb_ctl |= WB_TXCTL_FINT; 1569 sc->wb_cdata.wb_tx_tail = cur_tx; 1570 1571 if (sc->wb_cdata.wb_tx_head == NULL) { 1572 sc->wb_cdata.wb_tx_head = start_tx; 1573 WB_TXOWN(start_tx) = WB_TXSTAT_OWN; 1574 CSR_WRITE_4(sc, WB_TXSTART, 0xFFFFFFFF); 1575 } else { 1576 /* 1577 * We need to distinguish between the case where 1578 * the own bit is clear because the chip cleared it 1579 * and where the own bit is clear because we haven't 1580 * set it yet. The magic value WB_UNSET is just some 1581 * ramdomly chosen number which doesn't have the own 1582 * bit set. When we actually transmit the frame, the 1583 * status word will have _only_ the own bit set, so 1584 * the txeoc handler will be able to tell if it needs 1585 * to initiate another transmission to flush out pending 1586 * frames. 1587 */ 1588 WB_TXOWN(start_tx) = WB_UNSENT; 1589 } 1590 1591 /* 1592 * Set a timeout in case the chip goes out to lunch. 1593 */ 1594 ifp->if_timer = 5; 1595 WB_UNLOCK(sc); 1596 1597 return; 1598} 1599 1600static void wb_init(xsc) 1601 void *xsc; 1602{ 1603 struct wb_softc *sc = xsc; 1604 struct ifnet *ifp = &sc->arpcom.ac_if; 1605 int i; 1606 struct mii_data *mii; 1607 1608 WB_LOCK(sc); 1609 mii = device_get_softc(sc->wb_miibus); 1610 1611 /* 1612 * Cancel pending I/O and free all RX/TX buffers. 1613 */ 1614 wb_stop(sc); 1615 wb_reset(sc); 1616 1617 sc->wb_txthresh = WB_TXTHRESH_INIT; 1618 1619 /* 1620 * Set cache alignment and burst length. 1621 */ 1622#ifdef foo 1623 CSR_WRITE_4(sc, WB_BUSCTL, WB_BUSCTL_CONFIG); 1624 WB_CLRBIT(sc, WB_NETCFG, WB_NETCFG_TX_THRESH); 1625 WB_SETBIT(sc, WB_NETCFG, WB_TXTHRESH(sc->wb_txthresh)); 1626#endif 1627 1628 CSR_WRITE_4(sc, WB_BUSCTL, WB_BUSCTL_MUSTBEONE|WB_BUSCTL_ARBITRATION); 1629 WB_SETBIT(sc, WB_BUSCTL, WB_BURSTLEN_16LONG); 1630 switch(sc->wb_cachesize) { 1631 case 32: 1632 WB_SETBIT(sc, WB_BUSCTL, WB_CACHEALIGN_32LONG); 1633 break; 1634 case 16: 1635 WB_SETBIT(sc, WB_BUSCTL, WB_CACHEALIGN_16LONG); 1636 break; 1637 case 8: 1638 WB_SETBIT(sc, WB_BUSCTL, WB_CACHEALIGN_8LONG); 1639 break; 1640 case 0: 1641 default: 1642 WB_SETBIT(sc, WB_BUSCTL, WB_CACHEALIGN_NONE); 1643 break; 1644 } 1645 1646 /* This doesn't tend to work too well at 100Mbps. */ 1647 WB_CLRBIT(sc, WB_NETCFG, WB_NETCFG_TX_EARLY_ON); 1648 1649 /* Init our MAC address */ 1650 for (i = 0; i < ETHER_ADDR_LEN; i++) { 1651 CSR_WRITE_1(sc, WB_NODE0 + i, sc->arpcom.ac_enaddr[i]); 1652 } 1653 1654 /* Init circular RX list. */ 1655 if (wb_list_rx_init(sc) == ENOBUFS) { 1656 printf("wb%d: initialization failed: no " 1657 "memory for rx buffers\n", sc->wb_unit); 1658 wb_stop(sc); 1659 WB_UNLOCK(sc); 1660 return; 1661 } 1662 1663 /* Init TX descriptors. */ 1664 wb_list_tx_init(sc); 1665 1666 /* If we want promiscuous mode, set the allframes bit. */ 1667 if (ifp->if_flags & IFF_PROMISC) { 1668 WB_SETBIT(sc, WB_NETCFG, WB_NETCFG_RX_ALLPHYS); 1669 } else { 1670 WB_CLRBIT(sc, WB_NETCFG, WB_NETCFG_RX_ALLPHYS); 1671 } 1672 1673 /* 1674 * Set capture broadcast bit to capture broadcast frames. 1675 */ 1676 if (ifp->if_flags & IFF_BROADCAST) { 1677 WB_SETBIT(sc, WB_NETCFG, WB_NETCFG_RX_BROAD); 1678 } else { 1679 WB_CLRBIT(sc, WB_NETCFG, WB_NETCFG_RX_BROAD); 1680 } 1681 1682 /* 1683 * Program the multicast filter, if necessary. 1684 */ 1685 wb_setmulti(sc); 1686 1687 /* 1688 * Load the address of the RX list. 1689 */ 1690 WB_CLRBIT(sc, WB_NETCFG, WB_NETCFG_RX_ON); 1691 CSR_WRITE_4(sc, WB_RXADDR, vtophys(&sc->wb_ldata->wb_rx_list[0])); 1692 1693 /* 1694 * Enable interrupts. 1695 */ 1696 CSR_WRITE_4(sc, WB_IMR, WB_INTRS); 1697 CSR_WRITE_4(sc, WB_ISR, 0xFFFFFFFF); 1698 1699 /* Enable receiver and transmitter. */ 1700 WB_SETBIT(sc, WB_NETCFG, WB_NETCFG_RX_ON); 1701 CSR_WRITE_4(sc, WB_RXSTART, 0xFFFFFFFF); 1702 1703 WB_CLRBIT(sc, WB_NETCFG, WB_NETCFG_TX_ON); 1704 CSR_WRITE_4(sc, WB_TXADDR, vtophys(&sc->wb_ldata->wb_tx_list[0])); 1705 WB_SETBIT(sc, WB_NETCFG, WB_NETCFG_TX_ON); 1706 1707 mii_mediachg(mii); 1708 1709 ifp->if_flags |= IFF_RUNNING; 1710 ifp->if_flags &= ~IFF_OACTIVE; 1711 1712 sc->wb_stat_ch = timeout(wb_tick, sc, hz); 1713 WB_UNLOCK(sc); 1714 1715 return; 1716} 1717 1718/* 1719 * Set media options. 1720 */ 1721static int wb_ifmedia_upd(ifp) 1722 struct ifnet *ifp; 1723{ 1724 struct wb_softc *sc; 1725 1726 sc = ifp->if_softc; 1727 1728 if (ifp->if_flags & IFF_UP) 1729 wb_init(sc); 1730 1731 return(0); 1732} 1733 1734/* 1735 * Report current media status. 1736 */ 1737static void wb_ifmedia_sts(ifp, ifmr) 1738 struct ifnet *ifp; 1739 struct ifmediareq *ifmr; 1740{ 1741 struct wb_softc *sc; 1742 struct mii_data *mii; 1743 1744 sc = ifp->if_softc; 1745 1746 mii = device_get_softc(sc->wb_miibus); 1747 1748 mii_pollstat(mii); 1749 ifmr->ifm_active = mii->mii_media_active; 1750 ifmr->ifm_status = mii->mii_media_status; 1751 1752 return; 1753} 1754 1755static int wb_ioctl(ifp, command, data) 1756 struct ifnet *ifp; 1757 u_long command; 1758 caddr_t data; 1759{ 1760 struct wb_softc *sc = ifp->if_softc; 1761 struct mii_data *mii; 1762 struct ifreq *ifr = (struct ifreq *) data; 1763 int error = 0; 1764 1765 WB_LOCK(sc); 1766 1767 switch(command) { 1768 case SIOCSIFADDR: 1769 case SIOCGIFADDR: 1770 case SIOCSIFMTU: 1771 error = ether_ioctl(ifp, command, data); 1772 break; 1773 case SIOCSIFFLAGS: 1774 if (ifp->if_flags & IFF_UP) { 1775 wb_init(sc); 1776 } else { 1777 if (ifp->if_flags & IFF_RUNNING) 1778 wb_stop(sc); 1779 } 1780 error = 0; 1781 break; 1782 case SIOCADDMULTI: 1783 case SIOCDELMULTI: 1784 wb_setmulti(sc); 1785 error = 0; 1786 break; 1787 case SIOCGIFMEDIA: 1788 case SIOCSIFMEDIA: 1789 mii = device_get_softc(sc->wb_miibus); 1790 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command); 1791 break; 1792 default: 1793 error = EINVAL; 1794 break; 1795 } 1796 1797 WB_UNLOCK(sc); 1798 1799 return(error); 1800} 1801 1802static void wb_watchdog(ifp) 1803 struct ifnet *ifp; 1804{ 1805 struct wb_softc *sc; 1806 1807 sc = ifp->if_softc; 1808 1809 WB_LOCK(sc); 1810 ifp->if_oerrors++; 1811 printf("wb%d: watchdog timeout\n", sc->wb_unit); 1812#ifdef foo 1813 if (!(wb_phy_readreg(sc, PHY_BMSR) & PHY_BMSR_LINKSTAT)) 1814 printf("wb%d: no carrier - transceiver cable problem?\n", 1815 sc->wb_unit); 1816#endif 1817 wb_stop(sc); 1818 wb_reset(sc); 1819 wb_init(sc); 1820 1821 if (ifp->if_snd.ifq_head != NULL) 1822 wb_start(ifp); 1823 WB_UNLOCK(sc); 1824 1825 return; 1826} 1827 1828/* 1829 * Stop the adapter and free any mbufs allocated to the 1830 * RX and TX lists. 1831 */ 1832static void wb_stop(sc) 1833 struct wb_softc *sc; 1834{ 1835 register int i; 1836 struct ifnet *ifp; 1837 1838 WB_LOCK(sc); 1839 ifp = &sc->arpcom.ac_if; 1840 ifp->if_timer = 0; 1841 1842 untimeout(wb_tick, sc, sc->wb_stat_ch); 1843 1844 WB_CLRBIT(sc, WB_NETCFG, (WB_NETCFG_RX_ON|WB_NETCFG_TX_ON)); 1845 CSR_WRITE_4(sc, WB_IMR, 0x00000000); 1846 CSR_WRITE_4(sc, WB_TXADDR, 0x00000000); 1847 CSR_WRITE_4(sc, WB_RXADDR, 0x00000000); 1848 1849 /* 1850 * Free data in the RX lists. 1851 */ 1852 for (i = 0; i < WB_RX_LIST_CNT; i++) { 1853 if (sc->wb_cdata.wb_rx_chain[i].wb_mbuf != NULL) { 1854 m_freem(sc->wb_cdata.wb_rx_chain[i].wb_mbuf); 1855 sc->wb_cdata.wb_rx_chain[i].wb_mbuf = NULL; 1856 } 1857 } 1858 bzero((char *)&sc->wb_ldata->wb_rx_list, 1859 sizeof(sc->wb_ldata->wb_rx_list)); 1860 1861 /* 1862 * Free the TX list buffers. 1863 */ 1864 for (i = 0; i < WB_TX_LIST_CNT; i++) { 1865 if (sc->wb_cdata.wb_tx_chain[i].wb_mbuf != NULL) { 1866 m_freem(sc->wb_cdata.wb_tx_chain[i].wb_mbuf); 1867 sc->wb_cdata.wb_tx_chain[i].wb_mbuf = NULL; 1868 } 1869 } 1870 1871 bzero((char *)&sc->wb_ldata->wb_tx_list, 1872 sizeof(sc->wb_ldata->wb_tx_list)); 1873 1874 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 1875 WB_UNLOCK(sc); 1876 1877 return; 1878} 1879 1880/* 1881 * Stop all chip I/O so that the kernel's probe routines don't 1882 * get confused by errant DMAs when rebooting. 1883 */ 1884static void wb_shutdown(dev) 1885 device_t dev; 1886{ 1887 struct wb_softc *sc; 1888 1889 sc = device_get_softc(dev); 1890 wb_stop(sc); 1891 1892 return; 1893} 1894