if_wb.c revision 67087
1/* 2 * Copyright (c) 1997, 1998 3 * Bill Paul <wpaul@ctr.columbia.edu>. All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 3. All advertising materials mentioning features or use of this software 14 * must display the following acknowledgement: 15 * This product includes software developed by Bill Paul. 16 * 4. Neither the name of the author nor the names of any co-contributors 17 * may be used to endorse or promote products derived from this software 18 * without specific prior written permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 21 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 30 * THE POSSIBILITY OF SUCH DAMAGE. 31 * 32 * $FreeBSD: head/sys/pci/if_wb.c 67087 2000-10-13 17:54:19Z wpaul $ 33 */ 34 35/* 36 * Winbond fast ethernet PCI NIC driver 37 * 38 * Supports various cheap network adapters based on the Winbond W89C840F 39 * fast ethernet controller chip. This includes adapters manufactured by 40 * Winbond itself and some made by Linksys. 41 * 42 * Written by Bill Paul <wpaul@ctr.columbia.edu> 43 * Electrical Engineering Department 44 * Columbia University, New York City 45 */ 46 47/* 48 * The Winbond W89C840F chip is a bus master; in some ways it resembles 49 * a DEC 'tulip' chip, only not as complicated. Unfortunately, it has 50 * one major difference which is that while the registers do many of 51 * the same things as a tulip adapter, the offsets are different: where 52 * tulip registers are typically spaced 8 bytes apart, the Winbond 53 * registers are spaced 4 bytes apart. The receiver filter is also 54 * programmed differently. 55 * 56 * Like the tulip, the Winbond chip uses small descriptors containing 57 * a status word, a control word and 32-bit areas that can either be used 58 * to point to two external data blocks, or to point to a single block 59 * and another descriptor in a linked list. Descriptors can be grouped 60 * together in blocks to form fixed length rings or can be chained 61 * together in linked lists. A single packet may be spread out over 62 * several descriptors if necessary. 63 * 64 * For the receive ring, this driver uses a linked list of descriptors, 65 * each pointing to a single mbuf cluster buffer, which us large enough 66 * to hold an entire packet. The link list is looped back to created a 67 * closed ring. 68 * 69 * For transmission, the driver creates a linked list of 'super descriptors' 70 * which each contain several individual descriptors linked toghether. 71 * Each 'super descriptor' contains WB_MAXFRAGS descriptors, which we 72 * abuse as fragment pointers. This allows us to use a buffer managment 73 * scheme very similar to that used in the ThunderLAN and Etherlink XL 74 * drivers. 75 * 76 * Autonegotiation is performed using the external PHY via the MII bus. 77 * The sample boards I have all use a Davicom PHY. 78 * 79 * Note: the author of the Linux driver for the Winbond chip alludes 80 * to some sort of flaw in the chip's design that seems to mandate some 81 * drastic workaround which signigicantly impairs transmit performance. 82 * I have no idea what he's on about: transmit performance with all 83 * three of my test boards seems fine. 84 */ 85 86#include "opt_bdg.h" 87 88#include <sys/param.h> 89#include <sys/systm.h> 90#include <sys/sockio.h> 91#include <sys/mbuf.h> 92#include <sys/malloc.h> 93#include <sys/kernel.h> 94#include <sys/socket.h> 95#include <sys/queue.h> 96 97#include <net/if.h> 98#include <net/if_arp.h> 99#include <net/ethernet.h> 100#include <net/if_dl.h> 101#include <net/if_media.h> 102 103#include <net/bpf.h> 104 105#include <vm/vm.h> /* for vtophys */ 106#include <vm/pmap.h> /* for vtophys */ 107#include <machine/clock.h> /* for DELAY */ 108#include <machine/bus_memio.h> 109#include <machine/bus_pio.h> 110#include <machine/bus.h> 111#include <machine/resource.h> 112#include <sys/bus.h> 113#include <sys/rman.h> 114 115#include <pci/pcireg.h> 116#include <pci/pcivar.h> 117 118#include <dev/mii/mii.h> 119#include <dev/mii/miivar.h> 120 121/* "controller miibus0" required. See GENERIC if you get errors here. */ 122#include "miibus_if.h" 123 124#define WB_USEIOSPACE 125 126#include <pci/if_wbreg.h> 127 128MODULE_DEPEND(wb, miibus, 1, 1, 1); 129 130#ifndef lint 131static const char rcsid[] = 132 "$FreeBSD: head/sys/pci/if_wb.c 67087 2000-10-13 17:54:19Z wpaul $"; 133#endif 134 135/* 136 * Various supported device vendors/types and their names. 137 */ 138static struct wb_type wb_devs[] = { 139 { WB_VENDORID, WB_DEVICEID_840F, 140 "Winbond W89C840F 10/100BaseTX" }, 141 { CP_VENDORID, CP_DEVICEID_RL100, 142 "Compex RL100-ATX 10/100baseTX" }, 143 { 0, 0, NULL } 144}; 145 146static int wb_probe __P((device_t)); 147static int wb_attach __P((device_t)); 148static int wb_detach __P((device_t)); 149 150static void wb_bfree __P((caddr_t, void *args)); 151static int wb_newbuf __P((struct wb_softc *, 152 struct wb_chain_onefrag *, 153 struct mbuf *)); 154static int wb_encap __P((struct wb_softc *, struct wb_chain *, 155 struct mbuf *)); 156 157static void wb_rxeof __P((struct wb_softc *)); 158static void wb_rxeoc __P((struct wb_softc *)); 159static void wb_txeof __P((struct wb_softc *)); 160static void wb_txeoc __P((struct wb_softc *)); 161static void wb_intr __P((void *)); 162static void wb_tick __P((void *)); 163static void wb_start __P((struct ifnet *)); 164static int wb_ioctl __P((struct ifnet *, u_long, caddr_t)); 165static void wb_init __P((void *)); 166static void wb_stop __P((struct wb_softc *)); 167static void wb_watchdog __P((struct ifnet *)); 168static void wb_shutdown __P((device_t)); 169static int wb_ifmedia_upd __P((struct ifnet *)); 170static void wb_ifmedia_sts __P((struct ifnet *, struct ifmediareq *)); 171 172static void wb_eeprom_putbyte __P((struct wb_softc *, int)); 173static void wb_eeprom_getword __P((struct wb_softc *, int, u_int16_t *)); 174static void wb_read_eeprom __P((struct wb_softc *, caddr_t, int, 175 int, int)); 176static void wb_mii_sync __P((struct wb_softc *)); 177static void wb_mii_send __P((struct wb_softc *, u_int32_t, int)); 178static int wb_mii_readreg __P((struct wb_softc *, struct wb_mii_frame *)); 179static int wb_mii_writereg __P((struct wb_softc *, struct wb_mii_frame *)); 180 181static void wb_setcfg __P((struct wb_softc *, u_int32_t)); 182static u_int8_t wb_calchash __P((caddr_t)); 183static void wb_setmulti __P((struct wb_softc *)); 184static void wb_reset __P((struct wb_softc *)); 185static void wb_fixmedia __P((struct wb_softc *)); 186static int wb_list_rx_init __P((struct wb_softc *)); 187static int wb_list_tx_init __P((struct wb_softc *)); 188 189static int wb_miibus_readreg __P((device_t, int, int)); 190static int wb_miibus_writereg __P((device_t, int, int, int)); 191static void wb_miibus_statchg __P((device_t)); 192 193#ifdef WB_USEIOSPACE 194#define WB_RES SYS_RES_IOPORT 195#define WB_RID WB_PCI_LOIO 196#else 197#define WB_RES SYS_RES_MEMORY 198#define WB_RID WB_PCI_LOMEM 199#endif 200 201static device_method_t wb_methods[] = { 202 /* Device interface */ 203 DEVMETHOD(device_probe, wb_probe), 204 DEVMETHOD(device_attach, wb_attach), 205 DEVMETHOD(device_detach, wb_detach), 206 DEVMETHOD(device_shutdown, wb_shutdown), 207 208 /* bus interface, for miibus */ 209 DEVMETHOD(bus_print_child, bus_generic_print_child), 210 DEVMETHOD(bus_driver_added, bus_generic_driver_added), 211 212 /* MII interface */ 213 DEVMETHOD(miibus_readreg, wb_miibus_readreg), 214 DEVMETHOD(miibus_writereg, wb_miibus_writereg), 215 DEVMETHOD(miibus_statchg, wb_miibus_statchg), 216 { 0, 0 } 217}; 218 219static driver_t wb_driver = { 220 "wb", 221 wb_methods, 222 sizeof(struct wb_softc) 223}; 224 225static devclass_t wb_devclass; 226 227DRIVER_MODULE(if_wb, pci, wb_driver, wb_devclass, 0, 0); 228DRIVER_MODULE(miibus, wb, miibus_driver, miibus_devclass, 0, 0); 229 230#define WB_SETBIT(sc, reg, x) \ 231 CSR_WRITE_4(sc, reg, \ 232 CSR_READ_4(sc, reg) | x) 233 234#define WB_CLRBIT(sc, reg, x) \ 235 CSR_WRITE_4(sc, reg, \ 236 CSR_READ_4(sc, reg) & ~x) 237 238#define SIO_SET(x) \ 239 CSR_WRITE_4(sc, WB_SIO, \ 240 CSR_READ_4(sc, WB_SIO) | x) 241 242#define SIO_CLR(x) \ 243 CSR_WRITE_4(sc, WB_SIO, \ 244 CSR_READ_4(sc, WB_SIO) & ~x) 245 246/* 247 * Send a read command and address to the EEPROM, check for ACK. 248 */ 249static void wb_eeprom_putbyte(sc, addr) 250 struct wb_softc *sc; 251 int addr; 252{ 253 register int d, i; 254 255 d = addr | WB_EECMD_READ; 256 257 /* 258 * Feed in each bit and stobe the clock. 259 */ 260 for (i = 0x400; i; i >>= 1) { 261 if (d & i) { 262 SIO_SET(WB_SIO_EE_DATAIN); 263 } else { 264 SIO_CLR(WB_SIO_EE_DATAIN); 265 } 266 DELAY(100); 267 SIO_SET(WB_SIO_EE_CLK); 268 DELAY(150); 269 SIO_CLR(WB_SIO_EE_CLK); 270 DELAY(100); 271 } 272 273 return; 274} 275 276/* 277 * Read a word of data stored in the EEPROM at address 'addr.' 278 */ 279static void wb_eeprom_getword(sc, addr, dest) 280 struct wb_softc *sc; 281 int addr; 282 u_int16_t *dest; 283{ 284 register int i; 285 u_int16_t word = 0; 286 287 /* Enter EEPROM access mode. */ 288 CSR_WRITE_4(sc, WB_SIO, WB_SIO_EESEL|WB_SIO_EE_CS); 289 290 /* 291 * Send address of word we want to read. 292 */ 293 wb_eeprom_putbyte(sc, addr); 294 295 CSR_WRITE_4(sc, WB_SIO, WB_SIO_EESEL|WB_SIO_EE_CS); 296 297 /* 298 * Start reading bits from EEPROM. 299 */ 300 for (i = 0x8000; i; i >>= 1) { 301 SIO_SET(WB_SIO_EE_CLK); 302 DELAY(100); 303 if (CSR_READ_4(sc, WB_SIO) & WB_SIO_EE_DATAOUT) 304 word |= i; 305 SIO_CLR(WB_SIO_EE_CLK); 306 DELAY(100); 307 } 308 309 /* Turn off EEPROM access mode. */ 310 CSR_WRITE_4(sc, WB_SIO, 0); 311 312 *dest = word; 313 314 return; 315} 316 317/* 318 * Read a sequence of words from the EEPROM. 319 */ 320static void wb_read_eeprom(sc, dest, off, cnt, swap) 321 struct wb_softc *sc; 322 caddr_t dest; 323 int off; 324 int cnt; 325 int swap; 326{ 327 int i; 328 u_int16_t word = 0, *ptr; 329 330 for (i = 0; i < cnt; i++) { 331 wb_eeprom_getword(sc, off + i, &word); 332 ptr = (u_int16_t *)(dest + (i * 2)); 333 if (swap) 334 *ptr = ntohs(word); 335 else 336 *ptr = word; 337 } 338 339 return; 340} 341 342/* 343 * Sync the PHYs by setting data bit and strobing the clock 32 times. 344 */ 345static void wb_mii_sync(sc) 346 struct wb_softc *sc; 347{ 348 register int i; 349 350 SIO_SET(WB_SIO_MII_DIR|WB_SIO_MII_DATAIN); 351 352 for (i = 0; i < 32; i++) { 353 SIO_SET(WB_SIO_MII_CLK); 354 DELAY(1); 355 SIO_CLR(WB_SIO_MII_CLK); 356 DELAY(1); 357 } 358 359 return; 360} 361 362/* 363 * Clock a series of bits through the MII. 364 */ 365static void wb_mii_send(sc, bits, cnt) 366 struct wb_softc *sc; 367 u_int32_t bits; 368 int cnt; 369{ 370 int i; 371 372 SIO_CLR(WB_SIO_MII_CLK); 373 374 for (i = (0x1 << (cnt - 1)); i; i >>= 1) { 375 if (bits & i) { 376 SIO_SET(WB_SIO_MII_DATAIN); 377 } else { 378 SIO_CLR(WB_SIO_MII_DATAIN); 379 } 380 DELAY(1); 381 SIO_CLR(WB_SIO_MII_CLK); 382 DELAY(1); 383 SIO_SET(WB_SIO_MII_CLK); 384 } 385} 386 387/* 388 * Read an PHY register through the MII. 389 */ 390static int wb_mii_readreg(sc, frame) 391 struct wb_softc *sc; 392 struct wb_mii_frame *frame; 393 394{ 395 int i, ack; 396 397 WB_LOCK(sc); 398 399 /* 400 * Set up frame for RX. 401 */ 402 frame->mii_stdelim = WB_MII_STARTDELIM; 403 frame->mii_opcode = WB_MII_READOP; 404 frame->mii_turnaround = 0; 405 frame->mii_data = 0; 406 407 CSR_WRITE_4(sc, WB_SIO, 0); 408 409 /* 410 * Turn on data xmit. 411 */ 412 SIO_SET(WB_SIO_MII_DIR); 413 414 wb_mii_sync(sc); 415 416 /* 417 * Send command/address info. 418 */ 419 wb_mii_send(sc, frame->mii_stdelim, 2); 420 wb_mii_send(sc, frame->mii_opcode, 2); 421 wb_mii_send(sc, frame->mii_phyaddr, 5); 422 wb_mii_send(sc, frame->mii_regaddr, 5); 423 424 /* Idle bit */ 425 SIO_CLR((WB_SIO_MII_CLK|WB_SIO_MII_DATAIN)); 426 DELAY(1); 427 SIO_SET(WB_SIO_MII_CLK); 428 DELAY(1); 429 430 /* Turn off xmit. */ 431 SIO_CLR(WB_SIO_MII_DIR); 432 /* Check for ack */ 433 SIO_CLR(WB_SIO_MII_CLK); 434 DELAY(1); 435 SIO_SET(WB_SIO_MII_CLK); 436 DELAY(1); 437 ack = CSR_READ_4(sc, WB_SIO) & WB_SIO_MII_DATAOUT; 438 SIO_CLR(WB_SIO_MII_CLK); 439 DELAY(1); 440 SIO_SET(WB_SIO_MII_CLK); 441 DELAY(1); 442 443 /* 444 * Now try reading data bits. If the ack failed, we still 445 * need to clock through 16 cycles to keep the PHY(s) in sync. 446 */ 447 if (ack) { 448 for(i = 0; i < 16; i++) { 449 SIO_CLR(WB_SIO_MII_CLK); 450 DELAY(1); 451 SIO_SET(WB_SIO_MII_CLK); 452 DELAY(1); 453 } 454 goto fail; 455 } 456 457 for (i = 0x8000; i; i >>= 1) { 458 SIO_CLR(WB_SIO_MII_CLK); 459 DELAY(1); 460 if (!ack) { 461 if (CSR_READ_4(sc, WB_SIO) & WB_SIO_MII_DATAOUT) 462 frame->mii_data |= i; 463 DELAY(1); 464 } 465 SIO_SET(WB_SIO_MII_CLK); 466 DELAY(1); 467 } 468 469fail: 470 471 SIO_CLR(WB_SIO_MII_CLK); 472 DELAY(1); 473 SIO_SET(WB_SIO_MII_CLK); 474 DELAY(1); 475 476 WB_UNLOCK(sc); 477 478 if (ack) 479 return(1); 480 return(0); 481} 482 483/* 484 * Write to a PHY register through the MII. 485 */ 486static int wb_mii_writereg(sc, frame) 487 struct wb_softc *sc; 488 struct wb_mii_frame *frame; 489 490{ 491 WB_LOCK(sc); 492 493 /* 494 * Set up frame for TX. 495 */ 496 497 frame->mii_stdelim = WB_MII_STARTDELIM; 498 frame->mii_opcode = WB_MII_WRITEOP; 499 frame->mii_turnaround = WB_MII_TURNAROUND; 500 501 /* 502 * Turn on data output. 503 */ 504 SIO_SET(WB_SIO_MII_DIR); 505 506 wb_mii_sync(sc); 507 508 wb_mii_send(sc, frame->mii_stdelim, 2); 509 wb_mii_send(sc, frame->mii_opcode, 2); 510 wb_mii_send(sc, frame->mii_phyaddr, 5); 511 wb_mii_send(sc, frame->mii_regaddr, 5); 512 wb_mii_send(sc, frame->mii_turnaround, 2); 513 wb_mii_send(sc, frame->mii_data, 16); 514 515 /* Idle bit. */ 516 SIO_SET(WB_SIO_MII_CLK); 517 DELAY(1); 518 SIO_CLR(WB_SIO_MII_CLK); 519 DELAY(1); 520 521 /* 522 * Turn off xmit. 523 */ 524 SIO_CLR(WB_SIO_MII_DIR); 525 526 WB_UNLOCK(sc); 527 528 return(0); 529} 530 531static int wb_miibus_readreg(dev, phy, reg) 532 device_t dev; 533 int phy, reg; 534{ 535 struct wb_softc *sc; 536 struct wb_mii_frame frame; 537 538 sc = device_get_softc(dev); 539 540 bzero((char *)&frame, sizeof(frame)); 541 542 frame.mii_phyaddr = phy; 543 frame.mii_regaddr = reg; 544 wb_mii_readreg(sc, &frame); 545 546 return(frame.mii_data); 547} 548 549static int wb_miibus_writereg(dev, phy, reg, data) 550 device_t dev; 551 int phy, reg, data; 552{ 553 struct wb_softc *sc; 554 struct wb_mii_frame frame; 555 556 sc = device_get_softc(dev); 557 558 bzero((char *)&frame, sizeof(frame)); 559 560 frame.mii_phyaddr = phy; 561 frame.mii_regaddr = reg; 562 frame.mii_data = data; 563 564 wb_mii_writereg(sc, &frame); 565 566 return(0); 567} 568 569static void wb_miibus_statchg(dev) 570 device_t dev; 571{ 572 struct wb_softc *sc; 573 struct mii_data *mii; 574 575 sc = device_get_softc(dev); 576 WB_LOCK(sc); 577 mii = device_get_softc(sc->wb_miibus); 578 wb_setcfg(sc, mii->mii_media_active); 579 WB_UNLOCK(sc); 580 581 return; 582} 583 584static u_int8_t wb_calchash(addr) 585 caddr_t addr; 586{ 587 u_int32_t crc, carry; 588 int i, j; 589 u_int8_t c; 590 591 /* Compute CRC for the address value. */ 592 crc = 0xFFFFFFFF; /* initial value */ 593 594 for (i = 0; i < 6; i++) { 595 c = *(addr + i); 596 for (j = 0; j < 8; j++) { 597 carry = ((crc & 0x80000000) ? 1 : 0) ^ (c & 0x01); 598 crc <<= 1; 599 c >>= 1; 600 if (carry) 601 crc = (crc ^ 0x04c11db6) | carry; 602 } 603 } 604 605 /* 606 * return the filter bit position 607 * Note: I arrived at the following nonsense 608 * through experimentation. It's not the usual way to 609 * generate the bit position but it's the only thing 610 * I could come up with that works. 611 */ 612 return(~(crc >> 26) & 0x0000003F); 613} 614 615/* 616 * Program the 64-bit multicast hash filter. 617 */ 618static void wb_setmulti(sc) 619 struct wb_softc *sc; 620{ 621 struct ifnet *ifp; 622 int h = 0; 623 u_int32_t hashes[2] = { 0, 0 }; 624 struct ifmultiaddr *ifma; 625 u_int32_t rxfilt; 626 int mcnt = 0; 627 628 ifp = &sc->arpcom.ac_if; 629 630 rxfilt = CSR_READ_4(sc, WB_NETCFG); 631 632 if (ifp->if_flags & IFF_ALLMULTI || ifp->if_flags & IFF_PROMISC) { 633 rxfilt |= WB_NETCFG_RX_MULTI; 634 CSR_WRITE_4(sc, WB_NETCFG, rxfilt); 635 CSR_WRITE_4(sc, WB_MAR0, 0xFFFFFFFF); 636 CSR_WRITE_4(sc, WB_MAR1, 0xFFFFFFFF); 637 return; 638 } 639 640 /* first, zot all the existing hash bits */ 641 CSR_WRITE_4(sc, WB_MAR0, 0); 642 CSR_WRITE_4(sc, WB_MAR1, 0); 643 644 /* now program new ones */ 645 for (ifma = ifp->if_multiaddrs.lh_first; ifma != NULL; 646 ifma = ifma->ifma_link.le_next) { 647 if (ifma->ifma_addr->sa_family != AF_LINK) 648 continue; 649 h = wb_calchash(LLADDR((struct sockaddr_dl *)ifma->ifma_addr)); 650 if (h < 32) 651 hashes[0] |= (1 << h); 652 else 653 hashes[1] |= (1 << (h - 32)); 654 mcnt++; 655 } 656 657 if (mcnt) 658 rxfilt |= WB_NETCFG_RX_MULTI; 659 else 660 rxfilt &= ~WB_NETCFG_RX_MULTI; 661 662 CSR_WRITE_4(sc, WB_MAR0, hashes[0]); 663 CSR_WRITE_4(sc, WB_MAR1, hashes[1]); 664 CSR_WRITE_4(sc, WB_NETCFG, rxfilt); 665 666 return; 667} 668 669/* 670 * The Winbond manual states that in order to fiddle with the 671 * 'full-duplex' and '100Mbps' bits in the netconfig register, we 672 * first have to put the transmit and/or receive logic in the idle state. 673 */ 674static void wb_setcfg(sc, media) 675 struct wb_softc *sc; 676 u_int32_t media; 677{ 678 int i, restart = 0; 679 680 if (CSR_READ_4(sc, WB_NETCFG) & (WB_NETCFG_TX_ON|WB_NETCFG_RX_ON)) { 681 restart = 1; 682 WB_CLRBIT(sc, WB_NETCFG, (WB_NETCFG_TX_ON|WB_NETCFG_RX_ON)); 683 684 for (i = 0; i < WB_TIMEOUT; i++) { 685 DELAY(10); 686 if ((CSR_READ_4(sc, WB_ISR) & WB_ISR_TX_IDLE) && 687 (CSR_READ_4(sc, WB_ISR) & WB_ISR_RX_IDLE)) 688 break; 689 } 690 691 if (i == WB_TIMEOUT) 692 printf("wb%d: failed to force tx and " 693 "rx to idle state\n", sc->wb_unit); 694 } 695 696 if (IFM_SUBTYPE(media) == IFM_10_T) 697 WB_CLRBIT(sc, WB_NETCFG, WB_NETCFG_100MBPS); 698 else 699 WB_SETBIT(sc, WB_NETCFG, WB_NETCFG_100MBPS); 700 701 if ((media & IFM_GMASK) == IFM_FDX) 702 WB_SETBIT(sc, WB_NETCFG, WB_NETCFG_FULLDUPLEX); 703 else 704 WB_CLRBIT(sc, WB_NETCFG, WB_NETCFG_FULLDUPLEX); 705 706 if (restart) 707 WB_SETBIT(sc, WB_NETCFG, WB_NETCFG_TX_ON|WB_NETCFG_RX_ON); 708 709 return; 710} 711 712static void wb_reset(sc) 713 struct wb_softc *sc; 714{ 715 register int i; 716 struct mii_data *mii; 717 718 CSR_WRITE_4(sc, WB_NETCFG, 0); 719 CSR_WRITE_4(sc, WB_BUSCTL, 0); 720 CSR_WRITE_4(sc, WB_TXADDR, 0); 721 CSR_WRITE_4(sc, WB_RXADDR, 0); 722 723 WB_SETBIT(sc, WB_BUSCTL, WB_BUSCTL_RESET); 724 WB_SETBIT(sc, WB_BUSCTL, WB_BUSCTL_RESET); 725 726 for (i = 0; i < WB_TIMEOUT; i++) { 727 DELAY(10); 728 if (!(CSR_READ_4(sc, WB_BUSCTL) & WB_BUSCTL_RESET)) 729 break; 730 } 731 if (i == WB_TIMEOUT) 732 printf("wb%d: reset never completed!\n", sc->wb_unit); 733 734 /* Wait a little while for the chip to get its brains in order. */ 735 DELAY(1000); 736 737 if (sc->wb_miibus == NULL) 738 return; 739 740 mii = device_get_softc(sc->wb_miibus); 741 if (mii == NULL) 742 return; 743 744 if (mii->mii_instance) { 745 struct mii_softc *miisc; 746 for (miisc = LIST_FIRST(&mii->mii_phys); miisc != NULL; 747 miisc = LIST_NEXT(miisc, mii_list)) 748 mii_phy_reset(miisc); 749 } 750 751 return; 752} 753 754static void wb_fixmedia(sc) 755 struct wb_softc *sc; 756{ 757 struct mii_data *mii = NULL; 758 struct ifnet *ifp; 759 u_int32_t media; 760 761 if (sc->wb_miibus == NULL) 762 return; 763 764 mii = device_get_softc(sc->wb_miibus); 765 ifp = &sc->arpcom.ac_if; 766 767 mii_pollstat(mii); 768 if (IFM_SUBTYPE(mii->mii_media_active) == IFM_10_T) { 769 media = mii->mii_media_active & ~IFM_10_T; 770 media |= IFM_100_TX; 771 } else if (IFM_SUBTYPE(mii->mii_media_active) == IFM_100_TX) { 772 media = mii->mii_media_active & ~IFM_100_TX; 773 media |= IFM_10_T; 774 } else 775 return; 776 777 ifmedia_set(&mii->mii_media, media); 778 779 return; 780} 781 782/* 783 * Probe for a Winbond chip. Check the PCI vendor and device 784 * IDs against our list and return a device name if we find a match. 785 */ 786static int wb_probe(dev) 787 device_t dev; 788{ 789 struct wb_type *t; 790 791 t = wb_devs; 792 793 while(t->wb_name != NULL) { 794 if ((pci_get_vendor(dev) == t->wb_vid) && 795 (pci_get_device(dev) == t->wb_did)) { 796 device_set_desc(dev, t->wb_name); 797 return(0); 798 } 799 t++; 800 } 801 802 return(ENXIO); 803} 804 805/* 806 * Attach the interface. Allocate softc structures, do ifmedia 807 * setup and ethernet/BPF attach. 808 */ 809static int wb_attach(dev) 810 device_t dev; 811{ 812 u_char eaddr[ETHER_ADDR_LEN]; 813 u_int32_t command; 814 struct wb_softc *sc; 815 struct ifnet *ifp; 816 int unit, error = 0, rid; 817 818 sc = device_get_softc(dev); 819 unit = device_get_unit(dev); 820 821 /* 822 * Handle power management nonsense. 823 */ 824 825 command = pci_read_config(dev, WB_PCI_CAPID, 4) & 0x000000FF; 826 if (command == 0x01) { 827 828 command = pci_read_config(dev, WB_PCI_PWRMGMTCTRL, 4); 829 if (command & WB_PSTATE_MASK) { 830 u_int32_t iobase, membase, irq; 831 832 /* Save important PCI config data. */ 833 iobase = pci_read_config(dev, WB_PCI_LOIO, 4); 834 membase = pci_read_config(dev, WB_PCI_LOMEM, 4); 835 irq = pci_read_config(dev, WB_PCI_INTLINE, 4); 836 837 /* Reset the power state. */ 838 printf("wb%d: chip is in D%d power mode " 839 "-- setting to D0\n", unit, command & WB_PSTATE_MASK); 840 command &= 0xFFFFFFFC; 841 pci_write_config(dev, WB_PCI_PWRMGMTCTRL, command, 4); 842 843 /* Restore PCI config data. */ 844 pci_write_config(dev, WB_PCI_LOIO, iobase, 4); 845 pci_write_config(dev, WB_PCI_LOMEM, membase, 4); 846 pci_write_config(dev, WB_PCI_INTLINE, irq, 4); 847 } 848 } 849 850 /* 851 * Map control/status registers. 852 */ 853 command = pci_read_config(dev, PCIR_COMMAND, 4); 854 command |= (PCIM_CMD_PORTEN|PCIM_CMD_MEMEN|PCIM_CMD_BUSMASTEREN); 855 pci_write_config(dev, PCIR_COMMAND, command, 4); 856 command = pci_read_config(dev, PCIR_COMMAND, 4); 857 858#ifdef WB_USEIOSPACE 859 if (!(command & PCIM_CMD_PORTEN)) { 860 printf("wb%d: failed to enable I/O ports!\n", unit); 861 error = ENXIO; 862 goto fail; 863 } 864#else 865 if (!(command & PCIM_CMD_MEMEN)) { 866 printf("wb%d: failed to enable memory mapping!\n", unit); 867 error = ENXIO; 868 goto fail; 869 } 870#endif 871 872 rid = WB_RID; 873 sc->wb_res = bus_alloc_resource(dev, WB_RES, &rid, 874 0, ~0, 1, RF_ACTIVE); 875 876 if (sc->wb_res == NULL) { 877 printf("wb%d: couldn't map ports/memory\n", unit); 878 error = ENXIO; 879 goto fail; 880 } 881 882 sc->wb_btag = rman_get_bustag(sc->wb_res); 883 sc->wb_bhandle = rman_get_bushandle(sc->wb_res); 884 885 /* Allocate interrupt */ 886 rid = 0; 887 sc->wb_irq = bus_alloc_resource(dev, SYS_RES_IRQ, &rid, 0, ~0, 1, 888 RF_SHAREABLE | RF_ACTIVE); 889 890 if (sc->wb_irq == NULL) { 891 printf("wb%d: couldn't map interrupt\n", unit); 892 bus_release_resource(dev, WB_RES, WB_RID, sc->wb_res); 893 error = ENXIO; 894 goto fail; 895 } 896 897 error = bus_setup_intr(dev, sc->wb_irq, INTR_TYPE_NET, 898 wb_intr, sc, &sc->wb_intrhand); 899 900 if (error) { 901 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->wb_irq); 902 bus_release_resource(dev, WB_RES, WB_RID, sc->wb_res); 903 printf("wb%d: couldn't set up irq\n", unit); 904 goto fail; 905 } 906 907 /* Save the cache line size. */ 908 sc->wb_cachesize = pci_read_config(dev, WB_PCI_CACHELEN, 4) & 0xFF; 909 910 mtx_init(&sc->wb_mtx, "wb", MTX_DEF); 911 WB_LOCK(sc); 912 913 /* Reset the adapter. */ 914 wb_reset(sc); 915 916 /* 917 * Get station address from the EEPROM. 918 */ 919 wb_read_eeprom(sc, (caddr_t)&eaddr, 0, 3, 0); 920 921 /* 922 * A Winbond chip was detected. Inform the world. 923 */ 924 printf("wb%d: Ethernet address: %6D\n", unit, eaddr, ":"); 925 926 sc->wb_unit = unit; 927 bcopy(eaddr, (char *)&sc->arpcom.ac_enaddr, ETHER_ADDR_LEN); 928 929 sc->wb_ldata = contigmalloc(sizeof(struct wb_list_data) + 8, M_DEVBUF, 930 M_NOWAIT, 0, 0xffffffff, PAGE_SIZE, 0); 931 932 if (sc->wb_ldata == NULL) { 933 printf("wb%d: no memory for list buffers!\n", unit); 934 bus_teardown_intr(dev, sc->wb_irq, sc->wb_intrhand); 935 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->wb_irq); 936 bus_release_resource(dev, WB_RES, WB_RID, sc->wb_res); 937 error = ENXIO; 938 goto fail; 939 } 940 941 bzero(sc->wb_ldata, sizeof(struct wb_list_data)); 942 943 ifp = &sc->arpcom.ac_if; 944 ifp->if_softc = sc; 945 ifp->if_unit = unit; 946 ifp->if_name = "wb"; 947 ifp->if_mtu = ETHERMTU; 948 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 949 ifp->if_ioctl = wb_ioctl; 950 ifp->if_output = ether_output; 951 ifp->if_start = wb_start; 952 ifp->if_watchdog = wb_watchdog; 953 ifp->if_init = wb_init; 954 ifp->if_baudrate = 10000000; 955 ifp->if_snd.ifq_maxlen = WB_TX_LIST_CNT - 1; 956 957 /* 958 * Do MII setup. 959 */ 960 if (mii_phy_probe(dev, &sc->wb_miibus, 961 wb_ifmedia_upd, wb_ifmedia_sts)) { 962 bus_teardown_intr(dev, sc->wb_irq, sc->wb_intrhand); 963 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->wb_irq); 964 bus_release_resource(dev, WB_RES, WB_RID, sc->wb_res); 965 free(sc->wb_ldata_ptr, M_DEVBUF); 966 error = ENXIO; 967 goto fail; 968 } 969 970 /* 971 * Call MI attach routine. 972 */ 973 ether_ifattach(ifp, ETHER_BPF_SUPPORTED); 974 WB_UNLOCK(sc); 975 return(0); 976 977fail: 978 if (error) 979 device_delete_child(dev, sc->wb_miibus); 980 WB_UNLOCK(sc); 981 mtx_destroy(&sc->wb_mtx); 982 983 return(error); 984} 985 986static int wb_detach(dev) 987 device_t dev; 988{ 989 struct wb_softc *sc; 990 struct ifnet *ifp; 991 992 sc = device_get_softc(dev); 993 WB_LOCK(sc); 994 ifp = &sc->arpcom.ac_if; 995 996 wb_stop(sc); 997 ether_ifdetach(ifp, ETHER_BPF_SUPPORTED); 998 999 /* Delete any miibus and phy devices attached to this interface */ 1000 bus_generic_detach(dev); 1001 device_delete_child(dev, sc->wb_miibus); 1002 1003 bus_teardown_intr(dev, sc->wb_irq, sc->wb_intrhand); 1004 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->wb_irq); 1005 bus_release_resource(dev, WB_RES, WB_RID, sc->wb_res); 1006 1007 free(sc->wb_ldata_ptr, M_DEVBUF); 1008 1009 WB_UNLOCK(sc); 1010 mtx_destroy(&sc->wb_mtx); 1011 1012 return(0); 1013} 1014 1015/* 1016 * Initialize the transmit descriptors. 1017 */ 1018static int wb_list_tx_init(sc) 1019 struct wb_softc *sc; 1020{ 1021 struct wb_chain_data *cd; 1022 struct wb_list_data *ld; 1023 int i; 1024 1025 cd = &sc->wb_cdata; 1026 ld = sc->wb_ldata; 1027 1028 for (i = 0; i < WB_TX_LIST_CNT; i++) { 1029 cd->wb_tx_chain[i].wb_ptr = &ld->wb_tx_list[i]; 1030 if (i == (WB_TX_LIST_CNT - 1)) { 1031 cd->wb_tx_chain[i].wb_nextdesc = 1032 &cd->wb_tx_chain[0]; 1033 } else { 1034 cd->wb_tx_chain[i].wb_nextdesc = 1035 &cd->wb_tx_chain[i + 1]; 1036 } 1037 } 1038 1039 cd->wb_tx_free = &cd->wb_tx_chain[0]; 1040 cd->wb_tx_tail = cd->wb_tx_head = NULL; 1041 1042 return(0); 1043} 1044 1045 1046/* 1047 * Initialize the RX descriptors and allocate mbufs for them. Note that 1048 * we arrange the descriptors in a closed ring, so that the last descriptor 1049 * points back to the first. 1050 */ 1051static int wb_list_rx_init(sc) 1052 struct wb_softc *sc; 1053{ 1054 struct wb_chain_data *cd; 1055 struct wb_list_data *ld; 1056 int i; 1057 1058 cd = &sc->wb_cdata; 1059 ld = sc->wb_ldata; 1060 1061 for (i = 0; i < WB_RX_LIST_CNT; i++) { 1062 cd->wb_rx_chain[i].wb_ptr = 1063 (struct wb_desc *)&ld->wb_rx_list[i]; 1064 cd->wb_rx_chain[i].wb_buf = (void *)&ld->wb_rxbufs[i]; 1065 if (wb_newbuf(sc, &cd->wb_rx_chain[i], NULL) == ENOBUFS) 1066 return(ENOBUFS); 1067 if (i == (WB_RX_LIST_CNT - 1)) { 1068 cd->wb_rx_chain[i].wb_nextdesc = &cd->wb_rx_chain[0]; 1069 ld->wb_rx_list[i].wb_next = 1070 vtophys(&ld->wb_rx_list[0]); 1071 } else { 1072 cd->wb_rx_chain[i].wb_nextdesc = 1073 &cd->wb_rx_chain[i + 1]; 1074 ld->wb_rx_list[i].wb_next = 1075 vtophys(&ld->wb_rx_list[i + 1]); 1076 } 1077 } 1078 1079 cd->wb_rx_head = &cd->wb_rx_chain[0]; 1080 1081 return(0); 1082} 1083 1084static void wb_bfree(buf, args) 1085 caddr_t buf; 1086 void *args; 1087{ 1088 return; 1089} 1090 1091/* 1092 * Initialize an RX descriptor and attach an MBUF cluster. 1093 */ 1094static int wb_newbuf(sc, c, m) 1095 struct wb_softc *sc; 1096 struct wb_chain_onefrag *c; 1097 struct mbuf *m; 1098{ 1099 struct mbuf *m_new = NULL; 1100 1101 if (m == NULL) { 1102 MGETHDR(m_new, M_DONTWAIT, MT_DATA); 1103 if (m_new == NULL) { 1104 printf("wb%d: no memory for rx " 1105 "list -- packet dropped!\n", sc->wb_unit); 1106 return(ENOBUFS); 1107 } 1108 m_new->m_data = c->wb_buf; 1109 m_new->m_pkthdr.len = m_new->m_len = WB_BUFBYTES; 1110 MEXTADD(m_new, c->wb_buf, WB_BUFBYTES, wb_bfree, NULL); 1111 } else { 1112 m_new = m; 1113 m_new->m_len = m_new->m_pkthdr.len = WB_BUFBYTES; 1114 m_new->m_data = m_new->m_ext.ext_buf; 1115 } 1116 1117 m_adj(m_new, sizeof(u_int64_t)); 1118 1119 c->wb_mbuf = m_new; 1120 c->wb_ptr->wb_data = vtophys(mtod(m_new, caddr_t)); 1121 c->wb_ptr->wb_ctl = WB_RXCTL_RLINK | 1536; 1122 c->wb_ptr->wb_status = WB_RXSTAT; 1123 1124 return(0); 1125} 1126 1127/* 1128 * A frame has been uploaded: pass the resulting mbuf chain up to 1129 * the higher level protocols. 1130 */ 1131static void wb_rxeof(sc) 1132 struct wb_softc *sc; 1133{ 1134 struct ether_header *eh; 1135 struct mbuf *m = NULL; 1136 struct ifnet *ifp; 1137 struct wb_chain_onefrag *cur_rx; 1138 int total_len = 0; 1139 u_int32_t rxstat; 1140 1141 ifp = &sc->arpcom.ac_if; 1142 1143 while(!((rxstat = sc->wb_cdata.wb_rx_head->wb_ptr->wb_status) & 1144 WB_RXSTAT_OWN)) { 1145 struct mbuf *m0 = NULL; 1146 1147 cur_rx = sc->wb_cdata.wb_rx_head; 1148 sc->wb_cdata.wb_rx_head = cur_rx->wb_nextdesc; 1149 1150 m = cur_rx->wb_mbuf; 1151 1152 if ((rxstat & WB_RXSTAT_MIIERR) || 1153 (WB_RXBYTES(cur_rx->wb_ptr->wb_status) < WB_MIN_FRAMELEN) || 1154 (WB_RXBYTES(cur_rx->wb_ptr->wb_status) > 1536) || 1155 !(rxstat & WB_RXSTAT_LASTFRAG) || 1156 !(rxstat & WB_RXSTAT_RXCMP)) { 1157 ifp->if_ierrors++; 1158 wb_newbuf(sc, cur_rx, m); 1159 printf("wb%x: receiver babbling: possible chip " 1160 "bug, forcing reset\n", sc->wb_unit); 1161 wb_fixmedia(sc); 1162 wb_reset(sc); 1163 wb_init(sc); 1164 return; 1165 } 1166 1167 if (rxstat & WB_RXSTAT_RXERR) { 1168 ifp->if_ierrors++; 1169 wb_newbuf(sc, cur_rx, m); 1170 break; 1171 } 1172 1173 /* No errors; receive the packet. */ 1174 total_len = WB_RXBYTES(cur_rx->wb_ptr->wb_status); 1175 1176 /* 1177 * XXX The Winbond chip includes the CRC with every 1178 * received frame, and there's no way to turn this 1179 * behavior off (at least, I can't find anything in 1180 * the manual that explains how to do it) so we have 1181 * to trim off the CRC manually. 1182 */ 1183 total_len -= ETHER_CRC_LEN; 1184 1185 m0 = m_devget(mtod(m, char *) - ETHER_ALIGN, 1186 total_len + ETHER_ALIGN, 0, ifp, NULL); 1187 wb_newbuf(sc, cur_rx, m); 1188 if (m0 == NULL) { 1189 ifp->if_ierrors++; 1190 break; 1191 } 1192 m_adj(m0, ETHER_ALIGN); 1193 m = m0; 1194 1195 ifp->if_ipackets++; 1196 eh = mtod(m, struct ether_header *); 1197 1198 /* Remove header from mbuf and pass it on. */ 1199 m_adj(m, sizeof(struct ether_header)); 1200 ether_input(ifp, eh, m); 1201 } 1202} 1203 1204void wb_rxeoc(sc) 1205 struct wb_softc *sc; 1206{ 1207 wb_rxeof(sc); 1208 1209 WB_CLRBIT(sc, WB_NETCFG, WB_NETCFG_RX_ON); 1210 CSR_WRITE_4(sc, WB_RXADDR, vtophys(&sc->wb_ldata->wb_rx_list[0])); 1211 WB_SETBIT(sc, WB_NETCFG, WB_NETCFG_RX_ON); 1212 if (CSR_READ_4(sc, WB_ISR) & WB_RXSTATE_SUSPEND) 1213 CSR_WRITE_4(sc, WB_RXSTART, 0xFFFFFFFF); 1214 1215 return; 1216} 1217 1218/* 1219 * A frame was downloaded to the chip. It's safe for us to clean up 1220 * the list buffers. 1221 */ 1222static void wb_txeof(sc) 1223 struct wb_softc *sc; 1224{ 1225 struct wb_chain *cur_tx; 1226 struct ifnet *ifp; 1227 1228 ifp = &sc->arpcom.ac_if; 1229 1230 /* Clear the timeout timer. */ 1231 ifp->if_timer = 0; 1232 1233 if (sc->wb_cdata.wb_tx_head == NULL) 1234 return; 1235 1236 /* 1237 * Go through our tx list and free mbufs for those 1238 * frames that have been transmitted. 1239 */ 1240 while(sc->wb_cdata.wb_tx_head->wb_mbuf != NULL) { 1241 u_int32_t txstat; 1242 1243 cur_tx = sc->wb_cdata.wb_tx_head; 1244 txstat = WB_TXSTATUS(cur_tx); 1245 1246 if ((txstat & WB_TXSTAT_OWN) || txstat == WB_UNSENT) 1247 break; 1248 1249 if (txstat & WB_TXSTAT_TXERR) { 1250 ifp->if_oerrors++; 1251 if (txstat & WB_TXSTAT_ABORT) 1252 ifp->if_collisions++; 1253 if (txstat & WB_TXSTAT_LATECOLL) 1254 ifp->if_collisions++; 1255 } 1256 1257 ifp->if_collisions += (txstat & WB_TXSTAT_COLLCNT) >> 3; 1258 1259 ifp->if_opackets++; 1260 m_freem(cur_tx->wb_mbuf); 1261 cur_tx->wb_mbuf = NULL; 1262 1263 if (sc->wb_cdata.wb_tx_head == sc->wb_cdata.wb_tx_tail) { 1264 sc->wb_cdata.wb_tx_head = NULL; 1265 sc->wb_cdata.wb_tx_tail = NULL; 1266 break; 1267 } 1268 1269 sc->wb_cdata.wb_tx_head = cur_tx->wb_nextdesc; 1270 } 1271 1272 return; 1273} 1274 1275/* 1276 * TX 'end of channel' interrupt handler. 1277 */ 1278static void wb_txeoc(sc) 1279 struct wb_softc *sc; 1280{ 1281 struct ifnet *ifp; 1282 1283 ifp = &sc->arpcom.ac_if; 1284 1285 ifp->if_timer = 0; 1286 1287 if (sc->wb_cdata.wb_tx_head == NULL) { 1288 ifp->if_flags &= ~IFF_OACTIVE; 1289 sc->wb_cdata.wb_tx_tail = NULL; 1290 } else { 1291 if (WB_TXOWN(sc->wb_cdata.wb_tx_head) == WB_UNSENT) { 1292 WB_TXOWN(sc->wb_cdata.wb_tx_head) = WB_TXSTAT_OWN; 1293 ifp->if_timer = 5; 1294 CSR_WRITE_4(sc, WB_TXSTART, 0xFFFFFFFF); 1295 } 1296 } 1297 1298 return; 1299} 1300 1301static void wb_intr(arg) 1302 void *arg; 1303{ 1304 struct wb_softc *sc; 1305 struct ifnet *ifp; 1306 u_int32_t status; 1307 1308 sc = arg; 1309 WB_LOCK(sc); 1310 ifp = &sc->arpcom.ac_if; 1311 1312 if (!(ifp->if_flags & IFF_UP)) { 1313 WB_UNLOCK(sc); 1314 return; 1315 } 1316 1317 /* Disable interrupts. */ 1318 CSR_WRITE_4(sc, WB_IMR, 0x00000000); 1319 1320 for (;;) { 1321 1322 status = CSR_READ_4(sc, WB_ISR); 1323 if (status) 1324 CSR_WRITE_4(sc, WB_ISR, status); 1325 1326 if ((status & WB_INTRS) == 0) 1327 break; 1328 1329 if ((status & WB_ISR_RX_NOBUF) || (status & WB_ISR_RX_ERR)) { 1330 ifp->if_ierrors++; 1331 wb_reset(sc); 1332 if (status & WB_ISR_RX_ERR) 1333 wb_fixmedia(sc); 1334 wb_init(sc); 1335 continue; 1336 } 1337 1338 if (status & WB_ISR_RX_OK) 1339 wb_rxeof(sc); 1340 1341 if (status & WB_ISR_RX_IDLE) 1342 wb_rxeoc(sc); 1343 1344 if (status & WB_ISR_TX_OK) 1345 wb_txeof(sc); 1346 1347 if (status & WB_ISR_TX_NOBUF) 1348 wb_txeoc(sc); 1349 1350 if (status & WB_ISR_TX_IDLE) { 1351 wb_txeof(sc); 1352 if (sc->wb_cdata.wb_tx_head != NULL) { 1353 WB_SETBIT(sc, WB_NETCFG, WB_NETCFG_TX_ON); 1354 CSR_WRITE_4(sc, WB_TXSTART, 0xFFFFFFFF); 1355 } 1356 } 1357 1358 if (status & WB_ISR_TX_UNDERRUN) { 1359 ifp->if_oerrors++; 1360 wb_txeof(sc); 1361 WB_CLRBIT(sc, WB_NETCFG, WB_NETCFG_TX_ON); 1362 /* Jack up TX threshold */ 1363 sc->wb_txthresh += WB_TXTHRESH_CHUNK; 1364 WB_CLRBIT(sc, WB_NETCFG, WB_NETCFG_TX_THRESH); 1365 WB_SETBIT(sc, WB_NETCFG, WB_TXTHRESH(sc->wb_txthresh)); 1366 WB_SETBIT(sc, WB_NETCFG, WB_NETCFG_TX_ON); 1367 } 1368 1369 if (status & WB_ISR_BUS_ERR) { 1370 wb_reset(sc); 1371 wb_init(sc); 1372 } 1373 1374 } 1375 1376 /* Re-enable interrupts. */ 1377 CSR_WRITE_4(sc, WB_IMR, WB_INTRS); 1378 1379 if (ifp->if_snd.ifq_head != NULL) { 1380 wb_start(ifp); 1381 } 1382 1383 WB_UNLOCK(sc); 1384 1385 return; 1386} 1387 1388static void wb_tick(xsc) 1389 void *xsc; 1390{ 1391 struct wb_softc *sc; 1392 struct mii_data *mii; 1393 1394 sc = xsc; 1395 WB_LOCK(sc); 1396 mii = device_get_softc(sc->wb_miibus); 1397 1398 mii_tick(mii); 1399 1400 sc->wb_stat_ch = timeout(wb_tick, sc, hz); 1401 1402 WB_UNLOCK(sc); 1403 1404 return; 1405} 1406 1407/* 1408 * Encapsulate an mbuf chain in a descriptor by coupling the mbuf data 1409 * pointers to the fragment pointers. 1410 */ 1411static int wb_encap(sc, c, m_head) 1412 struct wb_softc *sc; 1413 struct wb_chain *c; 1414 struct mbuf *m_head; 1415{ 1416 int frag = 0; 1417 struct wb_desc *f = NULL; 1418 int total_len; 1419 struct mbuf *m; 1420 1421 /* 1422 * Start packing the mbufs in this chain into 1423 * the fragment pointers. Stop when we run out 1424 * of fragments or hit the end of the mbuf chain. 1425 */ 1426 m = m_head; 1427 total_len = 0; 1428 1429 for (m = m_head, frag = 0; m != NULL; m = m->m_next) { 1430 if (m->m_len != 0) { 1431 if (frag == WB_MAXFRAGS) 1432 break; 1433 total_len += m->m_len; 1434 f = &c->wb_ptr->wb_frag[frag]; 1435 f->wb_ctl = WB_TXCTL_TLINK | m->m_len; 1436 if (frag == 0) { 1437 f->wb_ctl |= WB_TXCTL_FIRSTFRAG; 1438 f->wb_status = 0; 1439 } else 1440 f->wb_status = WB_TXSTAT_OWN; 1441 f->wb_next = vtophys(&c->wb_ptr->wb_frag[frag + 1]); 1442 f->wb_data = vtophys(mtod(m, vm_offset_t)); 1443 frag++; 1444 } 1445 } 1446 1447 /* 1448 * Handle special case: we used up all 16 fragments, 1449 * but we have more mbufs left in the chain. Copy the 1450 * data into an mbuf cluster. Note that we don't 1451 * bother clearing the values in the other fragment 1452 * pointers/counters; it wouldn't gain us anything, 1453 * and would waste cycles. 1454 */ 1455 if (m != NULL) { 1456 struct mbuf *m_new = NULL; 1457 1458 MGETHDR(m_new, M_DONTWAIT, MT_DATA); 1459 if (m_new == NULL) { 1460 printf("wb%d: no memory for tx list", sc->wb_unit); 1461 return(1); 1462 } 1463 if (m_head->m_pkthdr.len > MHLEN) { 1464 MCLGET(m_new, M_DONTWAIT); 1465 if (!(m_new->m_flags & M_EXT)) { 1466 m_freem(m_new); 1467 printf("wb%d: no memory for tx list", 1468 sc->wb_unit); 1469 return(1); 1470 } 1471 } 1472 m_copydata(m_head, 0, m_head->m_pkthdr.len, 1473 mtod(m_new, caddr_t)); 1474 m_new->m_pkthdr.len = m_new->m_len = m_head->m_pkthdr.len; 1475 m_freem(m_head); 1476 m_head = m_new; 1477 f = &c->wb_ptr->wb_frag[0]; 1478 f->wb_status = 0; 1479 f->wb_data = vtophys(mtod(m_new, caddr_t)); 1480 f->wb_ctl = total_len = m_new->m_len; 1481 f->wb_ctl |= WB_TXCTL_TLINK|WB_TXCTL_FIRSTFRAG; 1482 frag = 1; 1483 } 1484 1485 if (total_len < WB_MIN_FRAMELEN) { 1486 f = &c->wb_ptr->wb_frag[frag]; 1487 f->wb_ctl = WB_MIN_FRAMELEN - total_len; 1488 f->wb_data = vtophys(&sc->wb_cdata.wb_pad); 1489 f->wb_ctl |= WB_TXCTL_TLINK; 1490 f->wb_status = WB_TXSTAT_OWN; 1491 frag++; 1492 } 1493 1494 c->wb_mbuf = m_head; 1495 c->wb_lastdesc = frag - 1; 1496 WB_TXCTL(c) |= WB_TXCTL_LASTFRAG; 1497 WB_TXNEXT(c) = vtophys(&c->wb_nextdesc->wb_ptr->wb_frag[0]); 1498 1499 return(0); 1500} 1501 1502/* 1503 * Main transmit routine. To avoid having to do mbuf copies, we put pointers 1504 * to the mbuf data regions directly in the transmit lists. We also save a 1505 * copy of the pointers since the transmit list fragment pointers are 1506 * physical addresses. 1507 */ 1508 1509static void wb_start(ifp) 1510 struct ifnet *ifp; 1511{ 1512 struct wb_softc *sc; 1513 struct mbuf *m_head = NULL; 1514 struct wb_chain *cur_tx = NULL, *start_tx; 1515 1516 sc = ifp->if_softc; 1517 WB_LOCK(sc); 1518 1519 /* 1520 * Check for an available queue slot. If there are none, 1521 * punt. 1522 */ 1523 if (sc->wb_cdata.wb_tx_free->wb_mbuf != NULL) { 1524 ifp->if_flags |= IFF_OACTIVE; 1525 WB_UNLOCK(sc); 1526 return; 1527 } 1528 1529 start_tx = sc->wb_cdata.wb_tx_free; 1530 1531 while(sc->wb_cdata.wb_tx_free->wb_mbuf == NULL) { 1532 IF_DEQUEUE(&ifp->if_snd, m_head); 1533 if (m_head == NULL) 1534 break; 1535 1536 /* Pick a descriptor off the free list. */ 1537 cur_tx = sc->wb_cdata.wb_tx_free; 1538 sc->wb_cdata.wb_tx_free = cur_tx->wb_nextdesc; 1539 1540 /* Pack the data into the descriptor. */ 1541 wb_encap(sc, cur_tx, m_head); 1542 1543 if (cur_tx != start_tx) 1544 WB_TXOWN(cur_tx) = WB_TXSTAT_OWN; 1545 1546 /* 1547 * If there's a BPF listener, bounce a copy of this frame 1548 * to him. 1549 */ 1550 if (ifp->if_bpf) 1551 bpf_mtap(ifp, cur_tx->wb_mbuf); 1552 } 1553 1554 /* 1555 * If there are no packets queued, bail. 1556 */ 1557 if (cur_tx == NULL) { 1558 WB_UNLOCK(sc); 1559 return; 1560 } 1561 1562 /* 1563 * Place the request for the upload interrupt 1564 * in the last descriptor in the chain. This way, if 1565 * we're chaining several packets at once, we'll only 1566 * get an interupt once for the whole chain rather than 1567 * once for each packet. 1568 */ 1569 WB_TXCTL(cur_tx) |= WB_TXCTL_FINT; 1570 cur_tx->wb_ptr->wb_frag[0].wb_ctl |= WB_TXCTL_FINT; 1571 sc->wb_cdata.wb_tx_tail = cur_tx; 1572 1573 if (sc->wb_cdata.wb_tx_head == NULL) { 1574 sc->wb_cdata.wb_tx_head = start_tx; 1575 WB_TXOWN(start_tx) = WB_TXSTAT_OWN; 1576 CSR_WRITE_4(sc, WB_TXSTART, 0xFFFFFFFF); 1577 } else { 1578 /* 1579 * We need to distinguish between the case where 1580 * the own bit is clear because the chip cleared it 1581 * and where the own bit is clear because we haven't 1582 * set it yet. The magic value WB_UNSET is just some 1583 * ramdomly chosen number which doesn't have the own 1584 * bit set. When we actually transmit the frame, the 1585 * status word will have _only_ the own bit set, so 1586 * the txeoc handler will be able to tell if it needs 1587 * to initiate another transmission to flush out pending 1588 * frames. 1589 */ 1590 WB_TXOWN(start_tx) = WB_UNSENT; 1591 } 1592 1593 /* 1594 * Set a timeout in case the chip goes out to lunch. 1595 */ 1596 ifp->if_timer = 5; 1597 WB_UNLOCK(sc); 1598 1599 return; 1600} 1601 1602static void wb_init(xsc) 1603 void *xsc; 1604{ 1605 struct wb_softc *sc = xsc; 1606 struct ifnet *ifp = &sc->arpcom.ac_if; 1607 int i; 1608 struct mii_data *mii; 1609 1610 WB_LOCK(sc); 1611 mii = device_get_softc(sc->wb_miibus); 1612 1613 /* 1614 * Cancel pending I/O and free all RX/TX buffers. 1615 */ 1616 wb_stop(sc); 1617 wb_reset(sc); 1618 1619 sc->wb_txthresh = WB_TXTHRESH_INIT; 1620 1621 /* 1622 * Set cache alignment and burst length. 1623 */ 1624#ifdef foo 1625 CSR_WRITE_4(sc, WB_BUSCTL, WB_BUSCTL_CONFIG); 1626 WB_CLRBIT(sc, WB_NETCFG, WB_NETCFG_TX_THRESH); 1627 WB_SETBIT(sc, WB_NETCFG, WB_TXTHRESH(sc->wb_txthresh)); 1628#endif 1629 1630 CSR_WRITE_4(sc, WB_BUSCTL, WB_BUSCTL_MUSTBEONE|WB_BUSCTL_ARBITRATION); 1631 WB_SETBIT(sc, WB_BUSCTL, WB_BURSTLEN_16LONG); 1632 switch(sc->wb_cachesize) { 1633 case 32: 1634 WB_SETBIT(sc, WB_BUSCTL, WB_CACHEALIGN_32LONG); 1635 break; 1636 case 16: 1637 WB_SETBIT(sc, WB_BUSCTL, WB_CACHEALIGN_16LONG); 1638 break; 1639 case 8: 1640 WB_SETBIT(sc, WB_BUSCTL, WB_CACHEALIGN_8LONG); 1641 break; 1642 case 0: 1643 default: 1644 WB_SETBIT(sc, WB_BUSCTL, WB_CACHEALIGN_NONE); 1645 break; 1646 } 1647 1648 /* This doesn't tend to work too well at 100Mbps. */ 1649 WB_CLRBIT(sc, WB_NETCFG, WB_NETCFG_TX_EARLY_ON); 1650 1651 /* Init our MAC address */ 1652 for (i = 0; i < ETHER_ADDR_LEN; i++) { 1653 CSR_WRITE_1(sc, WB_NODE0 + i, sc->arpcom.ac_enaddr[i]); 1654 } 1655 1656 /* Init circular RX list. */ 1657 if (wb_list_rx_init(sc) == ENOBUFS) { 1658 printf("wb%d: initialization failed: no " 1659 "memory for rx buffers\n", sc->wb_unit); 1660 wb_stop(sc); 1661 WB_UNLOCK(sc); 1662 return; 1663 } 1664 1665 /* Init TX descriptors. */ 1666 wb_list_tx_init(sc); 1667 1668 /* If we want promiscuous mode, set the allframes bit. */ 1669 if (ifp->if_flags & IFF_PROMISC) { 1670 WB_SETBIT(sc, WB_NETCFG, WB_NETCFG_RX_ALLPHYS); 1671 } else { 1672 WB_CLRBIT(sc, WB_NETCFG, WB_NETCFG_RX_ALLPHYS); 1673 } 1674 1675 /* 1676 * Set capture broadcast bit to capture broadcast frames. 1677 */ 1678 if (ifp->if_flags & IFF_BROADCAST) { 1679 WB_SETBIT(sc, WB_NETCFG, WB_NETCFG_RX_BROAD); 1680 } else { 1681 WB_CLRBIT(sc, WB_NETCFG, WB_NETCFG_RX_BROAD); 1682 } 1683 1684 /* 1685 * Program the multicast filter, if necessary. 1686 */ 1687 wb_setmulti(sc); 1688 1689 /* 1690 * Load the address of the RX list. 1691 */ 1692 WB_CLRBIT(sc, WB_NETCFG, WB_NETCFG_RX_ON); 1693 CSR_WRITE_4(sc, WB_RXADDR, vtophys(&sc->wb_ldata->wb_rx_list[0])); 1694 1695 /* 1696 * Enable interrupts. 1697 */ 1698 CSR_WRITE_4(sc, WB_IMR, WB_INTRS); 1699 CSR_WRITE_4(sc, WB_ISR, 0xFFFFFFFF); 1700 1701 /* Enable receiver and transmitter. */ 1702 WB_SETBIT(sc, WB_NETCFG, WB_NETCFG_RX_ON); 1703 CSR_WRITE_4(sc, WB_RXSTART, 0xFFFFFFFF); 1704 1705 WB_CLRBIT(sc, WB_NETCFG, WB_NETCFG_TX_ON); 1706 CSR_WRITE_4(sc, WB_TXADDR, vtophys(&sc->wb_ldata->wb_tx_list[0])); 1707 WB_SETBIT(sc, WB_NETCFG, WB_NETCFG_TX_ON); 1708 1709 mii_mediachg(mii); 1710 1711 ifp->if_flags |= IFF_RUNNING; 1712 ifp->if_flags &= ~IFF_OACTIVE; 1713 1714 sc->wb_stat_ch = timeout(wb_tick, sc, hz); 1715 WB_UNLOCK(sc); 1716 1717 return; 1718} 1719 1720/* 1721 * Set media options. 1722 */ 1723static int wb_ifmedia_upd(ifp) 1724 struct ifnet *ifp; 1725{ 1726 struct wb_softc *sc; 1727 1728 sc = ifp->if_softc; 1729 1730 if (ifp->if_flags & IFF_UP) 1731 wb_init(sc); 1732 1733 return(0); 1734} 1735 1736/* 1737 * Report current media status. 1738 */ 1739static void wb_ifmedia_sts(ifp, ifmr) 1740 struct ifnet *ifp; 1741 struct ifmediareq *ifmr; 1742{ 1743 struct wb_softc *sc; 1744 struct mii_data *mii; 1745 1746 sc = ifp->if_softc; 1747 1748 mii = device_get_softc(sc->wb_miibus); 1749 1750 mii_pollstat(mii); 1751 ifmr->ifm_active = mii->mii_media_active; 1752 ifmr->ifm_status = mii->mii_media_status; 1753 1754 return; 1755} 1756 1757static int wb_ioctl(ifp, command, data) 1758 struct ifnet *ifp; 1759 u_long command; 1760 caddr_t data; 1761{ 1762 struct wb_softc *sc = ifp->if_softc; 1763 struct mii_data *mii; 1764 struct ifreq *ifr = (struct ifreq *) data; 1765 int error = 0; 1766 1767 WB_LOCK(sc); 1768 1769 switch(command) { 1770 case SIOCSIFADDR: 1771 case SIOCGIFADDR: 1772 case SIOCSIFMTU: 1773 error = ether_ioctl(ifp, command, data); 1774 break; 1775 case SIOCSIFFLAGS: 1776 if (ifp->if_flags & IFF_UP) { 1777 wb_init(sc); 1778 } else { 1779 if (ifp->if_flags & IFF_RUNNING) 1780 wb_stop(sc); 1781 } 1782 error = 0; 1783 break; 1784 case SIOCADDMULTI: 1785 case SIOCDELMULTI: 1786 wb_setmulti(sc); 1787 error = 0; 1788 break; 1789 case SIOCGIFMEDIA: 1790 case SIOCSIFMEDIA: 1791 mii = device_get_softc(sc->wb_miibus); 1792 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command); 1793 break; 1794 default: 1795 error = EINVAL; 1796 break; 1797 } 1798 1799 WB_UNLOCK(sc); 1800 1801 return(error); 1802} 1803 1804static void wb_watchdog(ifp) 1805 struct ifnet *ifp; 1806{ 1807 struct wb_softc *sc; 1808 1809 sc = ifp->if_softc; 1810 1811 WB_LOCK(sc); 1812 ifp->if_oerrors++; 1813 printf("wb%d: watchdog timeout\n", sc->wb_unit); 1814#ifdef foo 1815 if (!(wb_phy_readreg(sc, PHY_BMSR) & PHY_BMSR_LINKSTAT)) 1816 printf("wb%d: no carrier - transceiver cable problem?\n", 1817 sc->wb_unit); 1818#endif 1819 wb_stop(sc); 1820 wb_reset(sc); 1821 wb_init(sc); 1822 1823 if (ifp->if_snd.ifq_head != NULL) 1824 wb_start(ifp); 1825 WB_UNLOCK(sc); 1826 1827 return; 1828} 1829 1830/* 1831 * Stop the adapter and free any mbufs allocated to the 1832 * RX and TX lists. 1833 */ 1834static void wb_stop(sc) 1835 struct wb_softc *sc; 1836{ 1837 register int i; 1838 struct ifnet *ifp; 1839 1840 WB_LOCK(sc); 1841 ifp = &sc->arpcom.ac_if; 1842 ifp->if_timer = 0; 1843 1844 untimeout(wb_tick, sc, sc->wb_stat_ch); 1845 1846 WB_CLRBIT(sc, WB_NETCFG, (WB_NETCFG_RX_ON|WB_NETCFG_TX_ON)); 1847 CSR_WRITE_4(sc, WB_IMR, 0x00000000); 1848 CSR_WRITE_4(sc, WB_TXADDR, 0x00000000); 1849 CSR_WRITE_4(sc, WB_RXADDR, 0x00000000); 1850 1851 /* 1852 * Free data in the RX lists. 1853 */ 1854 for (i = 0; i < WB_RX_LIST_CNT; i++) { 1855 if (sc->wb_cdata.wb_rx_chain[i].wb_mbuf != NULL) { 1856 m_freem(sc->wb_cdata.wb_rx_chain[i].wb_mbuf); 1857 sc->wb_cdata.wb_rx_chain[i].wb_mbuf = NULL; 1858 } 1859 } 1860 bzero((char *)&sc->wb_ldata->wb_rx_list, 1861 sizeof(sc->wb_ldata->wb_rx_list)); 1862 1863 /* 1864 * Free the TX list buffers. 1865 */ 1866 for (i = 0; i < WB_TX_LIST_CNT; i++) { 1867 if (sc->wb_cdata.wb_tx_chain[i].wb_mbuf != NULL) { 1868 m_freem(sc->wb_cdata.wb_tx_chain[i].wb_mbuf); 1869 sc->wb_cdata.wb_tx_chain[i].wb_mbuf = NULL; 1870 } 1871 } 1872 1873 bzero((char *)&sc->wb_ldata->wb_tx_list, 1874 sizeof(sc->wb_ldata->wb_tx_list)); 1875 1876 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 1877 WB_UNLOCK(sc); 1878 1879 return; 1880} 1881 1882/* 1883 * Stop all chip I/O so that the kernel's probe routines don't 1884 * get confused by errant DMAs when rebooting. 1885 */ 1886static void wb_shutdown(dev) 1887 device_t dev; 1888{ 1889 struct wb_softc *sc; 1890 1891 sc = device_get_softc(dev); 1892 wb_stop(sc); 1893 1894 return; 1895} 1896