if_wb.c revision 221407
1/*- 2 * Copyright (c) 1997, 1998 3 * Bill Paul <wpaul@ctr.columbia.edu>. All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 3. All advertising materials mentioning features or use of this software 14 * must display the following acknowledgement: 15 * This product includes software developed by Bill Paul. 16 * 4. Neither the name of the author nor the names of any co-contributors 17 * may be used to endorse or promote products derived from this software 18 * without specific prior written permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 21 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 30 * THE POSSIBILITY OF SUCH DAMAGE. 31 */ 32 33#include <sys/cdefs.h> 34__FBSDID("$FreeBSD: head/sys/dev/wb/if_wb.c 221407 2011-05-03 19:51:29Z marius $"); 35 36/* 37 * Winbond fast ethernet PCI NIC driver 38 * 39 * Supports various cheap network adapters based on the Winbond W89C840F 40 * fast ethernet controller chip. This includes adapters manufactured by 41 * Winbond itself and some made by Linksys. 42 * 43 * Written by Bill Paul <wpaul@ctr.columbia.edu> 44 * Electrical Engineering Department 45 * Columbia University, New York City 46 */ 47/* 48 * The Winbond W89C840F chip is a bus master; in some ways it resembles 49 * a DEC 'tulip' chip, only not as complicated. Unfortunately, it has 50 * one major difference which is that while the registers do many of 51 * the same things as a tulip adapter, the offsets are different: where 52 * tulip registers are typically spaced 8 bytes apart, the Winbond 53 * registers are spaced 4 bytes apart. The receiver filter is also 54 * programmed differently. 55 * 56 * Like the tulip, the Winbond chip uses small descriptors containing 57 * a status word, a control word and 32-bit areas that can either be used 58 * to point to two external data blocks, or to point to a single block 59 * and another descriptor in a linked list. Descriptors can be grouped 60 * together in blocks to form fixed length rings or can be chained 61 * together in linked lists. A single packet may be spread out over 62 * several descriptors if necessary. 63 * 64 * For the receive ring, this driver uses a linked list of descriptors, 65 * each pointing to a single mbuf cluster buffer, which us large enough 66 * to hold an entire packet. The link list is looped back to created a 67 * closed ring. 68 * 69 * For transmission, the driver creates a linked list of 'super descriptors' 70 * which each contain several individual descriptors linked toghether. 71 * Each 'super descriptor' contains WB_MAXFRAGS descriptors, which we 72 * abuse as fragment pointers. This allows us to use a buffer managment 73 * scheme very similar to that used in the ThunderLAN and Etherlink XL 74 * drivers. 75 * 76 * Autonegotiation is performed using the external PHY via the MII bus. 77 * The sample boards I have all use a Davicom PHY. 78 * 79 * Note: the author of the Linux driver for the Winbond chip alludes 80 * to some sort of flaw in the chip's design that seems to mandate some 81 * drastic workaround which signigicantly impairs transmit performance. 82 * I have no idea what he's on about: transmit performance with all 83 * three of my test boards seems fine. 84 */ 85 86#include <sys/param.h> 87#include <sys/systm.h> 88#include <sys/sockio.h> 89#include <sys/mbuf.h> 90#include <sys/malloc.h> 91#include <sys/module.h> 92#include <sys/kernel.h> 93#include <sys/socket.h> 94#include <sys/queue.h> 95 96#include <net/if.h> 97#include <net/if_arp.h> 98#include <net/ethernet.h> 99#include <net/if_dl.h> 100#include <net/if_media.h> 101#include <net/if_types.h> 102 103#include <net/bpf.h> 104 105#include <vm/vm.h> /* for vtophys */ 106#include <vm/pmap.h> /* for vtophys */ 107#include <machine/bus.h> 108#include <machine/resource.h> 109#include <sys/bus.h> 110#include <sys/rman.h> 111 112#include <dev/pci/pcireg.h> 113#include <dev/pci/pcivar.h> 114 115#include <dev/mii/mii.h> 116#include <dev/mii/miivar.h> 117 118/* "device miibus" required. See GENERIC if you get errors here. */ 119#include "miibus_if.h" 120 121#define WB_USEIOSPACE 122 123#include <dev/wb/if_wbreg.h> 124 125MODULE_DEPEND(wb, pci, 1, 1, 1); 126MODULE_DEPEND(wb, ether, 1, 1, 1); 127MODULE_DEPEND(wb, miibus, 1, 1, 1); 128 129/* 130 * Various supported device vendors/types and their names. 131 */ 132static struct wb_type wb_devs[] = { 133 { WB_VENDORID, WB_DEVICEID_840F, 134 "Winbond W89C840F 10/100BaseTX" }, 135 { CP_VENDORID, CP_DEVICEID_RL100, 136 "Compex RL100-ATX 10/100baseTX" }, 137 { 0, 0, NULL } 138}; 139 140static int wb_probe(device_t); 141static int wb_attach(device_t); 142static int wb_detach(device_t); 143 144static void wb_bfree(void *addr, void *args); 145static int wb_newbuf(struct wb_softc *, struct wb_chain_onefrag *, 146 struct mbuf *); 147static int wb_encap(struct wb_softc *, struct wb_chain *, struct mbuf *); 148 149static void wb_rxeof(struct wb_softc *); 150static void wb_rxeoc(struct wb_softc *); 151static void wb_txeof(struct wb_softc *); 152static void wb_txeoc(struct wb_softc *); 153static void wb_intr(void *); 154static void wb_tick(void *); 155static void wb_start(struct ifnet *); 156static void wb_start_locked(struct ifnet *); 157static int wb_ioctl(struct ifnet *, u_long, caddr_t); 158static void wb_init(void *); 159static void wb_init_locked(struct wb_softc *); 160static void wb_stop(struct wb_softc *); 161static void wb_watchdog(struct wb_softc *); 162static int wb_shutdown(device_t); 163static int wb_ifmedia_upd(struct ifnet *); 164static void wb_ifmedia_sts(struct ifnet *, struct ifmediareq *); 165 166static void wb_eeprom_putbyte(struct wb_softc *, int); 167static void wb_eeprom_getword(struct wb_softc *, int, u_int16_t *); 168static void wb_read_eeprom(struct wb_softc *, caddr_t, int, int, int); 169static void wb_mii_sync(struct wb_softc *); 170static void wb_mii_send(struct wb_softc *, u_int32_t, int); 171static int wb_mii_readreg(struct wb_softc *, struct wb_mii_frame *); 172static int wb_mii_writereg(struct wb_softc *, struct wb_mii_frame *); 173 174static void wb_setcfg(struct wb_softc *, u_int32_t); 175static void wb_setmulti(struct wb_softc *); 176static void wb_reset(struct wb_softc *); 177static void wb_fixmedia(struct wb_softc *); 178static int wb_list_rx_init(struct wb_softc *); 179static int wb_list_tx_init(struct wb_softc *); 180 181static int wb_miibus_readreg(device_t, int, int); 182static int wb_miibus_writereg(device_t, int, int, int); 183static void wb_miibus_statchg(device_t); 184 185#ifdef WB_USEIOSPACE 186#define WB_RES SYS_RES_IOPORT 187#define WB_RID WB_PCI_LOIO 188#else 189#define WB_RES SYS_RES_MEMORY 190#define WB_RID WB_PCI_LOMEM 191#endif 192 193static device_method_t wb_methods[] = { 194 /* Device interface */ 195 DEVMETHOD(device_probe, wb_probe), 196 DEVMETHOD(device_attach, wb_attach), 197 DEVMETHOD(device_detach, wb_detach), 198 DEVMETHOD(device_shutdown, wb_shutdown), 199 200 /* bus interface, for miibus */ 201 DEVMETHOD(bus_print_child, bus_generic_print_child), 202 DEVMETHOD(bus_driver_added, bus_generic_driver_added), 203 204 /* MII interface */ 205 DEVMETHOD(miibus_readreg, wb_miibus_readreg), 206 DEVMETHOD(miibus_writereg, wb_miibus_writereg), 207 DEVMETHOD(miibus_statchg, wb_miibus_statchg), 208 { 0, 0 } 209}; 210 211static driver_t wb_driver = { 212 "wb", 213 wb_methods, 214 sizeof(struct wb_softc) 215}; 216 217static devclass_t wb_devclass; 218 219DRIVER_MODULE(wb, pci, wb_driver, wb_devclass, 0, 0); 220DRIVER_MODULE(miibus, wb, miibus_driver, miibus_devclass, 0, 0); 221 222#define WB_SETBIT(sc, reg, x) \ 223 CSR_WRITE_4(sc, reg, \ 224 CSR_READ_4(sc, reg) | (x)) 225 226#define WB_CLRBIT(sc, reg, x) \ 227 CSR_WRITE_4(sc, reg, \ 228 CSR_READ_4(sc, reg) & ~(x)) 229 230#define SIO_SET(x) \ 231 CSR_WRITE_4(sc, WB_SIO, \ 232 CSR_READ_4(sc, WB_SIO) | (x)) 233 234#define SIO_CLR(x) \ 235 CSR_WRITE_4(sc, WB_SIO, \ 236 CSR_READ_4(sc, WB_SIO) & ~(x)) 237 238/* 239 * Send a read command and address to the EEPROM, check for ACK. 240 */ 241static void 242wb_eeprom_putbyte(sc, addr) 243 struct wb_softc *sc; 244 int addr; 245{ 246 register int d, i; 247 248 d = addr | WB_EECMD_READ; 249 250 /* 251 * Feed in each bit and stobe the clock. 252 */ 253 for (i = 0x400; i; i >>= 1) { 254 if (d & i) { 255 SIO_SET(WB_SIO_EE_DATAIN); 256 } else { 257 SIO_CLR(WB_SIO_EE_DATAIN); 258 } 259 DELAY(100); 260 SIO_SET(WB_SIO_EE_CLK); 261 DELAY(150); 262 SIO_CLR(WB_SIO_EE_CLK); 263 DELAY(100); 264 } 265 266 return; 267} 268 269/* 270 * Read a word of data stored in the EEPROM at address 'addr.' 271 */ 272static void 273wb_eeprom_getword(sc, addr, dest) 274 struct wb_softc *sc; 275 int addr; 276 u_int16_t *dest; 277{ 278 register int i; 279 u_int16_t word = 0; 280 281 /* Enter EEPROM access mode. */ 282 CSR_WRITE_4(sc, WB_SIO, WB_SIO_EESEL|WB_SIO_EE_CS); 283 284 /* 285 * Send address of word we want to read. 286 */ 287 wb_eeprom_putbyte(sc, addr); 288 289 CSR_WRITE_4(sc, WB_SIO, WB_SIO_EESEL|WB_SIO_EE_CS); 290 291 /* 292 * Start reading bits from EEPROM. 293 */ 294 for (i = 0x8000; i; i >>= 1) { 295 SIO_SET(WB_SIO_EE_CLK); 296 DELAY(100); 297 if (CSR_READ_4(sc, WB_SIO) & WB_SIO_EE_DATAOUT) 298 word |= i; 299 SIO_CLR(WB_SIO_EE_CLK); 300 DELAY(100); 301 } 302 303 /* Turn off EEPROM access mode. */ 304 CSR_WRITE_4(sc, WB_SIO, 0); 305 306 *dest = word; 307 308 return; 309} 310 311/* 312 * Read a sequence of words from the EEPROM. 313 */ 314static void 315wb_read_eeprom(sc, dest, off, cnt, swap) 316 struct wb_softc *sc; 317 caddr_t dest; 318 int off; 319 int cnt; 320 int swap; 321{ 322 int i; 323 u_int16_t word = 0, *ptr; 324 325 for (i = 0; i < cnt; i++) { 326 wb_eeprom_getword(sc, off + i, &word); 327 ptr = (u_int16_t *)(dest + (i * 2)); 328 if (swap) 329 *ptr = ntohs(word); 330 else 331 *ptr = word; 332 } 333 334 return; 335} 336 337/* 338 * Sync the PHYs by setting data bit and strobing the clock 32 times. 339 */ 340static void 341wb_mii_sync(sc) 342 struct wb_softc *sc; 343{ 344 register int i; 345 346 SIO_SET(WB_SIO_MII_DIR|WB_SIO_MII_DATAIN); 347 348 for (i = 0; i < 32; i++) { 349 SIO_SET(WB_SIO_MII_CLK); 350 DELAY(1); 351 SIO_CLR(WB_SIO_MII_CLK); 352 DELAY(1); 353 } 354 355 return; 356} 357 358/* 359 * Clock a series of bits through the MII. 360 */ 361static void 362wb_mii_send(sc, bits, cnt) 363 struct wb_softc *sc; 364 u_int32_t bits; 365 int cnt; 366{ 367 int i; 368 369 SIO_CLR(WB_SIO_MII_CLK); 370 371 for (i = (0x1 << (cnt - 1)); i; i >>= 1) { 372 if (bits & i) { 373 SIO_SET(WB_SIO_MII_DATAIN); 374 } else { 375 SIO_CLR(WB_SIO_MII_DATAIN); 376 } 377 DELAY(1); 378 SIO_CLR(WB_SIO_MII_CLK); 379 DELAY(1); 380 SIO_SET(WB_SIO_MII_CLK); 381 } 382} 383 384/* 385 * Read an PHY register through the MII. 386 */ 387static int 388wb_mii_readreg(sc, frame) 389 struct wb_softc *sc; 390 struct wb_mii_frame *frame; 391 392{ 393 int i, ack; 394 395 /* 396 * Set up frame for RX. 397 */ 398 frame->mii_stdelim = WB_MII_STARTDELIM; 399 frame->mii_opcode = WB_MII_READOP; 400 frame->mii_turnaround = 0; 401 frame->mii_data = 0; 402 403 CSR_WRITE_4(sc, WB_SIO, 0); 404 405 /* 406 * Turn on data xmit. 407 */ 408 SIO_SET(WB_SIO_MII_DIR); 409 410 wb_mii_sync(sc); 411 412 /* 413 * Send command/address info. 414 */ 415 wb_mii_send(sc, frame->mii_stdelim, 2); 416 wb_mii_send(sc, frame->mii_opcode, 2); 417 wb_mii_send(sc, frame->mii_phyaddr, 5); 418 wb_mii_send(sc, frame->mii_regaddr, 5); 419 420 /* Idle bit */ 421 SIO_CLR((WB_SIO_MII_CLK|WB_SIO_MII_DATAIN)); 422 DELAY(1); 423 SIO_SET(WB_SIO_MII_CLK); 424 DELAY(1); 425 426 /* Turn off xmit. */ 427 SIO_CLR(WB_SIO_MII_DIR); 428 /* Check for ack */ 429 SIO_CLR(WB_SIO_MII_CLK); 430 DELAY(1); 431 ack = CSR_READ_4(sc, WB_SIO) & WB_SIO_MII_DATAOUT; 432 SIO_SET(WB_SIO_MII_CLK); 433 DELAY(1); 434 SIO_CLR(WB_SIO_MII_CLK); 435 DELAY(1); 436 SIO_SET(WB_SIO_MII_CLK); 437 DELAY(1); 438 439 /* 440 * Now try reading data bits. If the ack failed, we still 441 * need to clock through 16 cycles to keep the PHY(s) in sync. 442 */ 443 if (ack) { 444 for(i = 0; i < 16; i++) { 445 SIO_CLR(WB_SIO_MII_CLK); 446 DELAY(1); 447 SIO_SET(WB_SIO_MII_CLK); 448 DELAY(1); 449 } 450 goto fail; 451 } 452 453 for (i = 0x8000; i; i >>= 1) { 454 SIO_CLR(WB_SIO_MII_CLK); 455 DELAY(1); 456 if (!ack) { 457 if (CSR_READ_4(sc, WB_SIO) & WB_SIO_MII_DATAOUT) 458 frame->mii_data |= i; 459 DELAY(1); 460 } 461 SIO_SET(WB_SIO_MII_CLK); 462 DELAY(1); 463 } 464 465fail: 466 467 SIO_CLR(WB_SIO_MII_CLK); 468 DELAY(1); 469 SIO_SET(WB_SIO_MII_CLK); 470 DELAY(1); 471 472 if (ack) 473 return(1); 474 return(0); 475} 476 477/* 478 * Write to a PHY register through the MII. 479 */ 480static int 481wb_mii_writereg(sc, frame) 482 struct wb_softc *sc; 483 struct wb_mii_frame *frame; 484 485{ 486 487 /* 488 * Set up frame for TX. 489 */ 490 491 frame->mii_stdelim = WB_MII_STARTDELIM; 492 frame->mii_opcode = WB_MII_WRITEOP; 493 frame->mii_turnaround = WB_MII_TURNAROUND; 494 495 /* 496 * Turn on data output. 497 */ 498 SIO_SET(WB_SIO_MII_DIR); 499 500 wb_mii_sync(sc); 501 502 wb_mii_send(sc, frame->mii_stdelim, 2); 503 wb_mii_send(sc, frame->mii_opcode, 2); 504 wb_mii_send(sc, frame->mii_phyaddr, 5); 505 wb_mii_send(sc, frame->mii_regaddr, 5); 506 wb_mii_send(sc, frame->mii_turnaround, 2); 507 wb_mii_send(sc, frame->mii_data, 16); 508 509 /* Idle bit. */ 510 SIO_SET(WB_SIO_MII_CLK); 511 DELAY(1); 512 SIO_CLR(WB_SIO_MII_CLK); 513 DELAY(1); 514 515 /* 516 * Turn off xmit. 517 */ 518 SIO_CLR(WB_SIO_MII_DIR); 519 520 return(0); 521} 522 523static int 524wb_miibus_readreg(dev, phy, reg) 525 device_t dev; 526 int phy, reg; 527{ 528 struct wb_softc *sc; 529 struct wb_mii_frame frame; 530 531 sc = device_get_softc(dev); 532 533 bzero((char *)&frame, sizeof(frame)); 534 535 frame.mii_phyaddr = phy; 536 frame.mii_regaddr = reg; 537 wb_mii_readreg(sc, &frame); 538 539 return(frame.mii_data); 540} 541 542static int 543wb_miibus_writereg(dev, phy, reg, data) 544 device_t dev; 545 int phy, reg, data; 546{ 547 struct wb_softc *sc; 548 struct wb_mii_frame frame; 549 550 sc = device_get_softc(dev); 551 552 bzero((char *)&frame, sizeof(frame)); 553 554 frame.mii_phyaddr = phy; 555 frame.mii_regaddr = reg; 556 frame.mii_data = data; 557 558 wb_mii_writereg(sc, &frame); 559 560 return(0); 561} 562 563static void 564wb_miibus_statchg(dev) 565 device_t dev; 566{ 567 struct wb_softc *sc; 568 struct mii_data *mii; 569 570 sc = device_get_softc(dev); 571 mii = device_get_softc(sc->wb_miibus); 572 wb_setcfg(sc, mii->mii_media_active); 573 574 return; 575} 576 577/* 578 * Program the 64-bit multicast hash filter. 579 */ 580static void 581wb_setmulti(sc) 582 struct wb_softc *sc; 583{ 584 struct ifnet *ifp; 585 int h = 0; 586 u_int32_t hashes[2] = { 0, 0 }; 587 struct ifmultiaddr *ifma; 588 u_int32_t rxfilt; 589 int mcnt = 0; 590 591 ifp = sc->wb_ifp; 592 593 rxfilt = CSR_READ_4(sc, WB_NETCFG); 594 595 if (ifp->if_flags & IFF_ALLMULTI || ifp->if_flags & IFF_PROMISC) { 596 rxfilt |= WB_NETCFG_RX_MULTI; 597 CSR_WRITE_4(sc, WB_NETCFG, rxfilt); 598 CSR_WRITE_4(sc, WB_MAR0, 0xFFFFFFFF); 599 CSR_WRITE_4(sc, WB_MAR1, 0xFFFFFFFF); 600 return; 601 } 602 603 /* first, zot all the existing hash bits */ 604 CSR_WRITE_4(sc, WB_MAR0, 0); 605 CSR_WRITE_4(sc, WB_MAR1, 0); 606 607 /* now program new ones */ 608 if_maddr_rlock(ifp); 609 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 610 if (ifma->ifma_addr->sa_family != AF_LINK) 611 continue; 612 h = ~ether_crc32_be(LLADDR((struct sockaddr_dl *) 613 ifma->ifma_addr), ETHER_ADDR_LEN) >> 26; 614 if (h < 32) 615 hashes[0] |= (1 << h); 616 else 617 hashes[1] |= (1 << (h - 32)); 618 mcnt++; 619 } 620 if_maddr_runlock(ifp); 621 622 if (mcnt) 623 rxfilt |= WB_NETCFG_RX_MULTI; 624 else 625 rxfilt &= ~WB_NETCFG_RX_MULTI; 626 627 CSR_WRITE_4(sc, WB_MAR0, hashes[0]); 628 CSR_WRITE_4(sc, WB_MAR1, hashes[1]); 629 CSR_WRITE_4(sc, WB_NETCFG, rxfilt); 630 631 return; 632} 633 634/* 635 * The Winbond manual states that in order to fiddle with the 636 * 'full-duplex' and '100Mbps' bits in the netconfig register, we 637 * first have to put the transmit and/or receive logic in the idle state. 638 */ 639static void 640wb_setcfg(sc, media) 641 struct wb_softc *sc; 642 u_int32_t media; 643{ 644 int i, restart = 0; 645 646 if (CSR_READ_4(sc, WB_NETCFG) & (WB_NETCFG_TX_ON|WB_NETCFG_RX_ON)) { 647 restart = 1; 648 WB_CLRBIT(sc, WB_NETCFG, (WB_NETCFG_TX_ON|WB_NETCFG_RX_ON)); 649 650 for (i = 0; i < WB_TIMEOUT; i++) { 651 DELAY(10); 652 if ((CSR_READ_4(sc, WB_ISR) & WB_ISR_TX_IDLE) && 653 (CSR_READ_4(sc, WB_ISR) & WB_ISR_RX_IDLE)) 654 break; 655 } 656 657 if (i == WB_TIMEOUT) 658 device_printf(sc->wb_dev, 659 "failed to force tx and rx to idle state\n"); 660 } 661 662 if (IFM_SUBTYPE(media) == IFM_10_T) 663 WB_CLRBIT(sc, WB_NETCFG, WB_NETCFG_100MBPS); 664 else 665 WB_SETBIT(sc, WB_NETCFG, WB_NETCFG_100MBPS); 666 667 if ((media & IFM_GMASK) == IFM_FDX) 668 WB_SETBIT(sc, WB_NETCFG, WB_NETCFG_FULLDUPLEX); 669 else 670 WB_CLRBIT(sc, WB_NETCFG, WB_NETCFG_FULLDUPLEX); 671 672 if (restart) 673 WB_SETBIT(sc, WB_NETCFG, WB_NETCFG_TX_ON|WB_NETCFG_RX_ON); 674 675 return; 676} 677 678static void 679wb_reset(sc) 680 struct wb_softc *sc; 681{ 682 register int i; 683 struct mii_data *mii; 684 struct mii_softc *miisc; 685 686 CSR_WRITE_4(sc, WB_NETCFG, 0); 687 CSR_WRITE_4(sc, WB_BUSCTL, 0); 688 CSR_WRITE_4(sc, WB_TXADDR, 0); 689 CSR_WRITE_4(sc, WB_RXADDR, 0); 690 691 WB_SETBIT(sc, WB_BUSCTL, WB_BUSCTL_RESET); 692 WB_SETBIT(sc, WB_BUSCTL, WB_BUSCTL_RESET); 693 694 for (i = 0; i < WB_TIMEOUT; i++) { 695 DELAY(10); 696 if (!(CSR_READ_4(sc, WB_BUSCTL) & WB_BUSCTL_RESET)) 697 break; 698 } 699 if (i == WB_TIMEOUT) 700 device_printf(sc->wb_dev, "reset never completed!\n"); 701 702 /* Wait a little while for the chip to get its brains in order. */ 703 DELAY(1000); 704 705 if (sc->wb_miibus == NULL) 706 return; 707 708 mii = device_get_softc(sc->wb_miibus); 709 LIST_FOREACH(miisc, &mii->mii_phys, mii_list) 710 PHY_RESET(miisc); 711} 712 713static void 714wb_fixmedia(sc) 715 struct wb_softc *sc; 716{ 717 struct mii_data *mii = NULL; 718 struct ifnet *ifp; 719 u_int32_t media; 720 721 mii = device_get_softc(sc->wb_miibus); 722 ifp = sc->wb_ifp; 723 724 mii_pollstat(mii); 725 if (IFM_SUBTYPE(mii->mii_media_active) == IFM_10_T) { 726 media = mii->mii_media_active & ~IFM_10_T; 727 media |= IFM_100_TX; 728 } else if (IFM_SUBTYPE(mii->mii_media_active) == IFM_100_TX) { 729 media = mii->mii_media_active & ~IFM_100_TX; 730 media |= IFM_10_T; 731 } else 732 return; 733 734 ifmedia_set(&mii->mii_media, media); 735} 736 737/* 738 * Probe for a Winbond chip. Check the PCI vendor and device 739 * IDs against our list and return a device name if we find a match. 740 */ 741static int 742wb_probe(dev) 743 device_t dev; 744{ 745 struct wb_type *t; 746 747 t = wb_devs; 748 749 while(t->wb_name != NULL) { 750 if ((pci_get_vendor(dev) == t->wb_vid) && 751 (pci_get_device(dev) == t->wb_did)) { 752 device_set_desc(dev, t->wb_name); 753 return (BUS_PROBE_DEFAULT); 754 } 755 t++; 756 } 757 758 return(ENXIO); 759} 760 761/* 762 * Attach the interface. Allocate softc structures, do ifmedia 763 * setup and ethernet/BPF attach. 764 */ 765static int 766wb_attach(dev) 767 device_t dev; 768{ 769 u_char eaddr[ETHER_ADDR_LEN]; 770 struct wb_softc *sc; 771 struct ifnet *ifp; 772 int error = 0, rid; 773 774 sc = device_get_softc(dev); 775 sc->wb_dev = dev; 776 777 mtx_init(&sc->wb_mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK, 778 MTX_DEF); 779 callout_init_mtx(&sc->wb_stat_callout, &sc->wb_mtx, 0); 780 781 /* 782 * Map control/status registers. 783 */ 784 pci_enable_busmaster(dev); 785 786 rid = WB_RID; 787 sc->wb_res = bus_alloc_resource_any(dev, WB_RES, &rid, RF_ACTIVE); 788 789 if (sc->wb_res == NULL) { 790 device_printf(dev, "couldn't map ports/memory\n"); 791 error = ENXIO; 792 goto fail; 793 } 794 795 /* Allocate interrupt */ 796 rid = 0; 797 sc->wb_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid, 798 RF_SHAREABLE | RF_ACTIVE); 799 800 if (sc->wb_irq == NULL) { 801 device_printf(dev, "couldn't map interrupt\n"); 802 error = ENXIO; 803 goto fail; 804 } 805 806 /* Save the cache line size. */ 807 sc->wb_cachesize = pci_read_config(dev, WB_PCI_CACHELEN, 4) & 0xFF; 808 809 /* Reset the adapter. */ 810 wb_reset(sc); 811 812 /* 813 * Get station address from the EEPROM. 814 */ 815 wb_read_eeprom(sc, (caddr_t)&eaddr, 0, 3, 0); 816 817 sc->wb_ldata = contigmalloc(sizeof(struct wb_list_data) + 8, M_DEVBUF, 818 M_NOWAIT, 0, 0xffffffff, PAGE_SIZE, 0); 819 820 if (sc->wb_ldata == NULL) { 821 device_printf(dev, "no memory for list buffers!\n"); 822 error = ENXIO; 823 goto fail; 824 } 825 826 bzero(sc->wb_ldata, sizeof(struct wb_list_data)); 827 828 ifp = sc->wb_ifp = if_alloc(IFT_ETHER); 829 if (ifp == NULL) { 830 device_printf(dev, "can not if_alloc()\n"); 831 error = ENOSPC; 832 goto fail; 833 } 834 ifp->if_softc = sc; 835 if_initname(ifp, device_get_name(dev), device_get_unit(dev)); 836 ifp->if_mtu = ETHERMTU; 837 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 838 ifp->if_ioctl = wb_ioctl; 839 ifp->if_start = wb_start; 840 ifp->if_init = wb_init; 841 ifp->if_snd.ifq_maxlen = WB_TX_LIST_CNT - 1; 842 843 /* 844 * Do MII setup. 845 */ 846 error = mii_attach(dev, &sc->wb_miibus, ifp, wb_ifmedia_upd, 847 wb_ifmedia_sts, BMSR_DEFCAPMASK, MII_PHY_ANY, MII_OFFSET_ANY, 0); 848 if (error != 0) { 849 device_printf(dev, "attaching PHYs failed\n"); 850 goto fail; 851 } 852 853 /* 854 * Call MI attach routine. 855 */ 856 ether_ifattach(ifp, eaddr); 857 858 /* Hook interrupt last to avoid having to lock softc */ 859 error = bus_setup_intr(dev, sc->wb_irq, INTR_TYPE_NET | INTR_MPSAFE, 860 NULL, wb_intr, sc, &sc->wb_intrhand); 861 862 if (error) { 863 device_printf(dev, "couldn't set up irq\n"); 864 ether_ifdetach(ifp); 865 goto fail; 866 } 867 868fail: 869 if (error) 870 wb_detach(dev); 871 872 return(error); 873} 874 875/* 876 * Shutdown hardware and free up resources. This can be called any 877 * time after the mutex has been initialized. It is called in both 878 * the error case in attach and the normal detach case so it needs 879 * to be careful about only freeing resources that have actually been 880 * allocated. 881 */ 882static int 883wb_detach(dev) 884 device_t dev; 885{ 886 struct wb_softc *sc; 887 struct ifnet *ifp; 888 889 sc = device_get_softc(dev); 890 KASSERT(mtx_initialized(&sc->wb_mtx), ("wb mutex not initialized")); 891 ifp = sc->wb_ifp; 892 893 /* 894 * Delete any miibus and phy devices attached to this interface. 895 * This should only be done if attach succeeded. 896 */ 897 if (device_is_attached(dev)) { 898 ether_ifdetach(ifp); 899 WB_LOCK(sc); 900 wb_stop(sc); 901 WB_UNLOCK(sc); 902 callout_drain(&sc->wb_stat_callout); 903 } 904 if (sc->wb_miibus) 905 device_delete_child(dev, sc->wb_miibus); 906 bus_generic_detach(dev); 907 908 if (sc->wb_intrhand) 909 bus_teardown_intr(dev, sc->wb_irq, sc->wb_intrhand); 910 if (sc->wb_irq) 911 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->wb_irq); 912 if (sc->wb_res) 913 bus_release_resource(dev, WB_RES, WB_RID, sc->wb_res); 914 915 if (ifp) 916 if_free(ifp); 917 918 if (sc->wb_ldata) { 919 contigfree(sc->wb_ldata, sizeof(struct wb_list_data) + 8, 920 M_DEVBUF); 921 } 922 923 mtx_destroy(&sc->wb_mtx); 924 925 return(0); 926} 927 928/* 929 * Initialize the transmit descriptors. 930 */ 931static int 932wb_list_tx_init(sc) 933 struct wb_softc *sc; 934{ 935 struct wb_chain_data *cd; 936 struct wb_list_data *ld; 937 int i; 938 939 cd = &sc->wb_cdata; 940 ld = sc->wb_ldata; 941 942 for (i = 0; i < WB_TX_LIST_CNT; i++) { 943 cd->wb_tx_chain[i].wb_ptr = &ld->wb_tx_list[i]; 944 if (i == (WB_TX_LIST_CNT - 1)) { 945 cd->wb_tx_chain[i].wb_nextdesc = 946 &cd->wb_tx_chain[0]; 947 } else { 948 cd->wb_tx_chain[i].wb_nextdesc = 949 &cd->wb_tx_chain[i + 1]; 950 } 951 } 952 953 cd->wb_tx_free = &cd->wb_tx_chain[0]; 954 cd->wb_tx_tail = cd->wb_tx_head = NULL; 955 956 return(0); 957} 958 959 960/* 961 * Initialize the RX descriptors and allocate mbufs for them. Note that 962 * we arrange the descriptors in a closed ring, so that the last descriptor 963 * points back to the first. 964 */ 965static int 966wb_list_rx_init(sc) 967 struct wb_softc *sc; 968{ 969 struct wb_chain_data *cd; 970 struct wb_list_data *ld; 971 int i; 972 973 cd = &sc->wb_cdata; 974 ld = sc->wb_ldata; 975 976 for (i = 0; i < WB_RX_LIST_CNT; i++) { 977 cd->wb_rx_chain[i].wb_ptr = 978 (struct wb_desc *)&ld->wb_rx_list[i]; 979 cd->wb_rx_chain[i].wb_buf = (void *)&ld->wb_rxbufs[i]; 980 if (wb_newbuf(sc, &cd->wb_rx_chain[i], NULL) == ENOBUFS) 981 return(ENOBUFS); 982 if (i == (WB_RX_LIST_CNT - 1)) { 983 cd->wb_rx_chain[i].wb_nextdesc = &cd->wb_rx_chain[0]; 984 ld->wb_rx_list[i].wb_next = 985 vtophys(&ld->wb_rx_list[0]); 986 } else { 987 cd->wb_rx_chain[i].wb_nextdesc = 988 &cd->wb_rx_chain[i + 1]; 989 ld->wb_rx_list[i].wb_next = 990 vtophys(&ld->wb_rx_list[i + 1]); 991 } 992 } 993 994 cd->wb_rx_head = &cd->wb_rx_chain[0]; 995 996 return(0); 997} 998 999static void 1000wb_bfree(buf, args) 1001 void *buf; 1002 void *args; 1003{ 1004 return; 1005} 1006 1007/* 1008 * Initialize an RX descriptor and attach an MBUF cluster. 1009 */ 1010static int 1011wb_newbuf(sc, c, m) 1012 struct wb_softc *sc; 1013 struct wb_chain_onefrag *c; 1014 struct mbuf *m; 1015{ 1016 struct mbuf *m_new = NULL; 1017 1018 if (m == NULL) { 1019 MGETHDR(m_new, M_DONTWAIT, MT_DATA); 1020 if (m_new == NULL) 1021 return(ENOBUFS); 1022 m_new->m_data = c->wb_buf; 1023 m_new->m_pkthdr.len = m_new->m_len = WB_BUFBYTES; 1024 MEXTADD(m_new, c->wb_buf, WB_BUFBYTES, wb_bfree, c->wb_buf, 1025 NULL, 0, EXT_NET_DRV); 1026 } else { 1027 m_new = m; 1028 m_new->m_len = m_new->m_pkthdr.len = WB_BUFBYTES; 1029 m_new->m_data = m_new->m_ext.ext_buf; 1030 } 1031 1032 m_adj(m_new, sizeof(u_int64_t)); 1033 1034 c->wb_mbuf = m_new; 1035 c->wb_ptr->wb_data = vtophys(mtod(m_new, caddr_t)); 1036 c->wb_ptr->wb_ctl = WB_RXCTL_RLINK | 1536; 1037 c->wb_ptr->wb_status = WB_RXSTAT; 1038 1039 return(0); 1040} 1041 1042/* 1043 * A frame has been uploaded: pass the resulting mbuf chain up to 1044 * the higher level protocols. 1045 */ 1046static void 1047wb_rxeof(sc) 1048 struct wb_softc *sc; 1049{ 1050 struct mbuf *m = NULL; 1051 struct ifnet *ifp; 1052 struct wb_chain_onefrag *cur_rx; 1053 int total_len = 0; 1054 u_int32_t rxstat; 1055 1056 WB_LOCK_ASSERT(sc); 1057 1058 ifp = sc->wb_ifp; 1059 1060 while(!((rxstat = sc->wb_cdata.wb_rx_head->wb_ptr->wb_status) & 1061 WB_RXSTAT_OWN)) { 1062 struct mbuf *m0 = NULL; 1063 1064 cur_rx = sc->wb_cdata.wb_rx_head; 1065 sc->wb_cdata.wb_rx_head = cur_rx->wb_nextdesc; 1066 1067 m = cur_rx->wb_mbuf; 1068 1069 if ((rxstat & WB_RXSTAT_MIIERR) || 1070 (WB_RXBYTES(cur_rx->wb_ptr->wb_status) < WB_MIN_FRAMELEN) || 1071 (WB_RXBYTES(cur_rx->wb_ptr->wb_status) > 1536) || 1072 !(rxstat & WB_RXSTAT_LASTFRAG) || 1073 !(rxstat & WB_RXSTAT_RXCMP)) { 1074 ifp->if_ierrors++; 1075 wb_newbuf(sc, cur_rx, m); 1076 device_printf(sc->wb_dev, 1077 "receiver babbling: possible chip bug," 1078 " forcing reset\n"); 1079 wb_fixmedia(sc); 1080 wb_reset(sc); 1081 wb_init_locked(sc); 1082 return; 1083 } 1084 1085 if (rxstat & WB_RXSTAT_RXERR) { 1086 ifp->if_ierrors++; 1087 wb_newbuf(sc, cur_rx, m); 1088 break; 1089 } 1090 1091 /* No errors; receive the packet. */ 1092 total_len = WB_RXBYTES(cur_rx->wb_ptr->wb_status); 1093 1094 /* 1095 * XXX The Winbond chip includes the CRC with every 1096 * received frame, and there's no way to turn this 1097 * behavior off (at least, I can't find anything in 1098 * the manual that explains how to do it) so we have 1099 * to trim off the CRC manually. 1100 */ 1101 total_len -= ETHER_CRC_LEN; 1102 1103 m0 = m_devget(mtod(m, char *), total_len, ETHER_ALIGN, ifp, 1104 NULL); 1105 wb_newbuf(sc, cur_rx, m); 1106 if (m0 == NULL) { 1107 ifp->if_ierrors++; 1108 break; 1109 } 1110 m = m0; 1111 1112 ifp->if_ipackets++; 1113 WB_UNLOCK(sc); 1114 (*ifp->if_input)(ifp, m); 1115 WB_LOCK(sc); 1116 } 1117} 1118 1119static void 1120wb_rxeoc(sc) 1121 struct wb_softc *sc; 1122{ 1123 wb_rxeof(sc); 1124 1125 WB_CLRBIT(sc, WB_NETCFG, WB_NETCFG_RX_ON); 1126 CSR_WRITE_4(sc, WB_RXADDR, vtophys(&sc->wb_ldata->wb_rx_list[0])); 1127 WB_SETBIT(sc, WB_NETCFG, WB_NETCFG_RX_ON); 1128 if (CSR_READ_4(sc, WB_ISR) & WB_RXSTATE_SUSPEND) 1129 CSR_WRITE_4(sc, WB_RXSTART, 0xFFFFFFFF); 1130 1131 return; 1132} 1133 1134/* 1135 * A frame was downloaded to the chip. It's safe for us to clean up 1136 * the list buffers. 1137 */ 1138static void 1139wb_txeof(sc) 1140 struct wb_softc *sc; 1141{ 1142 struct wb_chain *cur_tx; 1143 struct ifnet *ifp; 1144 1145 ifp = sc->wb_ifp; 1146 1147 /* Clear the timeout timer. */ 1148 sc->wb_timer = 0; 1149 1150 if (sc->wb_cdata.wb_tx_head == NULL) 1151 return; 1152 1153 /* 1154 * Go through our tx list and free mbufs for those 1155 * frames that have been transmitted. 1156 */ 1157 while(sc->wb_cdata.wb_tx_head->wb_mbuf != NULL) { 1158 u_int32_t txstat; 1159 1160 cur_tx = sc->wb_cdata.wb_tx_head; 1161 txstat = WB_TXSTATUS(cur_tx); 1162 1163 if ((txstat & WB_TXSTAT_OWN) || txstat == WB_UNSENT) 1164 break; 1165 1166 if (txstat & WB_TXSTAT_TXERR) { 1167 ifp->if_oerrors++; 1168 if (txstat & WB_TXSTAT_ABORT) 1169 ifp->if_collisions++; 1170 if (txstat & WB_TXSTAT_LATECOLL) 1171 ifp->if_collisions++; 1172 } 1173 1174 ifp->if_collisions += (txstat & WB_TXSTAT_COLLCNT) >> 3; 1175 1176 ifp->if_opackets++; 1177 m_freem(cur_tx->wb_mbuf); 1178 cur_tx->wb_mbuf = NULL; 1179 1180 if (sc->wb_cdata.wb_tx_head == sc->wb_cdata.wb_tx_tail) { 1181 sc->wb_cdata.wb_tx_head = NULL; 1182 sc->wb_cdata.wb_tx_tail = NULL; 1183 break; 1184 } 1185 1186 sc->wb_cdata.wb_tx_head = cur_tx->wb_nextdesc; 1187 } 1188 1189 return; 1190} 1191 1192/* 1193 * TX 'end of channel' interrupt handler. 1194 */ 1195static void 1196wb_txeoc(sc) 1197 struct wb_softc *sc; 1198{ 1199 struct ifnet *ifp; 1200 1201 ifp = sc->wb_ifp; 1202 1203 sc->wb_timer = 0; 1204 1205 if (sc->wb_cdata.wb_tx_head == NULL) { 1206 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 1207 sc->wb_cdata.wb_tx_tail = NULL; 1208 } else { 1209 if (WB_TXOWN(sc->wb_cdata.wb_tx_head) == WB_UNSENT) { 1210 WB_TXOWN(sc->wb_cdata.wb_tx_head) = WB_TXSTAT_OWN; 1211 sc->wb_timer = 5; 1212 CSR_WRITE_4(sc, WB_TXSTART, 0xFFFFFFFF); 1213 } 1214 } 1215 1216 return; 1217} 1218 1219static void 1220wb_intr(arg) 1221 void *arg; 1222{ 1223 struct wb_softc *sc; 1224 struct ifnet *ifp; 1225 u_int32_t status; 1226 1227 sc = arg; 1228 WB_LOCK(sc); 1229 ifp = sc->wb_ifp; 1230 1231 if (!(ifp->if_drv_flags & IFF_DRV_RUNNING)) { 1232 WB_UNLOCK(sc); 1233 return; 1234 } 1235 1236 /* Disable interrupts. */ 1237 CSR_WRITE_4(sc, WB_IMR, 0x00000000); 1238 1239 for (;;) { 1240 1241 status = CSR_READ_4(sc, WB_ISR); 1242 if (status) 1243 CSR_WRITE_4(sc, WB_ISR, status); 1244 1245 if ((status & WB_INTRS) == 0) 1246 break; 1247 1248 if ((status & WB_ISR_RX_NOBUF) || (status & WB_ISR_RX_ERR)) { 1249 ifp->if_ierrors++; 1250 wb_reset(sc); 1251 if (status & WB_ISR_RX_ERR) 1252 wb_fixmedia(sc); 1253 wb_init_locked(sc); 1254 continue; 1255 } 1256 1257 if (status & WB_ISR_RX_OK) 1258 wb_rxeof(sc); 1259 1260 if (status & WB_ISR_RX_IDLE) 1261 wb_rxeoc(sc); 1262 1263 if (status & WB_ISR_TX_OK) 1264 wb_txeof(sc); 1265 1266 if (status & WB_ISR_TX_NOBUF) 1267 wb_txeoc(sc); 1268 1269 if (status & WB_ISR_TX_IDLE) { 1270 wb_txeof(sc); 1271 if (sc->wb_cdata.wb_tx_head != NULL) { 1272 WB_SETBIT(sc, WB_NETCFG, WB_NETCFG_TX_ON); 1273 CSR_WRITE_4(sc, WB_TXSTART, 0xFFFFFFFF); 1274 } 1275 } 1276 1277 if (status & WB_ISR_TX_UNDERRUN) { 1278 ifp->if_oerrors++; 1279 wb_txeof(sc); 1280 WB_CLRBIT(sc, WB_NETCFG, WB_NETCFG_TX_ON); 1281 /* Jack up TX threshold */ 1282 sc->wb_txthresh += WB_TXTHRESH_CHUNK; 1283 WB_CLRBIT(sc, WB_NETCFG, WB_NETCFG_TX_THRESH); 1284 WB_SETBIT(sc, WB_NETCFG, WB_TXTHRESH(sc->wb_txthresh)); 1285 WB_SETBIT(sc, WB_NETCFG, WB_NETCFG_TX_ON); 1286 } 1287 1288 if (status & WB_ISR_BUS_ERR) { 1289 wb_reset(sc); 1290 wb_init_locked(sc); 1291 } 1292 1293 } 1294 1295 /* Re-enable interrupts. */ 1296 CSR_WRITE_4(sc, WB_IMR, WB_INTRS); 1297 1298 if (ifp->if_snd.ifq_head != NULL) { 1299 wb_start_locked(ifp); 1300 } 1301 1302 WB_UNLOCK(sc); 1303 1304 return; 1305} 1306 1307static void 1308wb_tick(xsc) 1309 void *xsc; 1310{ 1311 struct wb_softc *sc; 1312 struct mii_data *mii; 1313 1314 sc = xsc; 1315 WB_LOCK_ASSERT(sc); 1316 mii = device_get_softc(sc->wb_miibus); 1317 1318 mii_tick(mii); 1319 1320 if (sc->wb_timer > 0 && --sc->wb_timer == 0) 1321 wb_watchdog(sc); 1322 callout_reset(&sc->wb_stat_callout, hz, wb_tick, sc); 1323 1324 return; 1325} 1326 1327/* 1328 * Encapsulate an mbuf chain in a descriptor by coupling the mbuf data 1329 * pointers to the fragment pointers. 1330 */ 1331static int 1332wb_encap(sc, c, m_head) 1333 struct wb_softc *sc; 1334 struct wb_chain *c; 1335 struct mbuf *m_head; 1336{ 1337 int frag = 0; 1338 struct wb_desc *f = NULL; 1339 int total_len; 1340 struct mbuf *m; 1341 1342 /* 1343 * Start packing the mbufs in this chain into 1344 * the fragment pointers. Stop when we run out 1345 * of fragments or hit the end of the mbuf chain. 1346 */ 1347 m = m_head; 1348 total_len = 0; 1349 1350 for (m = m_head, frag = 0; m != NULL; m = m->m_next) { 1351 if (m->m_len != 0) { 1352 if (frag == WB_MAXFRAGS) 1353 break; 1354 total_len += m->m_len; 1355 f = &c->wb_ptr->wb_frag[frag]; 1356 f->wb_ctl = WB_TXCTL_TLINK | m->m_len; 1357 if (frag == 0) { 1358 f->wb_ctl |= WB_TXCTL_FIRSTFRAG; 1359 f->wb_status = 0; 1360 } else 1361 f->wb_status = WB_TXSTAT_OWN; 1362 f->wb_next = vtophys(&c->wb_ptr->wb_frag[frag + 1]); 1363 f->wb_data = vtophys(mtod(m, vm_offset_t)); 1364 frag++; 1365 } 1366 } 1367 1368 /* 1369 * Handle special case: we used up all 16 fragments, 1370 * but we have more mbufs left in the chain. Copy the 1371 * data into an mbuf cluster. Note that we don't 1372 * bother clearing the values in the other fragment 1373 * pointers/counters; it wouldn't gain us anything, 1374 * and would waste cycles. 1375 */ 1376 if (m != NULL) { 1377 struct mbuf *m_new = NULL; 1378 1379 MGETHDR(m_new, M_DONTWAIT, MT_DATA); 1380 if (m_new == NULL) 1381 return(1); 1382 if (m_head->m_pkthdr.len > MHLEN) { 1383 MCLGET(m_new, M_DONTWAIT); 1384 if (!(m_new->m_flags & M_EXT)) { 1385 m_freem(m_new); 1386 return(1); 1387 } 1388 } 1389 m_copydata(m_head, 0, m_head->m_pkthdr.len, 1390 mtod(m_new, caddr_t)); 1391 m_new->m_pkthdr.len = m_new->m_len = m_head->m_pkthdr.len; 1392 m_freem(m_head); 1393 m_head = m_new; 1394 f = &c->wb_ptr->wb_frag[0]; 1395 f->wb_status = 0; 1396 f->wb_data = vtophys(mtod(m_new, caddr_t)); 1397 f->wb_ctl = total_len = m_new->m_len; 1398 f->wb_ctl |= WB_TXCTL_TLINK|WB_TXCTL_FIRSTFRAG; 1399 frag = 1; 1400 } 1401 1402 if (total_len < WB_MIN_FRAMELEN) { 1403 f = &c->wb_ptr->wb_frag[frag]; 1404 f->wb_ctl = WB_MIN_FRAMELEN - total_len; 1405 f->wb_data = vtophys(&sc->wb_cdata.wb_pad); 1406 f->wb_ctl |= WB_TXCTL_TLINK; 1407 f->wb_status = WB_TXSTAT_OWN; 1408 frag++; 1409 } 1410 1411 c->wb_mbuf = m_head; 1412 c->wb_lastdesc = frag - 1; 1413 WB_TXCTL(c) |= WB_TXCTL_LASTFRAG; 1414 WB_TXNEXT(c) = vtophys(&c->wb_nextdesc->wb_ptr->wb_frag[0]); 1415 1416 return(0); 1417} 1418 1419/* 1420 * Main transmit routine. To avoid having to do mbuf copies, we put pointers 1421 * to the mbuf data regions directly in the transmit lists. We also save a 1422 * copy of the pointers since the transmit list fragment pointers are 1423 * physical addresses. 1424 */ 1425 1426static void 1427wb_start(ifp) 1428 struct ifnet *ifp; 1429{ 1430 struct wb_softc *sc; 1431 1432 sc = ifp->if_softc; 1433 WB_LOCK(sc); 1434 wb_start_locked(ifp); 1435 WB_UNLOCK(sc); 1436} 1437 1438static void 1439wb_start_locked(ifp) 1440 struct ifnet *ifp; 1441{ 1442 struct wb_softc *sc; 1443 struct mbuf *m_head = NULL; 1444 struct wb_chain *cur_tx = NULL, *start_tx; 1445 1446 sc = ifp->if_softc; 1447 WB_LOCK_ASSERT(sc); 1448 1449 /* 1450 * Check for an available queue slot. If there are none, 1451 * punt. 1452 */ 1453 if (sc->wb_cdata.wb_tx_free->wb_mbuf != NULL) { 1454 ifp->if_drv_flags |= IFF_DRV_OACTIVE; 1455 return; 1456 } 1457 1458 start_tx = sc->wb_cdata.wb_tx_free; 1459 1460 while(sc->wb_cdata.wb_tx_free->wb_mbuf == NULL) { 1461 IF_DEQUEUE(&ifp->if_snd, m_head); 1462 if (m_head == NULL) 1463 break; 1464 1465 /* Pick a descriptor off the free list. */ 1466 cur_tx = sc->wb_cdata.wb_tx_free; 1467 sc->wb_cdata.wb_tx_free = cur_tx->wb_nextdesc; 1468 1469 /* Pack the data into the descriptor. */ 1470 wb_encap(sc, cur_tx, m_head); 1471 1472 if (cur_tx != start_tx) 1473 WB_TXOWN(cur_tx) = WB_TXSTAT_OWN; 1474 1475 /* 1476 * If there's a BPF listener, bounce a copy of this frame 1477 * to him. 1478 */ 1479 BPF_MTAP(ifp, cur_tx->wb_mbuf); 1480 } 1481 1482 /* 1483 * If there are no packets queued, bail. 1484 */ 1485 if (cur_tx == NULL) 1486 return; 1487 1488 /* 1489 * Place the request for the upload interrupt 1490 * in the last descriptor in the chain. This way, if 1491 * we're chaining several packets at once, we'll only 1492 * get an interrupt once for the whole chain rather than 1493 * once for each packet. 1494 */ 1495 WB_TXCTL(cur_tx) |= WB_TXCTL_FINT; 1496 cur_tx->wb_ptr->wb_frag[0].wb_ctl |= WB_TXCTL_FINT; 1497 sc->wb_cdata.wb_tx_tail = cur_tx; 1498 1499 if (sc->wb_cdata.wb_tx_head == NULL) { 1500 sc->wb_cdata.wb_tx_head = start_tx; 1501 WB_TXOWN(start_tx) = WB_TXSTAT_OWN; 1502 CSR_WRITE_4(sc, WB_TXSTART, 0xFFFFFFFF); 1503 } else { 1504 /* 1505 * We need to distinguish between the case where 1506 * the own bit is clear because the chip cleared it 1507 * and where the own bit is clear because we haven't 1508 * set it yet. The magic value WB_UNSET is just some 1509 * ramdomly chosen number which doesn't have the own 1510 * bit set. When we actually transmit the frame, the 1511 * status word will have _only_ the own bit set, so 1512 * the txeoc handler will be able to tell if it needs 1513 * to initiate another transmission to flush out pending 1514 * frames. 1515 */ 1516 WB_TXOWN(start_tx) = WB_UNSENT; 1517 } 1518 1519 /* 1520 * Set a timeout in case the chip goes out to lunch. 1521 */ 1522 sc->wb_timer = 5; 1523 1524 return; 1525} 1526 1527static void 1528wb_init(xsc) 1529 void *xsc; 1530{ 1531 struct wb_softc *sc = xsc; 1532 1533 WB_LOCK(sc); 1534 wb_init_locked(sc); 1535 WB_UNLOCK(sc); 1536} 1537 1538static void 1539wb_init_locked(sc) 1540 struct wb_softc *sc; 1541{ 1542 struct ifnet *ifp = sc->wb_ifp; 1543 int i; 1544 struct mii_data *mii; 1545 1546 WB_LOCK_ASSERT(sc); 1547 mii = device_get_softc(sc->wb_miibus); 1548 1549 /* 1550 * Cancel pending I/O and free all RX/TX buffers. 1551 */ 1552 wb_stop(sc); 1553 wb_reset(sc); 1554 1555 sc->wb_txthresh = WB_TXTHRESH_INIT; 1556 1557 /* 1558 * Set cache alignment and burst length. 1559 */ 1560#ifdef foo 1561 CSR_WRITE_4(sc, WB_BUSCTL, WB_BUSCTL_CONFIG); 1562 WB_CLRBIT(sc, WB_NETCFG, WB_NETCFG_TX_THRESH); 1563 WB_SETBIT(sc, WB_NETCFG, WB_TXTHRESH(sc->wb_txthresh)); 1564#endif 1565 1566 CSR_WRITE_4(sc, WB_BUSCTL, WB_BUSCTL_MUSTBEONE|WB_BUSCTL_ARBITRATION); 1567 WB_SETBIT(sc, WB_BUSCTL, WB_BURSTLEN_16LONG); 1568 switch(sc->wb_cachesize) { 1569 case 32: 1570 WB_SETBIT(sc, WB_BUSCTL, WB_CACHEALIGN_32LONG); 1571 break; 1572 case 16: 1573 WB_SETBIT(sc, WB_BUSCTL, WB_CACHEALIGN_16LONG); 1574 break; 1575 case 8: 1576 WB_SETBIT(sc, WB_BUSCTL, WB_CACHEALIGN_8LONG); 1577 break; 1578 case 0: 1579 default: 1580 WB_SETBIT(sc, WB_BUSCTL, WB_CACHEALIGN_NONE); 1581 break; 1582 } 1583 1584 /* This doesn't tend to work too well at 100Mbps. */ 1585 WB_CLRBIT(sc, WB_NETCFG, WB_NETCFG_TX_EARLY_ON); 1586 1587 /* Init our MAC address */ 1588 for (i = 0; i < ETHER_ADDR_LEN; i++) { 1589 CSR_WRITE_1(sc, WB_NODE0 + i, IF_LLADDR(sc->wb_ifp)[i]); 1590 } 1591 1592 /* Init circular RX list. */ 1593 if (wb_list_rx_init(sc) == ENOBUFS) { 1594 device_printf(sc->wb_dev, 1595 "initialization failed: no memory for rx buffers\n"); 1596 wb_stop(sc); 1597 return; 1598 } 1599 1600 /* Init TX descriptors. */ 1601 wb_list_tx_init(sc); 1602 1603 /* If we want promiscuous mode, set the allframes bit. */ 1604 if (ifp->if_flags & IFF_PROMISC) { 1605 WB_SETBIT(sc, WB_NETCFG, WB_NETCFG_RX_ALLPHYS); 1606 } else { 1607 WB_CLRBIT(sc, WB_NETCFG, WB_NETCFG_RX_ALLPHYS); 1608 } 1609 1610 /* 1611 * Set capture broadcast bit to capture broadcast frames. 1612 */ 1613 if (ifp->if_flags & IFF_BROADCAST) { 1614 WB_SETBIT(sc, WB_NETCFG, WB_NETCFG_RX_BROAD); 1615 } else { 1616 WB_CLRBIT(sc, WB_NETCFG, WB_NETCFG_RX_BROAD); 1617 } 1618 1619 /* 1620 * Program the multicast filter, if necessary. 1621 */ 1622 wb_setmulti(sc); 1623 1624 /* 1625 * Load the address of the RX list. 1626 */ 1627 WB_CLRBIT(sc, WB_NETCFG, WB_NETCFG_RX_ON); 1628 CSR_WRITE_4(sc, WB_RXADDR, vtophys(&sc->wb_ldata->wb_rx_list[0])); 1629 1630 /* 1631 * Enable interrupts. 1632 */ 1633 CSR_WRITE_4(sc, WB_IMR, WB_INTRS); 1634 CSR_WRITE_4(sc, WB_ISR, 0xFFFFFFFF); 1635 1636 /* Enable receiver and transmitter. */ 1637 WB_SETBIT(sc, WB_NETCFG, WB_NETCFG_RX_ON); 1638 CSR_WRITE_4(sc, WB_RXSTART, 0xFFFFFFFF); 1639 1640 WB_CLRBIT(sc, WB_NETCFG, WB_NETCFG_TX_ON); 1641 CSR_WRITE_4(sc, WB_TXADDR, vtophys(&sc->wb_ldata->wb_tx_list[0])); 1642 WB_SETBIT(sc, WB_NETCFG, WB_NETCFG_TX_ON); 1643 1644 mii_mediachg(mii); 1645 1646 ifp->if_drv_flags |= IFF_DRV_RUNNING; 1647 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 1648 1649 callout_reset(&sc->wb_stat_callout, hz, wb_tick, sc); 1650 1651 return; 1652} 1653 1654/* 1655 * Set media options. 1656 */ 1657static int 1658wb_ifmedia_upd(ifp) 1659 struct ifnet *ifp; 1660{ 1661 struct wb_softc *sc; 1662 1663 sc = ifp->if_softc; 1664 1665 WB_LOCK(sc); 1666 if (ifp->if_flags & IFF_UP) 1667 wb_init_locked(sc); 1668 WB_UNLOCK(sc); 1669 1670 return(0); 1671} 1672 1673/* 1674 * Report current media status. 1675 */ 1676static void 1677wb_ifmedia_sts(ifp, ifmr) 1678 struct ifnet *ifp; 1679 struct ifmediareq *ifmr; 1680{ 1681 struct wb_softc *sc; 1682 struct mii_data *mii; 1683 1684 sc = ifp->if_softc; 1685 1686 WB_LOCK(sc); 1687 mii = device_get_softc(sc->wb_miibus); 1688 1689 mii_pollstat(mii); 1690 ifmr->ifm_active = mii->mii_media_active; 1691 ifmr->ifm_status = mii->mii_media_status; 1692 WB_UNLOCK(sc); 1693 1694 return; 1695} 1696 1697static int 1698wb_ioctl(ifp, command, data) 1699 struct ifnet *ifp; 1700 u_long command; 1701 caddr_t data; 1702{ 1703 struct wb_softc *sc = ifp->if_softc; 1704 struct mii_data *mii; 1705 struct ifreq *ifr = (struct ifreq *) data; 1706 int error = 0; 1707 1708 switch(command) { 1709 case SIOCSIFFLAGS: 1710 WB_LOCK(sc); 1711 if (ifp->if_flags & IFF_UP) { 1712 wb_init_locked(sc); 1713 } else { 1714 if (ifp->if_drv_flags & IFF_DRV_RUNNING) 1715 wb_stop(sc); 1716 } 1717 WB_UNLOCK(sc); 1718 error = 0; 1719 break; 1720 case SIOCADDMULTI: 1721 case SIOCDELMULTI: 1722 WB_LOCK(sc); 1723 wb_setmulti(sc); 1724 WB_UNLOCK(sc); 1725 error = 0; 1726 break; 1727 case SIOCGIFMEDIA: 1728 case SIOCSIFMEDIA: 1729 mii = device_get_softc(sc->wb_miibus); 1730 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command); 1731 break; 1732 default: 1733 error = ether_ioctl(ifp, command, data); 1734 break; 1735 } 1736 1737 return(error); 1738} 1739 1740static void 1741wb_watchdog(sc) 1742 struct wb_softc *sc; 1743{ 1744 struct ifnet *ifp; 1745 1746 WB_LOCK_ASSERT(sc); 1747 ifp = sc->wb_ifp; 1748 ifp->if_oerrors++; 1749 if_printf(ifp, "watchdog timeout\n"); 1750#ifdef foo 1751 if (!(wb_phy_readreg(sc, PHY_BMSR) & PHY_BMSR_LINKSTAT)) 1752 if_printf(ifp, "no carrier - transceiver cable problem?\n"); 1753#endif 1754 wb_stop(sc); 1755 wb_reset(sc); 1756 wb_init_locked(sc); 1757 1758 if (ifp->if_snd.ifq_head != NULL) 1759 wb_start_locked(ifp); 1760 1761 return; 1762} 1763 1764/* 1765 * Stop the adapter and free any mbufs allocated to the 1766 * RX and TX lists. 1767 */ 1768static void 1769wb_stop(sc) 1770 struct wb_softc *sc; 1771{ 1772 register int i; 1773 struct ifnet *ifp; 1774 1775 WB_LOCK_ASSERT(sc); 1776 ifp = sc->wb_ifp; 1777 sc->wb_timer = 0; 1778 1779 callout_stop(&sc->wb_stat_callout); 1780 1781 WB_CLRBIT(sc, WB_NETCFG, (WB_NETCFG_RX_ON|WB_NETCFG_TX_ON)); 1782 CSR_WRITE_4(sc, WB_IMR, 0x00000000); 1783 CSR_WRITE_4(sc, WB_TXADDR, 0x00000000); 1784 CSR_WRITE_4(sc, WB_RXADDR, 0x00000000); 1785 1786 /* 1787 * Free data in the RX lists. 1788 */ 1789 for (i = 0; i < WB_RX_LIST_CNT; i++) { 1790 if (sc->wb_cdata.wb_rx_chain[i].wb_mbuf != NULL) { 1791 m_freem(sc->wb_cdata.wb_rx_chain[i].wb_mbuf); 1792 sc->wb_cdata.wb_rx_chain[i].wb_mbuf = NULL; 1793 } 1794 } 1795 bzero((char *)&sc->wb_ldata->wb_rx_list, 1796 sizeof(sc->wb_ldata->wb_rx_list)); 1797 1798 /* 1799 * Free the TX list buffers. 1800 */ 1801 for (i = 0; i < WB_TX_LIST_CNT; i++) { 1802 if (sc->wb_cdata.wb_tx_chain[i].wb_mbuf != NULL) { 1803 m_freem(sc->wb_cdata.wb_tx_chain[i].wb_mbuf); 1804 sc->wb_cdata.wb_tx_chain[i].wb_mbuf = NULL; 1805 } 1806 } 1807 1808 bzero((char *)&sc->wb_ldata->wb_tx_list, 1809 sizeof(sc->wb_ldata->wb_tx_list)); 1810 1811 ifp->if_drv_flags &= ~(IFF_DRV_RUNNING | IFF_DRV_OACTIVE); 1812 1813 return; 1814} 1815 1816/* 1817 * Stop all chip I/O so that the kernel's probe routines don't 1818 * get confused by errant DMAs when rebooting. 1819 */ 1820static int 1821wb_shutdown(dev) 1822 device_t dev; 1823{ 1824 struct wb_softc *sc; 1825 1826 sc = device_get_softc(dev); 1827 1828 WB_LOCK(sc); 1829 wb_stop(sc); 1830 WB_UNLOCK(sc); 1831 1832 return (0); 1833} 1834