if_wb.c revision 148654
1/*- 2 * Copyright (c) 1997, 1998 3 * Bill Paul <wpaul@ctr.columbia.edu>. All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 3. All advertising materials mentioning features or use of this software 14 * must display the following acknowledgement: 15 * This product includes software developed by Bill Paul. 16 * 4. Neither the name of the author nor the names of any co-contributors 17 * may be used to endorse or promote products derived from this software 18 * without specific prior written permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 21 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 30 * THE POSSIBILITY OF SUCH DAMAGE. 31 */ 32 33#include <sys/cdefs.h> 34__FBSDID("$FreeBSD: head/sys/pci/if_wb.c 148654 2005-08-03 00:18:35Z rwatson $"); 35 36/* 37 * Winbond fast ethernet PCI NIC driver 38 * 39 * Supports various cheap network adapters based on the Winbond W89C840F 40 * fast ethernet controller chip. This includes adapters manufactured by 41 * Winbond itself and some made by Linksys. 42 * 43 * Written by Bill Paul <wpaul@ctr.columbia.edu> 44 * Electrical Engineering Department 45 * Columbia University, New York City 46 */ 47/* 48 * The Winbond W89C840F chip is a bus master; in some ways it resembles 49 * a DEC 'tulip' chip, only not as complicated. Unfortunately, it has 50 * one major difference which is that while the registers do many of 51 * the same things as a tulip adapter, the offsets are different: where 52 * tulip registers are typically spaced 8 bytes apart, the Winbond 53 * registers are spaced 4 bytes apart. The receiver filter is also 54 * programmed differently. 55 * 56 * Like the tulip, the Winbond chip uses small descriptors containing 57 * a status word, a control word and 32-bit areas that can either be used 58 * to point to two external data blocks, or to point to a single block 59 * and another descriptor in a linked list. Descriptors can be grouped 60 * together in blocks to form fixed length rings or can be chained 61 * together in linked lists. A single packet may be spread out over 62 * several descriptors if necessary. 63 * 64 * For the receive ring, this driver uses a linked list of descriptors, 65 * each pointing to a single mbuf cluster buffer, which us large enough 66 * to hold an entire packet. The link list is looped back to created a 67 * closed ring. 68 * 69 * For transmission, the driver creates a linked list of 'super descriptors' 70 * which each contain several individual descriptors linked toghether. 71 * Each 'super descriptor' contains WB_MAXFRAGS descriptors, which we 72 * abuse as fragment pointers. This allows us to use a buffer managment 73 * scheme very similar to that used in the ThunderLAN and Etherlink XL 74 * drivers. 75 * 76 * Autonegotiation is performed using the external PHY via the MII bus. 77 * The sample boards I have all use a Davicom PHY. 78 * 79 * Note: the author of the Linux driver for the Winbond chip alludes 80 * to some sort of flaw in the chip's design that seems to mandate some 81 * drastic workaround which signigicantly impairs transmit performance. 82 * I have no idea what he's on about: transmit performance with all 83 * three of my test boards seems fine. 84 */ 85 86#include "opt_bdg.h" 87 88#include <sys/param.h> 89#include <sys/systm.h> 90#include <sys/sockio.h> 91#include <sys/mbuf.h> 92#include <sys/malloc.h> 93#include <sys/module.h> 94#include <sys/kernel.h> 95#include <sys/socket.h> 96#include <sys/queue.h> 97 98#include <net/if.h> 99#include <net/if_arp.h> 100#include <net/ethernet.h> 101#include <net/if_dl.h> 102#include <net/if_media.h> 103#include <net/if_types.h> 104 105#include <net/bpf.h> 106 107#include <vm/vm.h> /* for vtophys */ 108#include <vm/pmap.h> /* for vtophys */ 109#include <machine/bus.h> 110#include <machine/resource.h> 111#include <sys/bus.h> 112#include <sys/rman.h> 113 114#include <dev/pci/pcireg.h> 115#include <dev/pci/pcivar.h> 116 117#include <dev/mii/mii.h> 118#include <dev/mii/miivar.h> 119 120/* "controller miibus0" required. See GENERIC if you get errors here. */ 121#include "miibus_if.h" 122 123#define WB_USEIOSPACE 124 125#include <pci/if_wbreg.h> 126 127MODULE_DEPEND(wb, pci, 1, 1, 1); 128MODULE_DEPEND(wb, ether, 1, 1, 1); 129MODULE_DEPEND(wb, miibus, 1, 1, 1); 130 131/* 132 * Various supported device vendors/types and their names. 133 */ 134static struct wb_type wb_devs[] = { 135 { WB_VENDORID, WB_DEVICEID_840F, 136 "Winbond W89C840F 10/100BaseTX" }, 137 { CP_VENDORID, CP_DEVICEID_RL100, 138 "Compex RL100-ATX 10/100baseTX" }, 139 { 0, 0, NULL } 140}; 141 142static int wb_probe(device_t); 143static int wb_attach(device_t); 144static int wb_detach(device_t); 145 146static void wb_bfree(void *addr, void *args); 147static int wb_newbuf(struct wb_softc *, struct wb_chain_onefrag *, 148 struct mbuf *); 149static int wb_encap(struct wb_softc *, struct wb_chain *, struct mbuf *); 150 151static void wb_rxeof(struct wb_softc *); 152static void wb_rxeoc(struct wb_softc *); 153static void wb_txeof(struct wb_softc *); 154static void wb_txeoc(struct wb_softc *); 155static void wb_intr(void *); 156static void wb_tick(void *); 157static void wb_start(struct ifnet *); 158static int wb_ioctl(struct ifnet *, u_long, caddr_t); 159static void wb_init(void *); 160static void wb_stop(struct wb_softc *); 161static void wb_watchdog(struct ifnet *); 162static void wb_shutdown(device_t); 163static int wb_ifmedia_upd(struct ifnet *); 164static void wb_ifmedia_sts(struct ifnet *, struct ifmediareq *); 165 166static void wb_eeprom_putbyte(struct wb_softc *, int); 167static void wb_eeprom_getword(struct wb_softc *, int, u_int16_t *); 168static void wb_read_eeprom(struct wb_softc *, caddr_t, int, int, int); 169static void wb_mii_sync(struct wb_softc *); 170static void wb_mii_send(struct wb_softc *, u_int32_t, int); 171static int wb_mii_readreg(struct wb_softc *, struct wb_mii_frame *); 172static int wb_mii_writereg(struct wb_softc *, struct wb_mii_frame *); 173 174static void wb_setcfg(struct wb_softc *, u_int32_t); 175static void wb_setmulti(struct wb_softc *); 176static void wb_reset(struct wb_softc *); 177static void wb_fixmedia(struct wb_softc *); 178static int wb_list_rx_init(struct wb_softc *); 179static int wb_list_tx_init(struct wb_softc *); 180 181static int wb_miibus_readreg(device_t, int, int); 182static int wb_miibus_writereg(device_t, int, int, int); 183static void wb_miibus_statchg(device_t); 184 185#ifdef WB_USEIOSPACE 186#define WB_RES SYS_RES_IOPORT 187#define WB_RID WB_PCI_LOIO 188#else 189#define WB_RES SYS_RES_MEMORY 190#define WB_RID WB_PCI_LOMEM 191#endif 192 193static device_method_t wb_methods[] = { 194 /* Device interface */ 195 DEVMETHOD(device_probe, wb_probe), 196 DEVMETHOD(device_attach, wb_attach), 197 DEVMETHOD(device_detach, wb_detach), 198 DEVMETHOD(device_shutdown, wb_shutdown), 199 200 /* bus interface, for miibus */ 201 DEVMETHOD(bus_print_child, bus_generic_print_child), 202 DEVMETHOD(bus_driver_added, bus_generic_driver_added), 203 204 /* MII interface */ 205 DEVMETHOD(miibus_readreg, wb_miibus_readreg), 206 DEVMETHOD(miibus_writereg, wb_miibus_writereg), 207 DEVMETHOD(miibus_statchg, wb_miibus_statchg), 208 { 0, 0 } 209}; 210 211static driver_t wb_driver = { 212 "wb", 213 wb_methods, 214 sizeof(struct wb_softc) 215}; 216 217static devclass_t wb_devclass; 218 219DRIVER_MODULE(wb, pci, wb_driver, wb_devclass, 0, 0); 220DRIVER_MODULE(miibus, wb, miibus_driver, miibus_devclass, 0, 0); 221 222#define WB_SETBIT(sc, reg, x) \ 223 CSR_WRITE_4(sc, reg, \ 224 CSR_READ_4(sc, reg) | (x)) 225 226#define WB_CLRBIT(sc, reg, x) \ 227 CSR_WRITE_4(sc, reg, \ 228 CSR_READ_4(sc, reg) & ~(x)) 229 230#define SIO_SET(x) \ 231 CSR_WRITE_4(sc, WB_SIO, \ 232 CSR_READ_4(sc, WB_SIO) | (x)) 233 234#define SIO_CLR(x) \ 235 CSR_WRITE_4(sc, WB_SIO, \ 236 CSR_READ_4(sc, WB_SIO) & ~(x)) 237 238/* 239 * Send a read command and address to the EEPROM, check for ACK. 240 */ 241static void 242wb_eeprom_putbyte(sc, addr) 243 struct wb_softc *sc; 244 int addr; 245{ 246 register int d, i; 247 248 d = addr | WB_EECMD_READ; 249 250 /* 251 * Feed in each bit and stobe the clock. 252 */ 253 for (i = 0x400; i; i >>= 1) { 254 if (d & i) { 255 SIO_SET(WB_SIO_EE_DATAIN); 256 } else { 257 SIO_CLR(WB_SIO_EE_DATAIN); 258 } 259 DELAY(100); 260 SIO_SET(WB_SIO_EE_CLK); 261 DELAY(150); 262 SIO_CLR(WB_SIO_EE_CLK); 263 DELAY(100); 264 } 265 266 return; 267} 268 269/* 270 * Read a word of data stored in the EEPROM at address 'addr.' 271 */ 272static void 273wb_eeprom_getword(sc, addr, dest) 274 struct wb_softc *sc; 275 int addr; 276 u_int16_t *dest; 277{ 278 register int i; 279 u_int16_t word = 0; 280 281 /* Enter EEPROM access mode. */ 282 CSR_WRITE_4(sc, WB_SIO, WB_SIO_EESEL|WB_SIO_EE_CS); 283 284 /* 285 * Send address of word we want to read. 286 */ 287 wb_eeprom_putbyte(sc, addr); 288 289 CSR_WRITE_4(sc, WB_SIO, WB_SIO_EESEL|WB_SIO_EE_CS); 290 291 /* 292 * Start reading bits from EEPROM. 293 */ 294 for (i = 0x8000; i; i >>= 1) { 295 SIO_SET(WB_SIO_EE_CLK); 296 DELAY(100); 297 if (CSR_READ_4(sc, WB_SIO) & WB_SIO_EE_DATAOUT) 298 word |= i; 299 SIO_CLR(WB_SIO_EE_CLK); 300 DELAY(100); 301 } 302 303 /* Turn off EEPROM access mode. */ 304 CSR_WRITE_4(sc, WB_SIO, 0); 305 306 *dest = word; 307 308 return; 309} 310 311/* 312 * Read a sequence of words from the EEPROM. 313 */ 314static void 315wb_read_eeprom(sc, dest, off, cnt, swap) 316 struct wb_softc *sc; 317 caddr_t dest; 318 int off; 319 int cnt; 320 int swap; 321{ 322 int i; 323 u_int16_t word = 0, *ptr; 324 325 for (i = 0; i < cnt; i++) { 326 wb_eeprom_getword(sc, off + i, &word); 327 ptr = (u_int16_t *)(dest + (i * 2)); 328 if (swap) 329 *ptr = ntohs(word); 330 else 331 *ptr = word; 332 } 333 334 return; 335} 336 337/* 338 * Sync the PHYs by setting data bit and strobing the clock 32 times. 339 */ 340static void 341wb_mii_sync(sc) 342 struct wb_softc *sc; 343{ 344 register int i; 345 346 SIO_SET(WB_SIO_MII_DIR|WB_SIO_MII_DATAIN); 347 348 for (i = 0; i < 32; i++) { 349 SIO_SET(WB_SIO_MII_CLK); 350 DELAY(1); 351 SIO_CLR(WB_SIO_MII_CLK); 352 DELAY(1); 353 } 354 355 return; 356} 357 358/* 359 * Clock a series of bits through the MII. 360 */ 361static void 362wb_mii_send(sc, bits, cnt) 363 struct wb_softc *sc; 364 u_int32_t bits; 365 int cnt; 366{ 367 int i; 368 369 SIO_CLR(WB_SIO_MII_CLK); 370 371 for (i = (0x1 << (cnt - 1)); i; i >>= 1) { 372 if (bits & i) { 373 SIO_SET(WB_SIO_MII_DATAIN); 374 } else { 375 SIO_CLR(WB_SIO_MII_DATAIN); 376 } 377 DELAY(1); 378 SIO_CLR(WB_SIO_MII_CLK); 379 DELAY(1); 380 SIO_SET(WB_SIO_MII_CLK); 381 } 382} 383 384/* 385 * Read an PHY register through the MII. 386 */ 387static int 388wb_mii_readreg(sc, frame) 389 struct wb_softc *sc; 390 struct wb_mii_frame *frame; 391 392{ 393 int i, ack; 394 395 WB_LOCK(sc); 396 397 /* 398 * Set up frame for RX. 399 */ 400 frame->mii_stdelim = WB_MII_STARTDELIM; 401 frame->mii_opcode = WB_MII_READOP; 402 frame->mii_turnaround = 0; 403 frame->mii_data = 0; 404 405 CSR_WRITE_4(sc, WB_SIO, 0); 406 407 /* 408 * Turn on data xmit. 409 */ 410 SIO_SET(WB_SIO_MII_DIR); 411 412 wb_mii_sync(sc); 413 414 /* 415 * Send command/address info. 416 */ 417 wb_mii_send(sc, frame->mii_stdelim, 2); 418 wb_mii_send(sc, frame->mii_opcode, 2); 419 wb_mii_send(sc, frame->mii_phyaddr, 5); 420 wb_mii_send(sc, frame->mii_regaddr, 5); 421 422 /* Idle bit */ 423 SIO_CLR((WB_SIO_MII_CLK|WB_SIO_MII_DATAIN)); 424 DELAY(1); 425 SIO_SET(WB_SIO_MII_CLK); 426 DELAY(1); 427 428 /* Turn off xmit. */ 429 SIO_CLR(WB_SIO_MII_DIR); 430 /* Check for ack */ 431 SIO_CLR(WB_SIO_MII_CLK); 432 DELAY(1); 433 ack = CSR_READ_4(sc, WB_SIO) & WB_SIO_MII_DATAOUT; 434 SIO_SET(WB_SIO_MII_CLK); 435 DELAY(1); 436 SIO_CLR(WB_SIO_MII_CLK); 437 DELAY(1); 438 SIO_SET(WB_SIO_MII_CLK); 439 DELAY(1); 440 441 /* 442 * Now try reading data bits. If the ack failed, we still 443 * need to clock through 16 cycles to keep the PHY(s) in sync. 444 */ 445 if (ack) { 446 for(i = 0; i < 16; i++) { 447 SIO_CLR(WB_SIO_MII_CLK); 448 DELAY(1); 449 SIO_SET(WB_SIO_MII_CLK); 450 DELAY(1); 451 } 452 goto fail; 453 } 454 455 for (i = 0x8000; i; i >>= 1) { 456 SIO_CLR(WB_SIO_MII_CLK); 457 DELAY(1); 458 if (!ack) { 459 if (CSR_READ_4(sc, WB_SIO) & WB_SIO_MII_DATAOUT) 460 frame->mii_data |= i; 461 DELAY(1); 462 } 463 SIO_SET(WB_SIO_MII_CLK); 464 DELAY(1); 465 } 466 467fail: 468 469 SIO_CLR(WB_SIO_MII_CLK); 470 DELAY(1); 471 SIO_SET(WB_SIO_MII_CLK); 472 DELAY(1); 473 474 WB_UNLOCK(sc); 475 476 if (ack) 477 return(1); 478 return(0); 479} 480 481/* 482 * Write to a PHY register through the MII. 483 */ 484static int 485wb_mii_writereg(sc, frame) 486 struct wb_softc *sc; 487 struct wb_mii_frame *frame; 488 489{ 490 WB_LOCK(sc); 491 492 /* 493 * Set up frame for TX. 494 */ 495 496 frame->mii_stdelim = WB_MII_STARTDELIM; 497 frame->mii_opcode = WB_MII_WRITEOP; 498 frame->mii_turnaround = WB_MII_TURNAROUND; 499 500 /* 501 * Turn on data output. 502 */ 503 SIO_SET(WB_SIO_MII_DIR); 504 505 wb_mii_sync(sc); 506 507 wb_mii_send(sc, frame->mii_stdelim, 2); 508 wb_mii_send(sc, frame->mii_opcode, 2); 509 wb_mii_send(sc, frame->mii_phyaddr, 5); 510 wb_mii_send(sc, frame->mii_regaddr, 5); 511 wb_mii_send(sc, frame->mii_turnaround, 2); 512 wb_mii_send(sc, frame->mii_data, 16); 513 514 /* Idle bit. */ 515 SIO_SET(WB_SIO_MII_CLK); 516 DELAY(1); 517 SIO_CLR(WB_SIO_MII_CLK); 518 DELAY(1); 519 520 /* 521 * Turn off xmit. 522 */ 523 SIO_CLR(WB_SIO_MII_DIR); 524 525 WB_UNLOCK(sc); 526 527 return(0); 528} 529 530static int 531wb_miibus_readreg(dev, phy, reg) 532 device_t dev; 533 int phy, reg; 534{ 535 struct wb_softc *sc; 536 struct wb_mii_frame frame; 537 538 sc = device_get_softc(dev); 539 540 bzero((char *)&frame, sizeof(frame)); 541 542 frame.mii_phyaddr = phy; 543 frame.mii_regaddr = reg; 544 wb_mii_readreg(sc, &frame); 545 546 return(frame.mii_data); 547} 548 549static int 550wb_miibus_writereg(dev, phy, reg, data) 551 device_t dev; 552 int phy, reg, data; 553{ 554 struct wb_softc *sc; 555 struct wb_mii_frame frame; 556 557 sc = device_get_softc(dev); 558 559 bzero((char *)&frame, sizeof(frame)); 560 561 frame.mii_phyaddr = phy; 562 frame.mii_regaddr = reg; 563 frame.mii_data = data; 564 565 wb_mii_writereg(sc, &frame); 566 567 return(0); 568} 569 570static void 571wb_miibus_statchg(dev) 572 device_t dev; 573{ 574 struct wb_softc *sc; 575 struct mii_data *mii; 576 577 sc = device_get_softc(dev); 578 WB_LOCK(sc); 579 mii = device_get_softc(sc->wb_miibus); 580 wb_setcfg(sc, mii->mii_media_active); 581 WB_UNLOCK(sc); 582 583 return; 584} 585 586/* 587 * Program the 64-bit multicast hash filter. 588 */ 589static void 590wb_setmulti(sc) 591 struct wb_softc *sc; 592{ 593 struct ifnet *ifp; 594 int h = 0; 595 u_int32_t hashes[2] = { 0, 0 }; 596 struct ifmultiaddr *ifma; 597 u_int32_t rxfilt; 598 int mcnt = 0; 599 600 ifp = sc->wb_ifp; 601 602 rxfilt = CSR_READ_4(sc, WB_NETCFG); 603 604 if (ifp->if_flags & IFF_ALLMULTI || ifp->if_flags & IFF_PROMISC) { 605 rxfilt |= WB_NETCFG_RX_MULTI; 606 CSR_WRITE_4(sc, WB_NETCFG, rxfilt); 607 CSR_WRITE_4(sc, WB_MAR0, 0xFFFFFFFF); 608 CSR_WRITE_4(sc, WB_MAR1, 0xFFFFFFFF); 609 return; 610 } 611 612 /* first, zot all the existing hash bits */ 613 CSR_WRITE_4(sc, WB_MAR0, 0); 614 CSR_WRITE_4(sc, WB_MAR1, 0); 615 616 /* now program new ones */ 617 IF_ADDR_LOCK(ifp); 618 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 619 if (ifma->ifma_addr->sa_family != AF_LINK) 620 continue; 621 h = ~ether_crc32_be(LLADDR((struct sockaddr_dl *) 622 ifma->ifma_addr), ETHER_ADDR_LEN) >> 26; 623 if (h < 32) 624 hashes[0] |= (1 << h); 625 else 626 hashes[1] |= (1 << (h - 32)); 627 mcnt++; 628 } 629 IF_ADDR_UNLOCK(ifp); 630 631 if (mcnt) 632 rxfilt |= WB_NETCFG_RX_MULTI; 633 else 634 rxfilt &= ~WB_NETCFG_RX_MULTI; 635 636 CSR_WRITE_4(sc, WB_MAR0, hashes[0]); 637 CSR_WRITE_4(sc, WB_MAR1, hashes[1]); 638 CSR_WRITE_4(sc, WB_NETCFG, rxfilt); 639 640 return; 641} 642 643/* 644 * The Winbond manual states that in order to fiddle with the 645 * 'full-duplex' and '100Mbps' bits in the netconfig register, we 646 * first have to put the transmit and/or receive logic in the idle state. 647 */ 648static void 649wb_setcfg(sc, media) 650 struct wb_softc *sc; 651 u_int32_t media; 652{ 653 int i, restart = 0; 654 655 if (CSR_READ_4(sc, WB_NETCFG) & (WB_NETCFG_TX_ON|WB_NETCFG_RX_ON)) { 656 restart = 1; 657 WB_CLRBIT(sc, WB_NETCFG, (WB_NETCFG_TX_ON|WB_NETCFG_RX_ON)); 658 659 for (i = 0; i < WB_TIMEOUT; i++) { 660 DELAY(10); 661 if ((CSR_READ_4(sc, WB_ISR) & WB_ISR_TX_IDLE) && 662 (CSR_READ_4(sc, WB_ISR) & WB_ISR_RX_IDLE)) 663 break; 664 } 665 666 if (i == WB_TIMEOUT) 667 printf("wb%d: failed to force tx and " 668 "rx to idle state\n", sc->wb_unit); 669 } 670 671 if (IFM_SUBTYPE(media) == IFM_10_T) 672 WB_CLRBIT(sc, WB_NETCFG, WB_NETCFG_100MBPS); 673 else 674 WB_SETBIT(sc, WB_NETCFG, WB_NETCFG_100MBPS); 675 676 if ((media & IFM_GMASK) == IFM_FDX) 677 WB_SETBIT(sc, WB_NETCFG, WB_NETCFG_FULLDUPLEX); 678 else 679 WB_CLRBIT(sc, WB_NETCFG, WB_NETCFG_FULLDUPLEX); 680 681 if (restart) 682 WB_SETBIT(sc, WB_NETCFG, WB_NETCFG_TX_ON|WB_NETCFG_RX_ON); 683 684 return; 685} 686 687static void 688wb_reset(sc) 689 struct wb_softc *sc; 690{ 691 register int i; 692 struct mii_data *mii; 693 694 CSR_WRITE_4(sc, WB_NETCFG, 0); 695 CSR_WRITE_4(sc, WB_BUSCTL, 0); 696 CSR_WRITE_4(sc, WB_TXADDR, 0); 697 CSR_WRITE_4(sc, WB_RXADDR, 0); 698 699 WB_SETBIT(sc, WB_BUSCTL, WB_BUSCTL_RESET); 700 WB_SETBIT(sc, WB_BUSCTL, WB_BUSCTL_RESET); 701 702 for (i = 0; i < WB_TIMEOUT; i++) { 703 DELAY(10); 704 if (!(CSR_READ_4(sc, WB_BUSCTL) & WB_BUSCTL_RESET)) 705 break; 706 } 707 if (i == WB_TIMEOUT) 708 printf("wb%d: reset never completed!\n", sc->wb_unit); 709 710 /* Wait a little while for the chip to get its brains in order. */ 711 DELAY(1000); 712 713 if (sc->wb_miibus == NULL) 714 return; 715 716 mii = device_get_softc(sc->wb_miibus); 717 if (mii == NULL) 718 return; 719 720 if (mii->mii_instance) { 721 struct mii_softc *miisc; 722 LIST_FOREACH(miisc, &mii->mii_phys, mii_list) 723 mii_phy_reset(miisc); 724 } 725 726 return; 727} 728 729static void 730wb_fixmedia(sc) 731 struct wb_softc *sc; 732{ 733 struct mii_data *mii = NULL; 734 struct ifnet *ifp; 735 u_int32_t media; 736 737 if (sc->wb_miibus == NULL) 738 return; 739 740 mii = device_get_softc(sc->wb_miibus); 741 ifp = sc->wb_ifp; 742 743 mii_pollstat(mii); 744 if (IFM_SUBTYPE(mii->mii_media_active) == IFM_10_T) { 745 media = mii->mii_media_active & ~IFM_10_T; 746 media |= IFM_100_TX; 747 } else if (IFM_SUBTYPE(mii->mii_media_active) == IFM_100_TX) { 748 media = mii->mii_media_active & ~IFM_100_TX; 749 media |= IFM_10_T; 750 } else 751 return; 752 753 ifmedia_set(&mii->mii_media, media); 754 755 return; 756} 757 758/* 759 * Probe for a Winbond chip. Check the PCI vendor and device 760 * IDs against our list and return a device name if we find a match. 761 */ 762static int 763wb_probe(dev) 764 device_t dev; 765{ 766 struct wb_type *t; 767 768 t = wb_devs; 769 770 while(t->wb_name != NULL) { 771 if ((pci_get_vendor(dev) == t->wb_vid) && 772 (pci_get_device(dev) == t->wb_did)) { 773 device_set_desc(dev, t->wb_name); 774 return (BUS_PROBE_DEFAULT); 775 } 776 t++; 777 } 778 779 return(ENXIO); 780} 781 782/* 783 * Attach the interface. Allocate softc structures, do ifmedia 784 * setup and ethernet/BPF attach. 785 */ 786static int 787wb_attach(dev) 788 device_t dev; 789{ 790 u_char eaddr[ETHER_ADDR_LEN]; 791 struct wb_softc *sc; 792 struct ifnet *ifp; 793 int unit, error = 0, rid; 794 795 sc = device_get_softc(dev); 796 unit = device_get_unit(dev); 797 798 mtx_init(&sc->wb_mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK, 799 MTX_DEF | MTX_RECURSE); 800 /* 801 * Map control/status registers. 802 */ 803 pci_enable_busmaster(dev); 804 805 rid = WB_RID; 806 sc->wb_res = bus_alloc_resource_any(dev, WB_RES, &rid, RF_ACTIVE); 807 808 if (sc->wb_res == NULL) { 809 printf("wb%d: couldn't map ports/memory\n", unit); 810 error = ENXIO; 811 goto fail; 812 } 813 814 sc->wb_btag = rman_get_bustag(sc->wb_res); 815 sc->wb_bhandle = rman_get_bushandle(sc->wb_res); 816 817 /* Allocate interrupt */ 818 rid = 0; 819 sc->wb_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid, 820 RF_SHAREABLE | RF_ACTIVE); 821 822 if (sc->wb_irq == NULL) { 823 printf("wb%d: couldn't map interrupt\n", unit); 824 error = ENXIO; 825 goto fail; 826 } 827 828 /* Save the cache line size. */ 829 sc->wb_cachesize = pci_read_config(dev, WB_PCI_CACHELEN, 4) & 0xFF; 830 831 /* Reset the adapter. */ 832 wb_reset(sc); 833 834 /* 835 * Get station address from the EEPROM. 836 */ 837 wb_read_eeprom(sc, (caddr_t)&eaddr, 0, 3, 0); 838 839 sc->wb_unit = unit; 840 841 sc->wb_ldata = contigmalloc(sizeof(struct wb_list_data) + 8, M_DEVBUF, 842 M_NOWAIT, 0, 0xffffffff, PAGE_SIZE, 0); 843 844 if (sc->wb_ldata == NULL) { 845 printf("wb%d: no memory for list buffers!\n", unit); 846 error = ENXIO; 847 goto fail; 848 } 849 850 bzero(sc->wb_ldata, sizeof(struct wb_list_data)); 851 852 ifp = sc->wb_ifp = if_alloc(IFT_ETHER); 853 if (ifp == NULL) { 854 printf("wb%d: can not if_alloc()\n", unit); 855 error = ENOSPC; 856 goto fail; 857 } 858 ifp->if_softc = sc; 859 if_initname(ifp, device_get_name(dev), device_get_unit(dev)); 860 ifp->if_mtu = ETHERMTU; 861 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST | 862 IFF_NEEDSGIANT; 863 ifp->if_ioctl = wb_ioctl; 864 ifp->if_start = wb_start; 865 ifp->if_watchdog = wb_watchdog; 866 ifp->if_init = wb_init; 867 ifp->if_baudrate = 10000000; 868 ifp->if_snd.ifq_maxlen = WB_TX_LIST_CNT - 1; 869 870 /* 871 * Do MII setup. 872 */ 873 if (mii_phy_probe(dev, &sc->wb_miibus, 874 wb_ifmedia_upd, wb_ifmedia_sts)) { 875 error = ENXIO; 876 goto fail; 877 } 878 879 /* 880 * Call MI attach routine. 881 */ 882 ether_ifattach(ifp, eaddr); 883 884 /* Hook interrupt last to avoid having to lock softc */ 885 error = bus_setup_intr(dev, sc->wb_irq, INTR_TYPE_NET, 886 wb_intr, sc, &sc->wb_intrhand); 887 888 if (error) { 889 printf("wb%d: couldn't set up irq\n", unit); 890 ether_ifdetach(ifp); 891 if_free(ifp); 892 goto fail; 893 } 894 895fail: 896 if (error) 897 wb_detach(dev); 898 899 return(error); 900} 901 902/* 903 * Shutdown hardware and free up resources. This can be called any 904 * time after the mutex has been initialized. It is called in both 905 * the error case in attach and the normal detach case so it needs 906 * to be careful about only freeing resources that have actually been 907 * allocated. 908 */ 909static int 910wb_detach(dev) 911 device_t dev; 912{ 913 struct wb_softc *sc; 914 struct ifnet *ifp; 915 916 sc = device_get_softc(dev); 917 KASSERT(mtx_initialized(&sc->wb_mtx), ("wb mutex not initialized")); 918 WB_LOCK(sc); 919 ifp = sc->wb_ifp; 920 921 /* 922 * Delete any miibus and phy devices attached to this interface. 923 * This should only be done if attach succeeded. 924 */ 925 if (device_is_attached(dev)) { 926 wb_stop(sc); 927 ether_ifdetach(ifp); 928 if_free(ifp); 929 } 930 if (sc->wb_miibus) 931 device_delete_child(dev, sc->wb_miibus); 932 bus_generic_detach(dev); 933 934 if (sc->wb_intrhand) 935 bus_teardown_intr(dev, sc->wb_irq, sc->wb_intrhand); 936 if (sc->wb_irq) 937 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->wb_irq); 938 if (sc->wb_res) 939 bus_release_resource(dev, WB_RES, WB_RID, sc->wb_res); 940 941 if (sc->wb_ldata) { 942 contigfree(sc->wb_ldata, sizeof(struct wb_list_data) + 8, 943 M_DEVBUF); 944 } 945 946 WB_UNLOCK(sc); 947 mtx_destroy(&sc->wb_mtx); 948 949 return(0); 950} 951 952/* 953 * Initialize the transmit descriptors. 954 */ 955static int 956wb_list_tx_init(sc) 957 struct wb_softc *sc; 958{ 959 struct wb_chain_data *cd; 960 struct wb_list_data *ld; 961 int i; 962 963 cd = &sc->wb_cdata; 964 ld = sc->wb_ldata; 965 966 for (i = 0; i < WB_TX_LIST_CNT; i++) { 967 cd->wb_tx_chain[i].wb_ptr = &ld->wb_tx_list[i]; 968 if (i == (WB_TX_LIST_CNT - 1)) { 969 cd->wb_tx_chain[i].wb_nextdesc = 970 &cd->wb_tx_chain[0]; 971 } else { 972 cd->wb_tx_chain[i].wb_nextdesc = 973 &cd->wb_tx_chain[i + 1]; 974 } 975 } 976 977 cd->wb_tx_free = &cd->wb_tx_chain[0]; 978 cd->wb_tx_tail = cd->wb_tx_head = NULL; 979 980 return(0); 981} 982 983 984/* 985 * Initialize the RX descriptors and allocate mbufs for them. Note that 986 * we arrange the descriptors in a closed ring, so that the last descriptor 987 * points back to the first. 988 */ 989static int 990wb_list_rx_init(sc) 991 struct wb_softc *sc; 992{ 993 struct wb_chain_data *cd; 994 struct wb_list_data *ld; 995 int i; 996 997 cd = &sc->wb_cdata; 998 ld = sc->wb_ldata; 999 1000 for (i = 0; i < WB_RX_LIST_CNT; i++) { 1001 cd->wb_rx_chain[i].wb_ptr = 1002 (struct wb_desc *)&ld->wb_rx_list[i]; 1003 cd->wb_rx_chain[i].wb_buf = (void *)&ld->wb_rxbufs[i]; 1004 if (wb_newbuf(sc, &cd->wb_rx_chain[i], NULL) == ENOBUFS) 1005 return(ENOBUFS); 1006 if (i == (WB_RX_LIST_CNT - 1)) { 1007 cd->wb_rx_chain[i].wb_nextdesc = &cd->wb_rx_chain[0]; 1008 ld->wb_rx_list[i].wb_next = 1009 vtophys(&ld->wb_rx_list[0]); 1010 } else { 1011 cd->wb_rx_chain[i].wb_nextdesc = 1012 &cd->wb_rx_chain[i + 1]; 1013 ld->wb_rx_list[i].wb_next = 1014 vtophys(&ld->wb_rx_list[i + 1]); 1015 } 1016 } 1017 1018 cd->wb_rx_head = &cd->wb_rx_chain[0]; 1019 1020 return(0); 1021} 1022 1023static void 1024wb_bfree(buf, args) 1025 void *buf; 1026 void *args; 1027{ 1028 return; 1029} 1030 1031/* 1032 * Initialize an RX descriptor and attach an MBUF cluster. 1033 */ 1034static int 1035wb_newbuf(sc, c, m) 1036 struct wb_softc *sc; 1037 struct wb_chain_onefrag *c; 1038 struct mbuf *m; 1039{ 1040 struct mbuf *m_new = NULL; 1041 1042 if (m == NULL) { 1043 MGETHDR(m_new, M_DONTWAIT, MT_DATA); 1044 if (m_new == NULL) 1045 return(ENOBUFS); 1046 m_new->m_data = c->wb_buf; 1047 m_new->m_pkthdr.len = m_new->m_len = WB_BUFBYTES; 1048 MEXTADD(m_new, c->wb_buf, WB_BUFBYTES, wb_bfree, NULL, 0, 1049 EXT_NET_DRV); 1050 } else { 1051 m_new = m; 1052 m_new->m_len = m_new->m_pkthdr.len = WB_BUFBYTES; 1053 m_new->m_data = m_new->m_ext.ext_buf; 1054 } 1055 1056 m_adj(m_new, sizeof(u_int64_t)); 1057 1058 c->wb_mbuf = m_new; 1059 c->wb_ptr->wb_data = vtophys(mtod(m_new, caddr_t)); 1060 c->wb_ptr->wb_ctl = WB_RXCTL_RLINK | 1536; 1061 c->wb_ptr->wb_status = WB_RXSTAT; 1062 1063 return(0); 1064} 1065 1066/* 1067 * A frame has been uploaded: pass the resulting mbuf chain up to 1068 * the higher level protocols. 1069 */ 1070static void 1071wb_rxeof(sc) 1072 struct wb_softc *sc; 1073{ 1074 struct mbuf *m = NULL; 1075 struct ifnet *ifp; 1076 struct wb_chain_onefrag *cur_rx; 1077 int total_len = 0; 1078 u_int32_t rxstat; 1079 1080 WB_LOCK_ASSERT(sc); 1081 1082 ifp = sc->wb_ifp; 1083 1084 while(!((rxstat = sc->wb_cdata.wb_rx_head->wb_ptr->wb_status) & 1085 WB_RXSTAT_OWN)) { 1086 struct mbuf *m0 = NULL; 1087 1088 cur_rx = sc->wb_cdata.wb_rx_head; 1089 sc->wb_cdata.wb_rx_head = cur_rx->wb_nextdesc; 1090 1091 m = cur_rx->wb_mbuf; 1092 1093 if ((rxstat & WB_RXSTAT_MIIERR) || 1094 (WB_RXBYTES(cur_rx->wb_ptr->wb_status) < WB_MIN_FRAMELEN) || 1095 (WB_RXBYTES(cur_rx->wb_ptr->wb_status) > 1536) || 1096 !(rxstat & WB_RXSTAT_LASTFRAG) || 1097 !(rxstat & WB_RXSTAT_RXCMP)) { 1098 ifp->if_ierrors++; 1099 wb_newbuf(sc, cur_rx, m); 1100 printf("wb%x: receiver babbling: possible chip " 1101 "bug, forcing reset\n", sc->wb_unit); 1102 wb_fixmedia(sc); 1103 wb_reset(sc); 1104 wb_init(sc); 1105 return; 1106 } 1107 1108 if (rxstat & WB_RXSTAT_RXERR) { 1109 ifp->if_ierrors++; 1110 wb_newbuf(sc, cur_rx, m); 1111 break; 1112 } 1113 1114 /* No errors; receive the packet. */ 1115 total_len = WB_RXBYTES(cur_rx->wb_ptr->wb_status); 1116 1117 /* 1118 * XXX The Winbond chip includes the CRC with every 1119 * received frame, and there's no way to turn this 1120 * behavior off (at least, I can't find anything in 1121 * the manual that explains how to do it) so we have 1122 * to trim off the CRC manually. 1123 */ 1124 total_len -= ETHER_CRC_LEN; 1125 1126 m0 = m_devget(mtod(m, char *), total_len, ETHER_ALIGN, ifp, 1127 NULL); 1128 wb_newbuf(sc, cur_rx, m); 1129 if (m0 == NULL) { 1130 ifp->if_ierrors++; 1131 break; 1132 } 1133 m = m0; 1134 1135 ifp->if_ipackets++; 1136 WB_UNLOCK(sc); 1137 (*ifp->if_input)(ifp, m); 1138 WB_LOCK(sc); 1139 } 1140} 1141 1142static void 1143wb_rxeoc(sc) 1144 struct wb_softc *sc; 1145{ 1146 wb_rxeof(sc); 1147 1148 WB_CLRBIT(sc, WB_NETCFG, WB_NETCFG_RX_ON); 1149 CSR_WRITE_4(sc, WB_RXADDR, vtophys(&sc->wb_ldata->wb_rx_list[0])); 1150 WB_SETBIT(sc, WB_NETCFG, WB_NETCFG_RX_ON); 1151 if (CSR_READ_4(sc, WB_ISR) & WB_RXSTATE_SUSPEND) 1152 CSR_WRITE_4(sc, WB_RXSTART, 0xFFFFFFFF); 1153 1154 return; 1155} 1156 1157/* 1158 * A frame was downloaded to the chip. It's safe for us to clean up 1159 * the list buffers. 1160 */ 1161static void 1162wb_txeof(sc) 1163 struct wb_softc *sc; 1164{ 1165 struct wb_chain *cur_tx; 1166 struct ifnet *ifp; 1167 1168 ifp = sc->wb_ifp; 1169 1170 /* Clear the timeout timer. */ 1171 ifp->if_timer = 0; 1172 1173 if (sc->wb_cdata.wb_tx_head == NULL) 1174 return; 1175 1176 /* 1177 * Go through our tx list and free mbufs for those 1178 * frames that have been transmitted. 1179 */ 1180 while(sc->wb_cdata.wb_tx_head->wb_mbuf != NULL) { 1181 u_int32_t txstat; 1182 1183 cur_tx = sc->wb_cdata.wb_tx_head; 1184 txstat = WB_TXSTATUS(cur_tx); 1185 1186 if ((txstat & WB_TXSTAT_OWN) || txstat == WB_UNSENT) 1187 break; 1188 1189 if (txstat & WB_TXSTAT_TXERR) { 1190 ifp->if_oerrors++; 1191 if (txstat & WB_TXSTAT_ABORT) 1192 ifp->if_collisions++; 1193 if (txstat & WB_TXSTAT_LATECOLL) 1194 ifp->if_collisions++; 1195 } 1196 1197 ifp->if_collisions += (txstat & WB_TXSTAT_COLLCNT) >> 3; 1198 1199 ifp->if_opackets++; 1200 m_freem(cur_tx->wb_mbuf); 1201 cur_tx->wb_mbuf = NULL; 1202 1203 if (sc->wb_cdata.wb_tx_head == sc->wb_cdata.wb_tx_tail) { 1204 sc->wb_cdata.wb_tx_head = NULL; 1205 sc->wb_cdata.wb_tx_tail = NULL; 1206 break; 1207 } 1208 1209 sc->wb_cdata.wb_tx_head = cur_tx->wb_nextdesc; 1210 } 1211 1212 return; 1213} 1214 1215/* 1216 * TX 'end of channel' interrupt handler. 1217 */ 1218static void 1219wb_txeoc(sc) 1220 struct wb_softc *sc; 1221{ 1222 struct ifnet *ifp; 1223 1224 ifp = sc->wb_ifp; 1225 1226 ifp->if_timer = 0; 1227 1228 if (sc->wb_cdata.wb_tx_head == NULL) { 1229 ifp->if_flags &= ~IFF_OACTIVE; 1230 sc->wb_cdata.wb_tx_tail = NULL; 1231 } else { 1232 if (WB_TXOWN(sc->wb_cdata.wb_tx_head) == WB_UNSENT) { 1233 WB_TXOWN(sc->wb_cdata.wb_tx_head) = WB_TXSTAT_OWN; 1234 ifp->if_timer = 5; 1235 CSR_WRITE_4(sc, WB_TXSTART, 0xFFFFFFFF); 1236 } 1237 } 1238 1239 return; 1240} 1241 1242static void 1243wb_intr(arg) 1244 void *arg; 1245{ 1246 struct wb_softc *sc; 1247 struct ifnet *ifp; 1248 u_int32_t status; 1249 1250 sc = arg; 1251 WB_LOCK(sc); 1252 ifp = sc->wb_ifp; 1253 1254 if (!(ifp->if_flags & IFF_UP)) { 1255 WB_UNLOCK(sc); 1256 return; 1257 } 1258 1259 /* Disable interrupts. */ 1260 CSR_WRITE_4(sc, WB_IMR, 0x00000000); 1261 1262 for (;;) { 1263 1264 status = CSR_READ_4(sc, WB_ISR); 1265 if (status) 1266 CSR_WRITE_4(sc, WB_ISR, status); 1267 1268 if ((status & WB_INTRS) == 0) 1269 break; 1270 1271 if ((status & WB_ISR_RX_NOBUF) || (status & WB_ISR_RX_ERR)) { 1272 ifp->if_ierrors++; 1273 wb_reset(sc); 1274 if (status & WB_ISR_RX_ERR) 1275 wb_fixmedia(sc); 1276 wb_init(sc); 1277 continue; 1278 } 1279 1280 if (status & WB_ISR_RX_OK) 1281 wb_rxeof(sc); 1282 1283 if (status & WB_ISR_RX_IDLE) 1284 wb_rxeoc(sc); 1285 1286 if (status & WB_ISR_TX_OK) 1287 wb_txeof(sc); 1288 1289 if (status & WB_ISR_TX_NOBUF) 1290 wb_txeoc(sc); 1291 1292 if (status & WB_ISR_TX_IDLE) { 1293 wb_txeof(sc); 1294 if (sc->wb_cdata.wb_tx_head != NULL) { 1295 WB_SETBIT(sc, WB_NETCFG, WB_NETCFG_TX_ON); 1296 CSR_WRITE_4(sc, WB_TXSTART, 0xFFFFFFFF); 1297 } 1298 } 1299 1300 if (status & WB_ISR_TX_UNDERRUN) { 1301 ifp->if_oerrors++; 1302 wb_txeof(sc); 1303 WB_CLRBIT(sc, WB_NETCFG, WB_NETCFG_TX_ON); 1304 /* Jack up TX threshold */ 1305 sc->wb_txthresh += WB_TXTHRESH_CHUNK; 1306 WB_CLRBIT(sc, WB_NETCFG, WB_NETCFG_TX_THRESH); 1307 WB_SETBIT(sc, WB_NETCFG, WB_TXTHRESH(sc->wb_txthresh)); 1308 WB_SETBIT(sc, WB_NETCFG, WB_NETCFG_TX_ON); 1309 } 1310 1311 if (status & WB_ISR_BUS_ERR) { 1312 wb_reset(sc); 1313 wb_init(sc); 1314 } 1315 1316 } 1317 1318 /* Re-enable interrupts. */ 1319 CSR_WRITE_4(sc, WB_IMR, WB_INTRS); 1320 1321 if (ifp->if_snd.ifq_head != NULL) { 1322 wb_start(ifp); 1323 } 1324 1325 WB_UNLOCK(sc); 1326 1327 return; 1328} 1329 1330static void 1331wb_tick(xsc) 1332 void *xsc; 1333{ 1334 struct wb_softc *sc; 1335 struct mii_data *mii; 1336 1337 sc = xsc; 1338 WB_LOCK(sc); 1339 mii = device_get_softc(sc->wb_miibus); 1340 1341 mii_tick(mii); 1342 1343 sc->wb_stat_ch = timeout(wb_tick, sc, hz); 1344 1345 WB_UNLOCK(sc); 1346 1347 return; 1348} 1349 1350/* 1351 * Encapsulate an mbuf chain in a descriptor by coupling the mbuf data 1352 * pointers to the fragment pointers. 1353 */ 1354static int 1355wb_encap(sc, c, m_head) 1356 struct wb_softc *sc; 1357 struct wb_chain *c; 1358 struct mbuf *m_head; 1359{ 1360 int frag = 0; 1361 struct wb_desc *f = NULL; 1362 int total_len; 1363 struct mbuf *m; 1364 1365 /* 1366 * Start packing the mbufs in this chain into 1367 * the fragment pointers. Stop when we run out 1368 * of fragments or hit the end of the mbuf chain. 1369 */ 1370 m = m_head; 1371 total_len = 0; 1372 1373 for (m = m_head, frag = 0; m != NULL; m = m->m_next) { 1374 if (m->m_len != 0) { 1375 if (frag == WB_MAXFRAGS) 1376 break; 1377 total_len += m->m_len; 1378 f = &c->wb_ptr->wb_frag[frag]; 1379 f->wb_ctl = WB_TXCTL_TLINK | m->m_len; 1380 if (frag == 0) { 1381 f->wb_ctl |= WB_TXCTL_FIRSTFRAG; 1382 f->wb_status = 0; 1383 } else 1384 f->wb_status = WB_TXSTAT_OWN; 1385 f->wb_next = vtophys(&c->wb_ptr->wb_frag[frag + 1]); 1386 f->wb_data = vtophys(mtod(m, vm_offset_t)); 1387 frag++; 1388 } 1389 } 1390 1391 /* 1392 * Handle special case: we used up all 16 fragments, 1393 * but we have more mbufs left in the chain. Copy the 1394 * data into an mbuf cluster. Note that we don't 1395 * bother clearing the values in the other fragment 1396 * pointers/counters; it wouldn't gain us anything, 1397 * and would waste cycles. 1398 */ 1399 if (m != NULL) { 1400 struct mbuf *m_new = NULL; 1401 1402 MGETHDR(m_new, M_DONTWAIT, MT_DATA); 1403 if (m_new == NULL) 1404 return(1); 1405 if (m_head->m_pkthdr.len > MHLEN) { 1406 MCLGET(m_new, M_DONTWAIT); 1407 if (!(m_new->m_flags & M_EXT)) { 1408 m_freem(m_new); 1409 return(1); 1410 } 1411 } 1412 m_copydata(m_head, 0, m_head->m_pkthdr.len, 1413 mtod(m_new, caddr_t)); 1414 m_new->m_pkthdr.len = m_new->m_len = m_head->m_pkthdr.len; 1415 m_freem(m_head); 1416 m_head = m_new; 1417 f = &c->wb_ptr->wb_frag[0]; 1418 f->wb_status = 0; 1419 f->wb_data = vtophys(mtod(m_new, caddr_t)); 1420 f->wb_ctl = total_len = m_new->m_len; 1421 f->wb_ctl |= WB_TXCTL_TLINK|WB_TXCTL_FIRSTFRAG; 1422 frag = 1; 1423 } 1424 1425 if (total_len < WB_MIN_FRAMELEN) { 1426 f = &c->wb_ptr->wb_frag[frag]; 1427 f->wb_ctl = WB_MIN_FRAMELEN - total_len; 1428 f->wb_data = vtophys(&sc->wb_cdata.wb_pad); 1429 f->wb_ctl |= WB_TXCTL_TLINK; 1430 f->wb_status = WB_TXSTAT_OWN; 1431 frag++; 1432 } 1433 1434 c->wb_mbuf = m_head; 1435 c->wb_lastdesc = frag - 1; 1436 WB_TXCTL(c) |= WB_TXCTL_LASTFRAG; 1437 WB_TXNEXT(c) = vtophys(&c->wb_nextdesc->wb_ptr->wb_frag[0]); 1438 1439 return(0); 1440} 1441 1442/* 1443 * Main transmit routine. To avoid having to do mbuf copies, we put pointers 1444 * to the mbuf data regions directly in the transmit lists. We also save a 1445 * copy of the pointers since the transmit list fragment pointers are 1446 * physical addresses. 1447 */ 1448 1449static void 1450wb_start(ifp) 1451 struct ifnet *ifp; 1452{ 1453 struct wb_softc *sc; 1454 struct mbuf *m_head = NULL; 1455 struct wb_chain *cur_tx = NULL, *start_tx; 1456 1457 sc = ifp->if_softc; 1458 WB_LOCK(sc); 1459 1460 /* 1461 * Check for an available queue slot. If there are none, 1462 * punt. 1463 */ 1464 if (sc->wb_cdata.wb_tx_free->wb_mbuf != NULL) { 1465 ifp->if_flags |= IFF_OACTIVE; 1466 WB_UNLOCK(sc); 1467 return; 1468 } 1469 1470 start_tx = sc->wb_cdata.wb_tx_free; 1471 1472 while(sc->wb_cdata.wb_tx_free->wb_mbuf == NULL) { 1473 IF_DEQUEUE(&ifp->if_snd, m_head); 1474 if (m_head == NULL) 1475 break; 1476 1477 /* Pick a descriptor off the free list. */ 1478 cur_tx = sc->wb_cdata.wb_tx_free; 1479 sc->wb_cdata.wb_tx_free = cur_tx->wb_nextdesc; 1480 1481 /* Pack the data into the descriptor. */ 1482 wb_encap(sc, cur_tx, m_head); 1483 1484 if (cur_tx != start_tx) 1485 WB_TXOWN(cur_tx) = WB_TXSTAT_OWN; 1486 1487 /* 1488 * If there's a BPF listener, bounce a copy of this frame 1489 * to him. 1490 */ 1491 BPF_MTAP(ifp, cur_tx->wb_mbuf); 1492 } 1493 1494 /* 1495 * If there are no packets queued, bail. 1496 */ 1497 if (cur_tx == NULL) { 1498 WB_UNLOCK(sc); 1499 return; 1500 } 1501 1502 /* 1503 * Place the request for the upload interrupt 1504 * in the last descriptor in the chain. This way, if 1505 * we're chaining several packets at once, we'll only 1506 * get an interupt once for the whole chain rather than 1507 * once for each packet. 1508 */ 1509 WB_TXCTL(cur_tx) |= WB_TXCTL_FINT; 1510 cur_tx->wb_ptr->wb_frag[0].wb_ctl |= WB_TXCTL_FINT; 1511 sc->wb_cdata.wb_tx_tail = cur_tx; 1512 1513 if (sc->wb_cdata.wb_tx_head == NULL) { 1514 sc->wb_cdata.wb_tx_head = start_tx; 1515 WB_TXOWN(start_tx) = WB_TXSTAT_OWN; 1516 CSR_WRITE_4(sc, WB_TXSTART, 0xFFFFFFFF); 1517 } else { 1518 /* 1519 * We need to distinguish between the case where 1520 * the own bit is clear because the chip cleared it 1521 * and where the own bit is clear because we haven't 1522 * set it yet. The magic value WB_UNSET is just some 1523 * ramdomly chosen number which doesn't have the own 1524 * bit set. When we actually transmit the frame, the 1525 * status word will have _only_ the own bit set, so 1526 * the txeoc handler will be able to tell if it needs 1527 * to initiate another transmission to flush out pending 1528 * frames. 1529 */ 1530 WB_TXOWN(start_tx) = WB_UNSENT; 1531 } 1532 1533 /* 1534 * Set a timeout in case the chip goes out to lunch. 1535 */ 1536 ifp->if_timer = 5; 1537 WB_UNLOCK(sc); 1538 1539 return; 1540} 1541 1542static void 1543wb_init(xsc) 1544 void *xsc; 1545{ 1546 struct wb_softc *sc = xsc; 1547 struct ifnet *ifp = sc->wb_ifp; 1548 int i; 1549 struct mii_data *mii; 1550 1551 WB_LOCK(sc); 1552 mii = device_get_softc(sc->wb_miibus); 1553 1554 /* 1555 * Cancel pending I/O and free all RX/TX buffers. 1556 */ 1557 wb_stop(sc); 1558 wb_reset(sc); 1559 1560 sc->wb_txthresh = WB_TXTHRESH_INIT; 1561 1562 /* 1563 * Set cache alignment and burst length. 1564 */ 1565#ifdef foo 1566 CSR_WRITE_4(sc, WB_BUSCTL, WB_BUSCTL_CONFIG); 1567 WB_CLRBIT(sc, WB_NETCFG, WB_NETCFG_TX_THRESH); 1568 WB_SETBIT(sc, WB_NETCFG, WB_TXTHRESH(sc->wb_txthresh)); 1569#endif 1570 1571 CSR_WRITE_4(sc, WB_BUSCTL, WB_BUSCTL_MUSTBEONE|WB_BUSCTL_ARBITRATION); 1572 WB_SETBIT(sc, WB_BUSCTL, WB_BURSTLEN_16LONG); 1573 switch(sc->wb_cachesize) { 1574 case 32: 1575 WB_SETBIT(sc, WB_BUSCTL, WB_CACHEALIGN_32LONG); 1576 break; 1577 case 16: 1578 WB_SETBIT(sc, WB_BUSCTL, WB_CACHEALIGN_16LONG); 1579 break; 1580 case 8: 1581 WB_SETBIT(sc, WB_BUSCTL, WB_CACHEALIGN_8LONG); 1582 break; 1583 case 0: 1584 default: 1585 WB_SETBIT(sc, WB_BUSCTL, WB_CACHEALIGN_NONE); 1586 break; 1587 } 1588 1589 /* This doesn't tend to work too well at 100Mbps. */ 1590 WB_CLRBIT(sc, WB_NETCFG, WB_NETCFG_TX_EARLY_ON); 1591 1592 /* Init our MAC address */ 1593 for (i = 0; i < ETHER_ADDR_LEN; i++) { 1594 CSR_WRITE_1(sc, WB_NODE0 + i, IFP2ENADDR(sc->wb_ifp)[i]); 1595 } 1596 1597 /* Init circular RX list. */ 1598 if (wb_list_rx_init(sc) == ENOBUFS) { 1599 printf("wb%d: initialization failed: no " 1600 "memory for rx buffers\n", sc->wb_unit); 1601 wb_stop(sc); 1602 WB_UNLOCK(sc); 1603 return; 1604 } 1605 1606 /* Init TX descriptors. */ 1607 wb_list_tx_init(sc); 1608 1609 /* If we want promiscuous mode, set the allframes bit. */ 1610 if (ifp->if_flags & IFF_PROMISC) { 1611 WB_SETBIT(sc, WB_NETCFG, WB_NETCFG_RX_ALLPHYS); 1612 } else { 1613 WB_CLRBIT(sc, WB_NETCFG, WB_NETCFG_RX_ALLPHYS); 1614 } 1615 1616 /* 1617 * Set capture broadcast bit to capture broadcast frames. 1618 */ 1619 if (ifp->if_flags & IFF_BROADCAST) { 1620 WB_SETBIT(sc, WB_NETCFG, WB_NETCFG_RX_BROAD); 1621 } else { 1622 WB_CLRBIT(sc, WB_NETCFG, WB_NETCFG_RX_BROAD); 1623 } 1624 1625 /* 1626 * Program the multicast filter, if necessary. 1627 */ 1628 wb_setmulti(sc); 1629 1630 /* 1631 * Load the address of the RX list. 1632 */ 1633 WB_CLRBIT(sc, WB_NETCFG, WB_NETCFG_RX_ON); 1634 CSR_WRITE_4(sc, WB_RXADDR, vtophys(&sc->wb_ldata->wb_rx_list[0])); 1635 1636 /* 1637 * Enable interrupts. 1638 */ 1639 CSR_WRITE_4(sc, WB_IMR, WB_INTRS); 1640 CSR_WRITE_4(sc, WB_ISR, 0xFFFFFFFF); 1641 1642 /* Enable receiver and transmitter. */ 1643 WB_SETBIT(sc, WB_NETCFG, WB_NETCFG_RX_ON); 1644 CSR_WRITE_4(sc, WB_RXSTART, 0xFFFFFFFF); 1645 1646 WB_CLRBIT(sc, WB_NETCFG, WB_NETCFG_TX_ON); 1647 CSR_WRITE_4(sc, WB_TXADDR, vtophys(&sc->wb_ldata->wb_tx_list[0])); 1648 WB_SETBIT(sc, WB_NETCFG, WB_NETCFG_TX_ON); 1649 1650 mii_mediachg(mii); 1651 1652 ifp->if_flags |= IFF_RUNNING; 1653 ifp->if_flags &= ~IFF_OACTIVE; 1654 1655 sc->wb_stat_ch = timeout(wb_tick, sc, hz); 1656 WB_UNLOCK(sc); 1657 1658 return; 1659} 1660 1661/* 1662 * Set media options. 1663 */ 1664static int 1665wb_ifmedia_upd(ifp) 1666 struct ifnet *ifp; 1667{ 1668 struct wb_softc *sc; 1669 1670 sc = ifp->if_softc; 1671 1672 if (ifp->if_flags & IFF_UP) 1673 wb_init(sc); 1674 1675 return(0); 1676} 1677 1678/* 1679 * Report current media status. 1680 */ 1681static void 1682wb_ifmedia_sts(ifp, ifmr) 1683 struct ifnet *ifp; 1684 struct ifmediareq *ifmr; 1685{ 1686 struct wb_softc *sc; 1687 struct mii_data *mii; 1688 1689 sc = ifp->if_softc; 1690 1691 mii = device_get_softc(sc->wb_miibus); 1692 1693 mii_pollstat(mii); 1694 ifmr->ifm_active = mii->mii_media_active; 1695 ifmr->ifm_status = mii->mii_media_status; 1696 1697 return; 1698} 1699 1700static int 1701wb_ioctl(ifp, command, data) 1702 struct ifnet *ifp; 1703 u_long command; 1704 caddr_t data; 1705{ 1706 struct wb_softc *sc = ifp->if_softc; 1707 struct mii_data *mii; 1708 struct ifreq *ifr = (struct ifreq *) data; 1709 int error = 0; 1710 1711 WB_LOCK(sc); 1712 1713 switch(command) { 1714 case SIOCSIFFLAGS: 1715 if (ifp->if_flags & IFF_UP) { 1716 wb_init(sc); 1717 } else { 1718 if (ifp->if_flags & IFF_RUNNING) 1719 wb_stop(sc); 1720 } 1721 error = 0; 1722 break; 1723 case SIOCADDMULTI: 1724 case SIOCDELMULTI: 1725 wb_setmulti(sc); 1726 error = 0; 1727 break; 1728 case SIOCGIFMEDIA: 1729 case SIOCSIFMEDIA: 1730 mii = device_get_softc(sc->wb_miibus); 1731 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command); 1732 break; 1733 default: 1734 error = ether_ioctl(ifp, command, data); 1735 break; 1736 } 1737 1738 WB_UNLOCK(sc); 1739 1740 return(error); 1741} 1742 1743static void 1744wb_watchdog(ifp) 1745 struct ifnet *ifp; 1746{ 1747 struct wb_softc *sc; 1748 1749 sc = ifp->if_softc; 1750 1751 WB_LOCK(sc); 1752 ifp->if_oerrors++; 1753 printf("wb%d: watchdog timeout\n", sc->wb_unit); 1754#ifdef foo 1755 if (!(wb_phy_readreg(sc, PHY_BMSR) & PHY_BMSR_LINKSTAT)) 1756 printf("wb%d: no carrier - transceiver cable problem?\n", 1757 sc->wb_unit); 1758#endif 1759 wb_stop(sc); 1760 wb_reset(sc); 1761 wb_init(sc); 1762 1763 if (ifp->if_snd.ifq_head != NULL) 1764 wb_start(ifp); 1765 WB_UNLOCK(sc); 1766 1767 return; 1768} 1769 1770/* 1771 * Stop the adapter and free any mbufs allocated to the 1772 * RX and TX lists. 1773 */ 1774static void 1775wb_stop(sc) 1776 struct wb_softc *sc; 1777{ 1778 register int i; 1779 struct ifnet *ifp; 1780 1781 WB_LOCK(sc); 1782 ifp = sc->wb_ifp; 1783 ifp->if_timer = 0; 1784 1785 untimeout(wb_tick, sc, sc->wb_stat_ch); 1786 1787 WB_CLRBIT(sc, WB_NETCFG, (WB_NETCFG_RX_ON|WB_NETCFG_TX_ON)); 1788 CSR_WRITE_4(sc, WB_IMR, 0x00000000); 1789 CSR_WRITE_4(sc, WB_TXADDR, 0x00000000); 1790 CSR_WRITE_4(sc, WB_RXADDR, 0x00000000); 1791 1792 /* 1793 * Free data in the RX lists. 1794 */ 1795 for (i = 0; i < WB_RX_LIST_CNT; i++) { 1796 if (sc->wb_cdata.wb_rx_chain[i].wb_mbuf != NULL) { 1797 m_freem(sc->wb_cdata.wb_rx_chain[i].wb_mbuf); 1798 sc->wb_cdata.wb_rx_chain[i].wb_mbuf = NULL; 1799 } 1800 } 1801 bzero((char *)&sc->wb_ldata->wb_rx_list, 1802 sizeof(sc->wb_ldata->wb_rx_list)); 1803 1804 /* 1805 * Free the TX list buffers. 1806 */ 1807 for (i = 0; i < WB_TX_LIST_CNT; i++) { 1808 if (sc->wb_cdata.wb_tx_chain[i].wb_mbuf != NULL) { 1809 m_freem(sc->wb_cdata.wb_tx_chain[i].wb_mbuf); 1810 sc->wb_cdata.wb_tx_chain[i].wb_mbuf = NULL; 1811 } 1812 } 1813 1814 bzero((char *)&sc->wb_ldata->wb_tx_list, 1815 sizeof(sc->wb_ldata->wb_tx_list)); 1816 1817 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 1818 WB_UNLOCK(sc); 1819 1820 return; 1821} 1822 1823/* 1824 * Stop all chip I/O so that the kernel's probe routines don't 1825 * get confused by errant DMAs when rebooting. 1826 */ 1827static void 1828wb_shutdown(dev) 1829 device_t dev; 1830{ 1831 struct wb_softc *sc; 1832 1833 sc = device_get_softc(dev); 1834 wb_stop(sc); 1835 1836 return; 1837} 1838