vxgehal-device.h revision 221167
11946Sks34972/*- 21946Sks34972 * Copyright(c) 2002-2011 Exar Corp. 31946Sks34972 * All rights reserved. 41946Sks34972 * 51946Sks34972 * Redistribution and use in source and binary forms, with or without 61946Sks34972 * modification are permitted provided the following conditions are met: 71946Sks34972 * 81946Sks34972 * 1. Redistributions of source code must retain the above copyright notice, 91946Sks34972 * this list of conditions and the following disclaimer. 101946Sks34972 * 111946Sks34972 * 2. Redistributions in binary form must reproduce the above copyright 121946Sks34972 * notice, this list of conditions and the following disclaimer in the 131946Sks34972 * documentation and/or other materials provided with the distribution. 141946Sks34972 * 151946Sks34972 * 3. Neither the name of the Exar Corporation nor the names of its 161946Sks34972 * contributors may be used to endorse or promote products derived from 171946Sks34972 * this software without specific prior written permission. 181946Sks34972 * 191946Sks34972 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 201946Sks34972 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 211946Sks34972 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 221946Sks34972 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE 231946Sks34972 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 241946Sks34972 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 251946Sks34972 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 261946Sks34972 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 271946Sks34972 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 281946Sks34972 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 291946Sks34972 * POSSIBILITY OF SUCH DAMAGE. 301946Sks34972 */ 311946Sks34972/*$FreeBSD: head/sys/dev/vxge/vxgehal/vxgehal-device.h 221167 2011-04-28 14:33:15Z gnn $*/ 321946Sks34972 331946Sks34972#ifndef VXGE_HAL_DEVICE_H 341946Sks34972#define VXGE_HAL_DEVICE_H 351946Sks34972 361946Sks34972__EXTERN_BEGIN_DECLS 371946Sks34972 381946Sks34972struct __hal_mrpcim_t; 391946Sks34972struct __hal_srpcim_t; 401946Sks34972 411946Sks34972/* 421946Sks34972 * vxge_hal_vpd_data_t 431946Sks34972 * 441946Sks34972 * Represents vpd capabilty structure 451946Sks34972 */ 461946Sks34972typedef struct vxge_hal_vpd_data_t { 471946Sks34972 u8 product_name[VXGE_HAL_VPD_LEN]; 481946Sks34972 u8 serial_num[VXGE_HAL_VPD_LEN]; 491946Sks34972} vxge_hal_vpd_data_t; 501946Sks34972 511946Sks34972#if defined(VXGE_TRACE_INTO_CIRCULAR_ARR) 521946Sks34972/* 531946Sks34972 * __hal_tracebuf_t 541946Sks34972 * 551946Sks34972 * HAL trace buffer object. 561946Sks34972 */ 571946Sks34972typedef struct __hal_tracebuf_t { 581946Sks34972 u8 *data; 591946Sks34972 u64 wrapped_count; 601946Sks34972 volatile u32 offset; 611946Sks34972 u32 size; 621946Sks34972} __hal_tracebuf_t; 631946Sks34972#endif 641946Sks34972 651946Sks34972/* 661946Sks34972 * __hal_msix_map_t 671946Sks34972 * 681946Sks34972 * HAL msix to vpath map. 691946Sks34972 */ 701946Sks34972typedef struct __hal_msix_map_t { 711946Sks34972 u32 vp_id; 721946Sks34972 u32 int_num; 731946Sks34972} __hal_msix_map_t; 741946Sks34972 751946Sks34972/* 761946Sks34972 * __hal_device_t 771946Sks34972 * 781946Sks34972 * HAL device object. Represents X3100. 791946Sks34972 */ 801946Sks34972typedef struct __hal_device_t { 811946Sks34972 vxge_hal_device_t header; 821946Sks34972 u32 host_type; 831946Sks34972 u32 vh_id; 841946Sks34972 u32 func_id; 851946Sks34972 u32 srpcim_id; 861946Sks34972 u32 access_rights; 871946Sks34972#define VXGE_HAL_DEVICE_ACCESS_RIGHT_VPATH 0x1 881946Sks34972#define VXGE_HAL_DEVICE_ACCESS_RIGHT_SRPCIM 0x2 891946Sks34972#define VXGE_HAL_DEVICE_ACCESS_RIGHT_MRPCIM 0x4 901946Sks34972 u32 ifmsg_seqno; 911946Sks34972 u32 manager_up; 921946Sks34972 vxge_hal_pci_config_t pci_config_space; 931946Sks34972 vxge_hal_pci_config_t pci_config_space_bios; 941946Sks34972 vxge_hal_pci_caps_offset_t pci_caps; 951946Sks34972 vxge_hal_pci_e_caps_offset_t pci_e_caps; 961946Sks34972 vxge_hal_pci_e_ext_caps_offset_t pci_e_ext_caps; 971946Sks34972 vxge_hal_legacy_reg_t *legacy_reg; 981946Sks34972 vxge_hal_toc_reg_t *toc_reg; 991946Sks34972 vxge_hal_common_reg_t *common_reg; 1001946Sks34972 vxge_hal_memrepair_reg_t *memrepair_reg; 1011946Sks34972 vxge_hal_pcicfgmgmt_reg_t 1021946Sks34972 *pcicfgmgmt_reg[VXGE_HAL_TITAN_PCICFGMGMT_REG_SPACES]; 1031946Sks34972 vxge_hal_mrpcim_reg_t *mrpcim_reg; 1041946Sks34972 vxge_hal_srpcim_reg_t 1051946Sks34972 *srpcim_reg[VXGE_HAL_TITAN_SRPCIM_REG_SPACES]; 1061946Sks34972 vxge_hal_vpmgmt_reg_t 1071946Sks34972 *vpmgmt_reg[VXGE_HAL_TITAN_VPMGMT_REG_SPACES]; 1081946Sks34972 vxge_hal_vpath_reg_t 1091946Sks34972 *vpath_reg[VXGE_HAL_TITAN_VPATH_REG_SPACES]; 1101946Sks34972 u8 *kdfc; 1111946Sks34972 u8 *usdc; 1121946Sks34972 __hal_virtualpath_t 1131946Sks34972 virtual_paths[VXGE_HAL_MAX_VIRTUAL_PATHS]; 1141946Sks34972 u64 vpath_assignments; 1151946Sks34972 u64 vpaths_deployed; 1161946Sks34972 u32 first_vp_id; 1171946Sks34972 u64 tim_int_mask0[4]; 1181946Sks34972 u32 tim_int_mask1[4]; 1191946Sks34972 __hal_msix_map_t 1201946Sks34972 msix_map[VXGE_HAL_MAX_VIRTUAL_PATHS * VXGE_HAL_VPATH_MSIX_MAX]; 1211946Sks34972 struct __hal_srpcim_t *srpcim; 1221946Sks34972 struct __hal_mrpcim_t *mrpcim; 1231946Sks34972 __hal_blockpool_t block_pool; 1241946Sks34972 vxge_list_t pending_channel_list; 1251946Sks34972 spinlock_t pending_channel_lock; 1261946Sks34972 vxge_hal_device_stats_t stats; 1271946Sks34972 volatile u32 msix_enabled; 1281946Sks34972 volatile u32 hw_is_initialized; 1291946Sks34972 volatile int device_resetting; 1301946Sks34972 volatile int is_promisc; 1311946Sks34972 int tti_enabled; 1321946Sks34972 spinlock_t titan_post_lock; 1331946Sks34972 u32 mtu_first_time_set; 1341946Sks34972 char *dump_buf; 1351946Sks34972#if defined(VXGE_TRACE_INTO_CIRCULAR_ARR) 1361946Sks34972 __hal_tracebuf_t trace_buf; 1371946Sks34972#endif 1381946Sks34972 volatile u32 in_poll; 1391946Sks34972 u32 d_err_mask; 1401946Sks34972 u32 d_info_mask; 1411946Sks34972 u32 d_trace_mask; 1421946Sks34972} __hal_device_t; 1431946Sks34972 1441946Sks34972/* 1451946Sks34972 * I2C device id. Used in I2C control register for accessing EEPROM device 1461946Sks34972 * memory. 1471946Sks34972 */ 1481946Sks34972#define VXGE_DEV_ID 5 1491946Sks34972 1501946Sks34972#define VXGE_HAL_DEVICE_MANAGER_STATE_SET(hldev, wmsg) { \ 1511946Sks34972 ((__hal_device_t *)hldev)->manager_up = \ 1521946Sks34972 __hal_ifmsg_is_manager_up(wmsg); \ 1531946Sks34972} 1541946Sks34972 1551946Sks34972#define VXGE_HAL_DEVICE_LINK_STATE_SET(hldev, ls) { \ 1561946Sks34972 ((vxge_hal_device_t *)hldev)->link_state = ls; \ 1571946Sks34972} 1581946Sks34972 1591946Sks34972#define VXGE_HAL_DEVICE_DATA_RATE_SET(hldev, dr) { \ 1601946Sks34972 ((vxge_hal_device_t *)hldev)->data_rate = dr; \ 1611946Sks34972} 1621946Sks34972 1631946Sks34972#define VXGE_HAL_DEVICE_TIM_INT_MASK_SET(hldev, i) { \ 1641946Sks34972 if (i < 16) { \ 1651946Sks34972 ((__hal_device_t *)hldev)->tim_int_mask0[0] |= \ 1661946Sks34972 vBIT(0x8, (i*4), 4); \ 1671946Sks34972 ((__hal_device_t *)hldev)->tim_int_mask0[1] |= \ 1681946Sks34972 vBIT(0x4, (i*4), 4); \ 1691946Sks34972 ((__hal_device_t *)hldev)->tim_int_mask0[3] |= \ 1701946Sks34972 vBIT(0x1, (i*4), 4); \ 1711946Sks34972 } else { \ 1721946Sks34972 ((__hal_device_t *)hldev)->tim_int_mask1[0] = 0x80000000; \ 1731946Sks34972 ((__hal_device_t *)hldev)->tim_int_mask1[1] = 0x40000000; \ 1741946Sks34972 ((__hal_device_t *)hldev)->tim_int_mask1[3] = 0x10000000; \ 1751946Sks34972 } \ 1761946Sks34972} 1771946Sks34972 1781946Sks34972#define VXGE_HAL_DEVICE_TIM_INT_MASK_RESET(hldev, i) { \ 1791946Sks34972 if (i < 16) { \ 1801946Sks34972 ((__hal_device_t *)hldev)->tim_int_mask0[0] &= \ 1811946Sks34972 ~vBIT(0x8, (i*4), 4); \ 1821946Sks34972 ((__hal_device_t *)hldev)->tim_int_mask0[1] &= \ 1831946Sks34972 ~vBIT(0x4, (i*4), 4); \ 1841946Sks34972 ((__hal_device_t *)hldev)->tim_int_mask0[3] &= \ 1851946Sks34972 ~vBIT(0x1, (i*4), 4); \ 1861946Sks34972 } else { \ 1871946Sks34972 ((__hal_device_t *)hldev)->tim_int_mask1[0] = 0; \ 1881946Sks34972 ((__hal_device_t *)hldev)->tim_int_mask1[1] = 0; \ 1891946Sks34972 ((__hal_device_t *)hldev)->tim_int_mask1[3] = 0; \ 1901946Sks34972 } \ 1911946Sks34972} 1921946Sks34972 1931946Sks34972/* ========================== PRIVATE API ================================= */ 1941946Sks34972 1951946Sks34972void 1961946Sks34972vxge_hal_pio_mem_write32_upper(pci_dev_h pdev, 1971946Sks34972 pci_reg_h regh, 1981946Sks34972 u32 val, 1991946Sks34972 void *addr); 2001946Sks34972 2011946Sks34972void 2021946Sks34972vxge_hal_pio_mem_write32_lower(pci_dev_h pdev, 2031946Sks34972 pci_reg_h regh, 2041946Sks34972 u32 val, 2051946Sks34972 void *addr); 2061946Sks34972 2071946Sks34972void 2081946Sks34972__hal_device_event_queued(void *data, 2091946Sks34972 u32 event_type); 2101946Sks34972 2111946Sks34972void 2121946Sks34972__hal_device_pci_caps_list_process(__hal_device_t *hldev); 2131946Sks34972 2141946Sks34972void 2151946Sks34972__hal_device_pci_e_init(__hal_device_t *hldev); 2161946Sks34972 2171946Sks34972vxge_hal_status_e 2181946Sks34972vxge_hal_device_register_poll(pci_dev_h pdev, 2191946Sks34972 pci_reg_h regh, 2201946Sks34972 u64 *reg, 2211946Sks34972 u32 op, 2221946Sks34972 u64 mask, 2231946Sks34972 u32 max_millis); 2241946Sks34972 2251946Sks34972vxge_hal_status_e 2261946Sks34972__hal_device_register_stall(pci_dev_h pdev, 2271946Sks34972 pci_reg_h regh, 2281946Sks34972 u64 *reg, 2291946Sks34972 u32 op, 2301946Sks34972 u64 mask, 2311946Sks34972 u32 max_millis); 2321946Sks34972 2331946Sks34972vxge_hal_status_e 2341946Sks34972__hal_device_reg_addr_get(__hal_device_t *hldev); 2351946Sks34972 2361946Sks34972void 2371946Sks34972__hal_device_id_get(__hal_device_t *hldev); 2381946Sks34972 2391946Sks34972u32 2401946Sks34972__hal_device_access_rights_get(u32 host_type, u32 func_id); 2411946Sks34972 2421946Sks34972void 2431946Sks34972__hal_device_host_info_get(__hal_device_t *hldev); 2441946Sks34972 2451946Sks34972vxge_hal_status_e 2461946Sks34972__hal_device_hw_initialize(__hal_device_t *hldev); 2471946Sks34972 2481946Sks34972vxge_hal_status_e 2491946Sks34972__hal_device_reset(__hal_device_t *hldev); 2501946Sks34972 2511946Sks34972vxge_hal_status_e 2521946Sks34972__hal_device_handle_link_up_ind(__hal_device_t *hldev); 2531946Sks34972 2541946Sks34972vxge_hal_status_e 2551946Sks34972__hal_device_handle_link_down_ind(__hal_device_t *hldev); 2561946Sks34972 2571946Sks34972void 2581946Sks34972__hal_device_handle_error( 2591946Sks34972 __hal_device_t *hldev, 2601946Sks34972 u32 vp_id, 2611946Sks34972 vxge_hal_event_e type); 2621946Sks34972 2631946Sks34972__EXTERN_END_DECLS 2641946Sks34972 2651946Sks34972#endif /* VXGE_HAL_DEVICE_H */ 2661946Sks34972