if_vr.c revision 62653
1/* 2 * Copyright (c) 1997, 1998 3 * Bill Paul <wpaul@ctr.columbia.edu>. All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 3. All advertising materials mentioning features or use of this software 14 * must display the following acknowledgement: 15 * This product includes software developed by Bill Paul. 16 * 4. Neither the name of the author nor the names of any co-contributors 17 * may be used to endorse or promote products derived from this software 18 * without specific prior written permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 21 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 30 * THE POSSIBILITY OF SUCH DAMAGE. 31 * 32 * $FreeBSD: head/sys/dev/vr/if_vr.c 62653 2000-07-05 21:37:21Z wpaul $ 33 */ 34 35/* 36 * VIA Rhine fast ethernet PCI NIC driver 37 * 38 * Supports various network adapters based on the VIA Rhine 39 * and Rhine II PCI controllers, including the D-Link DFE530TX. 40 * Datasheets are available at http://www.via.com.tw. 41 * 42 * Written by Bill Paul <wpaul@ctr.columbia.edu> 43 * Electrical Engineering Department 44 * Columbia University, New York City 45 */ 46 47/* 48 * The VIA Rhine controllers are similar in some respects to the 49 * the DEC tulip chips, except less complicated. The controller 50 * uses an MII bus and an external physical layer interface. The 51 * receiver has a one entry perfect filter and a 64-bit hash table 52 * multicast filter. Transmit and receive descriptors are similar 53 * to the tulip. 54 * 55 * The Rhine has a serious flaw in its transmit DMA mechanism: 56 * transmit buffers must be longword aligned. Unfortunately, 57 * FreeBSD doesn't guarantee that mbufs will be filled in starting 58 * at longword boundaries, so we have to do a buffer copy before 59 * transmission. 60 */ 61 62#include <sys/param.h> 63#include <sys/systm.h> 64#include <sys/sockio.h> 65#include <sys/mbuf.h> 66#include <sys/malloc.h> 67#include <sys/kernel.h> 68#include <sys/socket.h> 69 70#include <net/if.h> 71#include <net/if_arp.h> 72#include <net/ethernet.h> 73#include <net/if_dl.h> 74#include <net/if_media.h> 75 76#include <net/bpf.h> 77 78#include <vm/vm.h> /* for vtophys */ 79#include <vm/pmap.h> /* for vtophys */ 80#include <machine/clock.h> /* for DELAY */ 81#include <machine/bus_pio.h> 82#include <machine/bus_memio.h> 83#include <machine/bus.h> 84#include <machine/resource.h> 85#include <sys/bus.h> 86#include <sys/rman.h> 87 88#include <dev/mii/mii.h> 89#include <dev/mii/miivar.h> 90 91#include <pci/pcireg.h> 92#include <pci/pcivar.h> 93 94#define VR_USEIOSPACE 95 96#include <pci/if_vrreg.h> 97 98MODULE_DEPEND(vr, miibus, 1, 1, 1); 99 100/* "controller miibus0" required. See GENERIC if you get errors here. */ 101#include "miibus_if.h" 102 103#ifndef lint 104static const char rcsid[] = 105 "$FreeBSD: head/sys/dev/vr/if_vr.c 62653 2000-07-05 21:37:21Z wpaul $"; 106#endif 107 108/* 109 * Various supported device vendors/types and their names. 110 */ 111static struct vr_type vr_devs[] = { 112 { VIA_VENDORID, VIA_DEVICEID_RHINE, 113 "VIA VT3043 Rhine I 10/100BaseTX" }, 114 { VIA_VENDORID, VIA_DEVICEID_RHINE_II, 115 "VIA VT86C100A Rhine II 10/100BaseTX" }, 116 { VIA_VENDORID, VIA_DEVICEID_RHINE_II_2, 117 "VIA VT6102 Rhine II 10/100BaseTX" }, 118 { DELTA_VENDORID, DELTA_DEVICEID_RHINE_II, 119 "Delta Electronics Rhine II 10/100BaseTX" }, 120 { ADDTRON_VENDORID, ADDTRON_DEVICEID_RHINE_II, 121 "Addtron Technology Rhine II 10/100BaseTX" }, 122 { 0, 0, NULL } 123}; 124 125static int vr_probe __P((device_t)); 126static int vr_attach __P((device_t)); 127static int vr_detach __P((device_t)); 128 129static int vr_newbuf __P((struct vr_softc *, 130 struct vr_chain_onefrag *, 131 struct mbuf *)); 132static int vr_encap __P((struct vr_softc *, struct vr_chain *, 133 struct mbuf * )); 134 135static void vr_rxeof __P((struct vr_softc *)); 136static void vr_rxeoc __P((struct vr_softc *)); 137static void vr_txeof __P((struct vr_softc *)); 138static void vr_txeoc __P((struct vr_softc *)); 139static void vr_tick __P((void *)); 140static void vr_intr __P((void *)); 141static void vr_start __P((struct ifnet *)); 142static int vr_ioctl __P((struct ifnet *, u_long, caddr_t)); 143static void vr_init __P((void *)); 144static void vr_stop __P((struct vr_softc *)); 145static void vr_watchdog __P((struct ifnet *)); 146static void vr_shutdown __P((device_t)); 147static int vr_ifmedia_upd __P((struct ifnet *)); 148static void vr_ifmedia_sts __P((struct ifnet *, struct ifmediareq *)); 149 150static void vr_mii_sync __P((struct vr_softc *)); 151static void vr_mii_send __P((struct vr_softc *, u_int32_t, int)); 152static int vr_mii_readreg __P((struct vr_softc *, struct vr_mii_frame *)); 153static int vr_mii_writereg __P((struct vr_softc *, struct vr_mii_frame *)); 154static int vr_miibus_readreg __P((device_t, int, int)); 155static int vr_miibus_writereg __P((device_t, int, int, int)); 156static void vr_miibus_statchg __P((device_t)); 157 158static void vr_setcfg __P((struct vr_softc *, int)); 159static u_int8_t vr_calchash __P((u_int8_t *)); 160static void vr_setmulti __P((struct vr_softc *)); 161static void vr_reset __P((struct vr_softc *)); 162static int vr_list_rx_init __P((struct vr_softc *)); 163static int vr_list_tx_init __P((struct vr_softc *)); 164 165#ifdef VR_USEIOSPACE 166#define VR_RES SYS_RES_IOPORT 167#define VR_RID VR_PCI_LOIO 168#else 169#define VR_RES SYS_RES_MEMORY 170#define VR_RID VR_PCI_LOMEM 171#endif 172 173static device_method_t vr_methods[] = { 174 /* Device interface */ 175 DEVMETHOD(device_probe, vr_probe), 176 DEVMETHOD(device_attach, vr_attach), 177 DEVMETHOD(device_detach, vr_detach), 178 DEVMETHOD(device_shutdown, vr_shutdown), 179 180 /* bus interface */ 181 DEVMETHOD(bus_print_child, bus_generic_print_child), 182 DEVMETHOD(bus_driver_added, bus_generic_driver_added), 183 184 /* MII interface */ 185 DEVMETHOD(miibus_readreg, vr_miibus_readreg), 186 DEVMETHOD(miibus_writereg, vr_miibus_writereg), 187 DEVMETHOD(miibus_statchg, vr_miibus_statchg), 188 189 { 0, 0 } 190}; 191 192static driver_t vr_driver = { 193 "vr", 194 vr_methods, 195 sizeof(struct vr_softc) 196}; 197 198static devclass_t vr_devclass; 199 200DRIVER_MODULE(if_vr, pci, vr_driver, vr_devclass, 0, 0); 201DRIVER_MODULE(miibus, vr, miibus_driver, miibus_devclass, 0, 0); 202 203#define VR_SETBIT(sc, reg, x) \ 204 CSR_WRITE_1(sc, reg, \ 205 CSR_READ_1(sc, reg) | x) 206 207#define VR_CLRBIT(sc, reg, x) \ 208 CSR_WRITE_1(sc, reg, \ 209 CSR_READ_1(sc, reg) & ~x) 210 211#define VR_SETBIT16(sc, reg, x) \ 212 CSR_WRITE_2(sc, reg, \ 213 CSR_READ_2(sc, reg) | x) 214 215#define VR_CLRBIT16(sc, reg, x) \ 216 CSR_WRITE_2(sc, reg, \ 217 CSR_READ_2(sc, reg) & ~x) 218 219#define VR_SETBIT32(sc, reg, x) \ 220 CSR_WRITE_4(sc, reg, \ 221 CSR_READ_4(sc, reg) | x) 222 223#define VR_CLRBIT32(sc, reg, x) \ 224 CSR_WRITE_4(sc, reg, \ 225 CSR_READ_4(sc, reg) & ~x) 226 227#define SIO_SET(x) \ 228 CSR_WRITE_1(sc, VR_MIICMD, \ 229 CSR_READ_1(sc, VR_MIICMD) | x) 230 231#define SIO_CLR(x) \ 232 CSR_WRITE_1(sc, VR_MIICMD, \ 233 CSR_READ_1(sc, VR_MIICMD) & ~x) 234 235/* 236 * Sync the PHYs by setting data bit and strobing the clock 32 times. 237 */ 238static void vr_mii_sync(sc) 239 struct vr_softc *sc; 240{ 241 register int i; 242 243 SIO_SET(VR_MIICMD_DIR|VR_MIICMD_DATAIN); 244 245 for (i = 0; i < 32; i++) { 246 SIO_SET(VR_MIICMD_CLK); 247 DELAY(1); 248 SIO_CLR(VR_MIICMD_CLK); 249 DELAY(1); 250 } 251 252 return; 253} 254 255/* 256 * Clock a series of bits through the MII. 257 */ 258static void vr_mii_send(sc, bits, cnt) 259 struct vr_softc *sc; 260 u_int32_t bits; 261 int cnt; 262{ 263 int i; 264 265 SIO_CLR(VR_MIICMD_CLK); 266 267 for (i = (0x1 << (cnt - 1)); i; i >>= 1) { 268 if (bits & i) { 269 SIO_SET(VR_MIICMD_DATAIN); 270 } else { 271 SIO_CLR(VR_MIICMD_DATAIN); 272 } 273 DELAY(1); 274 SIO_CLR(VR_MIICMD_CLK); 275 DELAY(1); 276 SIO_SET(VR_MIICMD_CLK); 277 } 278} 279 280/* 281 * Read an PHY register through the MII. 282 */ 283static int vr_mii_readreg(sc, frame) 284 struct vr_softc *sc; 285 struct vr_mii_frame *frame; 286 287{ 288 int i, ack, s; 289 290 s = splimp(); 291 292 /* 293 * Set up frame for RX. 294 */ 295 frame->mii_stdelim = VR_MII_STARTDELIM; 296 frame->mii_opcode = VR_MII_READOP; 297 frame->mii_turnaround = 0; 298 frame->mii_data = 0; 299 300 CSR_WRITE_1(sc, VR_MIICMD, 0); 301 VR_SETBIT(sc, VR_MIICMD, VR_MIICMD_DIRECTPGM); 302 303 /* 304 * Turn on data xmit. 305 */ 306 SIO_SET(VR_MIICMD_DIR); 307 308 vr_mii_sync(sc); 309 310 /* 311 * Send command/address info. 312 */ 313 vr_mii_send(sc, frame->mii_stdelim, 2); 314 vr_mii_send(sc, frame->mii_opcode, 2); 315 vr_mii_send(sc, frame->mii_phyaddr, 5); 316 vr_mii_send(sc, frame->mii_regaddr, 5); 317 318 /* Idle bit */ 319 SIO_CLR((VR_MIICMD_CLK|VR_MIICMD_DATAIN)); 320 DELAY(1); 321 SIO_SET(VR_MIICMD_CLK); 322 DELAY(1); 323 324 /* Turn off xmit. */ 325 SIO_CLR(VR_MIICMD_DIR); 326 327 /* Check for ack */ 328 SIO_CLR(VR_MIICMD_CLK); 329 DELAY(1); 330 SIO_SET(VR_MIICMD_CLK); 331 DELAY(1); 332 ack = CSR_READ_4(sc, VR_MIICMD) & VR_MIICMD_DATAOUT; 333 334 /* 335 * Now try reading data bits. If the ack failed, we still 336 * need to clock through 16 cycles to keep the PHY(s) in sync. 337 */ 338 if (ack) { 339 for(i = 0; i < 16; i++) { 340 SIO_CLR(VR_MIICMD_CLK); 341 DELAY(1); 342 SIO_SET(VR_MIICMD_CLK); 343 DELAY(1); 344 } 345 goto fail; 346 } 347 348 for (i = 0x8000; i; i >>= 1) { 349 SIO_CLR(VR_MIICMD_CLK); 350 DELAY(1); 351 if (!ack) { 352 if (CSR_READ_4(sc, VR_MIICMD) & VR_MIICMD_DATAOUT) 353 frame->mii_data |= i; 354 DELAY(1); 355 } 356 SIO_SET(VR_MIICMD_CLK); 357 DELAY(1); 358 } 359 360fail: 361 362 SIO_CLR(VR_MIICMD_CLK); 363 DELAY(1); 364 SIO_SET(VR_MIICMD_CLK); 365 DELAY(1); 366 367 splx(s); 368 369 if (ack) 370 return(1); 371 return(0); 372} 373 374/* 375 * Write to a PHY register through the MII. 376 */ 377static int vr_mii_writereg(sc, frame) 378 struct vr_softc *sc; 379 struct vr_mii_frame *frame; 380 381{ 382 int s; 383 384 s = splimp(); 385 386 CSR_WRITE_1(sc, VR_MIICMD, 0); 387 VR_SETBIT(sc, VR_MIICMD, VR_MIICMD_DIRECTPGM); 388 389 /* 390 * Set up frame for TX. 391 */ 392 393 frame->mii_stdelim = VR_MII_STARTDELIM; 394 frame->mii_opcode = VR_MII_WRITEOP; 395 frame->mii_turnaround = VR_MII_TURNAROUND; 396 397 /* 398 * Turn on data output. 399 */ 400 SIO_SET(VR_MIICMD_DIR); 401 402 vr_mii_sync(sc); 403 404 vr_mii_send(sc, frame->mii_stdelim, 2); 405 vr_mii_send(sc, frame->mii_opcode, 2); 406 vr_mii_send(sc, frame->mii_phyaddr, 5); 407 vr_mii_send(sc, frame->mii_regaddr, 5); 408 vr_mii_send(sc, frame->mii_turnaround, 2); 409 vr_mii_send(sc, frame->mii_data, 16); 410 411 /* Idle bit. */ 412 SIO_SET(VR_MIICMD_CLK); 413 DELAY(1); 414 SIO_CLR(VR_MIICMD_CLK); 415 DELAY(1); 416 417 /* 418 * Turn off xmit. 419 */ 420 SIO_CLR(VR_MIICMD_DIR); 421 422 splx(s); 423 424 return(0); 425} 426 427static int vr_miibus_readreg(dev, phy, reg) 428 device_t dev; 429 int phy, reg; 430{ 431 struct vr_softc *sc; 432 struct vr_mii_frame frame; 433 434 sc = device_get_softc(dev); 435 bzero((char *)&frame, sizeof(frame)); 436 437 frame.mii_phyaddr = phy; 438 frame.mii_regaddr = reg; 439 vr_mii_readreg(sc, &frame); 440 441 return(frame.mii_data); 442} 443 444static int vr_miibus_writereg(dev, phy, reg, data) 445 device_t dev; 446 u_int16_t phy, reg, data; 447{ 448 struct vr_softc *sc; 449 struct vr_mii_frame frame; 450 451 sc = device_get_softc(dev); 452 bzero((char *)&frame, sizeof(frame)); 453 454 frame.mii_phyaddr = phy; 455 frame.mii_regaddr = reg; 456 frame.mii_data = data; 457 458 vr_mii_writereg(sc, &frame); 459 460 return(0); 461} 462 463static void vr_miibus_statchg(dev) 464 device_t dev; 465{ 466 struct vr_softc *sc; 467 struct mii_data *mii; 468 469 sc = device_get_softc(dev); 470 mii = device_get_softc(sc->vr_miibus); 471 vr_setcfg(sc, mii->mii_media_active); 472 473 return; 474} 475 476/* 477 * Calculate CRC of a multicast group address, return the lower 6 bits. 478 */ 479static u_int8_t vr_calchash(addr) 480 u_int8_t *addr; 481{ 482 u_int32_t crc, carry; 483 int i, j; 484 u_int8_t c; 485 486 /* Compute CRC for the address value. */ 487 crc = 0xFFFFFFFF; /* initial value */ 488 489 for (i = 0; i < 6; i++) { 490 c = *(addr + i); 491 for (j = 0; j < 8; j++) { 492 carry = ((crc & 0x80000000) ? 1 : 0) ^ (c & 0x01); 493 crc <<= 1; 494 c >>= 1; 495 if (carry) 496 crc = (crc ^ 0x04c11db6) | carry; 497 } 498 } 499 500 /* return the filter bit position */ 501 return((crc >> 26) & 0x0000003F); 502} 503 504/* 505 * Program the 64-bit multicast hash filter. 506 */ 507static void vr_setmulti(sc) 508 struct vr_softc *sc; 509{ 510 struct ifnet *ifp; 511 int h = 0; 512 u_int32_t hashes[2] = { 0, 0 }; 513 struct ifmultiaddr *ifma; 514 u_int8_t rxfilt; 515 int mcnt = 0; 516 517 ifp = &sc->arpcom.ac_if; 518 519 rxfilt = CSR_READ_1(sc, VR_RXCFG); 520 521 if (ifp->if_flags & IFF_ALLMULTI || ifp->if_flags & IFF_PROMISC) { 522 rxfilt |= VR_RXCFG_RX_MULTI; 523 CSR_WRITE_1(sc, VR_RXCFG, rxfilt); 524 CSR_WRITE_4(sc, VR_MAR0, 0xFFFFFFFF); 525 CSR_WRITE_4(sc, VR_MAR1, 0xFFFFFFFF); 526 return; 527 } 528 529 /* first, zot all the existing hash bits */ 530 CSR_WRITE_4(sc, VR_MAR0, 0); 531 CSR_WRITE_4(sc, VR_MAR1, 0); 532 533 /* now program new ones */ 534 for (ifma = ifp->if_multiaddrs.lh_first; ifma != NULL; 535 ifma = ifma->ifma_link.le_next) { 536 if (ifma->ifma_addr->sa_family != AF_LINK) 537 continue; 538 h = vr_calchash(LLADDR((struct sockaddr_dl *)ifma->ifma_addr)); 539 if (h < 32) 540 hashes[0] |= (1 << h); 541 else 542 hashes[1] |= (1 << (h - 32)); 543 mcnt++; 544 } 545 546 if (mcnt) 547 rxfilt |= VR_RXCFG_RX_MULTI; 548 else 549 rxfilt &= ~VR_RXCFG_RX_MULTI; 550 551 CSR_WRITE_4(sc, VR_MAR0, hashes[0]); 552 CSR_WRITE_4(sc, VR_MAR1, hashes[1]); 553 CSR_WRITE_1(sc, VR_RXCFG, rxfilt); 554 555 return; 556} 557 558/* 559 * In order to fiddle with the 560 * 'full-duplex' and '100Mbps' bits in the netconfig register, we 561 * first have to put the transmit and/or receive logic in the idle state. 562 */ 563static void vr_setcfg(sc, media) 564 struct vr_softc *sc; 565 int media; 566{ 567 int restart = 0; 568 569 if (CSR_READ_2(sc, VR_COMMAND) & (VR_CMD_TX_ON|VR_CMD_RX_ON)) { 570 restart = 1; 571 VR_CLRBIT16(sc, VR_COMMAND, (VR_CMD_TX_ON|VR_CMD_RX_ON)); 572 } 573 574 if ((media & IFM_GMASK) == IFM_FDX) 575 VR_SETBIT16(sc, VR_COMMAND, VR_CMD_FULLDUPLEX); 576 else 577 VR_CLRBIT16(sc, VR_COMMAND, VR_CMD_FULLDUPLEX); 578 579 if (restart) 580 VR_SETBIT16(sc, VR_COMMAND, VR_CMD_TX_ON|VR_CMD_RX_ON); 581 582 return; 583} 584 585static void vr_reset(sc) 586 struct vr_softc *sc; 587{ 588 register int i; 589 590 VR_SETBIT16(sc, VR_COMMAND, VR_CMD_RESET); 591 592 for (i = 0; i < VR_TIMEOUT; i++) { 593 DELAY(10); 594 if (!(CSR_READ_2(sc, VR_COMMAND) & VR_CMD_RESET)) 595 break; 596 } 597 if (i == VR_TIMEOUT) 598 printf("vr%d: reset never completed!\n", sc->vr_unit); 599 600 /* Wait a little while for the chip to get its brains in order. */ 601 DELAY(1000); 602 603 return; 604} 605 606/* 607 * Probe for a VIA Rhine chip. Check the PCI vendor and device 608 * IDs against our list and return a device name if we find a match. 609 */ 610static int vr_probe(dev) 611 device_t dev; 612{ 613 struct vr_type *t; 614 615 t = vr_devs; 616 617 while(t->vr_name != NULL) { 618 if ((pci_get_vendor(dev) == t->vr_vid) && 619 (pci_get_device(dev) == t->vr_did)) { 620 device_set_desc(dev, t->vr_name); 621 return(0); 622 } 623 t++; 624 } 625 626 return(ENXIO); 627} 628 629/* 630 * Attach the interface. Allocate softc structures, do ifmedia 631 * setup and ethernet/BPF attach. 632 */ 633static int vr_attach(dev) 634 device_t dev; 635{ 636 int i, s; 637 u_char eaddr[ETHER_ADDR_LEN]; 638 u_int32_t command; 639 struct vr_softc *sc; 640 struct ifnet *ifp; 641 int unit, error = 0, rid; 642 643 s = splimp(); 644 645 sc = device_get_softc(dev); 646 unit = device_get_unit(dev); 647 bzero(sc, sizeof(struct vr_softc *)); 648 649 /* 650 * Handle power management nonsense. 651 */ 652 653 command = pci_read_config(dev, VR_PCI_CAPID, 4) & 0x000000FF; 654 if (command == 0x01) { 655 656 command = pci_read_config(dev, VR_PCI_PWRMGMTCTRL, 4); 657 if (command & VR_PSTATE_MASK) { 658 u_int32_t iobase, membase, irq; 659 660 /* Save important PCI config data. */ 661 iobase = pci_read_config(dev, VR_PCI_LOIO, 4); 662 membase = pci_read_config(dev, VR_PCI_LOMEM, 4); 663 irq = pci_read_config(dev, VR_PCI_INTLINE, 4); 664 665 /* Reset the power state. */ 666 printf("vr%d: chip is in D%d power mode " 667 "-- setting to D0\n", unit, command & VR_PSTATE_MASK); 668 command &= 0xFFFFFFFC; 669 pci_write_config(dev, VR_PCI_PWRMGMTCTRL, command, 4); 670 671 /* Restore PCI config data. */ 672 pci_write_config(dev, VR_PCI_LOIO, iobase, 4); 673 pci_write_config(dev, VR_PCI_LOMEM, membase, 4); 674 pci_write_config(dev, VR_PCI_INTLINE, irq, 4); 675 } 676 } 677 678 /* 679 * Map control/status registers. 680 */ 681 command = pci_read_config(dev, PCIR_COMMAND, 4); 682 command |= (PCIM_CMD_PORTEN|PCIM_CMD_MEMEN|PCIM_CMD_BUSMASTEREN); 683 pci_write_config(dev, PCIR_COMMAND, command, 4); 684 command = pci_read_config(dev, PCIR_COMMAND, 4); 685 686#ifdef VR_USEIOSPACE 687 if (!(command & PCIM_CMD_PORTEN)) { 688 printf("vr%d: failed to enable I/O ports!\n", unit); 689 free(sc, M_DEVBUF); 690 goto fail; 691 } 692#else 693 if (!(command & PCIM_CMD_MEMEN)) { 694 printf("vr%d: failed to enable memory mapping!\n", unit); 695 goto fail; 696 } 697#endif 698 699 rid = VR_RID; 700 sc->vr_res = bus_alloc_resource(dev, VR_RES, &rid, 701 0, ~0, 1, RF_ACTIVE); 702 703 if (sc->vr_res == NULL) { 704 printf("vr%d: couldn't map ports/memory\n", unit); 705 error = ENXIO; 706 goto fail; 707 } 708 709 sc->vr_btag = rman_get_bustag(sc->vr_res); 710 sc->vr_bhandle = rman_get_bushandle(sc->vr_res); 711 712 /* Allocate interrupt */ 713 rid = 0; 714 sc->vr_irq = bus_alloc_resource(dev, SYS_RES_IRQ, &rid, 0, ~0, 1, 715 RF_SHAREABLE | RF_ACTIVE); 716 717 if (sc->vr_irq == NULL) { 718 printf("vr%d: couldn't map interrupt\n", unit); 719 bus_release_resource(dev, VR_RES, VR_RID, sc->vr_res); 720 error = ENXIO; 721 goto fail; 722 } 723 724 error = bus_setup_intr(dev, sc->vr_irq, INTR_TYPE_NET, 725 vr_intr, sc, &sc->vr_intrhand); 726 727 if (error) { 728 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->vr_irq); 729 bus_release_resource(dev, VR_RES, VR_RID, sc->vr_res); 730 printf("vr%d: couldn't set up irq\n", unit); 731 goto fail; 732 } 733 734 /* Reset the adapter. */ 735 vr_reset(sc); 736 737 /* 738 * Get station address. The way the Rhine chips work, 739 * you're not allowed to directly access the EEPROM once 740 * they've been programmed a special way. Consequently, 741 * we need to read the node address from the PAR0 and PAR1 742 * registers. 743 */ 744 VR_SETBIT(sc, VR_EECSR, VR_EECSR_LOAD); 745 DELAY(200); 746 for (i = 0; i < ETHER_ADDR_LEN; i++) 747 eaddr[i] = CSR_READ_1(sc, VR_PAR0 + i); 748 749 /* 750 * A Rhine chip was detected. Inform the world. 751 */ 752 printf("vr%d: Ethernet address: %6D\n", unit, eaddr, ":"); 753 754 sc->vr_unit = unit; 755 bcopy(eaddr, (char *)&sc->arpcom.ac_enaddr, ETHER_ADDR_LEN); 756 757 sc->vr_ldata = contigmalloc(sizeof(struct vr_list_data), M_DEVBUF, 758 M_NOWAIT, 0, 0xffffffff, PAGE_SIZE, 0); 759 760 if (sc->vr_ldata == NULL) { 761 printf("vr%d: no memory for list buffers!\n", unit); 762 bus_teardown_intr(dev, sc->vr_irq, sc->vr_intrhand); 763 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->vr_irq); 764 bus_release_resource(dev, VR_RES, VR_RID, sc->vr_res); 765 error = ENXIO; 766 goto fail; 767 } 768 769 bzero(sc->vr_ldata, sizeof(struct vr_list_data)); 770 771 ifp = &sc->arpcom.ac_if; 772 ifp->if_softc = sc; 773 ifp->if_unit = unit; 774 ifp->if_name = "vr"; 775 ifp->if_mtu = ETHERMTU; 776 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 777 ifp->if_ioctl = vr_ioctl; 778 ifp->if_output = ether_output; 779 ifp->if_start = vr_start; 780 ifp->if_watchdog = vr_watchdog; 781 ifp->if_init = vr_init; 782 ifp->if_baudrate = 10000000; 783 ifp->if_snd.ifq_maxlen = VR_TX_LIST_CNT - 1; 784 785 /* 786 * Do MII setup. 787 */ 788 if (mii_phy_probe(dev, &sc->vr_miibus, 789 vr_ifmedia_upd, vr_ifmedia_sts)) { 790 printf("vr%d: MII without any phy!\n", sc->vr_unit); 791 bus_teardown_intr(dev, sc->vr_irq, sc->vr_intrhand); 792 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->vr_irq); 793 bus_release_resource(dev, VR_RES, VR_RID, sc->vr_res); 794 contigfree(sc->vr_ldata, 795 sizeof(struct vr_list_data), M_DEVBUF); 796 error = ENXIO; 797 goto fail; 798 } 799 800 callout_handle_init(&sc->vr_stat_ch); 801 802 /* 803 * Call MI attach routines. 804 */ 805 if_attach(ifp); 806 ether_ifattach(ifp); 807 808 bpfattach(ifp, DLT_EN10MB, sizeof(struct ether_header)); 809 810fail: 811 splx(s); 812 return(error); 813} 814 815static int vr_detach(dev) 816 device_t dev; 817{ 818 struct vr_softc *sc; 819 struct ifnet *ifp; 820 int s; 821 822 s = splimp(); 823 824 sc = device_get_softc(dev); 825 ifp = &sc->arpcom.ac_if; 826 827 vr_stop(sc); 828 if_detach(ifp); 829 830 bus_generic_detach(dev); 831 device_delete_child(dev, sc->vr_miibus); 832 833 bus_teardown_intr(dev, sc->vr_irq, sc->vr_intrhand); 834 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->vr_irq); 835 bus_release_resource(dev, VR_RES, VR_RID, sc->vr_res); 836 837 contigfree(sc->vr_ldata, sizeof(struct vr_list_data), M_DEVBUF); 838 839 splx(s); 840 841 return(0); 842} 843 844/* 845 * Initialize the transmit descriptors. 846 */ 847static int vr_list_tx_init(sc) 848 struct vr_softc *sc; 849{ 850 struct vr_chain_data *cd; 851 struct vr_list_data *ld; 852 int i; 853 854 cd = &sc->vr_cdata; 855 ld = sc->vr_ldata; 856 for (i = 0; i < VR_TX_LIST_CNT; i++) { 857 cd->vr_tx_chain[i].vr_ptr = &ld->vr_tx_list[i]; 858 if (i == (VR_TX_LIST_CNT - 1)) 859 cd->vr_tx_chain[i].vr_nextdesc = 860 &cd->vr_tx_chain[0]; 861 else 862 cd->vr_tx_chain[i].vr_nextdesc = 863 &cd->vr_tx_chain[i + 1]; 864 } 865 866 cd->vr_tx_free = &cd->vr_tx_chain[0]; 867 cd->vr_tx_tail = cd->vr_tx_head = NULL; 868 869 return(0); 870} 871 872 873/* 874 * Initialize the RX descriptors and allocate mbufs for them. Note that 875 * we arrange the descriptors in a closed ring, so that the last descriptor 876 * points back to the first. 877 */ 878static int vr_list_rx_init(sc) 879 struct vr_softc *sc; 880{ 881 struct vr_chain_data *cd; 882 struct vr_list_data *ld; 883 int i; 884 885 cd = &sc->vr_cdata; 886 ld = sc->vr_ldata; 887 888 for (i = 0; i < VR_RX_LIST_CNT; i++) { 889 cd->vr_rx_chain[i].vr_ptr = 890 (struct vr_desc *)&ld->vr_rx_list[i]; 891 if (vr_newbuf(sc, &cd->vr_rx_chain[i], NULL) == ENOBUFS) 892 return(ENOBUFS); 893 if (i == (VR_RX_LIST_CNT - 1)) { 894 cd->vr_rx_chain[i].vr_nextdesc = 895 &cd->vr_rx_chain[0]; 896 ld->vr_rx_list[i].vr_next = 897 vtophys(&ld->vr_rx_list[0]); 898 } else { 899 cd->vr_rx_chain[i].vr_nextdesc = 900 &cd->vr_rx_chain[i + 1]; 901 ld->vr_rx_list[i].vr_next = 902 vtophys(&ld->vr_rx_list[i + 1]); 903 } 904 } 905 906 cd->vr_rx_head = &cd->vr_rx_chain[0]; 907 908 return(0); 909} 910 911/* 912 * Initialize an RX descriptor and attach an MBUF cluster. 913 * Note: the length fields are only 11 bits wide, which means the 914 * largest size we can specify is 2047. This is important because 915 * MCLBYTES is 2048, so we have to subtract one otherwise we'll 916 * overflow the field and make a mess. 917 */ 918static int vr_newbuf(sc, c, m) 919 struct vr_softc *sc; 920 struct vr_chain_onefrag *c; 921 struct mbuf *m; 922{ 923 struct mbuf *m_new = NULL; 924 925 if (m == NULL) { 926 MGETHDR(m_new, M_DONTWAIT, MT_DATA); 927 if (m_new == NULL) { 928 printf("vr%d: no memory for rx list " 929 "-- packet dropped!\n", sc->vr_unit); 930 return(ENOBUFS); 931 } 932 933 MCLGET(m_new, M_DONTWAIT); 934 if (!(m_new->m_flags & M_EXT)) { 935 printf("vr%d: no memory for rx list " 936 "-- packet dropped!\n", sc->vr_unit); 937 m_freem(m_new); 938 return(ENOBUFS); 939 } 940 m_new->m_len = m_new->m_pkthdr.len = MCLBYTES; 941 } else { 942 m_new = m; 943 m_new->m_len = m_new->m_pkthdr.len = MCLBYTES; 944 m_new->m_data = m_new->m_ext.ext_buf; 945 } 946 947 m_adj(m_new, sizeof(u_int64_t)); 948 949 c->vr_mbuf = m_new; 950 c->vr_ptr->vr_status = VR_RXSTAT; 951 c->vr_ptr->vr_data = vtophys(mtod(m_new, caddr_t)); 952 c->vr_ptr->vr_ctl = VR_RXCTL | VR_RXLEN; 953 954 return(0); 955} 956 957/* 958 * A frame has been uploaded: pass the resulting mbuf chain up to 959 * the higher level protocols. 960 */ 961static void vr_rxeof(sc) 962 struct vr_softc *sc; 963{ 964 struct ether_header *eh; 965 struct mbuf *m; 966 struct ifnet *ifp; 967 struct vr_chain_onefrag *cur_rx; 968 int total_len = 0; 969 u_int32_t rxstat; 970 971 ifp = &sc->arpcom.ac_if; 972 973 while(!((rxstat = sc->vr_cdata.vr_rx_head->vr_ptr->vr_status) & 974 VR_RXSTAT_OWN)) { 975 struct mbuf *m0 = NULL; 976 977 cur_rx = sc->vr_cdata.vr_rx_head; 978 sc->vr_cdata.vr_rx_head = cur_rx->vr_nextdesc; 979 m = cur_rx->vr_mbuf; 980 981 /* 982 * If an error occurs, update stats, clear the 983 * status word and leave the mbuf cluster in place: 984 * it should simply get re-used next time this descriptor 985 * comes up in the ring. 986 */ 987 if (rxstat & VR_RXSTAT_RXERR) { 988 ifp->if_ierrors++; 989 printf("vr%d: rx error: ", sc->vr_unit); 990 switch(rxstat & 0x000000FF) { 991 case VR_RXSTAT_CRCERR: 992 printf("crc error\n"); 993 break; 994 case VR_RXSTAT_FRAMEALIGNERR: 995 printf("frame alignment error\n"); 996 break; 997 case VR_RXSTAT_FIFOOFLOW: 998 printf("FIFO overflow\n"); 999 break; 1000 case VR_RXSTAT_GIANT: 1001 printf("received giant packet\n"); 1002 break; 1003 case VR_RXSTAT_RUNT: 1004 printf("received runt packet\n"); 1005 break; 1006 case VR_RXSTAT_BUSERR: 1007 printf("system bus error\n"); 1008 break; 1009 case VR_RXSTAT_BUFFERR: 1010 printf("rx buffer error\n"); 1011 break; 1012 default: 1013 printf("unknown rx error\n"); 1014 break; 1015 } 1016 vr_newbuf(sc, cur_rx, m); 1017 continue; 1018 } 1019 1020 /* No errors; receive the packet. */ 1021 total_len = VR_RXBYTES(cur_rx->vr_ptr->vr_status); 1022 1023 /* 1024 * XXX The VIA Rhine chip includes the CRC with every 1025 * received frame, and there's no way to turn this 1026 * behavior off (at least, I can't find anything in 1027 * the manual that explains how to do it) so we have 1028 * to trim off the CRC manually. 1029 */ 1030 total_len -= ETHER_CRC_LEN; 1031 1032 m0 = m_devget(mtod(m, char *) - ETHER_ALIGN, 1033 total_len + ETHER_ALIGN, 0, ifp, NULL); 1034 vr_newbuf(sc, cur_rx, m); 1035 if (m0 == NULL) { 1036 ifp->if_ierrors++; 1037 continue; 1038 } 1039 m_adj(m0, ETHER_ALIGN); 1040 m = m0; 1041 1042 ifp->if_ipackets++; 1043 eh = mtod(m, struct ether_header *); 1044 1045 /* Remove header from mbuf and pass it on. */ 1046 m_adj(m, sizeof(struct ether_header)); 1047 ether_input(ifp, eh, m); 1048 } 1049 1050 return; 1051} 1052 1053void vr_rxeoc(sc) 1054 struct vr_softc *sc; 1055{ 1056 1057 vr_rxeof(sc); 1058 VR_CLRBIT16(sc, VR_COMMAND, VR_CMD_RX_ON); 1059 CSR_WRITE_4(sc, VR_RXADDR, vtophys(sc->vr_cdata.vr_rx_head->vr_ptr)); 1060 VR_SETBIT16(sc, VR_COMMAND, VR_CMD_RX_ON); 1061 VR_SETBIT16(sc, VR_COMMAND, VR_CMD_RX_GO); 1062 1063 return; 1064} 1065 1066/* 1067 * A frame was downloaded to the chip. It's safe for us to clean up 1068 * the list buffers. 1069 */ 1070 1071static void vr_txeof(sc) 1072 struct vr_softc *sc; 1073{ 1074 struct vr_chain *cur_tx; 1075 struct ifnet *ifp; 1076 1077 ifp = &sc->arpcom.ac_if; 1078 1079 /* Clear the timeout timer. */ 1080 ifp->if_timer = 0; 1081 1082 /* Sanity check. */ 1083 if (sc->vr_cdata.vr_tx_head == NULL) 1084 return; 1085 1086 /* 1087 * Go through our tx list and free mbufs for those 1088 * frames that have been transmitted. 1089 */ 1090 while(sc->vr_cdata.vr_tx_head->vr_mbuf != NULL) { 1091 u_int32_t txstat; 1092 1093 cur_tx = sc->vr_cdata.vr_tx_head; 1094 txstat = cur_tx->vr_ptr->vr_status; 1095 1096 if (txstat & VR_TXSTAT_OWN) 1097 break; 1098 1099 if (txstat & VR_TXSTAT_ERRSUM) { 1100 ifp->if_oerrors++; 1101 if (txstat & VR_TXSTAT_DEFER) 1102 ifp->if_collisions++; 1103 if (txstat & VR_TXSTAT_LATECOLL) 1104 ifp->if_collisions++; 1105 } 1106 1107 ifp->if_collisions +=(txstat & VR_TXSTAT_COLLCNT) >> 3; 1108 1109 ifp->if_opackets++; 1110 if (cur_tx->vr_mbuf != NULL) { 1111 m_freem(cur_tx->vr_mbuf); 1112 cur_tx->vr_mbuf = NULL; 1113 } 1114 1115 if (sc->vr_cdata.vr_tx_head == sc->vr_cdata.vr_tx_tail) { 1116 sc->vr_cdata.vr_tx_head = NULL; 1117 sc->vr_cdata.vr_tx_tail = NULL; 1118 break; 1119 } 1120 1121 sc->vr_cdata.vr_tx_head = cur_tx->vr_nextdesc; 1122 } 1123 1124 return; 1125} 1126 1127/* 1128 * TX 'end of channel' interrupt handler. 1129 */ 1130static void vr_txeoc(sc) 1131 struct vr_softc *sc; 1132{ 1133 struct ifnet *ifp; 1134 1135 ifp = &sc->arpcom.ac_if; 1136 1137 ifp->if_timer = 0; 1138 1139 if (sc->vr_cdata.vr_tx_head == NULL) { 1140 ifp->if_flags &= ~IFF_OACTIVE; 1141 sc->vr_cdata.vr_tx_tail = NULL; 1142 } 1143 1144 return; 1145} 1146 1147static void vr_tick(xsc) 1148 void *xsc; 1149{ 1150 struct vr_softc *sc; 1151 struct mii_data *mii; 1152 int s; 1153 1154 s = splimp(); 1155 1156 sc = xsc; 1157 mii = device_get_softc(sc->vr_miibus); 1158 mii_tick(mii); 1159 1160 sc->vr_stat_ch = timeout(vr_tick, sc, hz); 1161 1162 splx(s); 1163 1164 return; 1165} 1166 1167static void vr_intr(arg) 1168 void *arg; 1169{ 1170 struct vr_softc *sc; 1171 struct ifnet *ifp; 1172 u_int16_t status; 1173 1174 sc = arg; 1175 ifp = &sc->arpcom.ac_if; 1176 1177 /* Supress unwanted interrupts. */ 1178 if (!(ifp->if_flags & IFF_UP)) { 1179 vr_stop(sc); 1180 return; 1181 } 1182 1183 /* Disable interrupts. */ 1184 CSR_WRITE_2(sc, VR_IMR, 0x0000); 1185 1186 for (;;) { 1187 1188 status = CSR_READ_2(sc, VR_ISR); 1189 if (status) 1190 CSR_WRITE_2(sc, VR_ISR, status); 1191 1192 if ((status & VR_INTRS) == 0) 1193 break; 1194 1195 if (status & VR_ISR_RX_OK) 1196 vr_rxeof(sc); 1197 1198 if ((status & VR_ISR_RX_ERR) || (status & VR_ISR_RX_NOBUF) || 1199 (status & VR_ISR_RX_NOBUF) || (status & VR_ISR_RX_OFLOW) || 1200 (status & VR_ISR_RX_DROPPED)) { 1201 vr_rxeof(sc); 1202 vr_rxeoc(sc); 1203 } 1204 1205 if (status & VR_ISR_TX_OK) { 1206 vr_txeof(sc); 1207 vr_txeoc(sc); 1208 } 1209 1210 if ((status & VR_ISR_TX_UNDERRUN)||(status & VR_ISR_TX_ABRT)){ 1211 ifp->if_oerrors++; 1212 vr_txeof(sc); 1213 if (sc->vr_cdata.vr_tx_head != NULL) { 1214 VR_SETBIT16(sc, VR_COMMAND, VR_CMD_TX_ON); 1215 VR_SETBIT16(sc, VR_COMMAND, VR_CMD_TX_GO); 1216 } 1217 } 1218 1219 if (status & VR_ISR_BUSERR) { 1220 vr_reset(sc); 1221 vr_init(sc); 1222 } 1223 } 1224 1225 /* Re-enable interrupts. */ 1226 CSR_WRITE_2(sc, VR_IMR, VR_INTRS); 1227 1228 if (ifp->if_snd.ifq_head != NULL) { 1229 vr_start(ifp); 1230 } 1231 1232 return; 1233} 1234 1235/* 1236 * Encapsulate an mbuf chain in a descriptor by coupling the mbuf data 1237 * pointers to the fragment pointers. 1238 */ 1239static int vr_encap(sc, c, m_head) 1240 struct vr_softc *sc; 1241 struct vr_chain *c; 1242 struct mbuf *m_head; 1243{ 1244 int frag = 0; 1245 struct vr_desc *f = NULL; 1246 int total_len; 1247 struct mbuf *m; 1248 1249 m = m_head; 1250 total_len = 0; 1251 1252 /* 1253 * The VIA Rhine wants packet buffers to be longword 1254 * aligned, but very often our mbufs aren't. Rather than 1255 * waste time trying to decide when to copy and when not 1256 * to copy, just do it all the time. 1257 */ 1258 if (m != NULL) { 1259 struct mbuf *m_new = NULL; 1260 1261 MGETHDR(m_new, M_DONTWAIT, MT_DATA); 1262 if (m_new == NULL) { 1263 printf("vr%d: no memory for tx list", sc->vr_unit); 1264 return(1); 1265 } 1266 if (m_head->m_pkthdr.len > MHLEN) { 1267 MCLGET(m_new, M_DONTWAIT); 1268 if (!(m_new->m_flags & M_EXT)) { 1269 m_freem(m_new); 1270 printf("vr%d: no memory for tx list", 1271 sc->vr_unit); 1272 return(1); 1273 } 1274 } 1275 m_copydata(m_head, 0, m_head->m_pkthdr.len, 1276 mtod(m_new, caddr_t)); 1277 m_new->m_pkthdr.len = m_new->m_len = m_head->m_pkthdr.len; 1278 m_freem(m_head); 1279 m_head = m_new; 1280 /* 1281 * The Rhine chip doesn't auto-pad, so we have to make 1282 * sure to pad short frames out to the minimum frame length 1283 * ourselves. 1284 */ 1285 if (m_head->m_len < VR_MIN_FRAMELEN) { 1286 m_new->m_pkthdr.len += VR_MIN_FRAMELEN - m_new->m_len; 1287 m_new->m_len = m_new->m_pkthdr.len; 1288 } 1289 f = c->vr_ptr; 1290 f->vr_data = vtophys(mtod(m_new, caddr_t)); 1291 f->vr_ctl = total_len = m_new->m_len; 1292 f->vr_ctl |= VR_TXCTL_TLINK|VR_TXCTL_FIRSTFRAG; 1293 f->vr_status = 0; 1294 frag = 1; 1295 } 1296 1297 c->vr_mbuf = m_head; 1298 c->vr_ptr->vr_ctl |= VR_TXCTL_LASTFRAG|VR_TXCTL_FINT; 1299 c->vr_ptr->vr_next = vtophys(c->vr_nextdesc->vr_ptr); 1300 1301 return(0); 1302} 1303 1304/* 1305 * Main transmit routine. To avoid having to do mbuf copies, we put pointers 1306 * to the mbuf data regions directly in the transmit lists. We also save a 1307 * copy of the pointers since the transmit list fragment pointers are 1308 * physical addresses. 1309 */ 1310 1311static void vr_start(ifp) 1312 struct ifnet *ifp; 1313{ 1314 struct vr_softc *sc; 1315 struct mbuf *m_head = NULL; 1316 struct vr_chain *cur_tx = NULL, *start_tx; 1317 1318 sc = ifp->if_softc; 1319 1320 if (ifp->if_flags & IFF_OACTIVE) 1321 return; 1322 1323 /* 1324 * Check for an available queue slot. If there are none, 1325 * punt. 1326 */ 1327 if (sc->vr_cdata.vr_tx_free->vr_mbuf != NULL) { 1328 ifp->if_flags |= IFF_OACTIVE; 1329 return; 1330 } 1331 1332 start_tx = sc->vr_cdata.vr_tx_free; 1333 1334 while(sc->vr_cdata.vr_tx_free->vr_mbuf == NULL) { 1335 IF_DEQUEUE(&ifp->if_snd, m_head); 1336 if (m_head == NULL) 1337 break; 1338 1339 /* Pick a descriptor off the free list. */ 1340 cur_tx = sc->vr_cdata.vr_tx_free; 1341 sc->vr_cdata.vr_tx_free = cur_tx->vr_nextdesc; 1342 1343 /* Pack the data into the descriptor. */ 1344 vr_encap(sc, cur_tx, m_head); 1345 1346 if (cur_tx != start_tx) 1347 VR_TXOWN(cur_tx) = VR_TXSTAT_OWN; 1348 1349 /* 1350 * If there's a BPF listener, bounce a copy of this frame 1351 * to him. 1352 */ 1353 if (ifp->if_bpf) 1354 bpf_mtap(ifp, cur_tx->vr_mbuf); 1355 1356 VR_TXOWN(cur_tx) = VR_TXSTAT_OWN; 1357 VR_SETBIT16(sc, VR_COMMAND, /*VR_CMD_TX_ON|*/VR_CMD_TX_GO); 1358 } 1359 1360 /* 1361 * If there are no frames queued, bail. 1362 */ 1363 if (cur_tx == NULL) 1364 return; 1365 1366 sc->vr_cdata.vr_tx_tail = cur_tx; 1367 1368 if (sc->vr_cdata.vr_tx_head == NULL) 1369 sc->vr_cdata.vr_tx_head = start_tx; 1370 1371 /* 1372 * Set a timeout in case the chip goes out to lunch. 1373 */ 1374 ifp->if_timer = 5; 1375 1376 return; 1377} 1378 1379static void vr_init(xsc) 1380 void *xsc; 1381{ 1382 struct vr_softc *sc = xsc; 1383 struct ifnet *ifp = &sc->arpcom.ac_if; 1384 struct mii_data *mii; 1385 int s; 1386 1387 s = splimp(); 1388 1389 mii = device_get_softc(sc->vr_miibus); 1390 1391 /* 1392 * Cancel pending I/O and free all RX/TX buffers. 1393 */ 1394 vr_stop(sc); 1395 vr_reset(sc); 1396 1397 VR_CLRBIT(sc, VR_RXCFG, VR_RXCFG_RX_THRESH); 1398 VR_SETBIT(sc, VR_RXCFG, VR_RXTHRESH_STORENFWD); 1399 1400 VR_CLRBIT(sc, VR_TXCFG, VR_TXCFG_TX_THRESH); 1401 VR_SETBIT(sc, VR_TXCFG, VR_TXTHRESH_STORENFWD); 1402 1403 /* Init circular RX list. */ 1404 if (vr_list_rx_init(sc) == ENOBUFS) { 1405 printf("vr%d: initialization failed: no " 1406 "memory for rx buffers\n", sc->vr_unit); 1407 vr_stop(sc); 1408 (void)splx(s); 1409 return; 1410 } 1411 1412 /* 1413 * Init tx descriptors. 1414 */ 1415 vr_list_tx_init(sc); 1416 1417 /* If we want promiscuous mode, set the allframes bit. */ 1418 if (ifp->if_flags & IFF_PROMISC) 1419 VR_SETBIT(sc, VR_RXCFG, VR_RXCFG_RX_PROMISC); 1420 else 1421 VR_CLRBIT(sc, VR_RXCFG, VR_RXCFG_RX_PROMISC); 1422 1423 /* Set capture broadcast bit to capture broadcast frames. */ 1424 if (ifp->if_flags & IFF_BROADCAST) 1425 VR_SETBIT(sc, VR_RXCFG, VR_RXCFG_RX_BROAD); 1426 else 1427 VR_CLRBIT(sc, VR_RXCFG, VR_RXCFG_RX_BROAD); 1428 1429 /* 1430 * Program the multicast filter, if necessary. 1431 */ 1432 vr_setmulti(sc); 1433 1434 /* 1435 * Load the address of the RX list. 1436 */ 1437 CSR_WRITE_4(sc, VR_RXADDR, vtophys(sc->vr_cdata.vr_rx_head->vr_ptr)); 1438 1439 /* Enable receiver and transmitter. */ 1440 CSR_WRITE_2(sc, VR_COMMAND, VR_CMD_TX_NOPOLL|VR_CMD_START| 1441 VR_CMD_TX_ON|VR_CMD_RX_ON| 1442 VR_CMD_RX_GO); 1443 1444 CSR_WRITE_4(sc, VR_TXADDR, vtophys(&sc->vr_ldata->vr_tx_list[0])); 1445 1446 /* 1447 * Enable interrupts. 1448 */ 1449 CSR_WRITE_2(sc, VR_ISR, 0xFFFF); 1450 CSR_WRITE_2(sc, VR_IMR, VR_INTRS); 1451 1452 mii_mediachg(mii); 1453 1454 ifp->if_flags |= IFF_RUNNING; 1455 ifp->if_flags &= ~IFF_OACTIVE; 1456 1457 (void)splx(s); 1458 1459 sc->vr_stat_ch = timeout(vr_tick, sc, hz); 1460 1461 return; 1462} 1463 1464/* 1465 * Set media options. 1466 */ 1467static int vr_ifmedia_upd(ifp) 1468 struct ifnet *ifp; 1469{ 1470 struct vr_softc *sc; 1471 1472 sc = ifp->if_softc; 1473 1474 if (ifp->if_flags & IFF_UP) 1475 vr_init(sc); 1476 1477 return(0); 1478} 1479 1480/* 1481 * Report current media status. 1482 */ 1483static void vr_ifmedia_sts(ifp, ifmr) 1484 struct ifnet *ifp; 1485 struct ifmediareq *ifmr; 1486{ 1487 struct vr_softc *sc; 1488 struct mii_data *mii; 1489 1490 sc = ifp->if_softc; 1491 mii = device_get_softc(sc->vr_miibus); 1492 mii_pollstat(mii); 1493 ifmr->ifm_active = mii->mii_media_active; 1494 ifmr->ifm_status = mii->mii_media_status; 1495 1496 return; 1497} 1498 1499static int vr_ioctl(ifp, command, data) 1500 struct ifnet *ifp; 1501 u_long command; 1502 caddr_t data; 1503{ 1504 struct vr_softc *sc = ifp->if_softc; 1505 struct ifreq *ifr = (struct ifreq *) data; 1506 struct mii_data *mii; 1507 int s, error = 0; 1508 1509 s = splimp(); 1510 1511 switch(command) { 1512 case SIOCSIFADDR: 1513 case SIOCGIFADDR: 1514 case SIOCSIFMTU: 1515 error = ether_ioctl(ifp, command, data); 1516 break; 1517 case SIOCSIFFLAGS: 1518 if (ifp->if_flags & IFF_UP) { 1519 vr_init(sc); 1520 } else { 1521 if (ifp->if_flags & IFF_RUNNING) 1522 vr_stop(sc); 1523 } 1524 error = 0; 1525 break; 1526 case SIOCADDMULTI: 1527 case SIOCDELMULTI: 1528 vr_setmulti(sc); 1529 error = 0; 1530 break; 1531 case SIOCGIFMEDIA: 1532 case SIOCSIFMEDIA: 1533 mii = device_get_softc(sc->vr_miibus); 1534 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command); 1535 break; 1536 default: 1537 error = EINVAL; 1538 break; 1539 } 1540 1541 (void)splx(s); 1542 1543 return(error); 1544} 1545 1546static void vr_watchdog(ifp) 1547 struct ifnet *ifp; 1548{ 1549 struct vr_softc *sc; 1550 1551 sc = ifp->if_softc; 1552 1553 ifp->if_oerrors++; 1554 printf("vr%d: watchdog timeout\n", sc->vr_unit); 1555 1556 vr_stop(sc); 1557 vr_reset(sc); 1558 vr_init(sc); 1559 1560 if (ifp->if_snd.ifq_head != NULL) 1561 vr_start(ifp); 1562 1563 return; 1564} 1565 1566/* 1567 * Stop the adapter and free any mbufs allocated to the 1568 * RX and TX lists. 1569 */ 1570static void vr_stop(sc) 1571 struct vr_softc *sc; 1572{ 1573 register int i; 1574 struct ifnet *ifp; 1575 1576 ifp = &sc->arpcom.ac_if; 1577 ifp->if_timer = 0; 1578 1579 untimeout(vr_tick, sc, sc->vr_stat_ch); 1580 1581 VR_SETBIT16(sc, VR_COMMAND, VR_CMD_STOP); 1582 VR_CLRBIT16(sc, VR_COMMAND, (VR_CMD_RX_ON|VR_CMD_TX_ON)); 1583 CSR_WRITE_2(sc, VR_IMR, 0x0000); 1584 CSR_WRITE_4(sc, VR_TXADDR, 0x00000000); 1585 CSR_WRITE_4(sc, VR_RXADDR, 0x00000000); 1586 1587 /* 1588 * Free data in the RX lists. 1589 */ 1590 for (i = 0; i < VR_RX_LIST_CNT; i++) { 1591 if (sc->vr_cdata.vr_rx_chain[i].vr_mbuf != NULL) { 1592 m_freem(sc->vr_cdata.vr_rx_chain[i].vr_mbuf); 1593 sc->vr_cdata.vr_rx_chain[i].vr_mbuf = NULL; 1594 } 1595 } 1596 bzero((char *)&sc->vr_ldata->vr_rx_list, 1597 sizeof(sc->vr_ldata->vr_rx_list)); 1598 1599 /* 1600 * Free the TX list buffers. 1601 */ 1602 for (i = 0; i < VR_TX_LIST_CNT; i++) { 1603 if (sc->vr_cdata.vr_tx_chain[i].vr_mbuf != NULL) { 1604 m_freem(sc->vr_cdata.vr_tx_chain[i].vr_mbuf); 1605 sc->vr_cdata.vr_tx_chain[i].vr_mbuf = NULL; 1606 } 1607 } 1608 1609 bzero((char *)&sc->vr_ldata->vr_tx_list, 1610 sizeof(sc->vr_ldata->vr_tx_list)); 1611 1612 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 1613 1614 return; 1615} 1616 1617/* 1618 * Stop all chip I/O so that the kernel's probe routines don't 1619 * get confused by errant DMAs when rebooting. 1620 */ 1621static void vr_shutdown(dev) 1622 device_t dev; 1623{ 1624 struct vr_softc *sc; 1625 1626 sc = device_get_softc(dev); 1627 1628 vr_stop(sc); 1629 1630 return; 1631} 1632