1251538Srpaulo/* $OpenBSD: if_urtwn.c,v 1.16 2011/02/10 17:26:40 jakemsr Exp $ */ 2251538Srpaulo 3251538Srpaulo/*- 4251538Srpaulo * Copyright (c) 2010 Damien Bergamini <damien.bergamini@free.fr> 5266578Shselasky * Copyright (c) 2014 Kevin Lo <kevlo@FreeBSD.org> 6251538Srpaulo * 7251538Srpaulo * Permission to use, copy, modify, and distribute this software for any 8251538Srpaulo * purpose with or without fee is hereby granted, provided that the above 9251538Srpaulo * copyright notice and this permission notice appear in all copies. 10251538Srpaulo * 11251538Srpaulo * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 12251538Srpaulo * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 13251538Srpaulo * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 14251538Srpaulo * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 15251538Srpaulo * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 16251538Srpaulo * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 17251538Srpaulo * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 18251538Srpaulo */ 19251538Srpaulo 20251538Srpaulo#include <sys/cdefs.h> 21251538Srpaulo__FBSDID("$FreeBSD$"); 22251538Srpaulo 23251538Srpaulo/* 24266578Shselasky * Driver for Realtek RTL8188CE-VAU/RTL8188CUS/RTL8188EU/RTL8188RU/RTL8192CU. 25251538Srpaulo */ 26251538Srpaulo 27251538Srpaulo#include <sys/param.h> 28251538Srpaulo#include <sys/sockio.h> 29251538Srpaulo#include <sys/sysctl.h> 30251538Srpaulo#include <sys/lock.h> 31251538Srpaulo#include <sys/mutex.h> 32251538Srpaulo#include <sys/mbuf.h> 33251538Srpaulo#include <sys/kernel.h> 34251538Srpaulo#include <sys/socket.h> 35251538Srpaulo#include <sys/systm.h> 36251538Srpaulo#include <sys/malloc.h> 37251538Srpaulo#include <sys/module.h> 38251538Srpaulo#include <sys/bus.h> 39251538Srpaulo#include <sys/endian.h> 40251538Srpaulo#include <sys/linker.h> 41251538Srpaulo#include <sys/firmware.h> 42251538Srpaulo#include <sys/kdb.h> 43251538Srpaulo 44251538Srpaulo#include <machine/bus.h> 45251538Srpaulo#include <machine/resource.h> 46251538Srpaulo#include <sys/rman.h> 47251538Srpaulo 48251538Srpaulo#include <net/bpf.h> 49251538Srpaulo#include <net/if.h> 50251538Srpaulo#include <net/if_arp.h> 51251538Srpaulo#include <net/ethernet.h> 52251538Srpaulo#include <net/if_dl.h> 53251538Srpaulo#include <net/if_media.h> 54251538Srpaulo#include <net/if_types.h> 55251538Srpaulo 56251538Srpaulo#include <netinet/in.h> 57251538Srpaulo#include <netinet/in_systm.h> 58251538Srpaulo#include <netinet/in_var.h> 59251538Srpaulo#include <netinet/if_ether.h> 60251538Srpaulo#include <netinet/ip.h> 61251538Srpaulo 62251538Srpaulo#include <net80211/ieee80211_var.h> 63251538Srpaulo#include <net80211/ieee80211_regdomain.h> 64251538Srpaulo#include <net80211/ieee80211_radiotap.h> 65251538Srpaulo#include <net80211/ieee80211_ratectl.h> 66251538Srpaulo 67251538Srpaulo#include <dev/usb/usb.h> 68251538Srpaulo#include <dev/usb/usbdi.h> 69251538Srpaulo#include "usbdevs.h" 70251538Srpaulo 71251538Srpaulo#define USB_DEBUG_VAR urtwn_debug 72251538Srpaulo#include <dev/usb/usb_debug.h> 73251538Srpaulo 74251538Srpaulo#include <dev/usb/wlan/if_urtwnreg.h> 75251538Srpaulo 76251538Srpaulo#ifdef USB_DEBUG 77251538Srpaulostatic int urtwn_debug = 0; 78251538Srpaulo 79251538SrpauloSYSCTL_NODE(_hw_usb, OID_AUTO, urtwn, CTLFLAG_RW, 0, "USB urtwn"); 80251538SrpauloSYSCTL_INT(_hw_usb_urtwn, OID_AUTO, debug, CTLFLAG_RW, &urtwn_debug, 0, 81251538Srpaulo "Debug level"); 82251538Srpaulo#endif 83251538Srpaulo 84252406Srpaulo#define URTWN_RSSI(r) (r) - 110 85251538Srpaulo#define IEEE80211_HAS_ADDR4(wh) \ 86251538Srpaulo (((wh)->i_fc[1] & IEEE80211_FC1_DIR_MASK) == IEEE80211_FC1_DIR_DSTODS) 87251538Srpaulo 88251538Srpaulo/* various supported device vendors/products */ 89251596Srpaulostatic const STRUCT_USB_HOST_ID urtwn_devs[] = { 90251538Srpaulo#define URTWN_DEV(v,p) { USB_VP(USB_VENDOR_##v, USB_PRODUCT_##v##_##p) } 91266578Shselasky#define URTWN_RTL8188E_DEV(v,p) \ 92266578Shselasky { USB_VPI(USB_VENDOR_##v, USB_PRODUCT_##v##_##p, URTWN_RTL8188E) } 93266578Shselasky#define URTWN_RTL8188E 1 94251538Srpaulo URTWN_DEV(ABOCOM, RTL8188CU_1), 95251538Srpaulo URTWN_DEV(ABOCOM, RTL8188CU_2), 96251538Srpaulo URTWN_DEV(ABOCOM, RTL8192CU), 97251538Srpaulo URTWN_DEV(ASUS, RTL8192CU), 98266722Skevlo URTWN_DEV(ASUS, USBN10NANO), 99251538Srpaulo URTWN_DEV(AZUREWAVE, RTL8188CE_1), 100251538Srpaulo URTWN_DEV(AZUREWAVE, RTL8188CE_2), 101251538Srpaulo URTWN_DEV(AZUREWAVE, RTL8188CU), 102251538Srpaulo URTWN_DEV(BELKIN, F7D2102), 103251538Srpaulo URTWN_DEV(BELKIN, RTL8188CU), 104251538Srpaulo URTWN_DEV(BELKIN, RTL8192CU), 105251538Srpaulo URTWN_DEV(CHICONY, RTL8188CUS_1), 106251538Srpaulo URTWN_DEV(CHICONY, RTL8188CUS_2), 107251538Srpaulo URTWN_DEV(CHICONY, RTL8188CUS_3), 108251538Srpaulo URTWN_DEV(CHICONY, RTL8188CUS_4), 109251538Srpaulo URTWN_DEV(CHICONY, RTL8188CUS_5), 110251538Srpaulo URTWN_DEV(COREGA, RTL8192CU), 111251538Srpaulo URTWN_DEV(DLINK, RTL8188CU), 112251538Srpaulo URTWN_DEV(DLINK, RTL8192CU_1), 113251538Srpaulo URTWN_DEV(DLINK, RTL8192CU_2), 114251538Srpaulo URTWN_DEV(DLINK, RTL8192CU_3), 115252196Skevlo URTWN_DEV(DLINK, DWA131B), 116251538Srpaulo URTWN_DEV(EDIMAX, EW7811UN), 117251538Srpaulo URTWN_DEV(EDIMAX, RTL8192CU), 118251538Srpaulo URTWN_DEV(FEIXUN, RTL8188CU), 119251538Srpaulo URTWN_DEV(FEIXUN, RTL8192CU), 120251538Srpaulo URTWN_DEV(GUILLEMOT, HWNUP150), 121251538Srpaulo URTWN_DEV(HAWKING, RTL8192CU), 122251538Srpaulo URTWN_DEV(HP3, RTL8188CU), 123251538Srpaulo URTWN_DEV(NETGEAR, WNA1000M), 124251538Srpaulo URTWN_DEV(NETGEAR, RTL8192CU), 125251538Srpaulo URTWN_DEV(NETGEAR4, RTL8188CU), 126251538Srpaulo URTWN_DEV(NOVATECH, RTL8188CU), 127251538Srpaulo URTWN_DEV(PLANEX2, RTL8188CU_1), 128251538Srpaulo URTWN_DEV(PLANEX2, RTL8188CU_2), 129251538Srpaulo URTWN_DEV(PLANEX2, RTL8188CU_3), 130251538Srpaulo URTWN_DEV(PLANEX2, RTL8188CU_4), 131251538Srpaulo URTWN_DEV(PLANEX2, RTL8188CUS), 132251538Srpaulo URTWN_DEV(PLANEX2, RTL8192CU), 133251538Srpaulo URTWN_DEV(REALTEK, RTL8188CE_0), 134251538Srpaulo URTWN_DEV(REALTEK, RTL8188CE_1), 135251538Srpaulo URTWN_DEV(REALTEK, RTL8188CTV), 136251538Srpaulo URTWN_DEV(REALTEK, RTL8188CU_0), 137251538Srpaulo URTWN_DEV(REALTEK, RTL8188CU_1), 138251538Srpaulo URTWN_DEV(REALTEK, RTL8188CU_2), 139282366Skevlo URTWN_DEV(REALTEK, RTL8188CU_3), 140251538Srpaulo URTWN_DEV(REALTEK, RTL8188CU_COMBO), 141251538Srpaulo URTWN_DEV(REALTEK, RTL8188CUS), 142251538Srpaulo URTWN_DEV(REALTEK, RTL8188RU_1), 143251538Srpaulo URTWN_DEV(REALTEK, RTL8188RU_2), 144272590Shselasky URTWN_DEV(REALTEK, RTL8188RU_3), 145251538Srpaulo URTWN_DEV(REALTEK, RTL8191CU), 146251538Srpaulo URTWN_DEV(REALTEK, RTL8192CE), 147251538Srpaulo URTWN_DEV(REALTEK, RTL8192CU), 148251538Srpaulo URTWN_DEV(SITECOMEU, RTL8188CU_1), 149251538Srpaulo URTWN_DEV(SITECOMEU, RTL8188CU_2), 150251538Srpaulo URTWN_DEV(SITECOMEU, RTL8192CU), 151251538Srpaulo URTWN_DEV(TRENDNET, RTL8188CU), 152251538Srpaulo URTWN_DEV(TRENDNET, RTL8192CU), 153251538Srpaulo URTWN_DEV(ZYXEL, RTL8192CU), 154266578Shselasky /* URTWN_RTL8188E */ 155270514Skevlo URTWN_RTL8188E_DEV(DLINK, DWA125D1), 156266578Shselasky URTWN_RTL8188E_DEV(REALTEK, RTL8188ETV), 157266578Shselasky URTWN_RTL8188E_DEV(REALTEK, RTL8188EU), 158266578Shselasky#undef URTWN_RTL8188E_DEV 159251538Srpaulo#undef URTWN_DEV 160251538Srpaulo}; 161251538Srpaulo 162251538Srpaulostatic device_probe_t urtwn_match; 163251538Srpaulostatic device_attach_t urtwn_attach; 164251538Srpaulostatic device_detach_t urtwn_detach; 165251538Srpaulo 166251538Srpaulostatic usb_callback_t urtwn_bulk_tx_callback; 167251538Srpaulostatic usb_callback_t urtwn_bulk_rx_callback; 168251538Srpaulo 169251538Srpaulostatic usb_error_t urtwn_do_request(struct urtwn_softc *sc, 170251538Srpaulo struct usb_device_request *req, void *data); 171251538Srpaulostatic struct ieee80211vap *urtwn_vap_create(struct ieee80211com *, 172251538Srpaulo const char [IFNAMSIZ], int, enum ieee80211_opmode, int, 173251538Srpaulo const uint8_t [IEEE80211_ADDR_LEN], 174251538Srpaulo const uint8_t [IEEE80211_ADDR_LEN]); 175251538Srpaulostatic void urtwn_vap_delete(struct ieee80211vap *); 176251538Srpaulostatic struct mbuf * urtwn_rx_frame(struct urtwn_softc *, uint8_t *, int, 177251538Srpaulo int *); 178251538Srpaulostatic struct mbuf * urtwn_rxeof(struct usb_xfer *, struct urtwn_data *, 179251538Srpaulo int *, int8_t *); 180251538Srpaulostatic void urtwn_txeof(struct usb_xfer *, struct urtwn_data *); 181251538Srpaulostatic int urtwn_alloc_list(struct urtwn_softc *, 182251538Srpaulo struct urtwn_data[], int, int); 183251538Srpaulostatic int urtwn_alloc_rx_list(struct urtwn_softc *); 184251538Srpaulostatic int urtwn_alloc_tx_list(struct urtwn_softc *); 185251538Srpaulostatic void urtwn_free_tx_list(struct urtwn_softc *); 186251538Srpaulostatic void urtwn_free_rx_list(struct urtwn_softc *); 187251538Srpaulostatic void urtwn_free_list(struct urtwn_softc *, 188251538Srpaulo struct urtwn_data data[], int); 189251538Srpaulostatic struct urtwn_data * _urtwn_getbuf(struct urtwn_softc *); 190251538Srpaulostatic struct urtwn_data * urtwn_getbuf(struct urtwn_softc *); 191251538Srpaulostatic int urtwn_write_region_1(struct urtwn_softc *, uint16_t, 192251538Srpaulo uint8_t *, int); 193251538Srpaulostatic void urtwn_write_1(struct urtwn_softc *, uint16_t, uint8_t); 194251538Srpaulostatic void urtwn_write_2(struct urtwn_softc *, uint16_t, uint16_t); 195251538Srpaulostatic void urtwn_write_4(struct urtwn_softc *, uint16_t, uint32_t); 196251538Srpaulostatic int urtwn_read_region_1(struct urtwn_softc *, uint16_t, 197251538Srpaulo uint8_t *, int); 198251538Srpaulostatic uint8_t urtwn_read_1(struct urtwn_softc *, uint16_t); 199251538Srpaulostatic uint16_t urtwn_read_2(struct urtwn_softc *, uint16_t); 200251538Srpaulostatic uint32_t urtwn_read_4(struct urtwn_softc *, uint16_t); 201251538Srpaulostatic int urtwn_fw_cmd(struct urtwn_softc *, uint8_t, 202251538Srpaulo const void *, int); 203266578Shselaskystatic void urtwn_r92c_rf_write(struct urtwn_softc *, int, 204266578Shselasky uint8_t, uint32_t); 205266578Shselaskystatic void urtwn_r88e_rf_write(struct urtwn_softc *, int, 206266578Shselasky uint8_t, uint32_t); 207251538Srpaulostatic uint32_t urtwn_rf_read(struct urtwn_softc *, int, uint8_t); 208251538Srpaulostatic int urtwn_llt_write(struct urtwn_softc *, uint32_t, 209251538Srpaulo uint32_t); 210251538Srpaulostatic uint8_t urtwn_efuse_read_1(struct urtwn_softc *, uint16_t); 211251538Srpaulostatic void urtwn_efuse_read(struct urtwn_softc *); 212266578Shselaskystatic void urtwn_efuse_switch_power(struct urtwn_softc *); 213251538Srpaulostatic int urtwn_read_chipid(struct urtwn_softc *); 214251538Srpaulostatic void urtwn_read_rom(struct urtwn_softc *); 215266578Shselaskystatic void urtwn_r88e_read_rom(struct urtwn_softc *); 216251538Srpaulostatic int urtwn_ra_init(struct urtwn_softc *); 217251538Srpaulostatic void urtwn_tsf_sync_enable(struct urtwn_softc *); 218251538Srpaulostatic void urtwn_set_led(struct urtwn_softc *, int, int); 219251538Srpaulostatic int urtwn_newstate(struct ieee80211vap *, 220251538Srpaulo enum ieee80211_state, int); 221251538Srpaulostatic void urtwn_watchdog(void *); 222251538Srpaulostatic void urtwn_update_avgrssi(struct urtwn_softc *, int, int8_t); 223251538Srpaulostatic int8_t urtwn_get_rssi(struct urtwn_softc *, int, void *); 224266578Shselaskystatic int8_t urtwn_r88e_get_rssi(struct urtwn_softc *, int, void *); 225251538Srpaulostatic int urtwn_tx_start(struct urtwn_softc *, 226251538Srpaulo struct ieee80211_node *, struct mbuf *, 227251538Srpaulo struct urtwn_data *); 228251538Srpaulostatic void urtwn_start(struct ifnet *); 229261961Srpaulostatic void urtwn_start_locked(struct ifnet *, 230261961Srpaulo struct urtwn_softc *); 231251538Srpaulostatic int urtwn_ioctl(struct ifnet *, u_long, caddr_t); 232266578Shselaskystatic int urtwn_r92c_power_on(struct urtwn_softc *); 233266578Shselaskystatic int urtwn_r88e_power_on(struct urtwn_softc *); 234251538Srpaulostatic int urtwn_llt_init(struct urtwn_softc *); 235251538Srpaulostatic void urtwn_fw_reset(struct urtwn_softc *); 236266578Shselaskystatic void urtwn_r88e_fw_reset(struct urtwn_softc *); 237251538Srpaulostatic int urtwn_fw_loadpage(struct urtwn_softc *, int, 238251538Srpaulo const uint8_t *, int); 239251538Srpaulostatic int urtwn_load_firmware(struct urtwn_softc *); 240266578Shselaskystatic int urtwn_r92c_dma_init(struct urtwn_softc *); 241266578Shselaskystatic int urtwn_r88e_dma_init(struct urtwn_softc *); 242251538Srpaulostatic void urtwn_mac_init(struct urtwn_softc *); 243251538Srpaulostatic void urtwn_bb_init(struct urtwn_softc *); 244251538Srpaulostatic void urtwn_rf_init(struct urtwn_softc *); 245251538Srpaulostatic void urtwn_cam_init(struct urtwn_softc *); 246251538Srpaulostatic void urtwn_pa_bias_init(struct urtwn_softc *); 247251538Srpaulostatic void urtwn_rxfilter_init(struct urtwn_softc *); 248251538Srpaulostatic void urtwn_edca_init(struct urtwn_softc *); 249251538Srpaulostatic void urtwn_write_txpower(struct urtwn_softc *, int, 250251538Srpaulo uint16_t[]); 251251538Srpaulostatic void urtwn_get_txpower(struct urtwn_softc *, int, 252251538Srpaulo struct ieee80211_channel *, 253251538Srpaulo struct ieee80211_channel *, uint16_t[]); 254266578Shselaskystatic void urtwn_r88e_get_txpower(struct urtwn_softc *, int, 255266578Shselasky struct ieee80211_channel *, 256266578Shselasky struct ieee80211_channel *, uint16_t[]); 257251538Srpaulostatic void urtwn_set_txpower(struct urtwn_softc *, 258251538Srpaulo struct ieee80211_channel *, 259251538Srpaulo struct ieee80211_channel *); 260251538Srpaulostatic void urtwn_scan_start(struct ieee80211com *); 261251538Srpaulostatic void urtwn_scan_end(struct ieee80211com *); 262251538Srpaulostatic void urtwn_set_channel(struct ieee80211com *); 263251538Srpaulostatic void urtwn_set_chan(struct urtwn_softc *, 264251538Srpaulo struct ieee80211_channel *, 265251538Srpaulo struct ieee80211_channel *); 266251538Srpaulostatic void urtwn_update_mcast(struct ifnet *); 267251538Srpaulostatic void urtwn_iq_calib(struct urtwn_softc *); 268251538Srpaulostatic void urtwn_lc_calib(struct urtwn_softc *); 269251538Srpaulostatic void urtwn_init(void *); 270251538Srpaulostatic void urtwn_init_locked(void *); 271263256Skevlostatic void urtwn_stop(struct ifnet *); 272263256Skevlostatic void urtwn_stop_locked(struct ifnet *); 273251538Srpaulostatic void urtwn_abort_xfers(struct urtwn_softc *); 274251538Srpaulostatic int urtwn_raw_xmit(struct ieee80211_node *, struct mbuf *, 275251538Srpaulo const struct ieee80211_bpf_params *); 276266578Shselaskystatic void urtwn_ms_delay(struct urtwn_softc *); 277251538Srpaulo 278251538Srpaulo/* Aliases. */ 279251538Srpaulo#define urtwn_bb_write urtwn_write_4 280251538Srpaulo#define urtwn_bb_read urtwn_read_4 281251538Srpaulo 282251538Srpaulostatic const struct usb_config urtwn_config[URTWN_N_TRANSFER] = { 283251538Srpaulo [URTWN_BULK_RX] = { 284251538Srpaulo .type = UE_BULK, 285251538Srpaulo .endpoint = UE_ADDR_ANY, 286251538Srpaulo .direction = UE_DIR_IN, 287251538Srpaulo .bufsize = URTWN_RXBUFSZ, 288251538Srpaulo .flags = { 289251538Srpaulo .pipe_bof = 1, 290251538Srpaulo .short_xfer_ok = 1 291251538Srpaulo }, 292251538Srpaulo .callback = urtwn_bulk_rx_callback, 293251538Srpaulo }, 294251538Srpaulo [URTWN_BULK_TX_BE] = { 295251538Srpaulo .type = UE_BULK, 296251538Srpaulo .endpoint = 0x03, 297251538Srpaulo .direction = UE_DIR_OUT, 298251538Srpaulo .bufsize = URTWN_TXBUFSZ, 299251538Srpaulo .flags = { 300251538Srpaulo .ext_buffer = 1, 301251538Srpaulo .pipe_bof = 1, 302251538Srpaulo .force_short_xfer = 1 303251538Srpaulo }, 304251538Srpaulo .callback = urtwn_bulk_tx_callback, 305251538Srpaulo .timeout = URTWN_TX_TIMEOUT, /* ms */ 306251538Srpaulo }, 307251538Srpaulo [URTWN_BULK_TX_BK] = { 308251538Srpaulo .type = UE_BULK, 309251538Srpaulo .endpoint = 0x03, 310251538Srpaulo .direction = UE_DIR_OUT, 311251538Srpaulo .bufsize = URTWN_TXBUFSZ, 312251538Srpaulo .flags = { 313251538Srpaulo .ext_buffer = 1, 314251538Srpaulo .pipe_bof = 1, 315251538Srpaulo .force_short_xfer = 1, 316251538Srpaulo }, 317251538Srpaulo .callback = urtwn_bulk_tx_callback, 318251538Srpaulo .timeout = URTWN_TX_TIMEOUT, /* ms */ 319251538Srpaulo }, 320251538Srpaulo [URTWN_BULK_TX_VI] = { 321251538Srpaulo .type = UE_BULK, 322251538Srpaulo .endpoint = 0x02, 323251538Srpaulo .direction = UE_DIR_OUT, 324251538Srpaulo .bufsize = URTWN_TXBUFSZ, 325251538Srpaulo .flags = { 326251538Srpaulo .ext_buffer = 1, 327251538Srpaulo .pipe_bof = 1, 328251538Srpaulo .force_short_xfer = 1 329251538Srpaulo }, 330251538Srpaulo .callback = urtwn_bulk_tx_callback, 331251538Srpaulo .timeout = URTWN_TX_TIMEOUT, /* ms */ 332251538Srpaulo }, 333251538Srpaulo [URTWN_BULK_TX_VO] = { 334251538Srpaulo .type = UE_BULK, 335251538Srpaulo .endpoint = 0x02, 336251538Srpaulo .direction = UE_DIR_OUT, 337251538Srpaulo .bufsize = URTWN_TXBUFSZ, 338251538Srpaulo .flags = { 339251538Srpaulo .ext_buffer = 1, 340251538Srpaulo .pipe_bof = 1, 341251538Srpaulo .force_short_xfer = 1 342251538Srpaulo }, 343251538Srpaulo .callback = urtwn_bulk_tx_callback, 344251538Srpaulo .timeout = URTWN_TX_TIMEOUT, /* ms */ 345251538Srpaulo }, 346251538Srpaulo}; 347251538Srpaulo 348251538Srpaulostatic int 349251538Srpaulourtwn_match(device_t self) 350251538Srpaulo{ 351251538Srpaulo struct usb_attach_arg *uaa = device_get_ivars(self); 352251538Srpaulo 353251538Srpaulo if (uaa->usb_mode != USB_MODE_HOST) 354251538Srpaulo return (ENXIO); 355251538Srpaulo if (uaa->info.bConfigIndex != URTWN_CONFIG_INDEX) 356251538Srpaulo return (ENXIO); 357251538Srpaulo if (uaa->info.bIfaceIndex != URTWN_IFACE_INDEX) 358251538Srpaulo return (ENXIO); 359251538Srpaulo 360251538Srpaulo return (usbd_lookup_id_by_uaa(urtwn_devs, sizeof(urtwn_devs), uaa)); 361251538Srpaulo} 362251538Srpaulo 363251538Srpaulostatic int 364251538Srpaulourtwn_attach(device_t self) 365251538Srpaulo{ 366251538Srpaulo struct usb_attach_arg *uaa = device_get_ivars(self); 367251538Srpaulo struct urtwn_softc *sc = device_get_softc(self); 368251538Srpaulo struct ifnet *ifp; 369251538Srpaulo struct ieee80211com *ic; 370251538Srpaulo uint8_t iface_index, bands; 371251538Srpaulo int error; 372251538Srpaulo 373251538Srpaulo device_set_usb_desc(self); 374251538Srpaulo sc->sc_udev = uaa->device; 375251538Srpaulo sc->sc_dev = self; 376266578Shselasky if (USB_GET_DRIVER_INFO(uaa) == URTWN_RTL8188E) 377266578Shselasky sc->chip |= URTWN_CHIP_88E; 378251538Srpaulo 379251538Srpaulo mtx_init(&sc->sc_mtx, device_get_nameunit(self), 380251538Srpaulo MTX_NETWORK_LOCK, MTX_DEF); 381251538Srpaulo callout_init(&sc->sc_watchdog_ch, 0); 382251538Srpaulo 383251538Srpaulo iface_index = URTWN_IFACE_INDEX; 384251538Srpaulo error = usbd_transfer_setup(uaa->device, &iface_index, sc->sc_xfer, 385251538Srpaulo urtwn_config, URTWN_N_TRANSFER, sc, &sc->sc_mtx); 386251538Srpaulo if (error) { 387251538Srpaulo device_printf(self, "could not allocate USB transfers, " 388251538Srpaulo "err=%s\n", usbd_errstr(error)); 389251538Srpaulo goto detach; 390251538Srpaulo } 391251538Srpaulo 392251538Srpaulo URTWN_LOCK(sc); 393251538Srpaulo 394251538Srpaulo error = urtwn_read_chipid(sc); 395251538Srpaulo if (error) { 396251538Srpaulo device_printf(sc->sc_dev, "unsupported test chip\n"); 397251538Srpaulo URTWN_UNLOCK(sc); 398251538Srpaulo goto detach; 399251538Srpaulo } 400251538Srpaulo 401251538Srpaulo /* Determine number of Tx/Rx chains. */ 402251538Srpaulo if (sc->chip & URTWN_CHIP_92C) { 403251538Srpaulo sc->ntxchains = (sc->chip & URTWN_CHIP_92C_1T2R) ? 1 : 2; 404251538Srpaulo sc->nrxchains = 2; 405251538Srpaulo } else { 406251538Srpaulo sc->ntxchains = 1; 407251538Srpaulo sc->nrxchains = 1; 408251538Srpaulo } 409251538Srpaulo 410266578Shselasky if (sc->chip & URTWN_CHIP_88E) 411266578Shselasky urtwn_r88e_read_rom(sc); 412266578Shselasky else 413266578Shselasky urtwn_read_rom(sc); 414266578Shselasky 415251538Srpaulo device_printf(sc->sc_dev, "MAC/BB RTL%s, RF 6052 %dT%dR\n", 416251538Srpaulo (sc->chip & URTWN_CHIP_92C) ? "8192CU" : 417266578Shselasky (sc->chip & URTWN_CHIP_88E) ? "8188EU" : 418251538Srpaulo (sc->board_type == R92C_BOARD_TYPE_HIGHPA) ? "8188RU" : 419251538Srpaulo (sc->board_type == R92C_BOARD_TYPE_MINICARD) ? "8188CE-VAU" : 420251538Srpaulo "8188CUS", sc->ntxchains, sc->nrxchains); 421251538Srpaulo 422251538Srpaulo URTWN_UNLOCK(sc); 423251538Srpaulo 424251538Srpaulo ifp = sc->sc_ifp = if_alloc(IFT_IEEE80211); 425251538Srpaulo if (ifp == NULL) { 426251538Srpaulo device_printf(sc->sc_dev, "can not if_alloc()\n"); 427251538Srpaulo goto detach; 428251538Srpaulo } 429251538Srpaulo ic = ifp->if_l2com; 430251538Srpaulo 431251538Srpaulo ifp->if_softc = sc; 432251538Srpaulo if_initname(ifp, "urtwn", device_get_unit(sc->sc_dev)); 433251538Srpaulo ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 434251538Srpaulo ifp->if_init = urtwn_init; 435251538Srpaulo ifp->if_ioctl = urtwn_ioctl; 436251538Srpaulo ifp->if_start = urtwn_start; 437251538Srpaulo IFQ_SET_MAXLEN(&ifp->if_snd, ifqmaxlen); 438251538Srpaulo ifp->if_snd.ifq_drv_maxlen = ifqmaxlen; 439251538Srpaulo IFQ_SET_READY(&ifp->if_snd); 440251538Srpaulo 441251538Srpaulo ic->ic_ifp = ifp; 442251538Srpaulo ic->ic_phytype = IEEE80211_T_OFDM; /* not only, but not used */ 443251538Srpaulo ic->ic_opmode = IEEE80211_M_STA; /* default to BSS mode */ 444251538Srpaulo 445251538Srpaulo /* set device capabilities */ 446251538Srpaulo ic->ic_caps = 447251538Srpaulo IEEE80211_C_STA /* station mode */ 448251538Srpaulo | IEEE80211_C_MONITOR /* monitor mode */ 449251538Srpaulo | IEEE80211_C_SHPREAMBLE /* short preamble supported */ 450251538Srpaulo | IEEE80211_C_SHSLOT /* short slot time supported */ 451251538Srpaulo | IEEE80211_C_BGSCAN /* capable of bg scanning */ 452251538Srpaulo | IEEE80211_C_WPA /* 802.11i */ 453251538Srpaulo ; 454251538Srpaulo 455251538Srpaulo bands = 0; 456251538Srpaulo setbit(&bands, IEEE80211_MODE_11B); 457251538Srpaulo setbit(&bands, IEEE80211_MODE_11G); 458251538Srpaulo ieee80211_init_channels(ic, NULL, &bands); 459251538Srpaulo 460251538Srpaulo ieee80211_ifattach(ic, sc->sc_bssid); 461251538Srpaulo ic->ic_raw_xmit = urtwn_raw_xmit; 462251538Srpaulo ic->ic_scan_start = urtwn_scan_start; 463251538Srpaulo ic->ic_scan_end = urtwn_scan_end; 464251538Srpaulo ic->ic_set_channel = urtwn_set_channel; 465251538Srpaulo 466251538Srpaulo ic->ic_vap_create = urtwn_vap_create; 467251538Srpaulo ic->ic_vap_delete = urtwn_vap_delete; 468251538Srpaulo ic->ic_update_mcast = urtwn_update_mcast; 469251538Srpaulo 470251538Srpaulo ieee80211_radiotap_attach(ic, &sc->sc_txtap.wt_ihdr, 471251538Srpaulo sizeof(sc->sc_txtap), URTWN_TX_RADIOTAP_PRESENT, 472251538Srpaulo &sc->sc_rxtap.wr_ihdr, sizeof(sc->sc_rxtap), 473251538Srpaulo URTWN_RX_RADIOTAP_PRESENT); 474251538Srpaulo 475251538Srpaulo if (bootverbose) 476251538Srpaulo ieee80211_announce(ic); 477251538Srpaulo 478251538Srpaulo return (0); 479251538Srpaulo 480251538Srpaulodetach: 481251538Srpaulo urtwn_detach(self); 482251538Srpaulo return (ENXIO); /* failure */ 483251538Srpaulo} 484251538Srpaulo 485251538Srpaulostatic int 486251538Srpaulourtwn_detach(device_t self) 487251538Srpaulo{ 488251538Srpaulo struct urtwn_softc *sc = device_get_softc(self); 489251538Srpaulo struct ifnet *ifp = sc->sc_ifp; 490251538Srpaulo struct ieee80211com *ic = ifp->if_l2com; 491263256Skevlo unsigned int x; 492251538Srpaulo 493263256Skevlo /* Prevent further ioctls. */ 494263256Skevlo URTWN_LOCK(sc); 495263256Skevlo sc->sc_flags |= URTWN_DETACHED; 496263256Skevlo URTWN_UNLOCK(sc); 497251538Srpaulo 498263256Skevlo urtwn_stop(ifp); 499251538Srpaulo 500251538Srpaulo callout_drain(&sc->sc_watchdog_ch); 501251538Srpaulo 502263256Skevlo /* Prevent further allocations from RX/TX data lists. */ 503263256Skevlo URTWN_LOCK(sc); 504263256Skevlo STAILQ_INIT(&sc->sc_tx_active); 505263256Skevlo STAILQ_INIT(&sc->sc_tx_inactive); 506263256Skevlo STAILQ_INIT(&sc->sc_tx_pending); 507263256Skevlo 508263256Skevlo STAILQ_INIT(&sc->sc_rx_active); 509263256Skevlo STAILQ_INIT(&sc->sc_rx_inactive); 510263256Skevlo URTWN_UNLOCK(sc); 511263256Skevlo 512263256Skevlo /* drain USB transfers */ 513263256Skevlo for (x = 0; x != URTWN_N_TRANSFER; x++) 514263256Skevlo usbd_transfer_drain(sc->sc_xfer[x]); 515263256Skevlo 516263256Skevlo /* Free data buffers. */ 517263256Skevlo URTWN_LOCK(sc); 518263256Skevlo urtwn_free_tx_list(sc); 519263256Skevlo urtwn_free_rx_list(sc); 520263256Skevlo URTWN_UNLOCK(sc); 521263256Skevlo 522251538Srpaulo /* stop all USB transfers */ 523251538Srpaulo usbd_transfer_unsetup(sc->sc_xfer, URTWN_N_TRANSFER); 524251538Srpaulo ieee80211_ifdetach(ic); 525251538Srpaulo 526251538Srpaulo if_free(ifp); 527251538Srpaulo mtx_destroy(&sc->sc_mtx); 528251538Srpaulo 529251538Srpaulo return (0); 530251538Srpaulo} 531251538Srpaulo 532251538Srpaulostatic void 533251538Srpaulourtwn_free_tx_list(struct urtwn_softc *sc) 534251538Srpaulo{ 535251538Srpaulo urtwn_free_list(sc, sc->sc_tx, URTWN_TX_LIST_COUNT); 536251538Srpaulo} 537251538Srpaulo 538251538Srpaulostatic void 539251538Srpaulourtwn_free_rx_list(struct urtwn_softc *sc) 540251538Srpaulo{ 541251538Srpaulo urtwn_free_list(sc, sc->sc_rx, URTWN_RX_LIST_COUNT); 542251538Srpaulo} 543251538Srpaulo 544251538Srpaulostatic void 545251538Srpaulourtwn_free_list(struct urtwn_softc *sc, struct urtwn_data data[], int ndata) 546251538Srpaulo{ 547251538Srpaulo int i; 548251538Srpaulo 549251538Srpaulo for (i = 0; i < ndata; i++) { 550251538Srpaulo struct urtwn_data *dp = &data[i]; 551251538Srpaulo 552251538Srpaulo if (dp->buf != NULL) { 553251538Srpaulo free(dp->buf, M_USBDEV); 554251538Srpaulo dp->buf = NULL; 555251538Srpaulo } 556251538Srpaulo if (dp->ni != NULL) { 557251538Srpaulo ieee80211_free_node(dp->ni); 558251538Srpaulo dp->ni = NULL; 559251538Srpaulo } 560251538Srpaulo } 561251538Srpaulo} 562251538Srpaulo 563251538Srpaulostatic usb_error_t 564251538Srpaulourtwn_do_request(struct urtwn_softc *sc, struct usb_device_request *req, 565251538Srpaulo void *data) 566251538Srpaulo{ 567251538Srpaulo usb_error_t err; 568251538Srpaulo int ntries = 10; 569251538Srpaulo 570251538Srpaulo URTWN_ASSERT_LOCKED(sc); 571251538Srpaulo 572251538Srpaulo while (ntries--) { 573251538Srpaulo err = usbd_do_request_flags(sc->sc_udev, &sc->sc_mtx, 574251538Srpaulo req, data, 0, NULL, 250 /* ms */); 575251538Srpaulo if (err == 0) 576251538Srpaulo break; 577251538Srpaulo 578251538Srpaulo DPRINTFN(1, "Control request failed, %s (retrying)\n", 579251538Srpaulo usbd_errstr(err)); 580251538Srpaulo usb_pause_mtx(&sc->sc_mtx, hz / 100); 581251538Srpaulo } 582251538Srpaulo return (err); 583251538Srpaulo} 584251538Srpaulo 585251538Srpaulostatic struct ieee80211vap * 586251538Srpaulourtwn_vap_create(struct ieee80211com *ic, const char name[IFNAMSIZ], int unit, 587251538Srpaulo enum ieee80211_opmode opmode, int flags, 588251538Srpaulo const uint8_t bssid[IEEE80211_ADDR_LEN], 589251538Srpaulo const uint8_t mac[IEEE80211_ADDR_LEN]) 590251538Srpaulo{ 591251538Srpaulo struct urtwn_vap *uvp; 592251538Srpaulo struct ieee80211vap *vap; 593251538Srpaulo 594251538Srpaulo if (!TAILQ_EMPTY(&ic->ic_vaps)) /* only one at a time */ 595251538Srpaulo return (NULL); 596251538Srpaulo 597251538Srpaulo uvp = (struct urtwn_vap *) malloc(sizeof(struct urtwn_vap), 598251538Srpaulo M_80211_VAP, M_NOWAIT | M_ZERO); 599251538Srpaulo if (uvp == NULL) 600251538Srpaulo return (NULL); 601251538Srpaulo vap = &uvp->vap; 602251538Srpaulo /* enable s/w bmiss handling for sta mode */ 603251538Srpaulo 604259453Shselasky if (ieee80211_vap_setup(ic, vap, name, unit, opmode, 605259453Shselasky flags | IEEE80211_CLONE_NOBEACONS, bssid, mac) != 0) { 606259453Shselasky /* out of memory */ 607259453Shselasky free(uvp, M_80211_VAP); 608259453Shselasky return (NULL); 609259453Shselasky } 610259453Shselasky 611251538Srpaulo /* override state transition machine */ 612251538Srpaulo uvp->newstate = vap->iv_newstate; 613251538Srpaulo vap->iv_newstate = urtwn_newstate; 614251538Srpaulo 615251538Srpaulo /* complete setup */ 616251538Srpaulo ieee80211_vap_attach(vap, ieee80211_media_change, 617251538Srpaulo ieee80211_media_status); 618251538Srpaulo ic->ic_opmode = opmode; 619251538Srpaulo return (vap); 620251538Srpaulo} 621251538Srpaulo 622251538Srpaulostatic void 623251538Srpaulourtwn_vap_delete(struct ieee80211vap *vap) 624251538Srpaulo{ 625251538Srpaulo struct urtwn_vap *uvp = URTWN_VAP(vap); 626251538Srpaulo 627251538Srpaulo ieee80211_vap_detach(vap); 628251538Srpaulo free(uvp, M_80211_VAP); 629251538Srpaulo} 630251538Srpaulo 631251538Srpaulostatic struct mbuf * 632251538Srpaulourtwn_rx_frame(struct urtwn_softc *sc, uint8_t *buf, int pktlen, int *rssi_p) 633251538Srpaulo{ 634251538Srpaulo struct ifnet *ifp = sc->sc_ifp; 635251538Srpaulo struct ieee80211com *ic = ifp->if_l2com; 636251538Srpaulo struct ieee80211_frame *wh; 637251538Srpaulo struct mbuf *m; 638251538Srpaulo struct r92c_rx_stat *stat; 639251538Srpaulo uint32_t rxdw0, rxdw3; 640251538Srpaulo uint8_t rate; 641251538Srpaulo int8_t rssi = 0; 642251538Srpaulo int infosz; 643251538Srpaulo 644251538Srpaulo /* 645251538Srpaulo * don't pass packets to the ieee80211 framework if the driver isn't 646251538Srpaulo * RUNNING. 647251538Srpaulo */ 648251538Srpaulo if (!(ifp->if_drv_flags & IFF_DRV_RUNNING)) 649251538Srpaulo return (NULL); 650251538Srpaulo 651251538Srpaulo stat = (struct r92c_rx_stat *)buf; 652251538Srpaulo rxdw0 = le32toh(stat->rxdw0); 653251538Srpaulo rxdw3 = le32toh(stat->rxdw3); 654251538Srpaulo 655251538Srpaulo if (rxdw0 & (R92C_RXDW0_CRCERR | R92C_RXDW0_ICVERR)) { 656251538Srpaulo /* 657251538Srpaulo * This should not happen since we setup our Rx filter 658251538Srpaulo * to not receive these frames. 659251538Srpaulo */ 660251538Srpaulo ifp->if_ierrors++; 661251538Srpaulo return (NULL); 662251538Srpaulo } 663251538Srpaulo 664251538Srpaulo rate = MS(rxdw3, R92C_RXDW3_RATE); 665251538Srpaulo infosz = MS(rxdw0, R92C_RXDW0_INFOSZ) * 8; 666251538Srpaulo 667251538Srpaulo /* Get RSSI from PHY status descriptor if present. */ 668251538Srpaulo if (infosz != 0 && (rxdw0 & R92C_RXDW0_PHYST)) { 669266578Shselasky if (sc->chip & URTWN_CHIP_88E) 670266578Shselasky rssi = urtwn_r88e_get_rssi(sc, rate, &stat[1]); 671266578Shselasky else 672266578Shselasky rssi = urtwn_get_rssi(sc, rate, &stat[1]); 673251538Srpaulo /* Update our average RSSI. */ 674251538Srpaulo urtwn_update_avgrssi(sc, rate, rssi); 675252405Srpaulo /* 676252405Srpaulo * Convert the RSSI to a range that will be accepted 677252405Srpaulo * by net80211. 678252405Srpaulo */ 679252405Srpaulo rssi = URTWN_RSSI(rssi); 680251538Srpaulo } 681251538Srpaulo 682262008Skevlo m = m_getcl(M_NOWAIT, MT_DATA, M_PKTHDR); 683251538Srpaulo if (m == NULL) { 684251538Srpaulo device_printf(sc->sc_dev, "could not create RX mbuf\n"); 685251538Srpaulo return (NULL); 686251538Srpaulo } 687251538Srpaulo 688251538Srpaulo /* Finalize mbuf. */ 689251538Srpaulo m->m_pkthdr.rcvif = ifp; 690251538Srpaulo wh = (struct ieee80211_frame *)((uint8_t *)&stat[1] + infosz); 691251538Srpaulo memcpy(mtod(m, uint8_t *), wh, pktlen); 692251538Srpaulo m->m_pkthdr.len = m->m_len = pktlen; 693251538Srpaulo 694251538Srpaulo if (ieee80211_radiotap_active(ic)) { 695251538Srpaulo struct urtwn_rx_radiotap_header *tap = &sc->sc_rxtap; 696251538Srpaulo 697251538Srpaulo tap->wr_flags = 0; 698251538Srpaulo /* Map HW rate index to 802.11 rate. */ 699251538Srpaulo if (!(rxdw3 & R92C_RXDW3_HT)) { 700251538Srpaulo switch (rate) { 701251538Srpaulo /* CCK. */ 702251538Srpaulo case 0: tap->wr_rate = 2; break; 703251538Srpaulo case 1: tap->wr_rate = 4; break; 704251538Srpaulo case 2: tap->wr_rate = 11; break; 705251538Srpaulo case 3: tap->wr_rate = 22; break; 706251538Srpaulo /* OFDM. */ 707251538Srpaulo case 4: tap->wr_rate = 12; break; 708251538Srpaulo case 5: tap->wr_rate = 18; break; 709251538Srpaulo case 6: tap->wr_rate = 24; break; 710251538Srpaulo case 7: tap->wr_rate = 36; break; 711251538Srpaulo case 8: tap->wr_rate = 48; break; 712251538Srpaulo case 9: tap->wr_rate = 72; break; 713251538Srpaulo case 10: tap->wr_rate = 96; break; 714251538Srpaulo case 11: tap->wr_rate = 108; break; 715251538Srpaulo } 716251538Srpaulo } else if (rate >= 12) { /* MCS0~15. */ 717251538Srpaulo /* Bit 7 set means HT MCS instead of rate. */ 718251538Srpaulo tap->wr_rate = 0x80 | (rate - 12); 719251538Srpaulo } 720251538Srpaulo tap->wr_dbm_antsignal = rssi; 721251538Srpaulo tap->wr_chan_freq = htole16(ic->ic_curchan->ic_freq); 722251538Srpaulo tap->wr_chan_flags = htole16(ic->ic_curchan->ic_flags); 723251538Srpaulo } 724251538Srpaulo 725251538Srpaulo *rssi_p = rssi; 726251538Srpaulo 727251538Srpaulo return (m); 728251538Srpaulo} 729251538Srpaulo 730251538Srpaulostatic struct mbuf * 731251538Srpaulourtwn_rxeof(struct usb_xfer *xfer, struct urtwn_data *data, int *rssi, 732251538Srpaulo int8_t *nf) 733251538Srpaulo{ 734251538Srpaulo struct urtwn_softc *sc = data->sc; 735251538Srpaulo struct ifnet *ifp = sc->sc_ifp; 736251538Srpaulo struct r92c_rx_stat *stat; 737251538Srpaulo struct mbuf *m, *m0 = NULL, *prevm = NULL; 738251538Srpaulo uint32_t rxdw0; 739251538Srpaulo uint8_t *buf; 740251538Srpaulo int len, totlen, pktlen, infosz, npkts; 741251538Srpaulo 742251538Srpaulo usbd_xfer_status(xfer, &len, NULL, NULL, NULL); 743251538Srpaulo 744251538Srpaulo if (len < sizeof(*stat)) { 745251538Srpaulo ifp->if_ierrors++; 746251538Srpaulo return (NULL); 747251538Srpaulo } 748251538Srpaulo 749251538Srpaulo buf = data->buf; 750251538Srpaulo /* Get the number of encapsulated frames. */ 751251538Srpaulo stat = (struct r92c_rx_stat *)buf; 752251538Srpaulo npkts = MS(le32toh(stat->rxdw2), R92C_RXDW2_PKTCNT); 753251538Srpaulo DPRINTFN(6, "Rx %d frames in one chunk\n", npkts); 754251538Srpaulo 755251538Srpaulo /* Process all of them. */ 756251538Srpaulo while (npkts-- > 0) { 757251538Srpaulo if (len < sizeof(*stat)) 758251538Srpaulo break; 759251538Srpaulo stat = (struct r92c_rx_stat *)buf; 760251538Srpaulo rxdw0 = le32toh(stat->rxdw0); 761251538Srpaulo 762251538Srpaulo pktlen = MS(rxdw0, R92C_RXDW0_PKTLEN); 763251538Srpaulo if (pktlen == 0) 764251538Srpaulo break; 765251538Srpaulo 766251538Srpaulo infosz = MS(rxdw0, R92C_RXDW0_INFOSZ) * 8; 767251538Srpaulo 768251538Srpaulo /* Make sure everything fits in xfer. */ 769251538Srpaulo totlen = sizeof(*stat) + infosz + pktlen; 770251538Srpaulo if (totlen > len) 771251538Srpaulo break; 772251538Srpaulo 773251538Srpaulo m = urtwn_rx_frame(sc, buf, pktlen, rssi); 774251538Srpaulo if (m0 == NULL) 775251538Srpaulo m0 = m; 776251538Srpaulo if (prevm == NULL) 777251538Srpaulo prevm = m; 778251538Srpaulo else { 779251538Srpaulo prevm->m_next = m; 780251538Srpaulo prevm = m; 781251538Srpaulo } 782251538Srpaulo 783251538Srpaulo /* Next chunk is 128-byte aligned. */ 784251538Srpaulo totlen = (totlen + 127) & ~127; 785251538Srpaulo buf += totlen; 786251538Srpaulo len -= totlen; 787251538Srpaulo } 788251538Srpaulo 789251538Srpaulo return (m0); 790251538Srpaulo} 791251538Srpaulo 792251538Srpaulostatic void 793251538Srpaulourtwn_bulk_rx_callback(struct usb_xfer *xfer, usb_error_t error) 794251538Srpaulo{ 795251538Srpaulo struct urtwn_softc *sc = usbd_xfer_softc(xfer); 796251538Srpaulo struct ifnet *ifp = sc->sc_ifp; 797251538Srpaulo struct ieee80211com *ic = ifp->if_l2com; 798251538Srpaulo struct ieee80211_frame *wh; 799251538Srpaulo struct ieee80211_node *ni; 800251538Srpaulo struct mbuf *m = NULL, *next; 801251538Srpaulo struct urtwn_data *data; 802251538Srpaulo int8_t nf; 803251538Srpaulo int rssi = 1; 804251538Srpaulo 805251538Srpaulo URTWN_ASSERT_LOCKED(sc); 806251538Srpaulo 807251538Srpaulo switch (USB_GET_STATE(xfer)) { 808251538Srpaulo case USB_ST_TRANSFERRED: 809251538Srpaulo data = STAILQ_FIRST(&sc->sc_rx_active); 810251538Srpaulo if (data == NULL) 811251538Srpaulo goto tr_setup; 812251538Srpaulo STAILQ_REMOVE_HEAD(&sc->sc_rx_active, next); 813251538Srpaulo m = urtwn_rxeof(xfer, data, &rssi, &nf); 814251538Srpaulo STAILQ_INSERT_TAIL(&sc->sc_rx_inactive, data, next); 815251538Srpaulo /* FALLTHROUGH */ 816251538Srpaulo case USB_ST_SETUP: 817251538Srpaulotr_setup: 818251538Srpaulo data = STAILQ_FIRST(&sc->sc_rx_inactive); 819251538Srpaulo if (data == NULL) { 820251538Srpaulo KASSERT(m == NULL, ("mbuf isn't NULL")); 821251538Srpaulo return; 822251538Srpaulo } 823251538Srpaulo STAILQ_REMOVE_HEAD(&sc->sc_rx_inactive, next); 824251538Srpaulo STAILQ_INSERT_TAIL(&sc->sc_rx_active, data, next); 825251538Srpaulo usbd_xfer_set_frame_data(xfer, 0, data->buf, 826251538Srpaulo usbd_xfer_max_len(xfer)); 827251538Srpaulo usbd_transfer_submit(xfer); 828251538Srpaulo 829251538Srpaulo /* 830251538Srpaulo * To avoid LOR we should unlock our private mutex here to call 831251538Srpaulo * ieee80211_input() because here is at the end of a USB 832251538Srpaulo * callback and safe to unlock. 833251538Srpaulo */ 834251538Srpaulo URTWN_UNLOCK(sc); 835251538Srpaulo while (m != NULL) { 836251538Srpaulo next = m->m_next; 837251538Srpaulo m->m_next = NULL; 838251538Srpaulo wh = mtod(m, struct ieee80211_frame *); 839251538Srpaulo ni = ieee80211_find_rxnode(ic, 840251538Srpaulo (struct ieee80211_frame_min *)wh); 841251538Srpaulo nf = URTWN_NOISE_FLOOR; 842251538Srpaulo if (ni != NULL) { 843251538Srpaulo (void)ieee80211_input(ni, m, rssi, nf); 844251538Srpaulo ieee80211_free_node(ni); 845251538Srpaulo } else 846251538Srpaulo (void)ieee80211_input_all(ic, m, rssi, nf); 847251538Srpaulo m = next; 848251538Srpaulo } 849251538Srpaulo URTWN_LOCK(sc); 850251538Srpaulo break; 851251538Srpaulo default: 852251538Srpaulo /* needs it to the inactive queue due to a error. */ 853251538Srpaulo data = STAILQ_FIRST(&sc->sc_rx_active); 854251538Srpaulo if (data != NULL) { 855251538Srpaulo STAILQ_REMOVE_HEAD(&sc->sc_rx_active, next); 856251538Srpaulo STAILQ_INSERT_TAIL(&sc->sc_rx_inactive, data, next); 857251538Srpaulo } 858251538Srpaulo if (error != USB_ERR_CANCELLED) { 859251538Srpaulo usbd_xfer_set_stall(xfer); 860251538Srpaulo ifp->if_ierrors++; 861251538Srpaulo goto tr_setup; 862251538Srpaulo } 863251538Srpaulo break; 864251538Srpaulo } 865251538Srpaulo} 866251538Srpaulo 867251538Srpaulostatic void 868251538Srpaulourtwn_txeof(struct usb_xfer *xfer, struct urtwn_data *data) 869251538Srpaulo{ 870251538Srpaulo struct urtwn_softc *sc = usbd_xfer_softc(xfer); 871251538Srpaulo struct ifnet *ifp = sc->sc_ifp; 872251538Srpaulo struct mbuf *m; 873251538Srpaulo 874251538Srpaulo URTWN_ASSERT_LOCKED(sc); 875251538Srpaulo 876251538Srpaulo /* 877251538Srpaulo * Do any tx complete callback. Note this must be done before releasing 878251538Srpaulo * the node reference. 879251538Srpaulo */ 880251538Srpaulo if (data->m) { 881251538Srpaulo m = data->m; 882251538Srpaulo if (m->m_flags & M_TXCB) { 883251538Srpaulo /* XXX status? */ 884251538Srpaulo ieee80211_process_callback(data->ni, m, 0); 885251538Srpaulo } 886251538Srpaulo m_freem(m); 887251538Srpaulo data->m = NULL; 888251538Srpaulo } 889251538Srpaulo if (data->ni) { 890251538Srpaulo ieee80211_free_node(data->ni); 891251538Srpaulo data->ni = NULL; 892251538Srpaulo } 893251538Srpaulo sc->sc_txtimer = 0; 894251538Srpaulo ifp->if_opackets++; 895251538Srpaulo ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 896251538Srpaulo} 897251538Srpaulo 898251538Srpaulostatic void 899251538Srpaulourtwn_bulk_tx_callback(struct usb_xfer *xfer, usb_error_t error) 900251538Srpaulo{ 901251538Srpaulo struct urtwn_softc *sc = usbd_xfer_softc(xfer); 902251538Srpaulo struct ifnet *ifp = sc->sc_ifp; 903251538Srpaulo struct urtwn_data *data; 904251538Srpaulo 905251538Srpaulo URTWN_ASSERT_LOCKED(sc); 906251538Srpaulo 907251538Srpaulo switch (USB_GET_STATE(xfer)){ 908251538Srpaulo case USB_ST_TRANSFERRED: 909251538Srpaulo data = STAILQ_FIRST(&sc->sc_tx_active); 910251538Srpaulo if (data == NULL) 911251538Srpaulo goto tr_setup; 912251538Srpaulo STAILQ_REMOVE_HEAD(&sc->sc_tx_active, next); 913251538Srpaulo urtwn_txeof(xfer, data); 914251538Srpaulo STAILQ_INSERT_TAIL(&sc->sc_tx_inactive, data, next); 915251538Srpaulo /* FALLTHROUGH */ 916251538Srpaulo case USB_ST_SETUP: 917251538Srpaulotr_setup: 918251538Srpaulo data = STAILQ_FIRST(&sc->sc_tx_pending); 919251538Srpaulo if (data == NULL) { 920251538Srpaulo DPRINTF("%s: empty pending queue\n", __func__); 921251538Srpaulo return; 922251538Srpaulo } 923251538Srpaulo STAILQ_REMOVE_HEAD(&sc->sc_tx_pending, next); 924251538Srpaulo STAILQ_INSERT_TAIL(&sc->sc_tx_active, data, next); 925251538Srpaulo usbd_xfer_set_frame_data(xfer, 0, data->buf, data->buflen); 926251538Srpaulo usbd_transfer_submit(xfer); 927261961Srpaulo urtwn_start_locked(ifp, sc); 928251538Srpaulo break; 929251538Srpaulo default: 930251538Srpaulo data = STAILQ_FIRST(&sc->sc_tx_active); 931251538Srpaulo if (data == NULL) 932251538Srpaulo goto tr_setup; 933251538Srpaulo if (data->ni != NULL) { 934251538Srpaulo ieee80211_free_node(data->ni); 935251538Srpaulo data->ni = NULL; 936251538Srpaulo ifp->if_oerrors++; 937251538Srpaulo } 938251538Srpaulo if (error != USB_ERR_CANCELLED) { 939251538Srpaulo usbd_xfer_set_stall(xfer); 940251538Srpaulo goto tr_setup; 941251538Srpaulo } 942251538Srpaulo break; 943251538Srpaulo } 944251538Srpaulo} 945251538Srpaulo 946251538Srpaulostatic struct urtwn_data * 947251538Srpaulo_urtwn_getbuf(struct urtwn_softc *sc) 948251538Srpaulo{ 949251538Srpaulo struct urtwn_data *bf; 950251538Srpaulo 951251538Srpaulo bf = STAILQ_FIRST(&sc->sc_tx_inactive); 952251538Srpaulo if (bf != NULL) 953251538Srpaulo STAILQ_REMOVE_HEAD(&sc->sc_tx_inactive, next); 954251538Srpaulo else 955251538Srpaulo bf = NULL; 956251538Srpaulo if (bf == NULL) 957251538Srpaulo DPRINTF("%s: %s\n", __func__, "out of xmit buffers"); 958251538Srpaulo return (bf); 959251538Srpaulo} 960251538Srpaulo 961251538Srpaulostatic struct urtwn_data * 962251538Srpaulourtwn_getbuf(struct urtwn_softc *sc) 963251538Srpaulo{ 964251538Srpaulo struct urtwn_data *bf; 965251538Srpaulo 966251538Srpaulo URTWN_ASSERT_LOCKED(sc); 967251538Srpaulo 968251538Srpaulo bf = _urtwn_getbuf(sc); 969251538Srpaulo if (bf == NULL) { 970251538Srpaulo struct ifnet *ifp = sc->sc_ifp; 971251538Srpaulo DPRINTF("%s: stop queue\n", __func__); 972251538Srpaulo ifp->if_drv_flags |= IFF_DRV_OACTIVE; 973251538Srpaulo } 974251538Srpaulo return (bf); 975251538Srpaulo} 976251538Srpaulo 977251538Srpaulostatic int 978251538Srpaulourtwn_write_region_1(struct urtwn_softc *sc, uint16_t addr, uint8_t *buf, 979251538Srpaulo int len) 980251538Srpaulo{ 981251538Srpaulo usb_device_request_t req; 982251538Srpaulo 983251538Srpaulo req.bmRequestType = UT_WRITE_VENDOR_DEVICE; 984251538Srpaulo req.bRequest = R92C_REQ_REGS; 985251538Srpaulo USETW(req.wValue, addr); 986251538Srpaulo USETW(req.wIndex, 0); 987251538Srpaulo USETW(req.wLength, len); 988251538Srpaulo return (urtwn_do_request(sc, &req, buf)); 989251538Srpaulo} 990251538Srpaulo 991251538Srpaulostatic void 992251538Srpaulourtwn_write_1(struct urtwn_softc *sc, uint16_t addr, uint8_t val) 993251538Srpaulo{ 994251538Srpaulo urtwn_write_region_1(sc, addr, &val, 1); 995251538Srpaulo} 996251538Srpaulo 997251538Srpaulo 998251538Srpaulostatic void 999251538Srpaulourtwn_write_2(struct urtwn_softc *sc, uint16_t addr, uint16_t val) 1000251538Srpaulo{ 1001251538Srpaulo val = htole16(val); 1002251538Srpaulo urtwn_write_region_1(sc, addr, (uint8_t *)&val, 2); 1003251538Srpaulo} 1004251538Srpaulo 1005251538Srpaulostatic void 1006251538Srpaulourtwn_write_4(struct urtwn_softc *sc, uint16_t addr, uint32_t val) 1007251538Srpaulo{ 1008251538Srpaulo val = htole32(val); 1009251538Srpaulo urtwn_write_region_1(sc, addr, (uint8_t *)&val, 4); 1010251538Srpaulo} 1011251538Srpaulo 1012251538Srpaulostatic int 1013251538Srpaulourtwn_read_region_1(struct urtwn_softc *sc, uint16_t addr, uint8_t *buf, 1014251538Srpaulo int len) 1015251538Srpaulo{ 1016251538Srpaulo usb_device_request_t req; 1017251538Srpaulo 1018251538Srpaulo req.bmRequestType = UT_READ_VENDOR_DEVICE; 1019251538Srpaulo req.bRequest = R92C_REQ_REGS; 1020251538Srpaulo USETW(req.wValue, addr); 1021251538Srpaulo USETW(req.wIndex, 0); 1022251538Srpaulo USETW(req.wLength, len); 1023251538Srpaulo return (urtwn_do_request(sc, &req, buf)); 1024251538Srpaulo} 1025251538Srpaulo 1026251538Srpaulostatic uint8_t 1027251538Srpaulourtwn_read_1(struct urtwn_softc *sc, uint16_t addr) 1028251538Srpaulo{ 1029251538Srpaulo uint8_t val; 1030251538Srpaulo 1031251538Srpaulo if (urtwn_read_region_1(sc, addr, &val, 1) != 0) 1032251538Srpaulo return (0xff); 1033251538Srpaulo return (val); 1034251538Srpaulo} 1035251538Srpaulo 1036251538Srpaulostatic uint16_t 1037251538Srpaulourtwn_read_2(struct urtwn_softc *sc, uint16_t addr) 1038251538Srpaulo{ 1039251538Srpaulo uint16_t val; 1040251538Srpaulo 1041251538Srpaulo if (urtwn_read_region_1(sc, addr, (uint8_t *)&val, 2) != 0) 1042251538Srpaulo return (0xffff); 1043251538Srpaulo return (le16toh(val)); 1044251538Srpaulo} 1045251538Srpaulo 1046251538Srpaulostatic uint32_t 1047251538Srpaulourtwn_read_4(struct urtwn_softc *sc, uint16_t addr) 1048251538Srpaulo{ 1049251538Srpaulo uint32_t val; 1050251538Srpaulo 1051251538Srpaulo if (urtwn_read_region_1(sc, addr, (uint8_t *)&val, 4) != 0) 1052251538Srpaulo return (0xffffffff); 1053251538Srpaulo return (le32toh(val)); 1054251538Srpaulo} 1055251538Srpaulo 1056251538Srpaulostatic int 1057251538Srpaulourtwn_fw_cmd(struct urtwn_softc *sc, uint8_t id, const void *buf, int len) 1058251538Srpaulo{ 1059251538Srpaulo struct r92c_fw_cmd cmd; 1060251538Srpaulo int ntries; 1061251538Srpaulo 1062251538Srpaulo /* Wait for current FW box to be empty. */ 1063251538Srpaulo for (ntries = 0; ntries < 100; ntries++) { 1064251538Srpaulo if (!(urtwn_read_1(sc, R92C_HMETFR) & (1 << sc->fwcur))) 1065251538Srpaulo break; 1066266578Shselasky urtwn_ms_delay(sc); 1067251538Srpaulo } 1068251538Srpaulo if (ntries == 100) { 1069251538Srpaulo device_printf(sc->sc_dev, 1070251538Srpaulo "could not send firmware command\n"); 1071251538Srpaulo return (ETIMEDOUT); 1072251538Srpaulo } 1073251538Srpaulo memset(&cmd, 0, sizeof(cmd)); 1074251538Srpaulo cmd.id = id; 1075251538Srpaulo if (len > 3) 1076251538Srpaulo cmd.id |= R92C_CMD_FLAG_EXT; 1077251538Srpaulo KASSERT(len <= sizeof(cmd.msg), ("urtwn_fw_cmd\n")); 1078251538Srpaulo memcpy(cmd.msg, buf, len); 1079251538Srpaulo 1080251538Srpaulo /* Write the first word last since that will trigger the FW. */ 1081251538Srpaulo urtwn_write_region_1(sc, R92C_HMEBOX_EXT(sc->fwcur), 1082251538Srpaulo (uint8_t *)&cmd + 4, 2); 1083251538Srpaulo urtwn_write_region_1(sc, R92C_HMEBOX(sc->fwcur), 1084251538Srpaulo (uint8_t *)&cmd + 0, 4); 1085251538Srpaulo 1086251538Srpaulo sc->fwcur = (sc->fwcur + 1) % R92C_H2C_NBOX; 1087251538Srpaulo return (0); 1088251538Srpaulo} 1089251538Srpaulo 1090266578Shselaskystatic __inline void 1091251538Srpaulourtwn_rf_write(struct urtwn_softc *sc, int chain, uint8_t addr, uint32_t val) 1092251538Srpaulo{ 1093266578Shselasky 1094266578Shselasky sc->sc_rf_write(sc, chain, addr, val); 1095266578Shselasky} 1096266578Shselasky 1097266578Shselaskystatic void 1098266578Shselaskyurtwn_r92c_rf_write(struct urtwn_softc *sc, int chain, uint8_t addr, 1099266578Shselasky uint32_t val) 1100266578Shselasky{ 1101251538Srpaulo urtwn_bb_write(sc, R92C_LSSI_PARAM(chain), 1102251538Srpaulo SM(R92C_LSSI_PARAM_ADDR, addr) | 1103251538Srpaulo SM(R92C_LSSI_PARAM_DATA, val)); 1104251538Srpaulo} 1105251538Srpaulo 1106266578Shselaskystatic void 1107266578Shselaskyurtwn_r88e_rf_write(struct urtwn_softc *sc, int chain, uint8_t addr, 1108266578Shselaskyuint32_t val) 1109266578Shselasky{ 1110266578Shselasky urtwn_bb_write(sc, R92C_LSSI_PARAM(chain), 1111266578Shselasky SM(R88E_LSSI_PARAM_ADDR, addr) | 1112266578Shselasky SM(R92C_LSSI_PARAM_DATA, val)); 1113266578Shselasky} 1114266578Shselasky 1115251538Srpaulostatic uint32_t 1116251538Srpaulourtwn_rf_read(struct urtwn_softc *sc, int chain, uint8_t addr) 1117251538Srpaulo{ 1118251538Srpaulo uint32_t reg[R92C_MAX_CHAINS], val; 1119251538Srpaulo 1120251538Srpaulo reg[0] = urtwn_bb_read(sc, R92C_HSSI_PARAM2(0)); 1121251538Srpaulo if (chain != 0) 1122251538Srpaulo reg[chain] = urtwn_bb_read(sc, R92C_HSSI_PARAM2(chain)); 1123251538Srpaulo 1124251538Srpaulo urtwn_bb_write(sc, R92C_HSSI_PARAM2(0), 1125251538Srpaulo reg[0] & ~R92C_HSSI_PARAM2_READ_EDGE); 1126266578Shselasky urtwn_ms_delay(sc); 1127251538Srpaulo 1128251538Srpaulo urtwn_bb_write(sc, R92C_HSSI_PARAM2(chain), 1129251538Srpaulo RW(reg[chain], R92C_HSSI_PARAM2_READ_ADDR, addr) | 1130251538Srpaulo R92C_HSSI_PARAM2_READ_EDGE); 1131266578Shselasky urtwn_ms_delay(sc); 1132251538Srpaulo 1133251538Srpaulo urtwn_bb_write(sc, R92C_HSSI_PARAM2(0), 1134251538Srpaulo reg[0] | R92C_HSSI_PARAM2_READ_EDGE); 1135266578Shselasky urtwn_ms_delay(sc); 1136251538Srpaulo 1137251538Srpaulo if (urtwn_bb_read(sc, R92C_HSSI_PARAM1(chain)) & R92C_HSSI_PARAM1_PI) 1138251538Srpaulo val = urtwn_bb_read(sc, R92C_HSPI_READBACK(chain)); 1139251538Srpaulo else 1140251538Srpaulo val = urtwn_bb_read(sc, R92C_LSSI_READBACK(chain)); 1141251538Srpaulo return (MS(val, R92C_LSSI_READBACK_DATA)); 1142251538Srpaulo} 1143251538Srpaulo 1144251538Srpaulostatic int 1145251538Srpaulourtwn_llt_write(struct urtwn_softc *sc, uint32_t addr, uint32_t data) 1146251538Srpaulo{ 1147251538Srpaulo int ntries; 1148251538Srpaulo 1149251538Srpaulo urtwn_write_4(sc, R92C_LLT_INIT, 1150251538Srpaulo SM(R92C_LLT_INIT_OP, R92C_LLT_INIT_OP_WRITE) | 1151251538Srpaulo SM(R92C_LLT_INIT_ADDR, addr) | 1152251538Srpaulo SM(R92C_LLT_INIT_DATA, data)); 1153251538Srpaulo /* Wait for write operation to complete. */ 1154251538Srpaulo for (ntries = 0; ntries < 20; ntries++) { 1155251538Srpaulo if (MS(urtwn_read_4(sc, R92C_LLT_INIT), R92C_LLT_INIT_OP) == 1156251538Srpaulo R92C_LLT_INIT_OP_NO_ACTIVE) 1157251538Srpaulo return (0); 1158266578Shselasky urtwn_ms_delay(sc); 1159251538Srpaulo } 1160251538Srpaulo return (ETIMEDOUT); 1161251538Srpaulo} 1162251538Srpaulo 1163251538Srpaulostatic uint8_t 1164251538Srpaulourtwn_efuse_read_1(struct urtwn_softc *sc, uint16_t addr) 1165251538Srpaulo{ 1166251538Srpaulo uint32_t reg; 1167251538Srpaulo int ntries; 1168251538Srpaulo 1169251538Srpaulo reg = urtwn_read_4(sc, R92C_EFUSE_CTRL); 1170251538Srpaulo reg = RW(reg, R92C_EFUSE_CTRL_ADDR, addr); 1171251538Srpaulo reg &= ~R92C_EFUSE_CTRL_VALID; 1172251538Srpaulo urtwn_write_4(sc, R92C_EFUSE_CTRL, reg); 1173251538Srpaulo /* Wait for read operation to complete. */ 1174251538Srpaulo for (ntries = 0; ntries < 100; ntries++) { 1175251538Srpaulo reg = urtwn_read_4(sc, R92C_EFUSE_CTRL); 1176251538Srpaulo if (reg & R92C_EFUSE_CTRL_VALID) 1177251538Srpaulo return (MS(reg, R92C_EFUSE_CTRL_DATA)); 1178266578Shselasky urtwn_ms_delay(sc); 1179251538Srpaulo } 1180251538Srpaulo device_printf(sc->sc_dev, 1181251538Srpaulo "could not read efuse byte at address 0x%x\n", addr); 1182251538Srpaulo return (0xff); 1183251538Srpaulo} 1184251538Srpaulo 1185251538Srpaulostatic void 1186251538Srpaulourtwn_efuse_read(struct urtwn_softc *sc) 1187251538Srpaulo{ 1188251538Srpaulo uint8_t *rom = (uint8_t *)&sc->rom; 1189251538Srpaulo uint16_t addr = 0; 1190251538Srpaulo uint32_t reg; 1191282366Skevlo uint8_t off, msk, vol; 1192251538Srpaulo int i; 1193251538Srpaulo 1194266578Shselasky urtwn_efuse_switch_power(sc); 1195266578Shselasky 1196251538Srpaulo memset(&sc->rom, 0xff, sizeof(sc->rom)); 1197251538Srpaulo while (addr < 512) { 1198251538Srpaulo reg = urtwn_efuse_read_1(sc, addr); 1199251538Srpaulo if (reg == 0xff) 1200251538Srpaulo break; 1201251538Srpaulo addr++; 1202251538Srpaulo off = reg >> 4; 1203251538Srpaulo msk = reg & 0xf; 1204251538Srpaulo for (i = 0; i < 4; i++) { 1205251538Srpaulo if (msk & (1 << i)) 1206251538Srpaulo continue; 1207251538Srpaulo rom[off * 8 + i * 2 + 0] = 1208251538Srpaulo urtwn_efuse_read_1(sc, addr); 1209251538Srpaulo addr++; 1210251538Srpaulo rom[off * 8 + i * 2 + 1] = 1211251538Srpaulo urtwn_efuse_read_1(sc, addr); 1212251538Srpaulo addr++; 1213251538Srpaulo } 1214251538Srpaulo } 1215251538Srpaulo#ifdef URTWN_DEBUG 1216251538Srpaulo if (urtwn_debug >= 2) { 1217251538Srpaulo /* Dump ROM content. */ 1218251538Srpaulo printf("\n"); 1219251538Srpaulo for (i = 0; i < sizeof(sc->rom); i++) 1220251538Srpaulo printf("%02x:", rom[i]); 1221251538Srpaulo printf("\n"); 1222251538Srpaulo } 1223251538Srpaulo#endif 1224282366Skevlo /* Disable LDO 2.5V. */ 1225282366Skevlo vol = urtwn_read_1(sc, R92C_EFUSE_TEST + 3); 1226282366Skevlo urtwn_write_1(sc, R92C_EFUSE_TEST + 3, vol & ~(0x80)); 1227282366Skevlo 1228251538Srpaulo} 1229266578Shselaskystatic void 1230266578Shselaskyurtwn_efuse_switch_power(struct urtwn_softc *sc) 1231266578Shselasky{ 1232266578Shselasky uint32_t reg; 1233251538Srpaulo 1234282366Skevlo if (sc->chip & URTWN_CHIP_88E) 1235282366Skevlo urtwn_write_1(sc, R92C_EFUSE_ACCESS, R92C_EFUSE_ACCESS_ON); 1236282366Skevlo 1237266578Shselasky reg = urtwn_read_2(sc, R92C_SYS_ISO_CTRL); 1238266578Shselasky if (!(reg & R92C_SYS_ISO_CTRL_PWC_EV12V)) { 1239266578Shselasky urtwn_write_2(sc, R92C_SYS_ISO_CTRL, 1240266578Shselasky reg | R92C_SYS_ISO_CTRL_PWC_EV12V); 1241266578Shselasky } 1242266578Shselasky reg = urtwn_read_2(sc, R92C_SYS_FUNC_EN); 1243266578Shselasky if (!(reg & R92C_SYS_FUNC_EN_ELDR)) { 1244266578Shselasky urtwn_write_2(sc, R92C_SYS_FUNC_EN, 1245266578Shselasky reg | R92C_SYS_FUNC_EN_ELDR); 1246266578Shselasky } 1247266578Shselasky reg = urtwn_read_2(sc, R92C_SYS_CLKR); 1248266578Shselasky if ((reg & (R92C_SYS_CLKR_LOADER_EN | R92C_SYS_CLKR_ANA8M)) != 1249266578Shselasky (R92C_SYS_CLKR_LOADER_EN | R92C_SYS_CLKR_ANA8M)) { 1250266578Shselasky urtwn_write_2(sc, R92C_SYS_CLKR, 1251266578Shselasky reg | R92C_SYS_CLKR_LOADER_EN | R92C_SYS_CLKR_ANA8M); 1252266578Shselasky } 1253282366Skevlo 1254282366Skevlo if (!(sc->chip & URTWN_CHIP_88E)) { 1255282366Skevlo uint8_t vol; 1256282366Skevlo 1257282366Skevlo /* Enable LDO 2.5V. */ 1258282366Skevlo vol = urtwn_read_1(sc, R92C_EFUSE_TEST + 3); 1259282366Skevlo vol &= 0x0f; 1260282366Skevlo vol |= 0x30; 1261282366Skevlo urtwn_write_1(sc, R92C_EFUSE_TEST + 3, (vol | 0x80)); 1262282366Skevlo } 1263266578Shselasky} 1264266578Shselasky 1265251538Srpaulostatic int 1266251538Srpaulourtwn_read_chipid(struct urtwn_softc *sc) 1267251538Srpaulo{ 1268251538Srpaulo uint32_t reg; 1269251538Srpaulo 1270266578Shselasky if (sc->chip & URTWN_CHIP_88E) 1271266578Shselasky return (0); 1272266578Shselasky 1273251538Srpaulo reg = urtwn_read_4(sc, R92C_SYS_CFG); 1274251538Srpaulo if (reg & R92C_SYS_CFG_TRP_VAUX_EN) 1275251538Srpaulo return (EIO); 1276251538Srpaulo 1277251538Srpaulo if (reg & R92C_SYS_CFG_TYPE_92C) { 1278251538Srpaulo sc->chip |= URTWN_CHIP_92C; 1279251538Srpaulo /* Check if it is a castrated 8192C. */ 1280251538Srpaulo if (MS(urtwn_read_4(sc, R92C_HPON_FSM), 1281251538Srpaulo R92C_HPON_FSM_CHIP_BONDING_ID) == 1282251538Srpaulo R92C_HPON_FSM_CHIP_BONDING_ID_92C_1T2R) 1283251538Srpaulo sc->chip |= URTWN_CHIP_92C_1T2R; 1284251538Srpaulo } 1285251538Srpaulo if (reg & R92C_SYS_CFG_VENDOR_UMC) { 1286251538Srpaulo sc->chip |= URTWN_CHIP_UMC; 1287251538Srpaulo if (MS(reg, R92C_SYS_CFG_CHIP_VER_RTL) == 0) 1288251538Srpaulo sc->chip |= URTWN_CHIP_UMC_A_CUT; 1289251538Srpaulo } 1290251538Srpaulo return (0); 1291251538Srpaulo} 1292251538Srpaulo 1293251538Srpaulostatic void 1294251538Srpaulourtwn_read_rom(struct urtwn_softc *sc) 1295251538Srpaulo{ 1296251538Srpaulo struct r92c_rom *rom = &sc->rom; 1297251538Srpaulo 1298251538Srpaulo /* Read full ROM image. */ 1299251538Srpaulo urtwn_efuse_read(sc); 1300251538Srpaulo 1301251538Srpaulo /* XXX Weird but this is what the vendor driver does. */ 1302251538Srpaulo sc->pa_setting = urtwn_efuse_read_1(sc, 0x1fa); 1303251538Srpaulo DPRINTF("PA setting=0x%x\n", sc->pa_setting); 1304251538Srpaulo 1305251538Srpaulo sc->board_type = MS(rom->rf_opt1, R92C_ROM_RF1_BOARD_TYPE); 1306251538Srpaulo 1307251538Srpaulo sc->regulatory = MS(rom->rf_opt1, R92C_ROM_RF1_REGULATORY); 1308251538Srpaulo DPRINTF("regulatory type=%d\n", sc->regulatory); 1309266578Shselasky IEEE80211_ADDR_COPY(sc->sc_bssid, rom->macaddr); 1310251538Srpaulo 1311266578Shselasky sc->sc_rf_write = urtwn_r92c_rf_write; 1312266578Shselasky sc->sc_power_on = urtwn_r92c_power_on; 1313266578Shselasky sc->sc_dma_init = urtwn_r92c_dma_init; 1314251538Srpaulo} 1315251538Srpaulo 1316266578Shselaskystatic void 1317266578Shselaskyurtwn_r88e_read_rom(struct urtwn_softc *sc) 1318266578Shselasky{ 1319266578Shselasky uint8_t *rom = sc->r88e_rom; 1320266578Shselasky uint16_t addr = 0; 1321266578Shselasky uint32_t reg; 1322266578Shselasky uint8_t off, msk, tmp; 1323266578Shselasky int i; 1324266578Shselasky 1325266578Shselasky off = 0; 1326266578Shselasky urtwn_efuse_switch_power(sc); 1327266578Shselasky 1328266578Shselasky /* Read full ROM image. */ 1329266578Shselasky memset(&sc->r88e_rom, 0xff, sizeof(sc->r88e_rom)); 1330282366Skevlo while (addr < 512) { 1331266578Shselasky reg = urtwn_efuse_read_1(sc, addr); 1332266578Shselasky if (reg == 0xff) 1333266578Shselasky break; 1334266578Shselasky addr++; 1335266578Shselasky if ((reg & 0x1f) == 0x0f) { 1336266578Shselasky tmp = (reg & 0xe0) >> 5; 1337266578Shselasky reg = urtwn_efuse_read_1(sc, addr); 1338266578Shselasky if ((reg & 0x0f) != 0x0f) 1339266578Shselasky off = ((reg & 0xf0) >> 1) | tmp; 1340266578Shselasky addr++; 1341266578Shselasky } else 1342266578Shselasky off = reg >> 4; 1343266578Shselasky msk = reg & 0xf; 1344266578Shselasky for (i = 0; i < 4; i++) { 1345266578Shselasky if (msk & (1 << i)) 1346266578Shselasky continue; 1347266578Shselasky rom[off * 8 + i * 2 + 0] = 1348266578Shselasky urtwn_efuse_read_1(sc, addr); 1349266578Shselasky addr++; 1350266578Shselasky rom[off * 8 + i * 2 + 1] = 1351266578Shselasky urtwn_efuse_read_1(sc, addr); 1352266578Shselasky addr++; 1353266578Shselasky } 1354266578Shselasky } 1355266578Shselasky 1356282366Skevlo urtwn_write_1(sc, R92C_EFUSE_ACCESS, R92C_EFUSE_ACCESS_OFF); 1357282366Skevlo 1358266578Shselasky addr = 0x10; 1359266578Shselasky for (i = 0; i < 6; i++) 1360266578Shselasky sc->cck_tx_pwr[i] = sc->r88e_rom[addr++]; 1361266578Shselasky for (i = 0; i < 5; i++) 1362266578Shselasky sc->ht40_tx_pwr[i] = sc->r88e_rom[addr++]; 1363266578Shselasky sc->bw20_tx_pwr_diff = (sc->r88e_rom[addr] & 0xf0) >> 4; 1364266578Shselasky if (sc->bw20_tx_pwr_diff & 0x08) 1365266578Shselasky sc->bw20_tx_pwr_diff |= 0xf0; 1366266578Shselasky sc->ofdm_tx_pwr_diff = (sc->r88e_rom[addr] & 0xf); 1367266578Shselasky if (sc->ofdm_tx_pwr_diff & 0x08) 1368266578Shselasky sc->ofdm_tx_pwr_diff |= 0xf0; 1369266578Shselasky sc->regulatory = MS(sc->r88e_rom[0xc1], R92C_ROM_RF1_REGULATORY); 1370266578Shselasky IEEE80211_ADDR_COPY(sc->sc_bssid, &sc->r88e_rom[0xd7]); 1371266578Shselasky 1372266578Shselasky sc->sc_rf_write = urtwn_r88e_rf_write; 1373266578Shselasky sc->sc_power_on = urtwn_r88e_power_on; 1374266578Shselasky sc->sc_dma_init = urtwn_r88e_dma_init; 1375266578Shselasky} 1376266578Shselasky 1377251538Srpaulo/* 1378251538Srpaulo * Initialize rate adaptation in firmware. 1379251538Srpaulo */ 1380251538Srpaulostatic int 1381251538Srpaulourtwn_ra_init(struct urtwn_softc *sc) 1382251538Srpaulo{ 1383251538Srpaulo static const uint8_t map[] = 1384251538Srpaulo { 2, 4, 11, 22, 12, 18, 24, 36, 48, 72, 96, 108 }; 1385251538Srpaulo struct ieee80211com *ic = sc->sc_ifp->if_l2com; 1386251538Srpaulo struct ieee80211vap *vap = TAILQ_FIRST(&ic->ic_vaps); 1387251538Srpaulo struct ieee80211_node *ni; 1388251538Srpaulo struct ieee80211_rateset *rs; 1389251538Srpaulo struct r92c_fw_cmd_macid_cfg cmd; 1390251538Srpaulo uint32_t rates, basicrates; 1391251538Srpaulo uint8_t mode; 1392251538Srpaulo int maxrate, maxbasicrate, error, i, j; 1393251538Srpaulo 1394251538Srpaulo ni = ieee80211_ref_node(vap->iv_bss); 1395251538Srpaulo rs = &ni->ni_rates; 1396251538Srpaulo 1397251538Srpaulo /* Get normal and basic rates mask. */ 1398251538Srpaulo rates = basicrates = 0; 1399251538Srpaulo maxrate = maxbasicrate = 0; 1400251538Srpaulo for (i = 0; i < rs->rs_nrates; i++) { 1401251538Srpaulo /* Convert 802.11 rate to HW rate index. */ 1402251538Srpaulo for (j = 0; j < nitems(map); j++) 1403251538Srpaulo if ((rs->rs_rates[i] & IEEE80211_RATE_VAL) == map[j]) 1404251538Srpaulo break; 1405251538Srpaulo if (j == nitems(map)) /* Unknown rate, skip. */ 1406251538Srpaulo continue; 1407251538Srpaulo rates |= 1 << j; 1408251538Srpaulo if (j > maxrate) 1409251538Srpaulo maxrate = j; 1410251538Srpaulo if (rs->rs_rates[i] & IEEE80211_RATE_BASIC) { 1411251538Srpaulo basicrates |= 1 << j; 1412251538Srpaulo if (j > maxbasicrate) 1413251538Srpaulo maxbasicrate = j; 1414251538Srpaulo } 1415251538Srpaulo } 1416251538Srpaulo if (ic->ic_curmode == IEEE80211_MODE_11B) 1417251538Srpaulo mode = R92C_RAID_11B; 1418251538Srpaulo else 1419251538Srpaulo mode = R92C_RAID_11BG; 1420251538Srpaulo DPRINTF("mode=0x%x rates=0x%08x, basicrates=0x%08x\n", 1421251538Srpaulo mode, rates, basicrates); 1422251538Srpaulo 1423251538Srpaulo /* Set rates mask for group addressed frames. */ 1424251538Srpaulo cmd.macid = URTWN_MACID_BC | URTWN_MACID_VALID; 1425251538Srpaulo cmd.mask = htole32(mode << 28 | basicrates); 1426251538Srpaulo error = urtwn_fw_cmd(sc, R92C_CMD_MACID_CONFIG, &cmd, sizeof(cmd)); 1427251538Srpaulo if (error != 0) { 1428252401Srpaulo ieee80211_free_node(ni); 1429251538Srpaulo device_printf(sc->sc_dev, 1430251538Srpaulo "could not add broadcast station\n"); 1431251538Srpaulo return (error); 1432251538Srpaulo } 1433251538Srpaulo /* Set initial MRR rate. */ 1434251538Srpaulo DPRINTF("maxbasicrate=%d\n", maxbasicrate); 1435251538Srpaulo urtwn_write_1(sc, R92C_INIDATA_RATE_SEL(URTWN_MACID_BC), 1436251538Srpaulo maxbasicrate); 1437251538Srpaulo 1438251538Srpaulo /* Set rates mask for unicast frames. */ 1439251538Srpaulo cmd.macid = URTWN_MACID_BSS | URTWN_MACID_VALID; 1440251538Srpaulo cmd.mask = htole32(mode << 28 | rates); 1441251538Srpaulo error = urtwn_fw_cmd(sc, R92C_CMD_MACID_CONFIG, &cmd, sizeof(cmd)); 1442251538Srpaulo if (error != 0) { 1443252401Srpaulo ieee80211_free_node(ni); 1444251538Srpaulo device_printf(sc->sc_dev, "could not add BSS station\n"); 1445251538Srpaulo return (error); 1446251538Srpaulo } 1447251538Srpaulo /* Set initial MRR rate. */ 1448251538Srpaulo DPRINTF("maxrate=%d\n", maxrate); 1449251538Srpaulo urtwn_write_1(sc, R92C_INIDATA_RATE_SEL(URTWN_MACID_BSS), 1450251538Srpaulo maxrate); 1451251538Srpaulo 1452251538Srpaulo /* Indicate highest supported rate. */ 1453252403Srpaulo ni->ni_txrate = rs->rs_rates[rs->rs_nrates - 1]; 1454252401Srpaulo ieee80211_free_node(ni); 1455252401Srpaulo 1456251538Srpaulo return (0); 1457251538Srpaulo} 1458251538Srpaulo 1459251538Srpaulovoid 1460251538Srpaulourtwn_tsf_sync_enable(struct urtwn_softc *sc) 1461251538Srpaulo{ 1462251538Srpaulo struct ifnet *ifp = sc->sc_ifp; 1463251538Srpaulo struct ieee80211com *ic = ifp->if_l2com; 1464251538Srpaulo struct ieee80211vap *vap = TAILQ_FIRST(&ic->ic_vaps); 1465251538Srpaulo struct ieee80211_node *ni = vap->iv_bss; 1466251538Srpaulo 1467251538Srpaulo uint64_t tsf; 1468251538Srpaulo 1469251538Srpaulo /* Enable TSF synchronization. */ 1470251538Srpaulo urtwn_write_1(sc, R92C_BCN_CTRL, 1471251538Srpaulo urtwn_read_1(sc, R92C_BCN_CTRL) & ~R92C_BCN_CTRL_DIS_TSF_UDT0); 1472251538Srpaulo 1473251538Srpaulo urtwn_write_1(sc, R92C_BCN_CTRL, 1474251538Srpaulo urtwn_read_1(sc, R92C_BCN_CTRL) & ~R92C_BCN_CTRL_EN_BCN); 1475251538Srpaulo 1476251538Srpaulo /* Set initial TSF. */ 1477251538Srpaulo memcpy(&tsf, ni->ni_tstamp.data, 8); 1478251538Srpaulo tsf = le64toh(tsf); 1479251538Srpaulo tsf = tsf - (tsf % (vap->iv_bss->ni_intval * IEEE80211_DUR_TU)); 1480251538Srpaulo tsf -= IEEE80211_DUR_TU; 1481251538Srpaulo urtwn_write_4(sc, R92C_TSFTR + 0, tsf); 1482251538Srpaulo urtwn_write_4(sc, R92C_TSFTR + 4, tsf >> 32); 1483251538Srpaulo 1484251538Srpaulo urtwn_write_1(sc, R92C_BCN_CTRL, 1485251538Srpaulo urtwn_read_1(sc, R92C_BCN_CTRL) | R92C_BCN_CTRL_EN_BCN); 1486251538Srpaulo} 1487251538Srpaulo 1488251538Srpaulostatic void 1489251538Srpaulourtwn_set_led(struct urtwn_softc *sc, int led, int on) 1490251538Srpaulo{ 1491251538Srpaulo uint8_t reg; 1492266578Shselasky 1493251538Srpaulo if (led == URTWN_LED_LINK) { 1494266578Shselasky if (sc->chip & URTWN_CHIP_88E) { 1495266578Shselasky reg = urtwn_read_1(sc, R92C_LEDCFG2) & 0xf0; 1496266578Shselasky urtwn_write_1(sc, R92C_LEDCFG2, reg | 0x60); 1497266578Shselasky if (!on) { 1498266578Shselasky reg = urtwn_read_1(sc, R92C_LEDCFG2) & 0x90; 1499266578Shselasky urtwn_write_1(sc, R92C_LEDCFG2, 1500266578Shselasky reg | R92C_LEDCFG0_DIS); 1501266578Shselasky urtwn_write_1(sc, R92C_MAC_PINMUX_CFG, 1502266578Shselasky urtwn_read_1(sc, R92C_MAC_PINMUX_CFG) & 1503266578Shselasky 0xfe); 1504266578Shselasky } 1505266578Shselasky } else { 1506266578Shselasky reg = urtwn_read_1(sc, R92C_LEDCFG0) & 0x70; 1507266578Shselasky if (!on) 1508266578Shselasky reg |= R92C_LEDCFG0_DIS; 1509266578Shselasky urtwn_write_1(sc, R92C_LEDCFG0, reg); 1510266578Shselasky } 1511266578Shselasky sc->ledlink = on; /* Save LED state. */ 1512251538Srpaulo } 1513251538Srpaulo} 1514251538Srpaulo 1515251538Srpaulostatic int 1516251538Srpaulourtwn_newstate(struct ieee80211vap *vap, enum ieee80211_state nstate, int arg) 1517251538Srpaulo{ 1518251538Srpaulo struct urtwn_vap *uvp = URTWN_VAP(vap); 1519251538Srpaulo struct ieee80211com *ic = vap->iv_ic; 1520251538Srpaulo struct urtwn_softc *sc = ic->ic_ifp->if_softc; 1521251538Srpaulo struct ieee80211_node *ni; 1522251538Srpaulo enum ieee80211_state ostate; 1523251538Srpaulo uint32_t reg; 1524251538Srpaulo 1525251538Srpaulo ostate = vap->iv_state; 1526251538Srpaulo DPRINTF("%s -> %s\n", ieee80211_state_name[ostate], 1527251538Srpaulo ieee80211_state_name[nstate]); 1528251538Srpaulo 1529251538Srpaulo IEEE80211_UNLOCK(ic); 1530251538Srpaulo URTWN_LOCK(sc); 1531251538Srpaulo callout_stop(&sc->sc_watchdog_ch); 1532251538Srpaulo 1533251538Srpaulo if (ostate == IEEE80211_S_RUN) { 1534251538Srpaulo /* Turn link LED off. */ 1535251538Srpaulo urtwn_set_led(sc, URTWN_LED_LINK, 0); 1536251538Srpaulo 1537251538Srpaulo /* Set media status to 'No Link'. */ 1538251538Srpaulo reg = urtwn_read_4(sc, R92C_CR); 1539251538Srpaulo reg = RW(reg, R92C_CR_NETTYPE, R92C_CR_NETTYPE_NOLINK); 1540251538Srpaulo urtwn_write_4(sc, R92C_CR, reg); 1541251538Srpaulo 1542251538Srpaulo /* Stop Rx of data frames. */ 1543251538Srpaulo urtwn_write_2(sc, R92C_RXFLTMAP2, 0); 1544251538Srpaulo 1545251538Srpaulo /* Rest TSF. */ 1546251538Srpaulo urtwn_write_1(sc, R92C_DUAL_TSF_RST, 0x03); 1547251538Srpaulo 1548251538Srpaulo /* Disable TSF synchronization. */ 1549251538Srpaulo urtwn_write_1(sc, R92C_BCN_CTRL, 1550251538Srpaulo urtwn_read_1(sc, R92C_BCN_CTRL) | 1551251538Srpaulo R92C_BCN_CTRL_DIS_TSF_UDT0); 1552251538Srpaulo 1553251538Srpaulo /* Reset EDCA parameters. */ 1554251538Srpaulo urtwn_write_4(sc, R92C_EDCA_VO_PARAM, 0x002f3217); 1555251538Srpaulo urtwn_write_4(sc, R92C_EDCA_VI_PARAM, 0x005e4317); 1556251538Srpaulo urtwn_write_4(sc, R92C_EDCA_BE_PARAM, 0x00105320); 1557251538Srpaulo urtwn_write_4(sc, R92C_EDCA_BK_PARAM, 0x0000a444); 1558251538Srpaulo } 1559251538Srpaulo 1560251538Srpaulo switch (nstate) { 1561251538Srpaulo case IEEE80211_S_INIT: 1562251538Srpaulo /* Turn link LED off. */ 1563251538Srpaulo urtwn_set_led(sc, URTWN_LED_LINK, 0); 1564251538Srpaulo break; 1565251538Srpaulo case IEEE80211_S_SCAN: 1566251538Srpaulo if (ostate != IEEE80211_S_SCAN) { 1567251538Srpaulo /* Allow Rx from any BSSID. */ 1568251538Srpaulo urtwn_write_4(sc, R92C_RCR, 1569251538Srpaulo urtwn_read_4(sc, R92C_RCR) & 1570251538Srpaulo ~(R92C_RCR_CBSSID_DATA | R92C_RCR_CBSSID_BCN)); 1571251538Srpaulo 1572251538Srpaulo /* Set gain for scanning. */ 1573251538Srpaulo reg = urtwn_bb_read(sc, R92C_OFDM0_AGCCORE1(0)); 1574251538Srpaulo reg = RW(reg, R92C_OFDM0_AGCCORE1_GAIN, 0x20); 1575251538Srpaulo urtwn_bb_write(sc, R92C_OFDM0_AGCCORE1(0), reg); 1576251538Srpaulo 1577266578Shselasky if (!(sc->chip & URTWN_CHIP_88E)) { 1578266578Shselasky reg = urtwn_bb_read(sc, R92C_OFDM0_AGCCORE1(1)); 1579266578Shselasky reg = RW(reg, R92C_OFDM0_AGCCORE1_GAIN, 0x20); 1580266578Shselasky urtwn_bb_write(sc, R92C_OFDM0_AGCCORE1(1), reg); 1581266578Shselasky } 1582251538Srpaulo } 1583251538Srpaulo /* Pause AC Tx queues. */ 1584251538Srpaulo urtwn_write_1(sc, R92C_TXPAUSE, 1585251538Srpaulo urtwn_read_1(sc, R92C_TXPAUSE) | 0x0f); 1586251538Srpaulo break; 1587251538Srpaulo case IEEE80211_S_AUTH: 1588251538Srpaulo /* Set initial gain under link. */ 1589251538Srpaulo reg = urtwn_bb_read(sc, R92C_OFDM0_AGCCORE1(0)); 1590251538Srpaulo reg = RW(reg, R92C_OFDM0_AGCCORE1_GAIN, 0x32); 1591251538Srpaulo urtwn_bb_write(sc, R92C_OFDM0_AGCCORE1(0), reg); 1592251538Srpaulo 1593266578Shselasky if (!(sc->chip & URTWN_CHIP_88E)) { 1594266578Shselasky reg = urtwn_bb_read(sc, R92C_OFDM0_AGCCORE1(1)); 1595266578Shselasky reg = RW(reg, R92C_OFDM0_AGCCORE1_GAIN, 0x32); 1596266578Shselasky urtwn_bb_write(sc, R92C_OFDM0_AGCCORE1(1), reg); 1597266578Shselasky } 1598251538Srpaulo urtwn_set_chan(sc, ic->ic_curchan, NULL); 1599251538Srpaulo break; 1600251538Srpaulo case IEEE80211_S_RUN: 1601251538Srpaulo if (vap->iv_opmode == IEEE80211_M_MONITOR) { 1602251538Srpaulo /* Enable Rx of data frames. */ 1603251538Srpaulo urtwn_write_2(sc, R92C_RXFLTMAP2, 0xffff); 1604251538Srpaulo 1605251538Srpaulo /* Turn link LED on. */ 1606251538Srpaulo urtwn_set_led(sc, URTWN_LED_LINK, 1); 1607251538Srpaulo break; 1608251538Srpaulo } 1609251538Srpaulo 1610251538Srpaulo ni = ieee80211_ref_node(vap->iv_bss); 1611251538Srpaulo /* Set media status to 'Associated'. */ 1612251538Srpaulo reg = urtwn_read_4(sc, R92C_CR); 1613251538Srpaulo reg = RW(reg, R92C_CR_NETTYPE, R92C_CR_NETTYPE_INFRA); 1614251538Srpaulo urtwn_write_4(sc, R92C_CR, reg); 1615251538Srpaulo 1616251538Srpaulo /* Set BSSID. */ 1617251538Srpaulo urtwn_write_4(sc, R92C_BSSID + 0, LE_READ_4(&ni->ni_bssid[0])); 1618251538Srpaulo urtwn_write_4(sc, R92C_BSSID + 4, LE_READ_2(&ni->ni_bssid[4])); 1619251538Srpaulo 1620251538Srpaulo if (ic->ic_curmode == IEEE80211_MODE_11B) 1621251538Srpaulo urtwn_write_1(sc, R92C_INIRTS_RATE_SEL, 0); 1622251538Srpaulo else /* 802.11b/g */ 1623251538Srpaulo urtwn_write_1(sc, R92C_INIRTS_RATE_SEL, 3); 1624251538Srpaulo 1625251538Srpaulo /* Enable Rx of data frames. */ 1626251538Srpaulo urtwn_write_2(sc, R92C_RXFLTMAP2, 0xffff); 1627251538Srpaulo 1628251538Srpaulo /* Flush all AC queues. */ 1629251538Srpaulo urtwn_write_1(sc, R92C_TXPAUSE, 0); 1630251538Srpaulo 1631251538Srpaulo /* Set beacon interval. */ 1632251538Srpaulo urtwn_write_2(sc, R92C_BCN_INTERVAL, ni->ni_intval); 1633251538Srpaulo 1634251538Srpaulo /* Allow Rx from our BSSID only. */ 1635251538Srpaulo urtwn_write_4(sc, R92C_RCR, 1636251538Srpaulo urtwn_read_4(sc, R92C_RCR) | 1637251538Srpaulo R92C_RCR_CBSSID_DATA | R92C_RCR_CBSSID_BCN); 1638251538Srpaulo 1639251538Srpaulo /* Enable TSF synchronization. */ 1640251538Srpaulo urtwn_tsf_sync_enable(sc); 1641251538Srpaulo 1642251538Srpaulo urtwn_write_1(sc, R92C_SIFS_CCK + 1, 10); 1643251538Srpaulo urtwn_write_1(sc, R92C_SIFS_OFDM + 1, 10); 1644251538Srpaulo urtwn_write_1(sc, R92C_SPEC_SIFS + 1, 10); 1645251538Srpaulo urtwn_write_1(sc, R92C_MAC_SPEC_SIFS + 1, 10); 1646251538Srpaulo urtwn_write_1(sc, R92C_R2T_SIFS + 1, 10); 1647251538Srpaulo urtwn_write_1(sc, R92C_T2T_SIFS + 1, 10); 1648251538Srpaulo 1649251538Srpaulo /* Intialize rate adaptation. */ 1650266578Shselasky if (sc->chip & URTWN_CHIP_88E) 1651266578Shselasky ni->ni_txrate = 1652266578Shselasky ni->ni_rates.rs_rates[ni->ni_rates.rs_nrates-1]; 1653266578Shselasky else 1654266578Shselasky urtwn_ra_init(sc); 1655251538Srpaulo /* Turn link LED on. */ 1656251538Srpaulo urtwn_set_led(sc, URTWN_LED_LINK, 1); 1657251538Srpaulo 1658251538Srpaulo sc->avg_pwdb = -1; /* Reset average RSSI. */ 1659251538Srpaulo /* Reset temperature calibration state machine. */ 1660251538Srpaulo sc->thcal_state = 0; 1661251538Srpaulo sc->thcal_lctemp = 0; 1662251538Srpaulo ieee80211_free_node(ni); 1663251538Srpaulo break; 1664251538Srpaulo default: 1665251538Srpaulo break; 1666251538Srpaulo } 1667251538Srpaulo URTWN_UNLOCK(sc); 1668251538Srpaulo IEEE80211_LOCK(ic); 1669251538Srpaulo return(uvp->newstate(vap, nstate, arg)); 1670251538Srpaulo} 1671251538Srpaulo 1672251538Srpaulostatic void 1673251538Srpaulourtwn_watchdog(void *arg) 1674251538Srpaulo{ 1675251538Srpaulo struct urtwn_softc *sc = arg; 1676251538Srpaulo struct ifnet *ifp = sc->sc_ifp; 1677251538Srpaulo 1678251538Srpaulo if (sc->sc_txtimer > 0) { 1679251538Srpaulo if (--sc->sc_txtimer == 0) { 1680251538Srpaulo device_printf(sc->sc_dev, "device timeout\n"); 1681251538Srpaulo ifp->if_oerrors++; 1682251538Srpaulo return; 1683251538Srpaulo } 1684251538Srpaulo callout_reset(&sc->sc_watchdog_ch, hz, urtwn_watchdog, sc); 1685251538Srpaulo } 1686251538Srpaulo} 1687251538Srpaulo 1688251538Srpaulostatic void 1689251538Srpaulourtwn_update_avgrssi(struct urtwn_softc *sc, int rate, int8_t rssi) 1690251538Srpaulo{ 1691251538Srpaulo int pwdb; 1692251538Srpaulo 1693251538Srpaulo /* Convert antenna signal to percentage. */ 1694251538Srpaulo if (rssi <= -100 || rssi >= 20) 1695251538Srpaulo pwdb = 0; 1696251538Srpaulo else if (rssi >= 0) 1697251538Srpaulo pwdb = 100; 1698251538Srpaulo else 1699251538Srpaulo pwdb = 100 + rssi; 1700266578Shselasky if (!(sc->chip & URTWN_CHIP_88E)) { 1701266578Shselasky if (rate <= 3) { 1702266578Shselasky /* CCK gain is smaller than OFDM/MCS gain. */ 1703266578Shselasky pwdb += 6; 1704266578Shselasky if (pwdb > 100) 1705266578Shselasky pwdb = 100; 1706266578Shselasky if (pwdb <= 14) 1707266578Shselasky pwdb -= 4; 1708266578Shselasky else if (pwdb <= 26) 1709266578Shselasky pwdb -= 8; 1710266578Shselasky else if (pwdb <= 34) 1711266578Shselasky pwdb -= 6; 1712266578Shselasky else if (pwdb <= 42) 1713266578Shselasky pwdb -= 2; 1714266578Shselasky } 1715251538Srpaulo } 1716251538Srpaulo if (sc->avg_pwdb == -1) /* Init. */ 1717251538Srpaulo sc->avg_pwdb = pwdb; 1718251538Srpaulo else if (sc->avg_pwdb < pwdb) 1719251538Srpaulo sc->avg_pwdb = ((sc->avg_pwdb * 19 + pwdb) / 20) + 1; 1720251538Srpaulo else 1721251538Srpaulo sc->avg_pwdb = ((sc->avg_pwdb * 19 + pwdb) / 20); 1722251538Srpaulo DPRINTFN(4, "PWDB=%d EMA=%d\n", pwdb, sc->avg_pwdb); 1723251538Srpaulo} 1724251538Srpaulo 1725251538Srpaulostatic int8_t 1726251538Srpaulourtwn_get_rssi(struct urtwn_softc *sc, int rate, void *physt) 1727251538Srpaulo{ 1728251538Srpaulo static const int8_t cckoff[] = { 16, -12, -26, -46 }; 1729251538Srpaulo struct r92c_rx_phystat *phy; 1730251538Srpaulo struct r92c_rx_cck *cck; 1731251538Srpaulo uint8_t rpt; 1732251538Srpaulo int8_t rssi; 1733251538Srpaulo 1734251538Srpaulo if (rate <= 3) { 1735251538Srpaulo cck = (struct r92c_rx_cck *)physt; 1736251538Srpaulo if (sc->sc_flags & URTWN_FLAG_CCK_HIPWR) { 1737251538Srpaulo rpt = (cck->agc_rpt >> 5) & 0x3; 1738251538Srpaulo rssi = (cck->agc_rpt & 0x1f) << 1; 1739251538Srpaulo } else { 1740251538Srpaulo rpt = (cck->agc_rpt >> 6) & 0x3; 1741251538Srpaulo rssi = cck->agc_rpt & 0x3e; 1742251538Srpaulo } 1743251538Srpaulo rssi = cckoff[rpt] - rssi; 1744251538Srpaulo } else { /* OFDM/HT. */ 1745251538Srpaulo phy = (struct r92c_rx_phystat *)physt; 1746251538Srpaulo rssi = ((le32toh(phy->phydw1) >> 1) & 0x7f) - 110; 1747251538Srpaulo } 1748251538Srpaulo return (rssi); 1749251538Srpaulo} 1750251538Srpaulo 1751266578Shselaskystatic int8_t 1752266578Shselaskyurtwn_r88e_get_rssi(struct urtwn_softc *sc, int rate, void *physt) 1753266578Shselasky{ 1754266578Shselasky struct r92c_rx_phystat *phy; 1755266578Shselasky struct r88e_rx_cck *cck; 1756266578Shselasky uint8_t cck_agc_rpt, lna_idx, vga_idx; 1757266578Shselasky int8_t rssi; 1758266578Shselasky 1759266578Shselasky rssi = 0; 1760266578Shselasky if (rate <= 3) { 1761266578Shselasky cck = (struct r88e_rx_cck *)physt; 1762266578Shselasky cck_agc_rpt = cck->agc_rpt; 1763266578Shselasky lna_idx = (cck_agc_rpt & 0xe0) >> 5; 1764266578Shselasky vga_idx = cck_agc_rpt & 0x1f; 1765266578Shselasky switch (lna_idx) { 1766266578Shselasky case 7: 1767266578Shselasky if (vga_idx <= 27) 1768266578Shselasky rssi = -100 + 2* (27 - vga_idx); 1769266578Shselasky else 1770266578Shselasky rssi = -100; 1771266578Shselasky break; 1772266578Shselasky case 6: 1773266578Shselasky rssi = -48 + 2 * (2 - vga_idx); 1774266578Shselasky break; 1775266578Shselasky case 5: 1776266578Shselasky rssi = -42 + 2 * (7 - vga_idx); 1777266578Shselasky break; 1778266578Shselasky case 4: 1779266578Shselasky rssi = -36 + 2 * (7 - vga_idx); 1780266578Shselasky break; 1781266578Shselasky case 3: 1782266578Shselasky rssi = -24 + 2 * (7 - vga_idx); 1783266578Shselasky break; 1784266578Shselasky case 2: 1785266578Shselasky rssi = -12 + 2 * (5 - vga_idx); 1786266578Shselasky break; 1787266578Shselasky case 1: 1788266578Shselasky rssi = 8 - (2 * vga_idx); 1789266578Shselasky break; 1790266578Shselasky case 0: 1791266578Shselasky rssi = 14 - (2 * vga_idx); 1792266578Shselasky break; 1793266578Shselasky } 1794266578Shselasky rssi += 6; 1795266578Shselasky } else { /* OFDM/HT. */ 1796266578Shselasky phy = (struct r92c_rx_phystat *)physt; 1797266578Shselasky rssi = ((le32toh(phy->phydw1) >> 1) & 0x7f) - 110; 1798266578Shselasky } 1799266578Shselasky return (rssi); 1800266578Shselasky} 1801266578Shselasky 1802266578Shselasky 1803251538Srpaulostatic int 1804251538Srpaulourtwn_tx_start(struct urtwn_softc *sc, struct ieee80211_node *ni, 1805251538Srpaulo struct mbuf *m0, struct urtwn_data *data) 1806251538Srpaulo{ 1807251538Srpaulo struct ifnet *ifp = sc->sc_ifp; 1808251538Srpaulo struct ieee80211_frame *wh; 1809251538Srpaulo struct ieee80211_key *k; 1810251538Srpaulo struct ieee80211com *ic = ifp->if_l2com; 1811251538Srpaulo struct ieee80211vap *vap = ni->ni_vap; 1812251538Srpaulo struct usb_xfer *xfer; 1813251538Srpaulo struct r92c_tx_desc *txd; 1814251538Srpaulo uint8_t raid, type; 1815251538Srpaulo uint16_t sum; 1816251538Srpaulo int i, hasqos, xferlen; 1817251538Srpaulo struct usb_xfer *urtwn_pipes[4] = { 1818251538Srpaulo sc->sc_xfer[URTWN_BULK_TX_BE], 1819251538Srpaulo sc->sc_xfer[URTWN_BULK_TX_BK], 1820251538Srpaulo sc->sc_xfer[URTWN_BULK_TX_VI], 1821251538Srpaulo sc->sc_xfer[URTWN_BULK_TX_VO] 1822251538Srpaulo }; 1823251538Srpaulo 1824251538Srpaulo URTWN_ASSERT_LOCKED(sc); 1825251538Srpaulo 1826251538Srpaulo /* 1827251538Srpaulo * Software crypto. 1828251538Srpaulo */ 1829251538Srpaulo wh = mtod(m0, struct ieee80211_frame *); 1830266578Shselasky type = wh->i_fc[0] & IEEE80211_FC0_TYPE_MASK; 1831266578Shselasky 1832262007Skevlo if (wh->i_fc[1] & IEEE80211_FC1_PROTECTED) { 1833251538Srpaulo k = ieee80211_crypto_encap(ni, m0); 1834251538Srpaulo if (k == NULL) { 1835251538Srpaulo device_printf(sc->sc_dev, 1836251538Srpaulo "ieee80211_crypto_encap returns NULL.\n"); 1837251538Srpaulo /* XXX we don't expect the fragmented frames */ 1838251538Srpaulo m_freem(m0); 1839251538Srpaulo return (ENOBUFS); 1840251538Srpaulo } 1841251538Srpaulo 1842251538Srpaulo /* in case packet header moved, reset pointer */ 1843251538Srpaulo wh = mtod(m0, struct ieee80211_frame *); 1844251538Srpaulo } 1845251538Srpaulo 1846266578Shselasky switch (type) { 1847251538Srpaulo case IEEE80211_FC0_TYPE_CTL: 1848251538Srpaulo case IEEE80211_FC0_TYPE_MGT: 1849251538Srpaulo xfer = sc->sc_xfer[URTWN_BULK_TX_VO]; 1850251538Srpaulo break; 1851251538Srpaulo default: 1852251538Srpaulo KASSERT(M_WME_GETAC(m0) < 4, 1853251538Srpaulo ("unsupported WME pipe %d", M_WME_GETAC(m0))); 1854251538Srpaulo xfer = urtwn_pipes[M_WME_GETAC(m0)]; 1855251538Srpaulo break; 1856251538Srpaulo } 1857251538Srpaulo 1858251538Srpaulo hasqos = 0; 1859251538Srpaulo 1860251538Srpaulo /* Fill Tx descriptor. */ 1861251538Srpaulo txd = (struct r92c_tx_desc *)data->buf; 1862251538Srpaulo memset(txd, 0, sizeof(*txd)); 1863251538Srpaulo 1864251538Srpaulo txd->txdw0 |= htole32( 1865251538Srpaulo SM(R92C_TXDW0_PKTLEN, m0->m_pkthdr.len) | 1866251538Srpaulo SM(R92C_TXDW0_OFFSET, sizeof(*txd)) | 1867251538Srpaulo R92C_TXDW0_OWN | R92C_TXDW0_FSG | R92C_TXDW0_LSG); 1868251538Srpaulo if (IEEE80211_IS_MULTICAST(wh->i_addr1)) 1869251538Srpaulo txd->txdw0 |= htole32(R92C_TXDW0_BMCAST); 1870251538Srpaulo if (!IEEE80211_IS_MULTICAST(wh->i_addr1) && 1871251538Srpaulo type == IEEE80211_FC0_TYPE_DATA) { 1872251538Srpaulo if (ic->ic_curmode == IEEE80211_MODE_11B) 1873251538Srpaulo raid = R92C_RAID_11B; 1874251538Srpaulo else 1875251538Srpaulo raid = R92C_RAID_11BG; 1876266578Shselasky if (sc->chip & URTWN_CHIP_88E) { 1877266578Shselasky txd->txdw1 |= htole32( 1878266578Shselasky SM(R88E_TXDW1_MACID, URTWN_MACID_BSS) | 1879266578Shselasky SM(R92C_TXDW1_QSEL, R92C_TXDW1_QSEL_BE) | 1880266578Shselasky SM(R92C_TXDW1_RAID, raid)); 1881266578Shselasky txd->txdw2 |= htole32(R88E_TXDW2_AGGBK); 1882266578Shselasky } else { 1883266578Shselasky txd->txdw1 |= htole32( 1884266578Shselasky SM(R92C_TXDW1_MACID, URTWN_MACID_BSS) | 1885266578Shselasky SM(R92C_TXDW1_QSEL, R92C_TXDW1_QSEL_BE) | 1886266578Shselasky SM(R92C_TXDW1_RAID, raid) | R92C_TXDW1_AGGBK); 1887266578Shselasky } 1888251538Srpaulo if (ic->ic_flags & IEEE80211_F_USEPROT) { 1889251538Srpaulo if (ic->ic_protmode == IEEE80211_PROT_CTSONLY) { 1890251538Srpaulo txd->txdw4 |= htole32(R92C_TXDW4_CTS2SELF | 1891251538Srpaulo R92C_TXDW4_HWRTSEN); 1892251538Srpaulo } else if (ic->ic_protmode == IEEE80211_PROT_RTSCTS) { 1893251538Srpaulo txd->txdw4 |= htole32(R92C_TXDW4_RTSEN | 1894251538Srpaulo R92C_TXDW4_HWRTSEN); 1895251538Srpaulo } 1896251538Srpaulo } 1897251538Srpaulo /* Send RTS at OFDM24. */ 1898251538Srpaulo txd->txdw4 |= htole32(SM(R92C_TXDW4_RTSRATE, 8)); 1899251538Srpaulo txd->txdw5 |= htole32(0x0001ff00); 1900251538Srpaulo /* Send data at OFDM54. */ 1901266578Shselasky if (sc->chip & URTWN_CHIP_88E) 1902266578Shselasky txd->txdw5 |= htole32(0x13 & 0x3f); 1903266578Shselasky else 1904266578Shselasky txd->txdw5 |= htole32(SM(R92C_TXDW5_DATARATE, 11)); 1905251538Srpaulo } else { 1906251538Srpaulo txd->txdw1 |= htole32( 1907251538Srpaulo SM(R92C_TXDW1_MACID, 0) | 1908251538Srpaulo SM(R92C_TXDW1_QSEL, R92C_TXDW1_QSEL_MGNT) | 1909251538Srpaulo SM(R92C_TXDW1_RAID, R92C_RAID_11B)); 1910251538Srpaulo 1911251538Srpaulo /* Force CCK1. */ 1912251538Srpaulo txd->txdw4 |= htole32(R92C_TXDW4_DRVRATE); 1913251538Srpaulo txd->txdw5 |= htole32(SM(R92C_TXDW5_DATARATE, 0)); 1914251538Srpaulo } 1915251538Srpaulo /* Set sequence number (already little endian). */ 1916251538Srpaulo txd->txdseq |= *(uint16_t *)wh->i_seq; 1917251538Srpaulo 1918251538Srpaulo if (!hasqos) { 1919251538Srpaulo /* Use HW sequence numbering for non-QoS frames. */ 1920251538Srpaulo txd->txdw4 |= htole32(R92C_TXDW4_HWSEQ); 1921251538Srpaulo txd->txdseq |= htole16(0x8000); 1922251538Srpaulo } else 1923251538Srpaulo txd->txdw4 |= htole32(R92C_TXDW4_QOS); 1924251538Srpaulo 1925251538Srpaulo /* Compute Tx descriptor checksum. */ 1926251538Srpaulo sum = 0; 1927251538Srpaulo for (i = 0; i < sizeof(*txd) / 2; i++) 1928251538Srpaulo sum ^= ((uint16_t *)txd)[i]; 1929251538Srpaulo txd->txdsum = sum; /* NB: already little endian. */ 1930251538Srpaulo 1931251538Srpaulo if (ieee80211_radiotap_active_vap(vap)) { 1932251538Srpaulo struct urtwn_tx_radiotap_header *tap = &sc->sc_txtap; 1933251538Srpaulo 1934251538Srpaulo tap->wt_flags = 0; 1935251538Srpaulo tap->wt_chan_freq = htole16(ic->ic_curchan->ic_freq); 1936251538Srpaulo tap->wt_chan_flags = htole16(ic->ic_curchan->ic_flags); 1937251538Srpaulo ieee80211_radiotap_tx(vap, m0); 1938251538Srpaulo } 1939251538Srpaulo 1940251538Srpaulo xferlen = sizeof(*txd) + m0->m_pkthdr.len; 1941251538Srpaulo m_copydata(m0, 0, m0->m_pkthdr.len, (caddr_t)&txd[1]); 1942251538Srpaulo 1943251538Srpaulo data->buflen = xferlen; 1944251538Srpaulo data->ni = ni; 1945251538Srpaulo data->m = m0; 1946251538Srpaulo 1947251538Srpaulo STAILQ_INSERT_TAIL(&sc->sc_tx_pending, data, next); 1948251538Srpaulo usbd_transfer_start(xfer); 1949251538Srpaulo return (0); 1950251538Srpaulo} 1951251538Srpaulo 1952251538Srpaulostatic void 1953251538Srpaulourtwn_start(struct ifnet *ifp) 1954251538Srpaulo{ 1955251538Srpaulo struct urtwn_softc *sc = ifp->if_softc; 1956261961Srpaulo 1957261961Srpaulo if ((ifp->if_drv_flags & IFF_DRV_RUNNING) == 0) 1958261961Srpaulo return; 1959261961Srpaulo URTWN_LOCK(sc); 1960261961Srpaulo urtwn_start_locked(ifp, sc); 1961261961Srpaulo URTWN_UNLOCK(sc); 1962261961Srpaulo} 1963261961Srpaulo 1964261961Srpaulostatic void 1965261961Srpaulourtwn_start_locked(struct ifnet *ifp, struct urtwn_softc *sc) 1966261961Srpaulo{ 1967251538Srpaulo struct ieee80211_node *ni; 1968251538Srpaulo struct mbuf *m; 1969251538Srpaulo struct urtwn_data *bf; 1970251538Srpaulo 1971261961Srpaulo URTWN_ASSERT_LOCKED(sc); 1972251538Srpaulo for (;;) { 1973251538Srpaulo IFQ_DRV_DEQUEUE(&ifp->if_snd, m); 1974251538Srpaulo if (m == NULL) 1975251538Srpaulo break; 1976251538Srpaulo bf = urtwn_getbuf(sc); 1977251538Srpaulo if (bf == NULL) { 1978251538Srpaulo IFQ_DRV_PREPEND(&ifp->if_snd, m); 1979251538Srpaulo break; 1980251538Srpaulo } 1981251538Srpaulo ni = (struct ieee80211_node *)m->m_pkthdr.rcvif; 1982251538Srpaulo m->m_pkthdr.rcvif = NULL; 1983251538Srpaulo 1984251538Srpaulo if (urtwn_tx_start(sc, ni, m, bf) != 0) { 1985251538Srpaulo ifp->if_oerrors++; 1986251538Srpaulo STAILQ_INSERT_HEAD(&sc->sc_tx_inactive, bf, next); 1987251538Srpaulo ieee80211_free_node(ni); 1988251538Srpaulo break; 1989251538Srpaulo } 1990251538Srpaulo 1991251538Srpaulo sc->sc_txtimer = 5; 1992251538Srpaulo callout_reset(&sc->sc_watchdog_ch, hz, urtwn_watchdog, sc); 1993251538Srpaulo } 1994251538Srpaulo} 1995251538Srpaulo 1996251538Srpaulostatic int 1997251538Srpaulourtwn_ioctl(struct ifnet *ifp, u_long cmd, caddr_t data) 1998251538Srpaulo{ 1999263256Skevlo struct urtwn_softc *sc = ifp->if_softc; 2000251538Srpaulo struct ieee80211com *ic = ifp->if_l2com; 2001251538Srpaulo struct ifreq *ifr = (struct ifreq *) data; 2002251538Srpaulo int error = 0, startall = 0; 2003251538Srpaulo 2004263256Skevlo URTWN_LOCK(sc); 2005263256Skevlo error = (sc->sc_flags & URTWN_DETACHED) ? ENXIO : 0; 2006263256Skevlo URTWN_UNLOCK(sc); 2007263256Skevlo if (error != 0) 2008263256Skevlo return (error); 2009263256Skevlo 2010251538Srpaulo switch (cmd) { 2011251538Srpaulo case SIOCSIFFLAGS: 2012251538Srpaulo if (ifp->if_flags & IFF_UP) { 2013251538Srpaulo if ((ifp->if_drv_flags & IFF_DRV_RUNNING) == 0) { 2014251538Srpaulo urtwn_init(ifp->if_softc); 2015251538Srpaulo startall = 1; 2016251538Srpaulo } 2017251538Srpaulo } else { 2018251538Srpaulo if (ifp->if_drv_flags & IFF_DRV_RUNNING) 2019263256Skevlo urtwn_stop(ifp); 2020251538Srpaulo } 2021251538Srpaulo if (startall) 2022251538Srpaulo ieee80211_start_all(ic); 2023251538Srpaulo break; 2024251538Srpaulo case SIOCGIFMEDIA: 2025251538Srpaulo error = ifmedia_ioctl(ifp, ifr, &ic->ic_media, cmd); 2026251538Srpaulo break; 2027251538Srpaulo case SIOCGIFADDR: 2028251538Srpaulo error = ether_ioctl(ifp, cmd, data); 2029251538Srpaulo break; 2030251538Srpaulo default: 2031251538Srpaulo error = EINVAL; 2032251538Srpaulo break; 2033251538Srpaulo } 2034251538Srpaulo return (error); 2035251538Srpaulo} 2036251538Srpaulo 2037251538Srpaulostatic int 2038251538Srpaulourtwn_alloc_list(struct urtwn_softc *sc, struct urtwn_data data[], 2039251538Srpaulo int ndata, int maxsz) 2040251538Srpaulo{ 2041251538Srpaulo int i, error; 2042251538Srpaulo 2043251538Srpaulo for (i = 0; i < ndata; i++) { 2044251538Srpaulo struct urtwn_data *dp = &data[i]; 2045251538Srpaulo dp->sc = sc; 2046251538Srpaulo dp->m = NULL; 2047251538Srpaulo dp->buf = malloc(maxsz, M_USBDEV, M_NOWAIT); 2048251538Srpaulo if (dp->buf == NULL) { 2049251538Srpaulo device_printf(sc->sc_dev, 2050251538Srpaulo "could not allocate buffer\n"); 2051251538Srpaulo error = ENOMEM; 2052251538Srpaulo goto fail; 2053251538Srpaulo } 2054251538Srpaulo dp->ni = NULL; 2055251538Srpaulo } 2056251538Srpaulo 2057251538Srpaulo return (0); 2058251538Srpaulofail: 2059251538Srpaulo urtwn_free_list(sc, data, ndata); 2060251538Srpaulo return (error); 2061251538Srpaulo} 2062251538Srpaulo 2063251538Srpaulostatic int 2064251538Srpaulourtwn_alloc_rx_list(struct urtwn_softc *sc) 2065251538Srpaulo{ 2066251538Srpaulo int error, i; 2067251538Srpaulo 2068251538Srpaulo error = urtwn_alloc_list(sc, sc->sc_rx, URTWN_RX_LIST_COUNT, 2069251538Srpaulo URTWN_RXBUFSZ); 2070251538Srpaulo if (error != 0) 2071251538Srpaulo return (error); 2072251538Srpaulo 2073251538Srpaulo STAILQ_INIT(&sc->sc_rx_active); 2074251538Srpaulo STAILQ_INIT(&sc->sc_rx_inactive); 2075251538Srpaulo 2076251538Srpaulo for (i = 0; i < URTWN_RX_LIST_COUNT; i++) 2077251538Srpaulo STAILQ_INSERT_HEAD(&sc->sc_rx_inactive, &sc->sc_rx[i], next); 2078251538Srpaulo 2079251538Srpaulo return (0); 2080251538Srpaulo} 2081251538Srpaulo 2082251538Srpaulostatic int 2083251538Srpaulourtwn_alloc_tx_list(struct urtwn_softc *sc) 2084251538Srpaulo{ 2085251538Srpaulo int error, i; 2086251538Srpaulo 2087251538Srpaulo error = urtwn_alloc_list(sc, sc->sc_tx, URTWN_TX_LIST_COUNT, 2088251538Srpaulo URTWN_TXBUFSZ); 2089251538Srpaulo if (error != 0) 2090251538Srpaulo return (error); 2091251538Srpaulo 2092251538Srpaulo STAILQ_INIT(&sc->sc_tx_active); 2093251538Srpaulo STAILQ_INIT(&sc->sc_tx_inactive); 2094251538Srpaulo STAILQ_INIT(&sc->sc_tx_pending); 2095251538Srpaulo 2096251538Srpaulo for (i = 0; i < URTWN_TX_LIST_COUNT; i++) 2097251538Srpaulo STAILQ_INSERT_HEAD(&sc->sc_tx_inactive, &sc->sc_tx[i], next); 2098251538Srpaulo 2099251538Srpaulo return (0); 2100251538Srpaulo} 2101251538Srpaulo 2102266578Shselaskystatic __inline int 2103251538Srpaulourtwn_power_on(struct urtwn_softc *sc) 2104251538Srpaulo{ 2105266578Shselasky 2106266578Shselasky return sc->sc_power_on(sc); 2107266578Shselasky} 2108266578Shselasky 2109266578Shselaskystatic int 2110266578Shselaskyurtwn_r92c_power_on(struct urtwn_softc *sc) 2111266578Shselasky{ 2112251538Srpaulo uint32_t reg; 2113251538Srpaulo int ntries; 2114251538Srpaulo 2115251538Srpaulo /* Wait for autoload done bit. */ 2116251538Srpaulo for (ntries = 0; ntries < 1000; ntries++) { 2117251538Srpaulo if (urtwn_read_1(sc, R92C_APS_FSMCO) & R92C_APS_FSMCO_PFM_ALDN) 2118251538Srpaulo break; 2119266578Shselasky urtwn_ms_delay(sc); 2120251538Srpaulo } 2121251538Srpaulo if (ntries == 1000) { 2122251538Srpaulo device_printf(sc->sc_dev, 2123251538Srpaulo "timeout waiting for chip autoload\n"); 2124251538Srpaulo return (ETIMEDOUT); 2125251538Srpaulo } 2126251538Srpaulo 2127251538Srpaulo /* Unlock ISO/CLK/Power control register. */ 2128251538Srpaulo urtwn_write_1(sc, R92C_RSV_CTRL, 0); 2129251538Srpaulo /* Move SPS into PWM mode. */ 2130251538Srpaulo urtwn_write_1(sc, R92C_SPS0_CTRL, 0x2b); 2131266578Shselasky urtwn_ms_delay(sc); 2132251538Srpaulo 2133251538Srpaulo reg = urtwn_read_1(sc, R92C_LDOV12D_CTRL); 2134251538Srpaulo if (!(reg & R92C_LDOV12D_CTRL_LDV12_EN)) { 2135251538Srpaulo urtwn_write_1(sc, R92C_LDOV12D_CTRL, 2136251538Srpaulo reg | R92C_LDOV12D_CTRL_LDV12_EN); 2137266578Shselasky urtwn_ms_delay(sc); 2138251538Srpaulo urtwn_write_1(sc, R92C_SYS_ISO_CTRL, 2139251538Srpaulo urtwn_read_1(sc, R92C_SYS_ISO_CTRL) & 2140251538Srpaulo ~R92C_SYS_ISO_CTRL_MD2PP); 2141251538Srpaulo } 2142251538Srpaulo 2143251538Srpaulo /* Auto enable WLAN. */ 2144251538Srpaulo urtwn_write_2(sc, R92C_APS_FSMCO, 2145251538Srpaulo urtwn_read_2(sc, R92C_APS_FSMCO) | R92C_APS_FSMCO_APFM_ONMAC); 2146251538Srpaulo for (ntries = 0; ntries < 1000; ntries++) { 2147263000Skevlo if (!(urtwn_read_2(sc, R92C_APS_FSMCO) & 2148263000Skevlo R92C_APS_FSMCO_APFM_ONMAC)) 2149251538Srpaulo break; 2150266578Shselasky urtwn_ms_delay(sc); 2151251538Srpaulo } 2152251538Srpaulo if (ntries == 1000) { 2153251538Srpaulo device_printf(sc->sc_dev, 2154251538Srpaulo "timeout waiting for MAC auto ON\n"); 2155251538Srpaulo return (ETIMEDOUT); 2156251538Srpaulo } 2157251538Srpaulo 2158251538Srpaulo /* Enable radio, GPIO and LED functions. */ 2159251538Srpaulo urtwn_write_2(sc, R92C_APS_FSMCO, 2160251538Srpaulo R92C_APS_FSMCO_AFSM_HSUS | 2161251538Srpaulo R92C_APS_FSMCO_PDN_EN | 2162251538Srpaulo R92C_APS_FSMCO_PFM_ALDN); 2163251538Srpaulo /* Release RF digital isolation. */ 2164251538Srpaulo urtwn_write_2(sc, R92C_SYS_ISO_CTRL, 2165251538Srpaulo urtwn_read_2(sc, R92C_SYS_ISO_CTRL) & ~R92C_SYS_ISO_CTRL_DIOR); 2166251538Srpaulo 2167251538Srpaulo /* Initialize MAC. */ 2168251538Srpaulo urtwn_write_1(sc, R92C_APSD_CTRL, 2169251538Srpaulo urtwn_read_1(sc, R92C_APSD_CTRL) & ~R92C_APSD_CTRL_OFF); 2170251538Srpaulo for (ntries = 0; ntries < 200; ntries++) { 2171251538Srpaulo if (!(urtwn_read_1(sc, R92C_APSD_CTRL) & 2172251538Srpaulo R92C_APSD_CTRL_OFF_STATUS)) 2173251538Srpaulo break; 2174266578Shselasky urtwn_ms_delay(sc); 2175251538Srpaulo } 2176251538Srpaulo if (ntries == 200) { 2177251538Srpaulo device_printf(sc->sc_dev, 2178251538Srpaulo "timeout waiting for MAC initialization\n"); 2179251538Srpaulo return (ETIMEDOUT); 2180251538Srpaulo } 2181251538Srpaulo 2182251538Srpaulo /* Enable MAC DMA/WMAC/SCHEDULE/SEC blocks. */ 2183251538Srpaulo reg = urtwn_read_2(sc, R92C_CR); 2184251538Srpaulo reg |= R92C_CR_HCI_TXDMA_EN | R92C_CR_HCI_RXDMA_EN | 2185251538Srpaulo R92C_CR_TXDMA_EN | R92C_CR_RXDMA_EN | R92C_CR_PROTOCOL_EN | 2186251538Srpaulo R92C_CR_SCHEDULE_EN | R92C_CR_MACTXEN | R92C_CR_MACRXEN | 2187251538Srpaulo R92C_CR_ENSEC; 2188251538Srpaulo urtwn_write_2(sc, R92C_CR, reg); 2189251538Srpaulo 2190251538Srpaulo urtwn_write_1(sc, 0xfe10, 0x19); 2191251538Srpaulo return (0); 2192251538Srpaulo} 2193251538Srpaulo 2194251538Srpaulostatic int 2195266578Shselaskyurtwn_r88e_power_on(struct urtwn_softc *sc) 2196266578Shselasky{ 2197266578Shselasky uint32_t reg; 2198266578Shselasky int ntries; 2199266578Shselasky 2200266578Shselasky /* Wait for power ready bit. */ 2201266578Shselasky for (ntries = 0; ntries < 5000; ntries++) { 2202282366Skevlo if (urtwn_read_4(sc, R92C_APS_FSMCO) & R92C_APS_FSMCO_SUS_HOST) 2203266578Shselasky break; 2204266578Shselasky urtwn_ms_delay(sc); 2205266578Shselasky } 2206266578Shselasky if (ntries == 5000) { 2207266578Shselasky device_printf(sc->sc_dev, 2208266578Shselasky "timeout waiting for chip power up\n"); 2209266578Shselasky return (ETIMEDOUT); 2210266578Shselasky } 2211266578Shselasky 2212266578Shselasky /* Reset BB. */ 2213266578Shselasky urtwn_write_1(sc, R92C_SYS_FUNC_EN, 2214266578Shselasky urtwn_read_1(sc, R92C_SYS_FUNC_EN) & ~(R92C_SYS_FUNC_EN_BBRSTB | 2215266578Shselasky R92C_SYS_FUNC_EN_BB_GLB_RST)); 2216266578Shselasky 2217282366Skevlo urtwn_write_1(sc, R92C_AFE_XTAL_CTRL + 2, 2218282366Skevlo urtwn_read_1(sc, R92C_AFE_XTAL_CTRL + 2) | 0x80); 2219266578Shselasky 2220266578Shselasky /* Disable HWPDN. */ 2221282366Skevlo urtwn_write_2(sc, R92C_APS_FSMCO, 2222282366Skevlo urtwn_read_2(sc, R92C_APS_FSMCO) & ~R92C_APS_FSMCO_APDM_HPDN); 2223266578Shselasky 2224266578Shselasky /* Disable WL suspend. */ 2225282366Skevlo urtwn_write_2(sc, R92C_APS_FSMCO, 2226282366Skevlo urtwn_read_2(sc, R92C_APS_FSMCO) & 2227282366Skevlo ~(R92C_APS_FSMCO_AFSM_HSUS | R92C_APS_FSMCO_AFSM_PCIE)); 2228266578Shselasky 2229282366Skevlo urtwn_write_2(sc, R92C_APS_FSMCO, 2230282366Skevlo urtwn_read_2(sc, R92C_APS_FSMCO) | R92C_APS_FSMCO_APFM_ONMAC); 2231266578Shselasky for (ntries = 0; ntries < 5000; ntries++) { 2232282366Skevlo if (!(urtwn_read_2(sc, R92C_APS_FSMCO) & 2233282366Skevlo R92C_APS_FSMCO_APFM_ONMAC)) 2234266578Shselasky break; 2235266578Shselasky urtwn_ms_delay(sc); 2236266578Shselasky } 2237266578Shselasky if (ntries == 5000) 2238266578Shselasky return (ETIMEDOUT); 2239266578Shselasky 2240266578Shselasky /* Enable LDO normal mode. */ 2241282366Skevlo urtwn_write_1(sc, R92C_LPLDO_CTRL, 2242282366Skevlo urtwn_read_1(sc, R92C_LPLDO_CTRL) & ~0x10); 2243266578Shselasky 2244266578Shselasky /* Enable MAC DMA/WMAC/SCHEDULE/SEC blocks. */ 2245266578Shselasky urtwn_write_2(sc, R92C_CR, 0); 2246266578Shselasky reg = urtwn_read_2(sc, R92C_CR); 2247266578Shselasky reg |= R92C_CR_HCI_TXDMA_EN | R92C_CR_HCI_RXDMA_EN | 2248266578Shselasky R92C_CR_TXDMA_EN | R92C_CR_RXDMA_EN | R92C_CR_PROTOCOL_EN | 2249266578Shselasky R92C_CR_SCHEDULE_EN | R92C_CR_ENSEC | R92C_CR_CALTMR_EN; 2250266578Shselasky urtwn_write_2(sc, R92C_CR, reg); 2251266578Shselasky 2252266578Shselasky return (0); 2253266578Shselasky} 2254266578Shselasky 2255266578Shselaskystatic int 2256251538Srpaulourtwn_llt_init(struct urtwn_softc *sc) 2257251538Srpaulo{ 2258266578Shselasky int i, error, page_count, pktbuf_count; 2259251538Srpaulo 2260266578Shselasky page_count = (sc->chip & URTWN_CHIP_88E) ? 2261266578Shselasky R88E_TX_PAGE_COUNT : R92C_TX_PAGE_COUNT; 2262266578Shselasky pktbuf_count = (sc->chip & URTWN_CHIP_88E) ? 2263266578Shselasky R88E_TXPKTBUF_COUNT : R92C_TXPKTBUF_COUNT; 2264266578Shselasky 2265266578Shselasky /* Reserve pages [0; page_count]. */ 2266266578Shselasky for (i = 0; i < page_count; i++) { 2267251538Srpaulo if ((error = urtwn_llt_write(sc, i, i + 1)) != 0) 2268251538Srpaulo return (error); 2269251538Srpaulo } 2270251538Srpaulo /* NB: 0xff indicates end-of-list. */ 2271251538Srpaulo if ((error = urtwn_llt_write(sc, i, 0xff)) != 0) 2272251538Srpaulo return (error); 2273251538Srpaulo /* 2274266578Shselasky * Use pages [page_count + 1; pktbuf_count - 1] 2275251538Srpaulo * as ring buffer. 2276251538Srpaulo */ 2277266578Shselasky for (++i; i < pktbuf_count - 1; i++) { 2278251538Srpaulo if ((error = urtwn_llt_write(sc, i, i + 1)) != 0) 2279251538Srpaulo return (error); 2280251538Srpaulo } 2281251538Srpaulo /* Make the last page point to the beginning of the ring buffer. */ 2282266578Shselasky error = urtwn_llt_write(sc, i, page_count + 1); 2283251538Srpaulo return (error); 2284251538Srpaulo} 2285251538Srpaulo 2286251538Srpaulostatic void 2287251538Srpaulourtwn_fw_reset(struct urtwn_softc *sc) 2288251538Srpaulo{ 2289251538Srpaulo uint16_t reg; 2290251538Srpaulo int ntries; 2291251538Srpaulo 2292251538Srpaulo /* Tell 8051 to reset itself. */ 2293251538Srpaulo urtwn_write_1(sc, R92C_HMETFR + 3, 0x20); 2294251538Srpaulo 2295251538Srpaulo /* Wait until 8051 resets by itself. */ 2296251538Srpaulo for (ntries = 0; ntries < 100; ntries++) { 2297251538Srpaulo reg = urtwn_read_2(sc, R92C_SYS_FUNC_EN); 2298251538Srpaulo if (!(reg & R92C_SYS_FUNC_EN_CPUEN)) 2299251538Srpaulo return; 2300266578Shselasky urtwn_ms_delay(sc); 2301251538Srpaulo } 2302251538Srpaulo /* Force 8051 reset. */ 2303251538Srpaulo urtwn_write_2(sc, R92C_SYS_FUNC_EN, reg & ~R92C_SYS_FUNC_EN_CPUEN); 2304251538Srpaulo} 2305251538Srpaulo 2306266578Shselaskystatic void 2307266578Shselaskyurtwn_r88e_fw_reset(struct urtwn_softc *sc) 2308266578Shselasky{ 2309266578Shselasky uint16_t reg; 2310266578Shselasky 2311266578Shselasky reg = urtwn_read_2(sc, R92C_SYS_FUNC_EN); 2312266578Shselasky urtwn_write_2(sc, R92C_SYS_FUNC_EN, reg & ~R92C_SYS_FUNC_EN_CPUEN); 2313266578Shselasky urtwn_write_2(sc, R92C_SYS_FUNC_EN, reg | R92C_SYS_FUNC_EN_CPUEN); 2314266578Shselasky} 2315266578Shselasky 2316251538Srpaulostatic int 2317251538Srpaulourtwn_fw_loadpage(struct urtwn_softc *sc, int page, const uint8_t *buf, int len) 2318251538Srpaulo{ 2319251538Srpaulo uint32_t reg; 2320251538Srpaulo int off, mlen, error = 0; 2321251538Srpaulo 2322251538Srpaulo reg = urtwn_read_4(sc, R92C_MCUFWDL); 2323251538Srpaulo reg = RW(reg, R92C_MCUFWDL_PAGE, page); 2324251538Srpaulo urtwn_write_4(sc, R92C_MCUFWDL, reg); 2325251538Srpaulo 2326251538Srpaulo off = R92C_FW_START_ADDR; 2327251538Srpaulo while (len > 0) { 2328251538Srpaulo if (len > 196) 2329251538Srpaulo mlen = 196; 2330251538Srpaulo else if (len > 4) 2331251538Srpaulo mlen = 4; 2332251538Srpaulo else 2333251538Srpaulo mlen = 1; 2334251538Srpaulo /* XXX fix this deconst */ 2335251538Srpaulo error = urtwn_write_region_1(sc, off, 2336251538Srpaulo __DECONST(uint8_t *, buf), mlen); 2337251538Srpaulo if (error != 0) 2338251538Srpaulo break; 2339251538Srpaulo off += mlen; 2340251538Srpaulo buf += mlen; 2341251538Srpaulo len -= mlen; 2342251538Srpaulo } 2343251538Srpaulo return (error); 2344251538Srpaulo} 2345251538Srpaulo 2346251538Srpaulostatic int 2347251538Srpaulourtwn_load_firmware(struct urtwn_softc *sc) 2348251538Srpaulo{ 2349251538Srpaulo const struct firmware *fw; 2350251538Srpaulo const struct r92c_fw_hdr *hdr; 2351251538Srpaulo const char *imagename; 2352251538Srpaulo const u_char *ptr; 2353251538Srpaulo size_t len; 2354251538Srpaulo uint32_t reg; 2355251538Srpaulo int mlen, ntries, page, error; 2356251538Srpaulo 2357265345Skevlo URTWN_UNLOCK(sc); 2358251538Srpaulo /* Read firmware image from the filesystem. */ 2359266578Shselasky if (sc->chip & URTWN_CHIP_88E) 2360266578Shselasky imagename = "urtwn-rtl8188eufw"; 2361266578Shselasky else if ((sc->chip & (URTWN_CHIP_UMC_A_CUT | URTWN_CHIP_92C)) == 2362266578Shselasky URTWN_CHIP_UMC_A_CUT) 2363251538Srpaulo imagename = "urtwn-rtl8192cfwU"; 2364251538Srpaulo else 2365251538Srpaulo imagename = "urtwn-rtl8192cfwT"; 2366251538Srpaulo 2367251538Srpaulo fw = firmware_get(imagename); 2368265345Skevlo URTWN_LOCK(sc); 2369251538Srpaulo if (fw == NULL) { 2370251538Srpaulo device_printf(sc->sc_dev, 2371251538Srpaulo "failed loadfirmware of file %s\n", imagename); 2372251538Srpaulo return (ENOENT); 2373251538Srpaulo } 2374251538Srpaulo 2375251538Srpaulo len = fw->datasize; 2376251538Srpaulo 2377251538Srpaulo if (len < sizeof(*hdr)) { 2378251538Srpaulo device_printf(sc->sc_dev, "firmware too short\n"); 2379251538Srpaulo error = EINVAL; 2380251538Srpaulo goto fail; 2381251538Srpaulo } 2382251538Srpaulo ptr = fw->data; 2383251538Srpaulo hdr = (const struct r92c_fw_hdr *)ptr; 2384251538Srpaulo /* Check if there is a valid FW header and skip it. */ 2385251538Srpaulo if ((le16toh(hdr->signature) >> 4) == 0x88c || 2386266578Shselasky (le16toh(hdr->signature) >> 4) == 0x88e || 2387251538Srpaulo (le16toh(hdr->signature) >> 4) == 0x92c) { 2388251538Srpaulo DPRINTF("FW V%d.%d %02d-%02d %02d:%02d\n", 2389251538Srpaulo le16toh(hdr->version), le16toh(hdr->subversion), 2390251538Srpaulo hdr->month, hdr->date, hdr->hour, hdr->minute); 2391251538Srpaulo ptr += sizeof(*hdr); 2392251538Srpaulo len -= sizeof(*hdr); 2393251538Srpaulo } 2394251538Srpaulo 2395266578Shselasky if (urtwn_read_1(sc, R92C_MCUFWDL) & R92C_MCUFWDL_RAM_DL_SEL) { 2396266578Shselasky if (sc->chip & URTWN_CHIP_88E) 2397266578Shselasky urtwn_r88e_fw_reset(sc); 2398266578Shselasky else 2399266578Shselasky urtwn_fw_reset(sc); 2400251538Srpaulo urtwn_write_1(sc, R92C_MCUFWDL, 0); 2401251538Srpaulo } 2402266578Shselasky 2403268586Skevlo if (!(sc->chip & URTWN_CHIP_88E)) { 2404268586Skevlo urtwn_write_2(sc, R92C_SYS_FUNC_EN, 2405268586Skevlo urtwn_read_2(sc, R92C_SYS_FUNC_EN) | 2406268586Skevlo R92C_SYS_FUNC_EN_CPUEN); 2407268586Skevlo } 2408251538Srpaulo urtwn_write_1(sc, R92C_MCUFWDL, 2409251538Srpaulo urtwn_read_1(sc, R92C_MCUFWDL) | R92C_MCUFWDL_EN); 2410251538Srpaulo urtwn_write_1(sc, R92C_MCUFWDL + 2, 2411251538Srpaulo urtwn_read_1(sc, R92C_MCUFWDL + 2) & ~0x08); 2412251538Srpaulo 2413263256Skevlo /* Reset the FWDL checksum. */ 2414263256Skevlo urtwn_write_1(sc, R92C_MCUFWDL, 2415263256Skevlo urtwn_read_1(sc, R92C_MCUFWDL) | R92C_MCUFWDL_CHKSUM_RPT); 2416263256Skevlo 2417251538Srpaulo for (page = 0; len > 0; page++) { 2418251538Srpaulo mlen = min(len, R92C_FW_PAGE_SIZE); 2419251538Srpaulo error = urtwn_fw_loadpage(sc, page, ptr, mlen); 2420251538Srpaulo if (error != 0) { 2421251538Srpaulo device_printf(sc->sc_dev, 2422251538Srpaulo "could not load firmware page\n"); 2423251538Srpaulo goto fail; 2424251538Srpaulo } 2425251538Srpaulo ptr += mlen; 2426251538Srpaulo len -= mlen; 2427251538Srpaulo } 2428251538Srpaulo urtwn_write_1(sc, R92C_MCUFWDL, 2429251538Srpaulo urtwn_read_1(sc, R92C_MCUFWDL) & ~R92C_MCUFWDL_EN); 2430251538Srpaulo urtwn_write_1(sc, R92C_MCUFWDL + 1, 0); 2431251538Srpaulo 2432251538Srpaulo /* Wait for checksum report. */ 2433251538Srpaulo for (ntries = 0; ntries < 1000; ntries++) { 2434251538Srpaulo if (urtwn_read_4(sc, R92C_MCUFWDL) & R92C_MCUFWDL_CHKSUM_RPT) 2435251538Srpaulo break; 2436266578Shselasky urtwn_ms_delay(sc); 2437251538Srpaulo } 2438251538Srpaulo if (ntries == 1000) { 2439251538Srpaulo device_printf(sc->sc_dev, 2440251538Srpaulo "timeout waiting for checksum report\n"); 2441251538Srpaulo error = ETIMEDOUT; 2442251538Srpaulo goto fail; 2443251538Srpaulo } 2444251538Srpaulo 2445251538Srpaulo reg = urtwn_read_4(sc, R92C_MCUFWDL); 2446251538Srpaulo reg = (reg & ~R92C_MCUFWDL_WINTINI_RDY) | R92C_MCUFWDL_RDY; 2447251538Srpaulo urtwn_write_4(sc, R92C_MCUFWDL, reg); 2448266578Shselasky if (sc->chip & URTWN_CHIP_88E) 2449266578Shselasky urtwn_r88e_fw_reset(sc); 2450251538Srpaulo /* Wait for firmware readiness. */ 2451251538Srpaulo for (ntries = 0; ntries < 1000; ntries++) { 2452251538Srpaulo if (urtwn_read_4(sc, R92C_MCUFWDL) & R92C_MCUFWDL_WINTINI_RDY) 2453251538Srpaulo break; 2454266578Shselasky urtwn_ms_delay(sc); 2455251538Srpaulo } 2456251538Srpaulo if (ntries == 1000) { 2457251538Srpaulo device_printf(sc->sc_dev, 2458251538Srpaulo "timeout waiting for firmware readiness\n"); 2459251538Srpaulo error = ETIMEDOUT; 2460251538Srpaulo goto fail; 2461251538Srpaulo } 2462251538Srpaulofail: 2463251538Srpaulo firmware_put(fw, FIRMWARE_UNLOAD); 2464251538Srpaulo return (error); 2465251538Srpaulo} 2466251538Srpaulo 2467266578Shselaskystatic __inline int 2468251538Srpaulourtwn_dma_init(struct urtwn_softc *sc) 2469251538Srpaulo{ 2470266578Shselasky 2471266578Shselasky return sc->sc_dma_init(sc); 2472266578Shselasky} 2473266578Shselasky 2474266578Shselaskystatic int 2475266578Shselaskyurtwn_r92c_dma_init(struct urtwn_softc *sc) 2476266578Shselasky{ 2477251538Srpaulo int hashq, hasnq, haslq, nqueues, nqpages, nrempages; 2478251538Srpaulo uint32_t reg; 2479251538Srpaulo int error; 2480251538Srpaulo 2481251538Srpaulo /* Initialize LLT table. */ 2482251538Srpaulo error = urtwn_llt_init(sc); 2483251538Srpaulo if (error != 0) 2484251538Srpaulo return (error); 2485251538Srpaulo 2486251538Srpaulo /* Get Tx queues to USB endpoints mapping. */ 2487251538Srpaulo hashq = hasnq = haslq = 0; 2488251538Srpaulo reg = urtwn_read_2(sc, R92C_USB_EP + 1); 2489251538Srpaulo DPRINTFN(2, "USB endpoints mapping 0x%x\n", reg); 2490251538Srpaulo if (MS(reg, R92C_USB_EP_HQ) != 0) 2491251538Srpaulo hashq = 1; 2492251538Srpaulo if (MS(reg, R92C_USB_EP_NQ) != 0) 2493251538Srpaulo hasnq = 1; 2494251538Srpaulo if (MS(reg, R92C_USB_EP_LQ) != 0) 2495251538Srpaulo haslq = 1; 2496251538Srpaulo nqueues = hashq + hasnq + haslq; 2497251538Srpaulo if (nqueues == 0) 2498251538Srpaulo return (EIO); 2499251538Srpaulo /* Get the number of pages for each queue. */ 2500251538Srpaulo nqpages = (R92C_TX_PAGE_COUNT - R92C_PUBQ_NPAGES) / nqueues; 2501251538Srpaulo /* The remaining pages are assigned to the high priority queue. */ 2502251538Srpaulo nrempages = (R92C_TX_PAGE_COUNT - R92C_PUBQ_NPAGES) % nqueues; 2503251538Srpaulo 2504251538Srpaulo /* Set number of pages for normal priority queue. */ 2505251538Srpaulo urtwn_write_1(sc, R92C_RQPN_NPQ, hasnq ? nqpages : 0); 2506251538Srpaulo urtwn_write_4(sc, R92C_RQPN, 2507251538Srpaulo /* Set number of pages for public queue. */ 2508251538Srpaulo SM(R92C_RQPN_PUBQ, R92C_PUBQ_NPAGES) | 2509251538Srpaulo /* Set number of pages for high priority queue. */ 2510251538Srpaulo SM(R92C_RQPN_HPQ, hashq ? nqpages + nrempages : 0) | 2511251538Srpaulo /* Set number of pages for low priority queue. */ 2512251538Srpaulo SM(R92C_RQPN_LPQ, haslq ? nqpages : 0) | 2513251538Srpaulo /* Load values. */ 2514251538Srpaulo R92C_RQPN_LD); 2515251538Srpaulo 2516251538Srpaulo urtwn_write_1(sc, R92C_TXPKTBUF_BCNQ_BDNY, R92C_TX_PAGE_BOUNDARY); 2517251538Srpaulo urtwn_write_1(sc, R92C_TXPKTBUF_MGQ_BDNY, R92C_TX_PAGE_BOUNDARY); 2518251538Srpaulo urtwn_write_1(sc, R92C_TXPKTBUF_WMAC_LBK_BF_HD, R92C_TX_PAGE_BOUNDARY); 2519251538Srpaulo urtwn_write_1(sc, R92C_TRXFF_BNDY, R92C_TX_PAGE_BOUNDARY); 2520251538Srpaulo urtwn_write_1(sc, R92C_TDECTRL + 1, R92C_TX_PAGE_BOUNDARY); 2521251538Srpaulo 2522251538Srpaulo /* Set queue to USB pipe mapping. */ 2523251538Srpaulo reg = urtwn_read_2(sc, R92C_TRXDMA_CTRL); 2524251538Srpaulo reg &= ~R92C_TRXDMA_CTRL_QMAP_M; 2525251538Srpaulo if (nqueues == 1) { 2526251538Srpaulo if (hashq) 2527251538Srpaulo reg |= R92C_TRXDMA_CTRL_QMAP_HQ; 2528251538Srpaulo else if (hasnq) 2529251538Srpaulo reg |= R92C_TRXDMA_CTRL_QMAP_NQ; 2530251538Srpaulo else 2531251538Srpaulo reg |= R92C_TRXDMA_CTRL_QMAP_LQ; 2532251538Srpaulo } else if (nqueues == 2) { 2533251538Srpaulo /* All 2-endpoints configs have a high priority queue. */ 2534251538Srpaulo if (!hashq) 2535251538Srpaulo return (EIO); 2536251538Srpaulo if (hasnq) 2537251538Srpaulo reg |= R92C_TRXDMA_CTRL_QMAP_HQ_NQ; 2538251538Srpaulo else 2539251538Srpaulo reg |= R92C_TRXDMA_CTRL_QMAP_HQ_LQ; 2540251538Srpaulo } else 2541251538Srpaulo reg |= R92C_TRXDMA_CTRL_QMAP_3EP; 2542251538Srpaulo urtwn_write_2(sc, R92C_TRXDMA_CTRL, reg); 2543251538Srpaulo 2544251538Srpaulo /* Set Tx/Rx transfer page boundary. */ 2545251538Srpaulo urtwn_write_2(sc, R92C_TRXFF_BNDY + 2, 0x27ff); 2546251538Srpaulo 2547251538Srpaulo /* Set Tx/Rx transfer page size. */ 2548251538Srpaulo urtwn_write_1(sc, R92C_PBP, 2549251538Srpaulo SM(R92C_PBP_PSRX, R92C_PBP_128) | 2550251538Srpaulo SM(R92C_PBP_PSTX, R92C_PBP_128)); 2551251538Srpaulo return (0); 2552251538Srpaulo} 2553251538Srpaulo 2554266578Shselaskystatic int 2555266578Shselaskyurtwn_r88e_dma_init(struct urtwn_softc *sc) 2556266578Shselasky{ 2557266578Shselasky struct usb_interface *iface; 2558266578Shselasky uint32_t reg; 2559266578Shselasky int nqueues; 2560266578Shselasky int error; 2561266578Shselasky 2562266578Shselasky /* Initialize LLT table. */ 2563266578Shselasky error = urtwn_llt_init(sc); 2564266578Shselasky if (error != 0) 2565266578Shselasky return (error); 2566266578Shselasky 2567266578Shselasky /* Get Tx queues to USB endpoints mapping. */ 2568266578Shselasky iface = usbd_get_iface(sc->sc_udev, 0); 2569266578Shselasky nqueues = iface->idesc->bNumEndpoints - 1; 2570266578Shselasky if (nqueues == 0) 2571266578Shselasky return (EIO); 2572266578Shselasky 2573266578Shselasky /* Set number of pages for normal priority queue. */ 2574266578Shselasky urtwn_write_2(sc, R92C_RQPN_NPQ, 0x000d); 2575266578Shselasky urtwn_write_4(sc, R92C_RQPN, 0x808e000d); 2576266578Shselasky 2577266578Shselasky urtwn_write_1(sc, R92C_TXPKTBUF_BCNQ_BDNY, R88E_TX_PAGE_BOUNDARY); 2578266578Shselasky urtwn_write_1(sc, R92C_TXPKTBUF_MGQ_BDNY, R88E_TX_PAGE_BOUNDARY); 2579266578Shselasky urtwn_write_1(sc, R92C_TXPKTBUF_WMAC_LBK_BF_HD, R88E_TX_PAGE_BOUNDARY); 2580266578Shselasky urtwn_write_1(sc, R92C_TRXFF_BNDY, R88E_TX_PAGE_BOUNDARY); 2581266578Shselasky urtwn_write_1(sc, R92C_TDECTRL + 1, R88E_TX_PAGE_BOUNDARY); 2582266578Shselasky 2583266578Shselasky /* Set queue to USB pipe mapping. */ 2584266578Shselasky reg = urtwn_read_2(sc, R92C_TRXDMA_CTRL); 2585266578Shselasky reg &= ~R92C_TRXDMA_CTRL_QMAP_M; 2586266578Shselasky if (nqueues == 1) 2587266578Shselasky reg |= R92C_TRXDMA_CTRL_QMAP_LQ; 2588266578Shselasky else if (nqueues == 2) 2589266578Shselasky reg |= R92C_TRXDMA_CTRL_QMAP_HQ_NQ; 2590266578Shselasky else 2591266578Shselasky reg |= R92C_TRXDMA_CTRL_QMAP_3EP; 2592266578Shselasky urtwn_write_2(sc, R92C_TRXDMA_CTRL, reg); 2593266578Shselasky 2594266578Shselasky /* Set Tx/Rx transfer page boundary. */ 2595266578Shselasky urtwn_write_2(sc, R92C_TRXFF_BNDY + 2, 0x23ff); 2596266578Shselasky 2597266578Shselasky /* Set Tx/Rx transfer page size. */ 2598266578Shselasky urtwn_write_1(sc, R92C_PBP, 2599266578Shselasky SM(R92C_PBP_PSRX, R92C_PBP_128) | 2600266578Shselasky SM(R92C_PBP_PSTX, R92C_PBP_128)); 2601266578Shselasky 2602266578Shselasky return (0); 2603266578Shselasky} 2604266578Shselasky 2605251538Srpaulostatic void 2606251538Srpaulourtwn_mac_init(struct urtwn_softc *sc) 2607251538Srpaulo{ 2608251538Srpaulo int i; 2609251538Srpaulo 2610251538Srpaulo /* Write MAC initialization values. */ 2611266578Shselasky if (sc->chip & URTWN_CHIP_88E) { 2612266578Shselasky for (i = 0; i < nitems(rtl8188eu_mac); i++) { 2613266578Shselasky urtwn_write_1(sc, rtl8188eu_mac[i].reg, 2614266578Shselasky rtl8188eu_mac[i].val); 2615266578Shselasky } 2616266578Shselasky urtwn_write_1(sc, R92C_MAX_AGGR_NUM, 0x07); 2617266578Shselasky } else { 2618266578Shselasky for (i = 0; i < nitems(rtl8192cu_mac); i++) 2619266578Shselasky urtwn_write_1(sc, rtl8192cu_mac[i].reg, 2620266578Shselasky rtl8192cu_mac[i].val); 2621266578Shselasky } 2622251538Srpaulo} 2623251538Srpaulo 2624251538Srpaulostatic void 2625251538Srpaulourtwn_bb_init(struct urtwn_softc *sc) 2626251538Srpaulo{ 2627251538Srpaulo const struct urtwn_bb_prog *prog; 2628251538Srpaulo uint32_t reg; 2629266578Shselasky uint8_t crystalcap; 2630251538Srpaulo int i; 2631251538Srpaulo 2632251538Srpaulo /* Enable BB and RF. */ 2633251538Srpaulo urtwn_write_2(sc, R92C_SYS_FUNC_EN, 2634251538Srpaulo urtwn_read_2(sc, R92C_SYS_FUNC_EN) | 2635251538Srpaulo R92C_SYS_FUNC_EN_BBRSTB | R92C_SYS_FUNC_EN_BB_GLB_RST | 2636251538Srpaulo R92C_SYS_FUNC_EN_DIO_RF); 2637251538Srpaulo 2638266578Shselasky if (!(sc->chip & URTWN_CHIP_88E)) 2639266578Shselasky urtwn_write_2(sc, R92C_AFE_PLL_CTRL, 0xdb83); 2640251538Srpaulo 2641251538Srpaulo urtwn_write_1(sc, R92C_RF_CTRL, 2642251538Srpaulo R92C_RF_CTRL_EN | R92C_RF_CTRL_RSTB | R92C_RF_CTRL_SDMRSTB); 2643251538Srpaulo urtwn_write_1(sc, R92C_SYS_FUNC_EN, 2644251538Srpaulo R92C_SYS_FUNC_EN_USBA | R92C_SYS_FUNC_EN_USBD | 2645251538Srpaulo R92C_SYS_FUNC_EN_BB_GLB_RST | R92C_SYS_FUNC_EN_BBRSTB); 2646251538Srpaulo 2647266578Shselasky if (!(sc->chip & URTWN_CHIP_88E)) { 2648266578Shselasky urtwn_write_1(sc, R92C_LDOHCI12_CTRL, 0x0f); 2649266578Shselasky urtwn_write_1(sc, 0x15, 0xe9); 2650266578Shselasky urtwn_write_1(sc, R92C_AFE_XTAL_CTRL + 1, 0x80); 2651266578Shselasky } 2652251538Srpaulo 2653251538Srpaulo /* Select BB programming based on board type. */ 2654266578Shselasky if (sc->chip & URTWN_CHIP_88E) 2655266578Shselasky prog = &rtl8188eu_bb_prog; 2656266578Shselasky else if (!(sc->chip & URTWN_CHIP_92C)) { 2657251538Srpaulo if (sc->board_type == R92C_BOARD_TYPE_MINICARD) 2658251538Srpaulo prog = &rtl8188ce_bb_prog; 2659251538Srpaulo else if (sc->board_type == R92C_BOARD_TYPE_HIGHPA) 2660251538Srpaulo prog = &rtl8188ru_bb_prog; 2661251538Srpaulo else 2662251538Srpaulo prog = &rtl8188cu_bb_prog; 2663251538Srpaulo } else { 2664251538Srpaulo if (sc->board_type == R92C_BOARD_TYPE_MINICARD) 2665251538Srpaulo prog = &rtl8192ce_bb_prog; 2666251538Srpaulo else 2667251538Srpaulo prog = &rtl8192cu_bb_prog; 2668251538Srpaulo } 2669251538Srpaulo /* Write BB initialization values. */ 2670251538Srpaulo for (i = 0; i < prog->count; i++) { 2671251538Srpaulo urtwn_bb_write(sc, prog->regs[i], prog->vals[i]); 2672266578Shselasky urtwn_ms_delay(sc); 2673251538Srpaulo } 2674251538Srpaulo 2675251538Srpaulo if (sc->chip & URTWN_CHIP_92C_1T2R) { 2676251538Srpaulo /* 8192C 1T only configuration. */ 2677251538Srpaulo reg = urtwn_bb_read(sc, R92C_FPGA0_TXINFO); 2678251538Srpaulo reg = (reg & ~0x00000003) | 0x2; 2679251538Srpaulo urtwn_bb_write(sc, R92C_FPGA0_TXINFO, reg); 2680251538Srpaulo 2681251538Srpaulo reg = urtwn_bb_read(sc, R92C_FPGA1_TXINFO); 2682251538Srpaulo reg = (reg & ~0x00300033) | 0x00200022; 2683251538Srpaulo urtwn_bb_write(sc, R92C_FPGA1_TXINFO, reg); 2684251538Srpaulo 2685251538Srpaulo reg = urtwn_bb_read(sc, R92C_CCK0_AFESETTING); 2686251538Srpaulo reg = (reg & ~0xff000000) | 0x45 << 24; 2687251538Srpaulo urtwn_bb_write(sc, R92C_CCK0_AFESETTING, reg); 2688251538Srpaulo 2689251538Srpaulo reg = urtwn_bb_read(sc, R92C_OFDM0_TRXPATHENA); 2690251538Srpaulo reg = (reg & ~0x000000ff) | 0x23; 2691251538Srpaulo urtwn_bb_write(sc, R92C_OFDM0_TRXPATHENA, reg); 2692251538Srpaulo 2693251538Srpaulo reg = urtwn_bb_read(sc, R92C_OFDM0_AGCPARAM1); 2694251538Srpaulo reg = (reg & ~0x00000030) | 1 << 4; 2695251538Srpaulo urtwn_bb_write(sc, R92C_OFDM0_AGCPARAM1, reg); 2696251538Srpaulo 2697251538Srpaulo reg = urtwn_bb_read(sc, 0xe74); 2698251538Srpaulo reg = (reg & ~0x0c000000) | 2 << 26; 2699251538Srpaulo urtwn_bb_write(sc, 0xe74, reg); 2700251538Srpaulo reg = urtwn_bb_read(sc, 0xe78); 2701251538Srpaulo reg = (reg & ~0x0c000000) | 2 << 26; 2702251538Srpaulo urtwn_bb_write(sc, 0xe78, reg); 2703251538Srpaulo reg = urtwn_bb_read(sc, 0xe7c); 2704251538Srpaulo reg = (reg & ~0x0c000000) | 2 << 26; 2705251538Srpaulo urtwn_bb_write(sc, 0xe7c, reg); 2706251538Srpaulo reg = urtwn_bb_read(sc, 0xe80); 2707251538Srpaulo reg = (reg & ~0x0c000000) | 2 << 26; 2708251538Srpaulo urtwn_bb_write(sc, 0xe80, reg); 2709251538Srpaulo reg = urtwn_bb_read(sc, 0xe88); 2710251538Srpaulo reg = (reg & ~0x0c000000) | 2 << 26; 2711251538Srpaulo urtwn_bb_write(sc, 0xe88, reg); 2712251538Srpaulo } 2713251538Srpaulo 2714251538Srpaulo /* Write AGC values. */ 2715251538Srpaulo for (i = 0; i < prog->agccount; i++) { 2716251538Srpaulo urtwn_bb_write(sc, R92C_OFDM0_AGCRSSITABLE, 2717251538Srpaulo prog->agcvals[i]); 2718266578Shselasky urtwn_ms_delay(sc); 2719251538Srpaulo } 2720251538Srpaulo 2721266578Shselasky if (sc->chip & URTWN_CHIP_88E) { 2722266578Shselasky urtwn_bb_write(sc, R92C_OFDM0_AGCCORE1(0), 0x69553422); 2723266578Shselasky urtwn_ms_delay(sc); 2724266578Shselasky urtwn_bb_write(sc, R92C_OFDM0_AGCCORE1(0), 0x69553420); 2725266578Shselasky urtwn_ms_delay(sc); 2726266578Shselasky 2727266578Shselasky crystalcap = sc->r88e_rom[0xb9]; 2728266578Shselasky if (crystalcap == 0xff) 2729266578Shselasky crystalcap = 0x20; 2730266578Shselasky crystalcap &= 0x3f; 2731266578Shselasky reg = urtwn_bb_read(sc, R92C_AFE_XTAL_CTRL); 2732266578Shselasky urtwn_bb_write(sc, R92C_AFE_XTAL_CTRL, 2733266578Shselasky RW(reg, R92C_AFE_XTAL_CTRL_ADDR, 2734266578Shselasky crystalcap | crystalcap << 6)); 2735266578Shselasky } else { 2736266578Shselasky if (urtwn_bb_read(sc, R92C_HSSI_PARAM2(0)) & 2737266578Shselasky R92C_HSSI_PARAM2_CCK_HIPWR) 2738266578Shselasky sc->sc_flags |= URTWN_FLAG_CCK_HIPWR; 2739266578Shselasky } 2740251538Srpaulo} 2741251538Srpaulo 2742251538Srpaulovoid 2743251538Srpaulourtwn_rf_init(struct urtwn_softc *sc) 2744251538Srpaulo{ 2745251538Srpaulo const struct urtwn_rf_prog *prog; 2746251538Srpaulo uint32_t reg, type; 2747251538Srpaulo int i, j, idx, off; 2748251538Srpaulo 2749251538Srpaulo /* Select RF programming based on board type. */ 2750266578Shselasky if (sc->chip & URTWN_CHIP_88E) 2751266578Shselasky prog = rtl8188eu_rf_prog; 2752266578Shselasky else if (!(sc->chip & URTWN_CHIP_92C)) { 2753251538Srpaulo if (sc->board_type == R92C_BOARD_TYPE_MINICARD) 2754251538Srpaulo prog = rtl8188ce_rf_prog; 2755251538Srpaulo else if (sc->board_type == R92C_BOARD_TYPE_HIGHPA) 2756251538Srpaulo prog = rtl8188ru_rf_prog; 2757251538Srpaulo else 2758251538Srpaulo prog = rtl8188cu_rf_prog; 2759251538Srpaulo } else 2760251538Srpaulo prog = rtl8192ce_rf_prog; 2761251538Srpaulo 2762251538Srpaulo for (i = 0; i < sc->nrxchains; i++) { 2763251538Srpaulo /* Save RF_ENV control type. */ 2764251538Srpaulo idx = i / 2; 2765251538Srpaulo off = (i % 2) * 16; 2766251538Srpaulo reg = urtwn_bb_read(sc, R92C_FPGA0_RFIFACESW(idx)); 2767251538Srpaulo type = (reg >> off) & 0x10; 2768251538Srpaulo 2769251538Srpaulo /* Set RF_ENV enable. */ 2770251538Srpaulo reg = urtwn_bb_read(sc, R92C_FPGA0_RFIFACEOE(i)); 2771251538Srpaulo reg |= 0x100000; 2772251538Srpaulo urtwn_bb_write(sc, R92C_FPGA0_RFIFACEOE(i), reg); 2773266578Shselasky urtwn_ms_delay(sc); 2774251538Srpaulo /* Set RF_ENV output high. */ 2775251538Srpaulo reg = urtwn_bb_read(sc, R92C_FPGA0_RFIFACEOE(i)); 2776251538Srpaulo reg |= 0x10; 2777251538Srpaulo urtwn_bb_write(sc, R92C_FPGA0_RFIFACEOE(i), reg); 2778266578Shselasky urtwn_ms_delay(sc); 2779251538Srpaulo /* Set address and data lengths of RF registers. */ 2780251538Srpaulo reg = urtwn_bb_read(sc, R92C_HSSI_PARAM2(i)); 2781251538Srpaulo reg &= ~R92C_HSSI_PARAM2_ADDR_LENGTH; 2782251538Srpaulo urtwn_bb_write(sc, R92C_HSSI_PARAM2(i), reg); 2783266578Shselasky urtwn_ms_delay(sc); 2784251538Srpaulo reg = urtwn_bb_read(sc, R92C_HSSI_PARAM2(i)); 2785251538Srpaulo reg &= ~R92C_HSSI_PARAM2_DATA_LENGTH; 2786251538Srpaulo urtwn_bb_write(sc, R92C_HSSI_PARAM2(i), reg); 2787266578Shselasky urtwn_ms_delay(sc); 2788251538Srpaulo 2789251538Srpaulo /* Write RF initialization values for this chain. */ 2790251538Srpaulo for (j = 0; j < prog[i].count; j++) { 2791251538Srpaulo if (prog[i].regs[j] >= 0xf9 && 2792251538Srpaulo prog[i].regs[j] <= 0xfe) { 2793251538Srpaulo /* 2794251538Srpaulo * These are fake RF registers offsets that 2795251538Srpaulo * indicate a delay is required. 2796251538Srpaulo */ 2797266578Shselasky usb_pause_mtx(&sc->sc_mtx, hz / 20); /* 50ms */ 2798251538Srpaulo continue; 2799251538Srpaulo } 2800251538Srpaulo urtwn_rf_write(sc, i, prog[i].regs[j], 2801251538Srpaulo prog[i].vals[j]); 2802266578Shselasky urtwn_ms_delay(sc); 2803251538Srpaulo } 2804251538Srpaulo 2805251538Srpaulo /* Restore RF_ENV control type. */ 2806251538Srpaulo reg = urtwn_bb_read(sc, R92C_FPGA0_RFIFACESW(idx)); 2807251538Srpaulo reg &= ~(0x10 << off) | (type << off); 2808251538Srpaulo urtwn_bb_write(sc, R92C_FPGA0_RFIFACESW(idx), reg); 2809251538Srpaulo 2810251538Srpaulo /* Cache RF register CHNLBW. */ 2811251538Srpaulo sc->rf_chnlbw[i] = urtwn_rf_read(sc, i, R92C_RF_CHNLBW); 2812251538Srpaulo } 2813251538Srpaulo 2814251538Srpaulo if ((sc->chip & (URTWN_CHIP_UMC_A_CUT | URTWN_CHIP_92C)) == 2815251538Srpaulo URTWN_CHIP_UMC_A_CUT) { 2816251538Srpaulo urtwn_rf_write(sc, 0, R92C_RF_RX_G1, 0x30255); 2817251538Srpaulo urtwn_rf_write(sc, 0, R92C_RF_RX_G2, 0x50a00); 2818251538Srpaulo } 2819251538Srpaulo} 2820251538Srpaulo 2821251538Srpaulostatic void 2822251538Srpaulourtwn_cam_init(struct urtwn_softc *sc) 2823251538Srpaulo{ 2824251538Srpaulo /* Invalidate all CAM entries. */ 2825251538Srpaulo urtwn_write_4(sc, R92C_CAMCMD, 2826251538Srpaulo R92C_CAMCMD_POLLING | R92C_CAMCMD_CLR); 2827251538Srpaulo} 2828251538Srpaulo 2829251538Srpaulostatic void 2830251538Srpaulourtwn_pa_bias_init(struct urtwn_softc *sc) 2831251538Srpaulo{ 2832251538Srpaulo uint8_t reg; 2833251538Srpaulo int i; 2834251538Srpaulo 2835251538Srpaulo for (i = 0; i < sc->nrxchains; i++) { 2836251538Srpaulo if (sc->pa_setting & (1 << i)) 2837251538Srpaulo continue; 2838251538Srpaulo urtwn_rf_write(sc, i, R92C_RF_IPA, 0x0f406); 2839251538Srpaulo urtwn_rf_write(sc, i, R92C_RF_IPA, 0x4f406); 2840251538Srpaulo urtwn_rf_write(sc, i, R92C_RF_IPA, 0x8f406); 2841251538Srpaulo urtwn_rf_write(sc, i, R92C_RF_IPA, 0xcf406); 2842251538Srpaulo } 2843251538Srpaulo if (!(sc->pa_setting & 0x10)) { 2844251538Srpaulo reg = urtwn_read_1(sc, 0x16); 2845251538Srpaulo reg = (reg & ~0xf0) | 0x90; 2846251538Srpaulo urtwn_write_1(sc, 0x16, reg); 2847251538Srpaulo } 2848251538Srpaulo} 2849251538Srpaulo 2850251538Srpaulostatic void 2851251538Srpaulourtwn_rxfilter_init(struct urtwn_softc *sc) 2852251538Srpaulo{ 2853251538Srpaulo /* Initialize Rx filter. */ 2854251538Srpaulo /* TODO: use better filter for monitor mode. */ 2855251538Srpaulo urtwn_write_4(sc, R92C_RCR, 2856251538Srpaulo R92C_RCR_AAP | R92C_RCR_APM | R92C_RCR_AM | R92C_RCR_AB | 2857251538Srpaulo R92C_RCR_APP_ICV | R92C_RCR_AMF | R92C_RCR_HTC_LOC_CTRL | 2858251538Srpaulo R92C_RCR_APP_MIC | R92C_RCR_APP_PHYSTS); 2859251538Srpaulo /* Accept all multicast frames. */ 2860251538Srpaulo urtwn_write_4(sc, R92C_MAR + 0, 0xffffffff); 2861251538Srpaulo urtwn_write_4(sc, R92C_MAR + 4, 0xffffffff); 2862251538Srpaulo /* Accept all management frames. */ 2863251538Srpaulo urtwn_write_2(sc, R92C_RXFLTMAP0, 0xffff); 2864251538Srpaulo /* Reject all control frames. */ 2865251538Srpaulo urtwn_write_2(sc, R92C_RXFLTMAP1, 0x0000); 2866251538Srpaulo /* Accept all data frames. */ 2867251538Srpaulo urtwn_write_2(sc, R92C_RXFLTMAP2, 0xffff); 2868251538Srpaulo} 2869251538Srpaulo 2870251538Srpaulostatic void 2871251538Srpaulourtwn_edca_init(struct urtwn_softc *sc) 2872251538Srpaulo{ 2873251538Srpaulo urtwn_write_2(sc, R92C_SPEC_SIFS, 0x100a); 2874251538Srpaulo urtwn_write_2(sc, R92C_MAC_SPEC_SIFS, 0x100a); 2875251538Srpaulo urtwn_write_2(sc, R92C_SIFS_CCK, 0x100a); 2876251538Srpaulo urtwn_write_2(sc, R92C_SIFS_OFDM, 0x100a); 2877251538Srpaulo urtwn_write_4(sc, R92C_EDCA_BE_PARAM, 0x005ea42b); 2878251538Srpaulo urtwn_write_4(sc, R92C_EDCA_BK_PARAM, 0x0000a44f); 2879251538Srpaulo urtwn_write_4(sc, R92C_EDCA_VI_PARAM, 0x005ea324); 2880251538Srpaulo urtwn_write_4(sc, R92C_EDCA_VO_PARAM, 0x002fa226); 2881251538Srpaulo} 2882251538Srpaulo 2883251538Srpaulovoid 2884251538Srpaulourtwn_write_txpower(struct urtwn_softc *sc, int chain, 2885251538Srpaulo uint16_t power[URTWN_RIDX_COUNT]) 2886251538Srpaulo{ 2887251538Srpaulo uint32_t reg; 2888251538Srpaulo 2889251538Srpaulo /* Write per-CCK rate Tx power. */ 2890251538Srpaulo if (chain == 0) { 2891251538Srpaulo reg = urtwn_bb_read(sc, R92C_TXAGC_A_CCK1_MCS32); 2892251538Srpaulo reg = RW(reg, R92C_TXAGC_A_CCK1, power[0]); 2893251538Srpaulo urtwn_bb_write(sc, R92C_TXAGC_A_CCK1_MCS32, reg); 2894251538Srpaulo reg = urtwn_bb_read(sc, R92C_TXAGC_B_CCK11_A_CCK2_11); 2895251538Srpaulo reg = RW(reg, R92C_TXAGC_A_CCK2, power[1]); 2896251538Srpaulo reg = RW(reg, R92C_TXAGC_A_CCK55, power[2]); 2897251538Srpaulo reg = RW(reg, R92C_TXAGC_A_CCK11, power[3]); 2898251538Srpaulo urtwn_bb_write(sc, R92C_TXAGC_B_CCK11_A_CCK2_11, reg); 2899251538Srpaulo } else { 2900251538Srpaulo reg = urtwn_bb_read(sc, R92C_TXAGC_B_CCK1_55_MCS32); 2901251538Srpaulo reg = RW(reg, R92C_TXAGC_B_CCK1, power[0]); 2902251538Srpaulo reg = RW(reg, R92C_TXAGC_B_CCK2, power[1]); 2903251538Srpaulo reg = RW(reg, R92C_TXAGC_B_CCK55, power[2]); 2904251538Srpaulo urtwn_bb_write(sc, R92C_TXAGC_B_CCK1_55_MCS32, reg); 2905251538Srpaulo reg = urtwn_bb_read(sc, R92C_TXAGC_B_CCK11_A_CCK2_11); 2906251538Srpaulo reg = RW(reg, R92C_TXAGC_B_CCK11, power[3]); 2907251538Srpaulo urtwn_bb_write(sc, R92C_TXAGC_B_CCK11_A_CCK2_11, reg); 2908251538Srpaulo } 2909251538Srpaulo /* Write per-OFDM rate Tx power. */ 2910251538Srpaulo urtwn_bb_write(sc, R92C_TXAGC_RATE18_06(chain), 2911251538Srpaulo SM(R92C_TXAGC_RATE06, power[ 4]) | 2912251538Srpaulo SM(R92C_TXAGC_RATE09, power[ 5]) | 2913251538Srpaulo SM(R92C_TXAGC_RATE12, power[ 6]) | 2914251538Srpaulo SM(R92C_TXAGC_RATE18, power[ 7])); 2915251538Srpaulo urtwn_bb_write(sc, R92C_TXAGC_RATE54_24(chain), 2916251538Srpaulo SM(R92C_TXAGC_RATE24, power[ 8]) | 2917251538Srpaulo SM(R92C_TXAGC_RATE36, power[ 9]) | 2918251538Srpaulo SM(R92C_TXAGC_RATE48, power[10]) | 2919251538Srpaulo SM(R92C_TXAGC_RATE54, power[11])); 2920251538Srpaulo /* Write per-MCS Tx power. */ 2921251538Srpaulo urtwn_bb_write(sc, R92C_TXAGC_MCS03_MCS00(chain), 2922251538Srpaulo SM(R92C_TXAGC_MCS00, power[12]) | 2923251538Srpaulo SM(R92C_TXAGC_MCS01, power[13]) | 2924251538Srpaulo SM(R92C_TXAGC_MCS02, power[14]) | 2925251538Srpaulo SM(R92C_TXAGC_MCS03, power[15])); 2926251538Srpaulo urtwn_bb_write(sc, R92C_TXAGC_MCS07_MCS04(chain), 2927251538Srpaulo SM(R92C_TXAGC_MCS04, power[16]) | 2928251538Srpaulo SM(R92C_TXAGC_MCS05, power[17]) | 2929251538Srpaulo SM(R92C_TXAGC_MCS06, power[18]) | 2930251538Srpaulo SM(R92C_TXAGC_MCS07, power[19])); 2931251538Srpaulo urtwn_bb_write(sc, R92C_TXAGC_MCS11_MCS08(chain), 2932251538Srpaulo SM(R92C_TXAGC_MCS08, power[20]) | 2933262009Skevlo SM(R92C_TXAGC_MCS09, power[21]) | 2934251538Srpaulo SM(R92C_TXAGC_MCS10, power[22]) | 2935251538Srpaulo SM(R92C_TXAGC_MCS11, power[23])); 2936251538Srpaulo urtwn_bb_write(sc, R92C_TXAGC_MCS15_MCS12(chain), 2937251538Srpaulo SM(R92C_TXAGC_MCS12, power[24]) | 2938251538Srpaulo SM(R92C_TXAGC_MCS13, power[25]) | 2939251538Srpaulo SM(R92C_TXAGC_MCS14, power[26]) | 2940251538Srpaulo SM(R92C_TXAGC_MCS15, power[27])); 2941251538Srpaulo} 2942251538Srpaulo 2943251538Srpaulovoid 2944251538Srpaulourtwn_get_txpower(struct urtwn_softc *sc, int chain, 2945251538Srpaulo struct ieee80211_channel *c, struct ieee80211_channel *extc, 2946251538Srpaulo uint16_t power[URTWN_RIDX_COUNT]) 2947251538Srpaulo{ 2948251538Srpaulo struct ieee80211com *ic = sc->sc_ifp->if_l2com; 2949251538Srpaulo struct r92c_rom *rom = &sc->rom; 2950251538Srpaulo uint16_t cckpow, ofdmpow, htpow, diff, max; 2951251538Srpaulo const struct urtwn_txpwr *base; 2952251538Srpaulo int ridx, chan, group; 2953251538Srpaulo 2954251538Srpaulo /* Determine channel group. */ 2955251538Srpaulo chan = ieee80211_chan2ieee(ic, c); /* XXX center freq! */ 2956251538Srpaulo if (chan <= 3) 2957251538Srpaulo group = 0; 2958251538Srpaulo else if (chan <= 9) 2959251538Srpaulo group = 1; 2960251538Srpaulo else 2961251538Srpaulo group = 2; 2962251538Srpaulo 2963251538Srpaulo /* Get original Tx power based on board type and RF chain. */ 2964251538Srpaulo if (!(sc->chip & URTWN_CHIP_92C)) { 2965251538Srpaulo if (sc->board_type == R92C_BOARD_TYPE_HIGHPA) 2966251538Srpaulo base = &rtl8188ru_txagc[chain]; 2967251538Srpaulo else 2968251538Srpaulo base = &rtl8192cu_txagc[chain]; 2969251538Srpaulo } else 2970251538Srpaulo base = &rtl8192cu_txagc[chain]; 2971251538Srpaulo 2972251538Srpaulo memset(power, 0, URTWN_RIDX_COUNT * sizeof(power[0])); 2973251538Srpaulo if (sc->regulatory == 0) { 2974251538Srpaulo for (ridx = 0; ridx <= 3; ridx++) 2975251538Srpaulo power[ridx] = base->pwr[0][ridx]; 2976251538Srpaulo } 2977251538Srpaulo for (ridx = 4; ridx < URTWN_RIDX_COUNT; ridx++) { 2978251538Srpaulo if (sc->regulatory == 3) { 2979251538Srpaulo power[ridx] = base->pwr[0][ridx]; 2980251538Srpaulo /* Apply vendor limits. */ 2981251538Srpaulo if (extc != NULL) 2982251538Srpaulo max = rom->ht40_max_pwr[group]; 2983251538Srpaulo else 2984251538Srpaulo max = rom->ht20_max_pwr[group]; 2985251538Srpaulo max = (max >> (chain * 4)) & 0xf; 2986251538Srpaulo if (power[ridx] > max) 2987251538Srpaulo power[ridx] = max; 2988251538Srpaulo } else if (sc->regulatory == 1) { 2989251538Srpaulo if (extc == NULL) 2990251538Srpaulo power[ridx] = base->pwr[group][ridx]; 2991251538Srpaulo } else if (sc->regulatory != 2) 2992251538Srpaulo power[ridx] = base->pwr[0][ridx]; 2993251538Srpaulo } 2994251538Srpaulo 2995251538Srpaulo /* Compute per-CCK rate Tx power. */ 2996251538Srpaulo cckpow = rom->cck_tx_pwr[chain][group]; 2997251538Srpaulo for (ridx = 0; ridx <= 3; ridx++) { 2998251538Srpaulo power[ridx] += cckpow; 2999251538Srpaulo if (power[ridx] > R92C_MAX_TX_PWR) 3000251538Srpaulo power[ridx] = R92C_MAX_TX_PWR; 3001251538Srpaulo } 3002251538Srpaulo 3003251538Srpaulo htpow = rom->ht40_1s_tx_pwr[chain][group]; 3004251538Srpaulo if (sc->ntxchains > 1) { 3005251538Srpaulo /* Apply reduction for 2 spatial streams. */ 3006251538Srpaulo diff = rom->ht40_2s_tx_pwr_diff[group]; 3007251538Srpaulo diff = (diff >> (chain * 4)) & 0xf; 3008251538Srpaulo htpow = (htpow > diff) ? htpow - diff : 0; 3009251538Srpaulo } 3010251538Srpaulo 3011251538Srpaulo /* Compute per-OFDM rate Tx power. */ 3012251538Srpaulo diff = rom->ofdm_tx_pwr_diff[group]; 3013251538Srpaulo diff = (diff >> (chain * 4)) & 0xf; 3014251538Srpaulo ofdmpow = htpow + diff; /* HT->OFDM correction. */ 3015251538Srpaulo for (ridx = 4; ridx <= 11; ridx++) { 3016251538Srpaulo power[ridx] += ofdmpow; 3017251538Srpaulo if (power[ridx] > R92C_MAX_TX_PWR) 3018251538Srpaulo power[ridx] = R92C_MAX_TX_PWR; 3019251538Srpaulo } 3020251538Srpaulo 3021251538Srpaulo /* Compute per-MCS Tx power. */ 3022251538Srpaulo if (extc == NULL) { 3023251538Srpaulo diff = rom->ht20_tx_pwr_diff[group]; 3024251538Srpaulo diff = (diff >> (chain * 4)) & 0xf; 3025251538Srpaulo htpow += diff; /* HT40->HT20 correction. */ 3026251538Srpaulo } 3027251538Srpaulo for (ridx = 12; ridx <= 27; ridx++) { 3028251538Srpaulo power[ridx] += htpow; 3029251538Srpaulo if (power[ridx] > R92C_MAX_TX_PWR) 3030251538Srpaulo power[ridx] = R92C_MAX_TX_PWR; 3031251538Srpaulo } 3032251538Srpaulo#ifdef URTWN_DEBUG 3033251538Srpaulo if (urtwn_debug >= 4) { 3034251538Srpaulo /* Dump per-rate Tx power values. */ 3035251538Srpaulo printf("Tx power for chain %d:\n", chain); 3036251538Srpaulo for (ridx = 0; ridx < URTWN_RIDX_COUNT; ridx++) 3037251538Srpaulo printf("Rate %d = %u\n", ridx, power[ridx]); 3038251538Srpaulo } 3039251538Srpaulo#endif 3040251538Srpaulo} 3041251538Srpaulo 3042251538Srpaulovoid 3043266578Shselaskyurtwn_r88e_get_txpower(struct urtwn_softc *sc, int chain, 3044266578Shselasky struct ieee80211_channel *c, struct ieee80211_channel *extc, 3045266578Shselasky uint16_t power[URTWN_RIDX_COUNT]) 3046266578Shselasky{ 3047266578Shselasky struct ieee80211com *ic = sc->sc_ifp->if_l2com; 3048266578Shselasky uint16_t cckpow, ofdmpow, bw20pow, htpow; 3049266578Shselasky const struct urtwn_r88e_txpwr *base; 3050266578Shselasky int ridx, chan, group; 3051266578Shselasky 3052266578Shselasky /* Determine channel group. */ 3053266578Shselasky chan = ieee80211_chan2ieee(ic, c); /* XXX center freq! */ 3054266578Shselasky if (chan <= 2) 3055266578Shselasky group = 0; 3056266578Shselasky else if (chan <= 5) 3057266578Shselasky group = 1; 3058266578Shselasky else if (chan <= 8) 3059266578Shselasky group = 2; 3060266578Shselasky else if (chan <= 11) 3061266578Shselasky group = 3; 3062266578Shselasky else if (chan <= 13) 3063266578Shselasky group = 4; 3064266578Shselasky else 3065266578Shselasky group = 5; 3066266578Shselasky 3067266578Shselasky /* Get original Tx power based on board type and RF chain. */ 3068266578Shselasky base = &rtl8188eu_txagc[chain]; 3069266578Shselasky 3070266578Shselasky memset(power, 0, URTWN_RIDX_COUNT * sizeof(power[0])); 3071266578Shselasky if (sc->regulatory == 0) { 3072266578Shselasky for (ridx = 0; ridx <= 3; ridx++) 3073266578Shselasky power[ridx] = base->pwr[0][ridx]; 3074266578Shselasky } 3075266578Shselasky for (ridx = 4; ridx < URTWN_RIDX_COUNT; ridx++) { 3076266578Shselasky if (sc->regulatory == 3) 3077266578Shselasky power[ridx] = base->pwr[0][ridx]; 3078266578Shselasky else if (sc->regulatory == 1) { 3079266578Shselasky if (extc == NULL) 3080266578Shselasky power[ridx] = base->pwr[group][ridx]; 3081266578Shselasky } else if (sc->regulatory != 2) 3082266578Shselasky power[ridx] = base->pwr[0][ridx]; 3083266578Shselasky } 3084266578Shselasky 3085266578Shselasky /* Compute per-CCK rate Tx power. */ 3086266578Shselasky cckpow = sc->cck_tx_pwr[group]; 3087266578Shselasky for (ridx = 0; ridx <= 3; ridx++) { 3088266578Shselasky power[ridx] += cckpow; 3089266578Shselasky if (power[ridx] > R92C_MAX_TX_PWR) 3090266578Shselasky power[ridx] = R92C_MAX_TX_PWR; 3091266578Shselasky } 3092266578Shselasky 3093266578Shselasky htpow = sc->ht40_tx_pwr[group]; 3094266578Shselasky 3095266578Shselasky /* Compute per-OFDM rate Tx power. */ 3096266578Shselasky ofdmpow = htpow + sc->ofdm_tx_pwr_diff; 3097266578Shselasky for (ridx = 4; ridx <= 11; ridx++) { 3098266578Shselasky power[ridx] += ofdmpow; 3099266578Shselasky if (power[ridx] > R92C_MAX_TX_PWR) 3100266578Shselasky power[ridx] = R92C_MAX_TX_PWR; 3101266578Shselasky } 3102266578Shselasky 3103266578Shselasky bw20pow = htpow + sc->bw20_tx_pwr_diff; 3104266578Shselasky for (ridx = 12; ridx <= 27; ridx++) { 3105266578Shselasky power[ridx] += bw20pow; 3106266578Shselasky if (power[ridx] > R92C_MAX_TX_PWR) 3107266578Shselasky power[ridx] = R92C_MAX_TX_PWR; 3108266578Shselasky } 3109266578Shselasky} 3110266578Shselasky 3111266578Shselaskyvoid 3112251538Srpaulourtwn_set_txpower(struct urtwn_softc *sc, struct ieee80211_channel *c, 3113251538Srpaulo struct ieee80211_channel *extc) 3114251538Srpaulo{ 3115251538Srpaulo uint16_t power[URTWN_RIDX_COUNT]; 3116251538Srpaulo int i; 3117251538Srpaulo 3118251538Srpaulo for (i = 0; i < sc->ntxchains; i++) { 3119251538Srpaulo /* Compute per-rate Tx power values. */ 3120266578Shselasky if (sc->chip & URTWN_CHIP_88E) 3121266578Shselasky urtwn_r88e_get_txpower(sc, i, c, extc, power); 3122266578Shselasky else 3123266578Shselasky urtwn_get_txpower(sc, i, c, extc, power); 3124251538Srpaulo /* Write per-rate Tx power values to hardware. */ 3125251538Srpaulo urtwn_write_txpower(sc, i, power); 3126251538Srpaulo } 3127251538Srpaulo} 3128251538Srpaulo 3129251538Srpaulostatic void 3130251538Srpaulourtwn_scan_start(struct ieee80211com *ic) 3131251538Srpaulo{ 3132251538Srpaulo /* XXX do nothing? */ 3133251538Srpaulo} 3134251538Srpaulo 3135251538Srpaulostatic void 3136251538Srpaulourtwn_scan_end(struct ieee80211com *ic) 3137251538Srpaulo{ 3138251538Srpaulo /* XXX do nothing? */ 3139251538Srpaulo} 3140251538Srpaulo 3141251538Srpaulostatic void 3142251538Srpaulourtwn_set_channel(struct ieee80211com *ic) 3143251538Srpaulo{ 3144251538Srpaulo struct urtwn_softc *sc = ic->ic_ifp->if_softc; 3145281390Srpaulo struct ieee80211vap *vap = TAILQ_FIRST(&ic->ic_vaps); 3146251538Srpaulo 3147251538Srpaulo URTWN_LOCK(sc); 3148281390Srpaulo if (vap->iv_state == IEEE80211_S_SCAN) { 3149281390Srpaulo /* Make link LED blink during scan. */ 3150281390Srpaulo urtwn_set_led(sc, URTWN_LED_LINK, !sc->ledlink); 3151281390Srpaulo } 3152251538Srpaulo urtwn_set_chan(sc, ic->ic_curchan, NULL); 3153251538Srpaulo URTWN_UNLOCK(sc); 3154251538Srpaulo} 3155251538Srpaulo 3156251538Srpaulostatic void 3157251538Srpaulourtwn_update_mcast(struct ifnet *ifp) 3158251538Srpaulo{ 3159251538Srpaulo /* XXX do nothing? */ 3160251538Srpaulo} 3161251538Srpaulo 3162251538Srpaulostatic void 3163251538Srpaulourtwn_set_chan(struct urtwn_softc *sc, struct ieee80211_channel *c, 3164251538Srpaulo struct ieee80211_channel *extc) 3165251538Srpaulo{ 3166251538Srpaulo struct ieee80211com *ic = sc->sc_ifp->if_l2com; 3167251538Srpaulo uint32_t reg; 3168251538Srpaulo u_int chan; 3169251538Srpaulo int i; 3170251538Srpaulo 3171251538Srpaulo chan = ieee80211_chan2ieee(ic, c); /* XXX center freq! */ 3172251538Srpaulo if (chan == 0 || chan == IEEE80211_CHAN_ANY) { 3173251538Srpaulo device_printf(sc->sc_dev, 3174251538Srpaulo "%s: invalid channel %x\n", __func__, chan); 3175251538Srpaulo return; 3176251538Srpaulo } 3177251538Srpaulo 3178251538Srpaulo /* Set Tx power for this new channel. */ 3179251538Srpaulo urtwn_set_txpower(sc, c, extc); 3180251538Srpaulo 3181251538Srpaulo for (i = 0; i < sc->nrxchains; i++) { 3182251538Srpaulo urtwn_rf_write(sc, i, R92C_RF_CHNLBW, 3183251538Srpaulo RW(sc->rf_chnlbw[i], R92C_RF_CHNLBW_CHNL, chan)); 3184251538Srpaulo } 3185251538Srpaulo#ifndef IEEE80211_NO_HT 3186251538Srpaulo if (extc != NULL) { 3187251538Srpaulo /* Is secondary channel below or above primary? */ 3188251538Srpaulo int prichlo = c->ic_freq < extc->ic_freq; 3189251538Srpaulo 3190251538Srpaulo urtwn_write_1(sc, R92C_BWOPMODE, 3191251538Srpaulo urtwn_read_1(sc, R92C_BWOPMODE) & ~R92C_BWOPMODE_20MHZ); 3192251538Srpaulo 3193251538Srpaulo reg = urtwn_read_1(sc, R92C_RRSR + 2); 3194251538Srpaulo reg = (reg & ~0x6f) | (prichlo ? 1 : 2) << 5; 3195251538Srpaulo urtwn_write_1(sc, R92C_RRSR + 2, reg); 3196251538Srpaulo 3197251538Srpaulo urtwn_bb_write(sc, R92C_FPGA0_RFMOD, 3198251538Srpaulo urtwn_bb_read(sc, R92C_FPGA0_RFMOD) | R92C_RFMOD_40MHZ); 3199251538Srpaulo urtwn_bb_write(sc, R92C_FPGA1_RFMOD, 3200251538Srpaulo urtwn_bb_read(sc, R92C_FPGA1_RFMOD) | R92C_RFMOD_40MHZ); 3201251538Srpaulo 3202251538Srpaulo /* Set CCK side band. */ 3203251538Srpaulo reg = urtwn_bb_read(sc, R92C_CCK0_SYSTEM); 3204251538Srpaulo reg = (reg & ~0x00000010) | (prichlo ? 0 : 1) << 4; 3205251538Srpaulo urtwn_bb_write(sc, R92C_CCK0_SYSTEM, reg); 3206251538Srpaulo 3207251538Srpaulo reg = urtwn_bb_read(sc, R92C_OFDM1_LSTF); 3208251538Srpaulo reg = (reg & ~0x00000c00) | (prichlo ? 1 : 2) << 10; 3209251538Srpaulo urtwn_bb_write(sc, R92C_OFDM1_LSTF, reg); 3210251538Srpaulo 3211251538Srpaulo urtwn_bb_write(sc, R92C_FPGA0_ANAPARAM2, 3212251538Srpaulo urtwn_bb_read(sc, R92C_FPGA0_ANAPARAM2) & 3213251538Srpaulo ~R92C_FPGA0_ANAPARAM2_CBW20); 3214251538Srpaulo 3215251538Srpaulo reg = urtwn_bb_read(sc, 0x818); 3216251538Srpaulo reg = (reg & ~0x0c000000) | (prichlo ? 2 : 1) << 26; 3217251538Srpaulo urtwn_bb_write(sc, 0x818, reg); 3218251538Srpaulo 3219251538Srpaulo /* Select 40MHz bandwidth. */ 3220251538Srpaulo urtwn_rf_write(sc, 0, R92C_RF_CHNLBW, 3221251538Srpaulo (sc->rf_chnlbw[0] & ~0xfff) | chan); 3222251538Srpaulo } else 3223251538Srpaulo#endif 3224251538Srpaulo { 3225251538Srpaulo urtwn_write_1(sc, R92C_BWOPMODE, 3226251538Srpaulo urtwn_read_1(sc, R92C_BWOPMODE) | R92C_BWOPMODE_20MHZ); 3227251538Srpaulo 3228251538Srpaulo urtwn_bb_write(sc, R92C_FPGA0_RFMOD, 3229251538Srpaulo urtwn_bb_read(sc, R92C_FPGA0_RFMOD) & ~R92C_RFMOD_40MHZ); 3230251538Srpaulo urtwn_bb_write(sc, R92C_FPGA1_RFMOD, 3231251538Srpaulo urtwn_bb_read(sc, R92C_FPGA1_RFMOD) & ~R92C_RFMOD_40MHZ); 3232251538Srpaulo 3233266578Shselasky if (!(sc->chip & URTWN_CHIP_88E)) { 3234266578Shselasky urtwn_bb_write(sc, R92C_FPGA0_ANAPARAM2, 3235266578Shselasky urtwn_bb_read(sc, R92C_FPGA0_ANAPARAM2) | 3236266578Shselasky R92C_FPGA0_ANAPARAM2_CBW20); 3237266578Shselasky } 3238266578Shselasky 3239251538Srpaulo /* Select 20MHz bandwidth. */ 3240251538Srpaulo urtwn_rf_write(sc, 0, R92C_RF_CHNLBW, 3241266578Shselasky (sc->rf_chnlbw[0] & ~0xfff) | chan | 3242266578Shselasky ((sc->chip & URTWN_CHIP_88E) ? R88E_RF_CHNLBW_BW20 : 3243266578Shselasky R92C_RF_CHNLBW_BW20)); 3244251538Srpaulo } 3245251538Srpaulo} 3246251538Srpaulo 3247251538Srpaulostatic void 3248251538Srpaulourtwn_iq_calib(struct urtwn_softc *sc) 3249251538Srpaulo{ 3250251538Srpaulo /* TODO */ 3251251538Srpaulo} 3252251538Srpaulo 3253251538Srpaulostatic void 3254251538Srpaulourtwn_lc_calib(struct urtwn_softc *sc) 3255251538Srpaulo{ 3256251538Srpaulo uint32_t rf_ac[2]; 3257251538Srpaulo uint8_t txmode; 3258251538Srpaulo int i; 3259251538Srpaulo 3260251538Srpaulo txmode = urtwn_read_1(sc, R92C_OFDM1_LSTF + 3); 3261251538Srpaulo if ((txmode & 0x70) != 0) { 3262251538Srpaulo /* Disable all continuous Tx. */ 3263251538Srpaulo urtwn_write_1(sc, R92C_OFDM1_LSTF + 3, txmode & ~0x70); 3264251538Srpaulo 3265251538Srpaulo /* Set RF mode to standby mode. */ 3266251538Srpaulo for (i = 0; i < sc->nrxchains; i++) { 3267251538Srpaulo rf_ac[i] = urtwn_rf_read(sc, i, R92C_RF_AC); 3268251538Srpaulo urtwn_rf_write(sc, i, R92C_RF_AC, 3269251538Srpaulo RW(rf_ac[i], R92C_RF_AC_MODE, 3270251538Srpaulo R92C_RF_AC_MODE_STANDBY)); 3271251538Srpaulo } 3272251538Srpaulo } else { 3273251538Srpaulo /* Block all Tx queues. */ 3274251538Srpaulo urtwn_write_1(sc, R92C_TXPAUSE, 0xff); 3275251538Srpaulo } 3276251538Srpaulo /* Start calibration. */ 3277251538Srpaulo urtwn_rf_write(sc, 0, R92C_RF_CHNLBW, 3278251538Srpaulo urtwn_rf_read(sc, 0, R92C_RF_CHNLBW) | R92C_RF_CHNLBW_LCSTART); 3279251538Srpaulo 3280251538Srpaulo /* Give calibration the time to complete. */ 3281266578Shselasky usb_pause_mtx(&sc->sc_mtx, hz / 10); /* 100ms */ 3282251538Srpaulo 3283251538Srpaulo /* Restore configuration. */ 3284251538Srpaulo if ((txmode & 0x70) != 0) { 3285251538Srpaulo /* Restore Tx mode. */ 3286251538Srpaulo urtwn_write_1(sc, R92C_OFDM1_LSTF + 3, txmode); 3287251538Srpaulo /* Restore RF mode. */ 3288251538Srpaulo for (i = 0; i < sc->nrxchains; i++) 3289251538Srpaulo urtwn_rf_write(sc, i, R92C_RF_AC, rf_ac[i]); 3290251538Srpaulo } else { 3291251538Srpaulo /* Unblock all Tx queues. */ 3292251538Srpaulo urtwn_write_1(sc, R92C_TXPAUSE, 0x00); 3293251538Srpaulo } 3294251538Srpaulo} 3295251538Srpaulo 3296251538Srpaulostatic void 3297251538Srpaulourtwn_init_locked(void *arg) 3298251538Srpaulo{ 3299251538Srpaulo struct urtwn_softc *sc = arg; 3300251538Srpaulo struct ifnet *ifp = sc->sc_ifp; 3301251538Srpaulo uint32_t reg; 3302251538Srpaulo int error; 3303251538Srpaulo 3304265345Skevlo URTWN_ASSERT_LOCKED(sc); 3305265345Skevlo 3306251538Srpaulo if (ifp->if_drv_flags & IFF_DRV_RUNNING) 3307263256Skevlo urtwn_stop_locked(ifp); 3308251538Srpaulo 3309251538Srpaulo /* Init firmware commands ring. */ 3310251538Srpaulo sc->fwcur = 0; 3311251538Srpaulo 3312251538Srpaulo /* Allocate Tx/Rx buffers. */ 3313251538Srpaulo error = urtwn_alloc_rx_list(sc); 3314251538Srpaulo if (error != 0) 3315251538Srpaulo goto fail; 3316251538Srpaulo 3317251538Srpaulo error = urtwn_alloc_tx_list(sc); 3318251538Srpaulo if (error != 0) 3319251538Srpaulo goto fail; 3320251538Srpaulo 3321251538Srpaulo /* Power on adapter. */ 3322251538Srpaulo error = urtwn_power_on(sc); 3323251538Srpaulo if (error != 0) 3324251538Srpaulo goto fail; 3325251538Srpaulo 3326251538Srpaulo /* Initialize DMA. */ 3327251538Srpaulo error = urtwn_dma_init(sc); 3328251538Srpaulo if (error != 0) 3329251538Srpaulo goto fail; 3330251538Srpaulo 3331251538Srpaulo /* Set info size in Rx descriptors (in 64-bit words). */ 3332251538Srpaulo urtwn_write_1(sc, R92C_RX_DRVINFO_SZ, 4); 3333251538Srpaulo 3334251538Srpaulo /* Init interrupts. */ 3335266578Shselasky if (sc->chip & URTWN_CHIP_88E) { 3336266578Shselasky urtwn_write_4(sc, R88E_HISR, 0xffffffff); 3337266578Shselasky urtwn_write_4(sc, R88E_HIMR, R88E_HIMR_CPWM | R88E_HIMR_CPWM2 | 3338266578Shselasky R88E_HIMR_TBDER | R88E_HIMR_PSTIMEOUT); 3339266578Shselasky urtwn_write_4(sc, R88E_HIMRE, R88E_HIMRE_RXFOVW | 3340266578Shselasky R88E_HIMRE_TXFOVW | R88E_HIMRE_RXERR | R88E_HIMRE_TXERR); 3341266578Shselasky urtwn_write_1(sc, R92C_USB_SPECIAL_OPTION, 3342266578Shselasky urtwn_read_1(sc, R92C_USB_SPECIAL_OPTION) | 3343266578Shselasky R92C_USB_SPECIAL_OPTION_INT_BULK_SEL); 3344266578Shselasky } else { 3345266578Shselasky urtwn_write_4(sc, R92C_HISR, 0xffffffff); 3346266578Shselasky urtwn_write_4(sc, R92C_HIMR, 0xffffffff); 3347266578Shselasky } 3348251538Srpaulo 3349251538Srpaulo /* Set MAC address. */ 3350251538Srpaulo urtwn_write_region_1(sc, R92C_MACID, IF_LLADDR(ifp), 3351251538Srpaulo IEEE80211_ADDR_LEN); 3352251538Srpaulo 3353251538Srpaulo /* Set initial network type. */ 3354251538Srpaulo reg = urtwn_read_4(sc, R92C_CR); 3355251538Srpaulo reg = RW(reg, R92C_CR_NETTYPE, R92C_CR_NETTYPE_INFRA); 3356251538Srpaulo urtwn_write_4(sc, R92C_CR, reg); 3357251538Srpaulo 3358251538Srpaulo urtwn_rxfilter_init(sc); 3359251538Srpaulo 3360251538Srpaulo reg = urtwn_read_4(sc, R92C_RRSR); 3361251538Srpaulo reg = RW(reg, R92C_RRSR_RATE_BITMAP, R92C_RRSR_RATE_CCK_ONLY_1M); 3362251538Srpaulo urtwn_write_4(sc, R92C_RRSR, reg); 3363251538Srpaulo 3364251538Srpaulo /* Set short/long retry limits. */ 3365251538Srpaulo urtwn_write_2(sc, R92C_RL, 3366251538Srpaulo SM(R92C_RL_SRL, 0x30) | SM(R92C_RL_LRL, 0x30)); 3367251538Srpaulo 3368251538Srpaulo /* Initialize EDCA parameters. */ 3369251538Srpaulo urtwn_edca_init(sc); 3370251538Srpaulo 3371251538Srpaulo /* Setup rate fallback. */ 3372266578Shselasky if (!(sc->chip & URTWN_CHIP_88E)) { 3373266578Shselasky urtwn_write_4(sc, R92C_DARFRC + 0, 0x00000000); 3374266578Shselasky urtwn_write_4(sc, R92C_DARFRC + 4, 0x10080404); 3375266578Shselasky urtwn_write_4(sc, R92C_RARFRC + 0, 0x04030201); 3376266578Shselasky urtwn_write_4(sc, R92C_RARFRC + 4, 0x08070605); 3377266578Shselasky } 3378251538Srpaulo 3379251538Srpaulo urtwn_write_1(sc, R92C_FWHW_TXQ_CTRL, 3380251538Srpaulo urtwn_read_1(sc, R92C_FWHW_TXQ_CTRL) | 3381251538Srpaulo R92C_FWHW_TXQ_CTRL_AMPDU_RTY_NEW); 3382251538Srpaulo /* Set ACK timeout. */ 3383251538Srpaulo urtwn_write_1(sc, R92C_ACKTO, 0x40); 3384251538Srpaulo 3385251538Srpaulo /* Setup USB aggregation. */ 3386251538Srpaulo reg = urtwn_read_4(sc, R92C_TDECTRL); 3387251538Srpaulo reg = RW(reg, R92C_TDECTRL_BLK_DESC_NUM, 6); 3388251538Srpaulo urtwn_write_4(sc, R92C_TDECTRL, reg); 3389251538Srpaulo urtwn_write_1(sc, R92C_TRXDMA_CTRL, 3390251538Srpaulo urtwn_read_1(sc, R92C_TRXDMA_CTRL) | 3391251538Srpaulo R92C_TRXDMA_CTRL_RXDMA_AGG_EN); 3392251538Srpaulo urtwn_write_1(sc, R92C_RXDMA_AGG_PG_TH, 48); 3393266578Shselasky if (sc->chip & URTWN_CHIP_88E) 3394266578Shselasky urtwn_write_1(sc, R92C_RXDMA_AGG_PG_TH + 1, 4); 3395282366Skevlo else { 3396266578Shselasky urtwn_write_1(sc, R92C_USB_DMA_AGG_TO, 4); 3397282366Skevlo urtwn_write_1(sc, R92C_USB_SPECIAL_OPTION, 3398282366Skevlo urtwn_read_1(sc, R92C_USB_SPECIAL_OPTION) | 3399282366Skevlo R92C_USB_SPECIAL_OPTION_AGG_EN); 3400282366Skevlo urtwn_write_1(sc, R92C_USB_AGG_TH, 8); 3401282366Skevlo urtwn_write_1(sc, R92C_USB_AGG_TO, 6); 3402282366Skevlo } 3403251538Srpaulo 3404251538Srpaulo /* Initialize beacon parameters. */ 3405266578Shselasky urtwn_write_2(sc, R92C_BCN_CTRL, 0x1010); 3406251538Srpaulo urtwn_write_2(sc, R92C_TBTT_PROHIBIT, 0x6404); 3407251538Srpaulo urtwn_write_1(sc, R92C_DRVERLYINT, 0x05); 3408251538Srpaulo urtwn_write_1(sc, R92C_BCNDMATIM, 0x02); 3409251538Srpaulo urtwn_write_2(sc, R92C_BCNTCFG, 0x660f); 3410251538Srpaulo 3411266578Shselasky if (!(sc->chip & URTWN_CHIP_88E)) { 3412266578Shselasky /* Setup AMPDU aggregation. */ 3413266578Shselasky urtwn_write_4(sc, R92C_AGGLEN_LMT, 0x99997631); /* MCS7~0 */ 3414266578Shselasky urtwn_write_1(sc, R92C_AGGR_BREAK_TIME, 0x16); 3415266578Shselasky urtwn_write_2(sc, R92C_MAX_AGGR_NUM, 0x0708); 3416251538Srpaulo 3417266578Shselasky urtwn_write_1(sc, R92C_BCN_MAX_ERR, 0xff); 3418266578Shselasky } 3419251538Srpaulo 3420251538Srpaulo /* Load 8051 microcode. */ 3421251538Srpaulo error = urtwn_load_firmware(sc); 3422251538Srpaulo if (error != 0) 3423251538Srpaulo goto fail; 3424251538Srpaulo 3425251538Srpaulo /* Initialize MAC/BB/RF blocks. */ 3426251538Srpaulo urtwn_mac_init(sc); 3427251538Srpaulo urtwn_bb_init(sc); 3428251538Srpaulo urtwn_rf_init(sc); 3429251538Srpaulo 3430266578Shselasky if (sc->chip & URTWN_CHIP_88E) { 3431266578Shselasky urtwn_write_2(sc, R92C_CR, 3432266578Shselasky urtwn_read_2(sc, R92C_CR) | R92C_CR_MACTXEN | 3433266578Shselasky R92C_CR_MACRXEN); 3434266578Shselasky } 3435266578Shselasky 3436251538Srpaulo /* Turn CCK and OFDM blocks on. */ 3437251538Srpaulo reg = urtwn_bb_read(sc, R92C_FPGA0_RFMOD); 3438251538Srpaulo reg |= R92C_RFMOD_CCK_EN; 3439251538Srpaulo urtwn_bb_write(sc, R92C_FPGA0_RFMOD, reg); 3440251538Srpaulo reg = urtwn_bb_read(sc, R92C_FPGA0_RFMOD); 3441251538Srpaulo reg |= R92C_RFMOD_OFDM_EN; 3442251538Srpaulo urtwn_bb_write(sc, R92C_FPGA0_RFMOD, reg); 3443251538Srpaulo 3444251538Srpaulo /* Clear per-station keys table. */ 3445251538Srpaulo urtwn_cam_init(sc); 3446251538Srpaulo 3447251538Srpaulo /* Enable hardware sequence numbering. */ 3448251538Srpaulo urtwn_write_1(sc, R92C_HWSEQ_CTRL, 0xff); 3449251538Srpaulo 3450251538Srpaulo /* Perform LO and IQ calibrations. */ 3451251538Srpaulo urtwn_iq_calib(sc); 3452251538Srpaulo /* Perform LC calibration. */ 3453251538Srpaulo urtwn_lc_calib(sc); 3454251538Srpaulo 3455251538Srpaulo /* Fix USB interference issue. */ 3456266578Shselasky if (!(sc->chip & URTWN_CHIP_88E)) { 3457266578Shselasky urtwn_write_1(sc, 0xfe40, 0xe0); 3458266578Shselasky urtwn_write_1(sc, 0xfe41, 0x8d); 3459266578Shselasky urtwn_write_1(sc, 0xfe42, 0x80); 3460251538Srpaulo 3461266578Shselasky urtwn_pa_bias_init(sc); 3462266578Shselasky } 3463251538Srpaulo 3464251538Srpaulo /* Initialize GPIO setting. */ 3465251538Srpaulo urtwn_write_1(sc, R92C_GPIO_MUXCFG, 3466251538Srpaulo urtwn_read_1(sc, R92C_GPIO_MUXCFG) & ~R92C_GPIO_MUXCFG_ENBT); 3467251538Srpaulo 3468251538Srpaulo /* Fix for lower temperature. */ 3469266578Shselasky if (!(sc->chip & URTWN_CHIP_88E)) 3470266578Shselasky urtwn_write_1(sc, 0x15, 0xe9); 3471251538Srpaulo 3472251538Srpaulo usbd_transfer_start(sc->sc_xfer[URTWN_BULK_RX]); 3473251538Srpaulo 3474251538Srpaulo ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 3475251538Srpaulo ifp->if_drv_flags |= IFF_DRV_RUNNING; 3476251538Srpaulo 3477251538Srpaulo callout_reset(&sc->sc_watchdog_ch, hz, urtwn_watchdog, sc); 3478251538Srpaulofail: 3479251538Srpaulo return; 3480251538Srpaulo} 3481251538Srpaulo 3482251538Srpaulostatic void 3483251538Srpaulourtwn_init(void *arg) 3484251538Srpaulo{ 3485251538Srpaulo struct urtwn_softc *sc = arg; 3486251538Srpaulo 3487251538Srpaulo URTWN_LOCK(sc); 3488251538Srpaulo urtwn_init_locked(arg); 3489251538Srpaulo URTWN_UNLOCK(sc); 3490251538Srpaulo} 3491251538Srpaulo 3492251538Srpaulostatic void 3493263256Skevlourtwn_stop_locked(struct ifnet *ifp) 3494251538Srpaulo{ 3495251538Srpaulo struct urtwn_softc *sc = ifp->if_softc; 3496251538Srpaulo 3497265345Skevlo URTWN_ASSERT_LOCKED(sc); 3498265345Skevlo 3499251538Srpaulo ifp->if_drv_flags &= ~(IFF_DRV_RUNNING | IFF_DRV_OACTIVE); 3500251538Srpaulo 3501251538Srpaulo callout_stop(&sc->sc_watchdog_ch); 3502251538Srpaulo urtwn_abort_xfers(sc); 3503251538Srpaulo} 3504251538Srpaulo 3505251538Srpaulostatic void 3506263256Skevlourtwn_stop(struct ifnet *ifp) 3507251538Srpaulo{ 3508251538Srpaulo struct urtwn_softc *sc = ifp->if_softc; 3509251538Srpaulo 3510251538Srpaulo URTWN_LOCK(sc); 3511263256Skevlo urtwn_stop_locked(ifp); 3512251538Srpaulo URTWN_UNLOCK(sc); 3513251538Srpaulo} 3514251538Srpaulo 3515251538Srpaulostatic void 3516251538Srpaulourtwn_abort_xfers(struct urtwn_softc *sc) 3517251538Srpaulo{ 3518251538Srpaulo int i; 3519251538Srpaulo 3520251538Srpaulo URTWN_ASSERT_LOCKED(sc); 3521251538Srpaulo 3522251538Srpaulo /* abort any pending transfers */ 3523251538Srpaulo for (i = 0; i < URTWN_N_TRANSFER; i++) 3524251538Srpaulo usbd_transfer_stop(sc->sc_xfer[i]); 3525251538Srpaulo} 3526251538Srpaulo 3527251538Srpaulostatic int 3528251538Srpaulourtwn_raw_xmit(struct ieee80211_node *ni, struct mbuf *m, 3529251538Srpaulo const struct ieee80211_bpf_params *params) 3530251538Srpaulo{ 3531251538Srpaulo struct ieee80211com *ic = ni->ni_ic; 3532251538Srpaulo struct ifnet *ifp = ic->ic_ifp; 3533251538Srpaulo struct urtwn_softc *sc = ifp->if_softc; 3534251538Srpaulo struct urtwn_data *bf; 3535251538Srpaulo 3536251538Srpaulo /* prevent management frames from being sent if we're not ready */ 3537251538Srpaulo if (!(ifp->if_drv_flags & IFF_DRV_RUNNING)) { 3538251538Srpaulo m_freem(m); 3539251538Srpaulo ieee80211_free_node(ni); 3540251538Srpaulo return (ENETDOWN); 3541251538Srpaulo } 3542251538Srpaulo URTWN_LOCK(sc); 3543251538Srpaulo bf = urtwn_getbuf(sc); 3544251538Srpaulo if (bf == NULL) { 3545251538Srpaulo ieee80211_free_node(ni); 3546251538Srpaulo m_freem(m); 3547251538Srpaulo URTWN_UNLOCK(sc); 3548251538Srpaulo return (ENOBUFS); 3549251538Srpaulo } 3550251538Srpaulo 3551251538Srpaulo ifp->if_opackets++; 3552251538Srpaulo if (urtwn_tx_start(sc, ni, m, bf) != 0) { 3553251538Srpaulo ieee80211_free_node(ni); 3554251538Srpaulo ifp->if_oerrors++; 3555251538Srpaulo STAILQ_INSERT_HEAD(&sc->sc_tx_inactive, bf, next); 3556251538Srpaulo URTWN_UNLOCK(sc); 3557251538Srpaulo return (EIO); 3558251538Srpaulo } 3559251538Srpaulo URTWN_UNLOCK(sc); 3560251538Srpaulo 3561251538Srpaulo sc->sc_txtimer = 5; 3562251538Srpaulo return (0); 3563251538Srpaulo} 3564251538Srpaulo 3565266578Shselaskystatic void 3566266578Shselaskyurtwn_ms_delay(struct urtwn_softc *sc) 3567266578Shselasky{ 3568266578Shselasky usb_pause_mtx(&sc->sc_mtx, hz / 1000); 3569266578Shselasky} 3570266578Shselasky 3571251538Srpaulostatic device_method_t urtwn_methods[] = { 3572251538Srpaulo /* Device interface */ 3573251538Srpaulo DEVMETHOD(device_probe, urtwn_match), 3574251538Srpaulo DEVMETHOD(device_attach, urtwn_attach), 3575251538Srpaulo DEVMETHOD(device_detach, urtwn_detach), 3576251538Srpaulo 3577266578Shselasky DEVMETHOD_END 3578251538Srpaulo}; 3579251538Srpaulo 3580251538Srpaulostatic driver_t urtwn_driver = { 3581251538Srpaulo "urtwn", 3582251538Srpaulo urtwn_methods, 3583251538Srpaulo sizeof(struct urtwn_softc) 3584251538Srpaulo}; 3585251538Srpaulo 3586251538Srpaulostatic devclass_t urtwn_devclass; 3587251538Srpaulo 3588251538SrpauloDRIVER_MODULE(urtwn, uhub, urtwn_driver, urtwn_devclass, NULL, NULL); 3589251538SrpauloMODULE_DEPEND(urtwn, usb, 1, 1, 1); 3590251538SrpauloMODULE_DEPEND(urtwn, wlan, 1, 1, 1); 3591251538SrpauloMODULE_DEPEND(urtwn, firmware, 1, 1, 1); 3592251538SrpauloMODULE_VERSION(urtwn, 1); 3593