1258331Smarkj/*- 2266991Skevlo * Copyright (c) 2013-2014 Kevin Lo 3258331Smarkj * All rights reserved. 4258331Smarkj * 5258331Smarkj * Redistribution and use in source and binary forms, with or without 6258331Smarkj * modification, are permitted provided that the following conditions 7258331Smarkj * are met: 8258331Smarkj * 1. Redistributions of source code must retain the above copyright 9258331Smarkj * notice, this list of conditions and the following disclaimer. 10258331Smarkj * 2. Redistributions in binary form must reproduce the above copyright 11258331Smarkj * notice, this list of conditions and the following disclaimer in the 12258331Smarkj * documentation and/or other materials provided with the distribution. 13258331Smarkj * 14258331Smarkj * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 15258331Smarkj * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 16258331Smarkj * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 17258331Smarkj * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 18258331Smarkj * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 19258331Smarkj * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 20258331Smarkj * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 21258331Smarkj * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 22258331Smarkj * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 23258331Smarkj * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 24258331Smarkj * THE POSSIBILITY OF SUCH DAMAGE. 25258331Smarkj * 26258331Smarkj * $FreeBSD$ 27258331Smarkj */ 28258331Smarkj 29258331Smarkj#define AXGE_ACCESS_MAC 0x01 30258331Smarkj#define AXGE_ACCESS_PHY 0x02 31258331Smarkj#define AXGE_ACCESS_WAKEUP 0x03 32258331Smarkj#define AXGE_ACCESS_EEPROM 0x04 33258331Smarkj#define AXGE_ACCESS_EFUSE 0x05 34258331Smarkj#define AXGE_RELOAD_EEPROM_EFUSE 0x06 35258331Smarkj#define AXGE_WRITE_EFUSE_EN 0x09 36258331Smarkj#define AXGE_WRITE_EFUSE_DIS 0x0A 37258331Smarkj#define AXGE_ACCESS_MFAB 0x10 38258331Smarkj 39266991Skevlo/* Physical link status register */ 40266991Skevlo#define AXGE_PLSR 0x02 41266991Skevlo#define PLSR_USB_FS 0x01 42266991Skevlo#define PLSR_USB_HS 0x02 43266991Skevlo#define PLSR_USB_SS 0x04 44258331Smarkj 45266991Skevlo/* EEPROM address register */ 46266991Skevlo#define AXGE_EAR 0x07 47258331Smarkj 48266991Skevlo/* EEPROM data low register */ 49266991Skevlo#define AXGE_EDLR 0x08 50258331Smarkj 51266991Skevlo/* EEPROM data high register */ 52266991Skevlo#define AXGE_EDHR 0x09 53258331Smarkj 54266991Skevlo/* EEPROM command register */ 55266991Skevlo#define AXGE_ECR 0x0a 56258331Smarkj 57266991Skevlo/* Rx control register */ 58266991Skevlo#define AXGE_RCR 0x0b 59266991Skevlo#define RCR_STOP 0x0000 60266991Skevlo#define RCR_PRO 0x0001 61266991Skevlo#define RCR_AMALL 0x0002 62266991Skevlo#define RCR_AB 0x0008 63266991Skevlo#define RCR_AM 0x0010 64266991Skevlo#define RCR_AP 0x0020 65266991Skevlo#define RCR_SO 0x0080 66266991Skevlo#define RCR_DROP_CRCE 0x0100 67266991Skevlo#define RCR_IPE 0x0200 68266991Skevlo#define RCR_TX_CRC_PAD 0x0400 69258331Smarkj 70266991Skevlo/* Node id register */ 71266991Skevlo#define AXGE_NIDR 0x10 72258331Smarkj 73266991Skevlo/* Multicast filter array */ 74266991Skevlo#define AXGE_MFA 0x16 75258331Smarkj 76266991Skevlo/* Medium status register */ 77266991Skevlo#define AXGE_MSR 0x22 78266991Skevlo#define MSR_GM 0x0001 79266991Skevlo#define MSR_FD 0x0002 80266991Skevlo#define MSR_EN_125MHZ 0x0008 81266991Skevlo#define MSR_RFC 0x0010 82266991Skevlo#define MSR_TFC 0x0020 83266991Skevlo#define MSR_RE 0x0100 84266991Skevlo#define MSR_PS 0x0200 85266991Skevlo 86266991Skevlo/* Monitor mode status register */ 87266991Skevlo#define AXGE_MMSR 0x24 88266991Skevlo#define MMSR_RWLC 0x02 89266991Skevlo#define MMSR_RWMP 0x04 90266991Skevlo#define MMSR_RWWF 0x08 91266991Skevlo#define MMSR_RW_FLAG 0x10 92266991Skevlo#define MMSR_PME_POL 0x20 93266991Skevlo#define MMSR_PME_TYPE 0x40 94266991Skevlo#define MMSR_PME_IND 0x80 95266991Skevlo 96266991Skevlo/* GPIO control/status register */ 97266991Skevlo#define AXGE_GPIOCR 0x25 98266991Skevlo 99266991Skevlo/* Ethernet PHY power & reset control register */ 100266991Skevlo#define AXGE_EPPRCR 0x26 101266991Skevlo#define EPPRCR_BZ 0x0010 102266991Skevlo#define EPPRCR_IPRL 0x0020 103266991Skevlo#define EPPRCR_AUTODETACH 0x1000 104266991Skevlo 105258331Smarkj#define AXGE_RX_BULKIN_QCTRL 0x2e 106258331Smarkj 107258331Smarkj#define AXGE_CLK_SELECT 0x33 108258331Smarkj#define AXGE_CLK_SELECT_BCS 0x01 109258331Smarkj#define AXGE_CLK_SELECT_ACS 0x02 110258331Smarkj#define AXGE_CLK_SELECT_ACSREQ 0x10 111258331Smarkj#define AXGE_CLK_SELECT_ULR 0x08 112258331Smarkj 113266991Skevlo/* COE Rx control register */ 114266991Skevlo#define AXGE_CRCR 0x34 115266991Skevlo#define CRCR_IP 0x01 116266991Skevlo#define CRCR_TCP 0x02 117266991Skevlo#define CRCR_UDP 0x04 118266991Skevlo#define CRCR_ICMP 0x08 119266991Skevlo#define CRCR_IGMP 0x10 120266991Skevlo#define CRCR_TCPV6 0x20 121266991Skevlo#define CRCR_UDPV6 0x40 122266991Skevlo#define CRCR_ICMPV6 0x80 123258331Smarkj 124266991Skevlo/* COE Tx control register */ 125266991Skevlo#define AXGE_CTCR 0x35 126266991Skevlo#define CTCR_IP 0x01 127266991Skevlo#define CTCR_TCP 0x02 128266991Skevlo#define CTCR_UDP 0x04 129266991Skevlo#define CTCR_ICMP 0x08 130266991Skevlo#define CTCR_IGMP 0x10 131266991Skevlo#define CTCR_TCPV6 0x20 132266991Skevlo#define CTCR_UDPV6 0x40 133266991Skevlo#define CTCR_ICMPV6 0x80 134258331Smarkj 135266991Skevlo/* Pause water level high register */ 136266991Skevlo#define AXGE_PWLHR 0x54 137258331Smarkj 138266991Skevlo/* Pause water level low register */ 139266991Skevlo#define AXGE_PWLLR 0x55 140258331Smarkj 141258331Smarkj#define AXGE_CONFIG_IDX 0 /* config number 1 */ 142258331Smarkj#define AXGE_IFACE_IDX 0 143258331Smarkj 144258331Smarkj#define AXGE_RXHDR_L4_TYPE_MASK 0x1c 145266991Skevlo#define AXGE_RXHDR_L4CSUM_ERR 1 146266991Skevlo#define AXGE_RXHDR_L3CSUM_ERR 2 147258331Smarkj#define AXGE_RXHDR_L4_TYPE_UDP 4 148258331Smarkj#define AXGE_RXHDR_L4_TYPE_TCP 16 149266991Skevlo#define AXGE_RXHDR_CRC_ERR 0x20000000 150266991Skevlo#define AXGE_RXHDR_DROP_ERR 0x80000000 151258331Smarkj 152258331Smarkj#define GET_MII(sc) uether_getmii(&(sc)->sc_ue) 153258331Smarkj 154258331Smarkj/* The interrupt endpoint is currently unused by the ASIX part. */ 155258331Smarkjenum { 156258331Smarkj AXGE_BULK_DT_WR, 157258331Smarkj AXGE_BULK_DT_RD, 158258331Smarkj AXGE_N_TRANSFER, 159258331Smarkj}; 160258331Smarkj 161258331Smarkjstruct axge_softc { 162258331Smarkj struct usb_ether sc_ue; 163258331Smarkj struct mtx sc_mtx; 164258331Smarkj struct usb_xfer *sc_xfer[AXGE_N_TRANSFER]; 165258331Smarkj int sc_phyno; 166258331Smarkj 167258331Smarkj int sc_flags; 168258331Smarkj#define AXGE_FLAG_LINK 0x0001 /* got a link */ 169258331Smarkj}; 170258331Smarkj 171258331Smarkj#define AXGE_LOCK(_sc) mtx_lock(&(_sc)->sc_mtx) 172258331Smarkj#define AXGE_UNLOCK(_sc) mtx_unlock(&(_sc)->sc_mtx) 173258331Smarkj#define AXGE_LOCK_ASSERT(_sc, t) mtx_assert(&(_sc)->sc_mtx, t) 174