if_axereg.h revision 212130
1184610Salfred/*- 2184610Salfred * Copyright (c) 1997, 1998, 1999, 2000-2003 3184610Salfred * Bill Paul <wpaul@windriver.com>. All rights reserved. 4184610Salfred * 5184610Salfred * Redistribution and use in source and binary forms, with or without 6184610Salfred * modification, are permitted provided that the following conditions 7184610Salfred * are met: 8184610Salfred * 1. Redistributions of source code must retain the above copyright 9184610Salfred * notice, this list of conditions and the following disclaimer. 10184610Salfred * 2. Redistributions in binary form must reproduce the above copyright 11184610Salfred * notice, this list of conditions and the following disclaimer in the 12184610Salfred * documentation and/or other materials provided with the distribution. 13184610Salfred * 3. All advertising materials mentioning features or use of this software 14184610Salfred * must display the following acknowledgement: 15184610Salfred * This product includes software developed by Bill Paul. 16184610Salfred * 4. Neither the name of the author nor the names of any co-contributors 17184610Salfred * may be used to endorse or promote products derived from this software 18184610Salfred * without specific prior written permission. 19184610Salfred * 20184610Salfred * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 21184610Salfred * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22184610Salfred * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23184610Salfred * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 24184610Salfred * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25184610Salfred * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26184610Salfred * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27184610Salfred * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28184610Salfred * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29184610Salfred * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 30184610Salfred * THE POSSIBILITY OF SUCH DAMAGE. 31184610Salfred * 32184610Salfred * $FreeBSD: head/sys/dev/usb/net/if_axereg.h 212130 2010-09-02 03:47:07Z thompsa $ 33184610Salfred */ 34184610Salfred 35184610Salfred/* 36184610Salfred * Definitions for the ASIX Electronics AX88172, AX88178 37184610Salfred * and AX88772 to ethernet controllers. 38184610Salfred */ 39184610Salfred 40184610Salfred/* 41184610Salfred * Vendor specific commands. ASIX conveniently doesn't document the 'set 42184610Salfred * NODEID' command in their datasheet (thanks a lot guys). 43184610Salfred * To make handling these commands easier, I added some extra data which is 44184610Salfred * decided by the axe_cmd() routine. Commands are encoded in 16 bits, with 45184610Salfred * the format: LDCC. L and D are both nibbles in the high byte. L represents 46184610Salfred * the data length (0 to 15) and D represents the direction (0 for vendor read, 47184610Salfred * 1 for vendor write). CC is the command byte, as specified in the manual. 48184610Salfred */ 49184610Salfred 50184610Salfred#define AXE_CMD_IS_WRITE(x) (((x) & 0x0F00) >> 8) 51184610Salfred#define AXE_CMD_LEN(x) (((x) & 0xF000) >> 12) 52184610Salfred#define AXE_CMD_CMD(x) ((x) & 0x00FF) 53184610Salfred 54184610Salfred#define AXE_172_CMD_READ_RXTX_SRAM 0x2002 55184610Salfred#define AXE_182_CMD_READ_RXTX_SRAM 0x8002 56184610Salfred#define AXE_172_CMD_WRITE_RX_SRAM 0x0103 57184610Salfred#define AXE_182_CMD_WRITE_RXTX_SRAM 0x8103 58184610Salfred#define AXE_172_CMD_WRITE_TX_SRAM 0x0104 59184610Salfred#define AXE_CMD_MII_OPMODE_SW 0x0106 60184610Salfred#define AXE_CMD_MII_READ_REG 0x2007 61184610Salfred#define AXE_CMD_MII_WRITE_REG 0x2108 62184610Salfred#define AXE_CMD_MII_READ_OPMODE 0x1009 63184610Salfred#define AXE_CMD_MII_OPMODE_HW 0x010A 64184610Salfred#define AXE_CMD_SROM_READ 0x200B 65184610Salfred#define AXE_CMD_SROM_WRITE 0x010C 66184610Salfred#define AXE_CMD_SROM_WR_ENABLE 0x010D 67184610Salfred#define AXE_CMD_SROM_WR_DISABLE 0x010E 68184610Salfred#define AXE_CMD_RXCTL_READ 0x200F 69184610Salfred#define AXE_CMD_RXCTL_WRITE 0x0110 70184610Salfred#define AXE_CMD_READ_IPG012 0x3011 71184610Salfred#define AXE_172_CMD_WRITE_IPG0 0x0112 72184610Salfred#define AXE_178_CMD_WRITE_IPG012 0x0112 73184610Salfred#define AXE_172_CMD_WRITE_IPG1 0x0113 74184610Salfred#define AXE_178_CMD_READ_NODEID 0x6013 75184610Salfred#define AXE_172_CMD_WRITE_IPG2 0x0114 76184610Salfred#define AXE_178_CMD_WRITE_NODEID 0x6114 77184610Salfred#define AXE_CMD_READ_MCAST 0x8015 78184610Salfred#define AXE_CMD_WRITE_MCAST 0x8116 79184610Salfred#define AXE_172_CMD_READ_NODEID 0x6017 80184610Salfred#define AXE_172_CMD_WRITE_NODEID 0x6118 81184610Salfred 82184610Salfred#define AXE_CMD_READ_PHYID 0x2019 83184610Salfred#define AXE_172_CMD_READ_MEDIA 0x101A 84184610Salfred#define AXE_178_CMD_READ_MEDIA 0x201A 85184610Salfred#define AXE_CMD_WRITE_MEDIA 0x011B 86184610Salfred#define AXE_CMD_READ_MONITOR_MODE 0x101C 87184610Salfred#define AXE_CMD_WRITE_MONITOR_MODE 0x011D 88184610Salfred#define AXE_CMD_READ_GPIO 0x101E 89184610Salfred#define AXE_CMD_WRITE_GPIO 0x011F 90184610Salfred 91184610Salfred#define AXE_CMD_SW_RESET_REG 0x0120 92184610Salfred#define AXE_CMD_SW_PHY_STATUS 0x0021 93184610Salfred#define AXE_CMD_SW_PHY_SELECT 0x0122 94184610Salfred 95184610Salfred#define AXE_SW_RESET_CLEAR 0x00 96184610Salfred#define AXE_SW_RESET_RR 0x01 97184610Salfred#define AXE_SW_RESET_RT 0x02 98184610Salfred#define AXE_SW_RESET_PRTE 0x04 99184610Salfred#define AXE_SW_RESET_PRL 0x08 100184610Salfred#define AXE_SW_RESET_BZ 0x10 101184610Salfred#define AXE_SW_RESET_IPRL 0x20 102184610Salfred#define AXE_SW_RESET_IPPD 0x40 103184610Salfred 104184610Salfred/* AX88178 documentation says to always write this bit... */ 105184610Salfred#define AXE_178_RESET_MAGIC 0x40 106184610Salfred 107184610Salfred#define AXE_178_MEDIA_GMII 0x0001 108184610Salfred#define AXE_MEDIA_FULL_DUPLEX 0x0002 109184610Salfred#define AXE_172_MEDIA_TX_ABORT_ALLOW 0x0004 110184610Salfred 111184610Salfred/* AX88178/88772 documentation says to always write 1 to bit 2 */ 112184610Salfred#define AXE_178_MEDIA_MAGIC 0x0004 113184610Salfred/* AX88772 documentation says to always write 0 to bit 3 */ 114184610Salfred#define AXE_178_MEDIA_ENCK 0x0008 115184610Salfred#define AXE_172_MEDIA_FLOW_CONTROL_EN 0x0010 116184610Salfred#define AXE_178_MEDIA_RXFLOW_CONTROL_EN 0x0010 117184610Salfred#define AXE_178_MEDIA_TXFLOW_CONTROL_EN 0x0020 118184610Salfred#define AXE_178_MEDIA_JUMBO_EN 0x0040 119184610Salfred#define AXE_178_MEDIA_LTPF_ONLY 0x0080 120184610Salfred#define AXE_178_MEDIA_RX_EN 0x0100 121184610Salfred#define AXE_178_MEDIA_100TX 0x0200 122184610Salfred#define AXE_178_MEDIA_SBP 0x0800 123184610Salfred#define AXE_178_MEDIA_SUPERMAC 0x1000 124184610Salfred 125184610Salfred#define AXE_RXCMD_PROMISC 0x0001 126184610Salfred#define AXE_RXCMD_ALLMULTI 0x0002 127184610Salfred#define AXE_172_RXCMD_UNICAST 0x0004 128184610Salfred#define AXE_178_RXCMD_KEEP_INVALID_CRC 0x0004 129184610Salfred#define AXE_RXCMD_BROADCAST 0x0008 130184610Salfred#define AXE_RXCMD_MULTICAST 0x0010 131184610Salfred#define AXE_RXCMD_ENABLE 0x0080 132184610Salfred#define AXE_178_RXCMD_MFB_MASK 0x0300 133184610Salfred#define AXE_178_RXCMD_MFB_2048 0x0000 134184610Salfred#define AXE_178_RXCMD_MFB_4096 0x0100 135184610Salfred#define AXE_178_RXCMD_MFB_8192 0x0200 136184610Salfred#define AXE_178_RXCMD_MFB_16384 0x0300 137184610Salfred 138186730Salfred#define AXE_PHY_SEL_PRI 1 139186730Salfred#define AXE_PHY_SEL_SEC 0 140186730Salfred#define AXE_PHY_TYPE_MASK 0xE0 141186730Salfred#define AXE_PHY_TYPE_SHIFT 5 142186730Salfred#define AXE_PHY_TYPE(x) \ 143186730Salfred (((x) & AXE_PHY_TYPE_MASK) >> AXE_PHY_TYPE_SHIFT) 144184610Salfred 145186730Salfred#define PHY_TYPE_100_HOME 0 /* 10/100 or 1M HOME PHY */ 146186730Salfred#define PHY_TYPE_GIG 1 /* Gigabit PHY */ 147186730Salfred#define PHY_TYPE_SPECIAL 4 /* Special case */ 148186730Salfred#define PHY_TYPE_RSVD 5 /* Reserved */ 149186730Salfred#define PHY_TYPE_NON_SUP 7 /* Non-supported PHY */ 150186730Salfred 151186730Salfred#define AXE_PHY_NO_MASK 0x1F 152186730Salfred#define AXE_PHY_NO(x) ((x) & AXE_PHY_NO_MASK) 153186730Salfred 154186730Salfred#define AXE_772_PHY_NO_EPHY 0x10 /* Embedded 10/100 PHY of AX88772 */ 155186730Salfred 156212130Sthompsa#define AXE_GPIO0_EN 0x01 157212130Sthompsa#define AXE_GPIO0 0x02 158212130Sthompsa#define AXE_GPIO1_EN 0x04 159212130Sthompsa#define AXE_GPIO1 0x08 160212130Sthompsa#define AXE_GPIO2_EN 0x10 161212130Sthompsa#define AXE_GPIO2 0x20 162212130Sthompsa#define AXE_GPIO_RELOAD_EEPROM 0x80 163212130Sthompsa 164212130Sthompsa#define AXE_PHY_MODE_MARVELL 0x00 165212130Sthompsa#define AXE_PHY_MODE_CICADA 0x01 166212130Sthompsa#define AXE_PHY_MODE_AGERE 0x02 167212130Sthompsa#define AXE_PHY_MODE_CICADA_V2 0x05 168212130Sthompsa#define AXE_PHY_MODE_AGERE_GMII 0x06 169212130Sthompsa#define AXE_PHY_MODE_CICADA_V2_ASIX 0x09 170212130Sthompsa#define AXE_PHY_MODE_REALTEK_8211CL 0x0C 171212130Sthompsa#define AXE_PHY_MODE_REALTEK_8211BN 0x0D 172212130Sthompsa#define AXE_PHY_MODE_REALTEK_8251CL 0x0E 173212130Sthompsa#define AXE_PHY_MODE_ATTANSIC 0x40 174212130Sthompsa 175184610Salfred#define AXE_BULK_BUF_SIZE 16384 /* bytes */ 176184610Salfred 177184610Salfred#define AXE_CTL_READ 0x01 178184610Salfred#define AXE_CTL_WRITE 0x02 179184610Salfred 180184610Salfred#define AXE_CONFIG_IDX 0 /* config number 1 */ 181184610Salfred#define AXE_IFACE_IDX 0 182184610Salfred 183184610Salfredstruct axe_sframe_hdr { 184184610Salfred uint16_t len; 185184610Salfred uint16_t ilen; 186184610Salfred} __packed; 187184610Salfred 188194228Sthompsa#define GET_MII(sc) uether_getmii(&(sc)->sc_ue) 189184610Salfred 190187259Sthompsa/* The interrupt endpoint is currently unused by the ASIX part. */ 191187259Sthompsaenum { 192187259Sthompsa AXE_BULK_DT_WR, 193187259Sthompsa AXE_BULK_DT_RD, 194187259Sthompsa AXE_INTR_DT_RD, 195188412Sthompsa AXE_N_TRANSFER, 196187259Sthompsa}; 197187259Sthompsa 198184610Salfredstruct axe_softc { 199192984Sthompsa struct usb_ether sc_ue; 200188412Sthompsa struct mtx sc_mtx; 201192984Sthompsa struct usb_xfer *sc_xfer[AXE_N_TRANSFER]; 202188412Sthompsa int sc_phyno; 203184610Salfred 204188412Sthompsa int sc_flags; 205186730Salfred#define AXE_FLAG_LINK 0x0001 206188412Sthompsa#define AXE_FLAG_772 0x1000 /* AX88772 */ 207188412Sthompsa#define AXE_FLAG_178 0x2000 /* AX88178 */ 208184610Salfred 209188412Sthompsa uint8_t sc_ipgs[3]; 210188412Sthompsa uint8_t sc_phyaddrs[2]; 211188412Sthompsa}; 212184610Salfred 213188412Sthompsa#define AXE_LOCK(_sc) mtx_lock(&(_sc)->sc_mtx) 214188412Sthompsa#define AXE_UNLOCK(_sc) mtx_unlock(&(_sc)->sc_mtx) 215188412Sthompsa#define AXE_LOCK_ASSERT(_sc, t) mtx_assert(&(_sc)->sc_mtx, t) 216