1184610Salfred/*- 2184610Salfred * Copyright (c) 1997, 1998, 1999, 2000-2003 3184610Salfred * Bill Paul <wpaul@windriver.com>. All rights reserved. 4184610Salfred * 5184610Salfred * Redistribution and use in source and binary forms, with or without 6184610Salfred * modification, are permitted provided that the following conditions 7184610Salfred * are met: 8184610Salfred * 1. Redistributions of source code must retain the above copyright 9184610Salfred * notice, this list of conditions and the following disclaimer. 10184610Salfred * 2. Redistributions in binary form must reproduce the above copyright 11184610Salfred * notice, this list of conditions and the following disclaimer in the 12184610Salfred * documentation and/or other materials provided with the distribution. 13184610Salfred * 3. All advertising materials mentioning features or use of this software 14184610Salfred * must display the following acknowledgement: 15184610Salfred * This product includes software developed by Bill Paul. 16184610Salfred * 4. Neither the name of the author nor the names of any co-contributors 17184610Salfred * may be used to endorse or promote products derived from this software 18184610Salfred * without specific prior written permission. 19184610Salfred * 20184610Salfred * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 21184610Salfred * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22184610Salfred * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23184610Salfred * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 24184610Salfred * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25184610Salfred * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26184610Salfred * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27184610Salfred * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28184610Salfred * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29184610Salfred * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 30184610Salfred * THE POSSIBILITY OF SUCH DAMAGE. 31184610Salfred * 32184610Salfred * $FreeBSD$ 33184610Salfred */ 34184610Salfred 35184610Salfred/* 36184610Salfred * Definitions for the ASIX Electronics AX88172, AX88178 37184610Salfred * and AX88772 to ethernet controllers. 38184610Salfred */ 39184610Salfred 40184610Salfred/* 41184610Salfred * Vendor specific commands. ASIX conveniently doesn't document the 'set 42184610Salfred * NODEID' command in their datasheet (thanks a lot guys). 43184610Salfred * To make handling these commands easier, I added some extra data which is 44184610Salfred * decided by the axe_cmd() routine. Commands are encoded in 16 bits, with 45184610Salfred * the format: LDCC. L and D are both nibbles in the high byte. L represents 46184610Salfred * the data length (0 to 15) and D represents the direction (0 for vendor read, 47184610Salfred * 1 for vendor write). CC is the command byte, as specified in the manual. 48184610Salfred */ 49184610Salfred 50184610Salfred#define AXE_CMD_IS_WRITE(x) (((x) & 0x0F00) >> 8) 51184610Salfred#define AXE_CMD_LEN(x) (((x) & 0xF000) >> 12) 52184610Salfred#define AXE_CMD_CMD(x) ((x) & 0x00FF) 53184610Salfred 54184610Salfred#define AXE_172_CMD_READ_RXTX_SRAM 0x2002 55184610Salfred#define AXE_182_CMD_READ_RXTX_SRAM 0x8002 56184610Salfred#define AXE_172_CMD_WRITE_RX_SRAM 0x0103 57184610Salfred#define AXE_182_CMD_WRITE_RXTX_SRAM 0x8103 58184610Salfred#define AXE_172_CMD_WRITE_TX_SRAM 0x0104 59184610Salfred#define AXE_CMD_MII_OPMODE_SW 0x0106 60184610Salfred#define AXE_CMD_MII_READ_REG 0x2007 61184610Salfred#define AXE_CMD_MII_WRITE_REG 0x2108 62184610Salfred#define AXE_CMD_MII_READ_OPMODE 0x1009 63184610Salfred#define AXE_CMD_MII_OPMODE_HW 0x010A 64184610Salfred#define AXE_CMD_SROM_READ 0x200B 65184610Salfred#define AXE_CMD_SROM_WRITE 0x010C 66184610Salfred#define AXE_CMD_SROM_WR_ENABLE 0x010D 67184610Salfred#define AXE_CMD_SROM_WR_DISABLE 0x010E 68184610Salfred#define AXE_CMD_RXCTL_READ 0x200F 69184610Salfred#define AXE_CMD_RXCTL_WRITE 0x0110 70184610Salfred#define AXE_CMD_READ_IPG012 0x3011 71184610Salfred#define AXE_172_CMD_WRITE_IPG0 0x0112 72184610Salfred#define AXE_178_CMD_WRITE_IPG012 0x0112 73184610Salfred#define AXE_172_CMD_WRITE_IPG1 0x0113 74184610Salfred#define AXE_178_CMD_READ_NODEID 0x6013 75184610Salfred#define AXE_172_CMD_WRITE_IPG2 0x0114 76184610Salfred#define AXE_178_CMD_WRITE_NODEID 0x6114 77184610Salfred#define AXE_CMD_READ_MCAST 0x8015 78184610Salfred#define AXE_CMD_WRITE_MCAST 0x8116 79184610Salfred#define AXE_172_CMD_READ_NODEID 0x6017 80184610Salfred#define AXE_172_CMD_WRITE_NODEID 0x6118 81184610Salfred 82184610Salfred#define AXE_CMD_READ_PHYID 0x2019 83184610Salfred#define AXE_172_CMD_READ_MEDIA 0x101A 84184610Salfred#define AXE_178_CMD_READ_MEDIA 0x201A 85184610Salfred#define AXE_CMD_WRITE_MEDIA 0x011B 86184610Salfred#define AXE_CMD_READ_MONITOR_MODE 0x101C 87184610Salfred#define AXE_CMD_WRITE_MONITOR_MODE 0x011D 88184610Salfred#define AXE_CMD_READ_GPIO 0x101E 89184610Salfred#define AXE_CMD_WRITE_GPIO 0x011F 90184610Salfred 91184610Salfred#define AXE_CMD_SW_RESET_REG 0x0120 92184610Salfred#define AXE_CMD_SW_PHY_STATUS 0x0021 93184610Salfred#define AXE_CMD_SW_PHY_SELECT 0x0122 94184610Salfred 95215969Syongari/* AX88772A and AX88772B only. */ 96215969Syongari#define AXE_CMD_READ_VLAN_CTRL 0x4027 97215969Syongari#define AXE_CMD_WRITE_VLAN_CTRL 0x4028 98215969Syongari 99224020Syongari#define AXE_772B_CMD_RXCTL_WRITE_CFG 0x012A 100226743Syongari#define AXE_772B_CMD_READ_RXCSUM 0x002B 101226743Syongari#define AXE_772B_CMD_WRITE_RXCSUM 0x012C 102226743Syongari#define AXE_772B_CMD_READ_TXCSUM 0x002D 103226743Syongari#define AXE_772B_CMD_WRITE_TXCSUM 0x012E 104224020Syongari 105184610Salfred#define AXE_SW_RESET_CLEAR 0x00 106184610Salfred#define AXE_SW_RESET_RR 0x01 107184610Salfred#define AXE_SW_RESET_RT 0x02 108184610Salfred#define AXE_SW_RESET_PRTE 0x04 109184610Salfred#define AXE_SW_RESET_PRL 0x08 110184610Salfred#define AXE_SW_RESET_BZ 0x10 111184610Salfred#define AXE_SW_RESET_IPRL 0x20 112184610Salfred#define AXE_SW_RESET_IPPD 0x40 113184610Salfred 114184610Salfred/* AX88178 documentation says to always write this bit... */ 115184610Salfred#define AXE_178_RESET_MAGIC 0x40 116184610Salfred 117184610Salfred#define AXE_178_MEDIA_GMII 0x0001 118184610Salfred#define AXE_MEDIA_FULL_DUPLEX 0x0002 119184610Salfred#define AXE_172_MEDIA_TX_ABORT_ALLOW 0x0004 120184610Salfred 121184610Salfred/* AX88178/88772 documentation says to always write 1 to bit 2 */ 122184610Salfred#define AXE_178_MEDIA_MAGIC 0x0004 123184610Salfred/* AX88772 documentation says to always write 0 to bit 3 */ 124184610Salfred#define AXE_178_MEDIA_ENCK 0x0008 125184610Salfred#define AXE_172_MEDIA_FLOW_CONTROL_EN 0x0010 126184610Salfred#define AXE_178_MEDIA_RXFLOW_CONTROL_EN 0x0010 127184610Salfred#define AXE_178_MEDIA_TXFLOW_CONTROL_EN 0x0020 128184610Salfred#define AXE_178_MEDIA_JUMBO_EN 0x0040 129184610Salfred#define AXE_178_MEDIA_LTPF_ONLY 0x0080 130184610Salfred#define AXE_178_MEDIA_RX_EN 0x0100 131184610Salfred#define AXE_178_MEDIA_100TX 0x0200 132184610Salfred#define AXE_178_MEDIA_SBP 0x0800 133184610Salfred#define AXE_178_MEDIA_SUPERMAC 0x1000 134184610Salfred 135184610Salfred#define AXE_RXCMD_PROMISC 0x0001 136184610Salfred#define AXE_RXCMD_ALLMULTI 0x0002 137184610Salfred#define AXE_172_RXCMD_UNICAST 0x0004 138184610Salfred#define AXE_178_RXCMD_KEEP_INVALID_CRC 0x0004 139184610Salfred#define AXE_RXCMD_BROADCAST 0x0008 140184610Salfred#define AXE_RXCMD_MULTICAST 0x0010 141224020Syongari#define AXE_RXCMD_ACCEPT_RUNT 0x0040 /* AX88772B */ 142184610Salfred#define AXE_RXCMD_ENABLE 0x0080 143184610Salfred#define AXE_178_RXCMD_MFB_MASK 0x0300 144184610Salfred#define AXE_178_RXCMD_MFB_2048 0x0000 145184610Salfred#define AXE_178_RXCMD_MFB_4096 0x0100 146184610Salfred#define AXE_178_RXCMD_MFB_8192 0x0200 147184610Salfred#define AXE_178_RXCMD_MFB_16384 0x0300 148224020Syongari#define AXE_772B_RXCMD_HDR_TYPE_0 0x0000 149224020Syongari#define AXE_772B_RXCMD_HDR_TYPE_1 0x0100 150224020Syongari#define AXE_772B_RXCMD_IPHDR_ALIGN 0x0200 151224020Syongari#define AXE_772B_RXCMD_ADD_CHKSUM 0x0400 152224020Syongari#define AXE_RXCMD_LOOPBACK 0x1000 /* AX88772A/AX88772B */ 153184610Salfred 154186730Salfred#define AXE_PHY_SEL_PRI 1 155186730Salfred#define AXE_PHY_SEL_SEC 0 156186730Salfred#define AXE_PHY_TYPE_MASK 0xE0 157186730Salfred#define AXE_PHY_TYPE_SHIFT 5 158186730Salfred#define AXE_PHY_TYPE(x) \ 159186730Salfred (((x) & AXE_PHY_TYPE_MASK) >> AXE_PHY_TYPE_SHIFT) 160184610Salfred 161186730Salfred#define PHY_TYPE_100_HOME 0 /* 10/100 or 1M HOME PHY */ 162186730Salfred#define PHY_TYPE_GIG 1 /* Gigabit PHY */ 163186730Salfred#define PHY_TYPE_SPECIAL 4 /* Special case */ 164186730Salfred#define PHY_TYPE_RSVD 5 /* Reserved */ 165186730Salfred#define PHY_TYPE_NON_SUP 7 /* Non-supported PHY */ 166186730Salfred 167186730Salfred#define AXE_PHY_NO_MASK 0x1F 168186730Salfred#define AXE_PHY_NO(x) ((x) & AXE_PHY_NO_MASK) 169186730Salfred 170186730Salfred#define AXE_772_PHY_NO_EPHY 0x10 /* Embedded 10/100 PHY of AX88772 */ 171186730Salfred 172212130Sthompsa#define AXE_GPIO0_EN 0x01 173212130Sthompsa#define AXE_GPIO0 0x02 174212130Sthompsa#define AXE_GPIO1_EN 0x04 175212130Sthompsa#define AXE_GPIO1 0x08 176212130Sthompsa#define AXE_GPIO2_EN 0x10 177212130Sthompsa#define AXE_GPIO2 0x20 178212130Sthompsa#define AXE_GPIO_RELOAD_EEPROM 0x80 179212130Sthompsa 180212130Sthompsa#define AXE_PHY_MODE_MARVELL 0x00 181212130Sthompsa#define AXE_PHY_MODE_CICADA 0x01 182212130Sthompsa#define AXE_PHY_MODE_AGERE 0x02 183212130Sthompsa#define AXE_PHY_MODE_CICADA_V2 0x05 184212130Sthompsa#define AXE_PHY_MODE_AGERE_GMII 0x06 185212130Sthompsa#define AXE_PHY_MODE_CICADA_V2_ASIX 0x09 186212130Sthompsa#define AXE_PHY_MODE_REALTEK_8211CL 0x0C 187212130Sthompsa#define AXE_PHY_MODE_REALTEK_8211BN 0x0D 188212130Sthompsa#define AXE_PHY_MODE_REALTEK_8251CL 0x0E 189212130Sthompsa#define AXE_PHY_MODE_ATTANSIC 0x40 190212130Sthompsa 191224020Syongari/* AX88772A/AX88772B only. */ 192215969Syongari#define AXE_SW_PHY_SELECT_EXT 0x0000 193215969Syongari#define AXE_SW_PHY_SELECT_EMBEDDED 0x0001 194215969Syongari#define AXE_SW_PHY_SELECT_AUTO 0x0002 195215969Syongari#define AXE_SW_PHY_SELECT_SS_MII 0x0004 196215969Syongari#define AXE_SW_PHY_SELECT_SS_RVRS_MII 0x0008 197215969Syongari#define AXE_SW_PHY_SELECT_SS_RVRS_RMII 0x000C 198215969Syongari#define AXE_SW_PHY_SELECT_SS_ENB 0x0010 199215969Syongari 200215969Syongari/* AX88772A/AX88772B VLAN control. */ 201215969Syongari#define AXE_VLAN_CTRL_ENB 0x00001000 202215969Syongari#define AXE_VLAN_CTRL_STRIP 0x00002000 203215969Syongari#define AXE_VLAN_CTRL_VID1_MASK 0x00000FFF 204215969Syongari#define AXE_VLAN_CTRL_VID2_MASK 0x0FFF0000 205215969Syongari 206226743Syongari#define AXE_RXCSUM_IP 0x0001 207226743Syongari#define AXE_RXCSUM_IPVE 0x0002 208226743Syongari#define AXE_RXCSUM_IPV6E 0x0004 209226743Syongari#define AXE_RXCSUM_TCP 0x0008 210226743Syongari#define AXE_RXCSUM_UDP 0x0010 211226743Syongari#define AXE_RXCSUM_ICMP 0x0020 212226743Syongari#define AXE_RXCSUM_IGMP 0x0040 213226743Syongari#define AXE_RXCSUM_ICMP6 0x0080 214226743Syongari#define AXE_RXCSUM_TCPV6 0x0100 215226743Syongari#define AXE_RXCSUM_UDPV6 0x0200 216226743Syongari#define AXE_RXCSUM_ICMPV6 0x0400 217226743Syongari#define AXE_RXCSUM_IGMPV6 0x0800 218226743Syongari#define AXE_RXCSUM_ICMP6V6 0x1000 219226743Syongari#define AXE_RXCSUM_FOPC 0x8000 220226743Syongari 221226743Syongari#define AXE_RXCSUM_64TE 0x0100 222226743Syongari#define AXE_RXCSUM_PPPOE 0x0200 223226743Syongari#define AXE_RXCSUM_RPCE 0x8000 224226743Syongari 225226743Syongari#define AXE_TXCSUM_IP 0x0001 226226743Syongari#define AXE_TXCSUM_TCP 0x0002 227226743Syongari#define AXE_TXCSUM_UDP 0x0004 228226743Syongari#define AXE_TXCSUM_ICMP 0x0008 229226743Syongari#define AXE_TXCSUM_IGMP 0x0010 230226743Syongari#define AXE_TXCSUM_ICMP6 0x0020 231226743Syongari#define AXE_TXCSUM_TCPV6 0x0100 232226743Syongari#define AXE_TXCSUM_UDPV6 0x0200 233226743Syongari#define AXE_TXCSUM_ICMPV6 0x0400 234226743Syongari#define AXE_TXCSUM_IGMPV6 0x0800 235226743Syongari#define AXE_TXCSUM_ICMP6V6 0x1000 236226743Syongari 237226743Syongari#define AXE_TXCSUM_64TE 0x0001 238226743Syongari#define AXE_TXCSUM_PPPOE 0x0002 239226743Syongari 240184610Salfred#define AXE_BULK_BUF_SIZE 16384 /* bytes */ 241184610Salfred 242184610Salfred#define AXE_CTL_READ 0x01 243184610Salfred#define AXE_CTL_WRITE 0x02 244184610Salfred 245184610Salfred#define AXE_CONFIG_IDX 0 /* config number 1 */ 246184610Salfred#define AXE_IFACE_IDX 0 247184610Salfred 248224020Syongari/* EEPROM Map. */ 249224020Syongari#define AXE_EEPROM_772B_NODE_ID 0x04 250224020Syongari#define AXE_EEPROM_772B_PHY_PWRCFG 0x18 251224020Syongari 252224020Syongaristruct ax88772b_mfb { 253224020Syongari int byte_cnt; 254224020Syongari int threshold; 255224020Syongari int size; 256224020Syongari}; 257224020Syongari#define AX88772B_MFB_2K 0 258224020Syongari#define AX88772B_MFB_4K 1 259224020Syongari#define AX88772B_MFB_6K 2 260224020Syongari#define AX88772B_MFB_8K 3 261224020Syongari#define AX88772B_MFB_16K 4 262224020Syongari#define AX88772B_MFB_20K 5 263224020Syongari#define AX88772B_MFB_24K 6 264224020Syongari#define AX88772B_MFB_32K 7 265224020Syongari 266184610Salfredstruct axe_sframe_hdr { 267184610Salfred uint16_t len; 268226743Syongari#define AXE_HDR_LEN_MASK 0xFFFF 269184610Salfred uint16_t ilen; 270184610Salfred} __packed; 271184610Salfred 272226743Syongari#define AXE_TX_CSUM_PSEUDO_HDR 0x4000 273226743Syongari#define AXE_TX_CSUM_DIS 0x8000 274226743Syongari 275226743Syongari/* 276226743Syongari * When RX checksum offloading is enabled, AX88772B uses new RX header 277226743Syongari * format and it's not compatible with previous RX header format. In 278226743Syongari * addition, IP header align option should be enabled to get correct 279226743Syongari * frame size including RX header. Total transferred size including 280226743Syongari * the RX header is multiple of 4 and controller will pad necessary 281226743Syongari * bytes if the length is not multiple of 4. 282226743Syongari * This driver does not enable partial checksum feature which will 283226743Syongari * compute 16bit checksum from 14th byte to the end of the frame. If 284226743Syongari * this feature is enabled, computed checksum value is embedded into 285226743Syongari * RX header which in turn means it uses different RX header format. 286226743Syongari */ 287226743Syongaristruct axe_csum_hdr { 288226743Syongari uint16_t len; 289226743Syongari#define AXE_CSUM_HDR_LEN_MASK 0x07FF 290226743Syongari#define AXE_CSUM_HDR_CRC_ERR 0x1000 291226743Syongari#define AXE_CSUM_HDR_MII_ERR 0x2000 292226743Syongari#define AXE_CSUM_HDR_RUNT 0x4000 293226743Syongari#define AXE_CSUM_HDR_BMCAST 0x8000 294226743Syongari uint16_t ilen; 295226743Syongari uint16_t cstatus; 296226743Syongari#define AXE_CSUM_HDR_VLAN_MASK 0x0007 297226743Syongari#define AXE_CSUM_HDR_VLAN_STRIP 0x0008 298226743Syongari#define AXE_CSUM_HDR_VLAN_PRI_MASK 0x0070 299226743Syongari#define AXE_CSUM_HDR_L4_CSUM_ERR 0x0100 300226743Syongari#define AXE_CSUM_HDR_L3_CSUM_ERR 0x0200 301226743Syongari#define AXE_CSUM_HDR_L4_TYPE_UDP 0x0400 302226743Syongari#define AXE_CSUM_HDR_L4_TYPE_ICMP 0x0800 303226743Syongari#define AXE_CSUM_HDR_L4_TYPE_IGMP 0x0C00 304226743Syongari#define AXE_CSUM_HDR_L4_TYPE_TCP 0x1000 305226743Syongari#define AXE_CSUM_HDR_L4_TYPE_TCPV6 0x1400 306226743Syongari#define AXE_CSUM_HDR_L4_TYPE_MASK 0x1C00 307226743Syongari#define AXE_CSUM_HDR_L3_TYPE_IPV4 0x2000 308226743Syongari#define AXE_CSUM_HDR_L3_TYPE_IPV6 0x4000 309226743Syongari 310226743Syongari#ifdef AXE_APPEND_PARTIAL_CSUM 311226743Syongari /* 312226743Syongari * These members present only when partial checksum 313226743Syongari * offloading is enabled. The checksum value is simple 314226743Syongari * 16bit sum of received frame starting at offset 14 of 315226743Syongari * the frame to the end of the frame excluding FCS bytes. 316226743Syongari */ 317226743Syongari uint16_t csum_value; 318226743Syongari uint16_t dummy; 319226743Syongari#endif 320226743Syongari} __packed; 321226743Syongari 322226743Syongari#define AXE_CSUM_RXBYTES(x) ((x) & AXE_CSUM_HDR_LEN_MASK) 323226743Syongari 324194228Sthompsa#define GET_MII(sc) uether_getmii(&(sc)->sc_ue) 325184610Salfred 326187259Sthompsa/* The interrupt endpoint is currently unused by the ASIX part. */ 327187259Sthompsaenum { 328187259Sthompsa AXE_BULK_DT_WR, 329187259Sthompsa AXE_BULK_DT_RD, 330188412Sthompsa AXE_N_TRANSFER, 331187259Sthompsa}; 332187259Sthompsa 333184610Salfredstruct axe_softc { 334192984Sthompsa struct usb_ether sc_ue; 335188412Sthompsa struct mtx sc_mtx; 336192984Sthompsa struct usb_xfer *sc_xfer[AXE_N_TRANSFER]; 337188412Sthompsa int sc_phyno; 338184610Salfred 339188412Sthompsa int sc_flags; 340186730Salfred#define AXE_FLAG_LINK 0x0001 341226743Syongari#define AXE_FLAG_STD_FRAME 0x0010 342226743Syongari#define AXE_FLAG_CSUM_FRAME 0x0020 343188412Sthompsa#define AXE_FLAG_772 0x1000 /* AX88772 */ 344215968Syongari#define AXE_FLAG_772A 0x2000 /* AX88772A */ 345215968Syongari#define AXE_FLAG_772B 0x4000 /* AX88772B */ 346215968Syongari#define AXE_FLAG_178 0x8000 /* AX88178 */ 347184610Salfred 348188412Sthompsa uint8_t sc_ipgs[3]; 349188412Sthompsa uint8_t sc_phyaddrs[2]; 350224020Syongari uint16_t sc_pwrcfg; 351226743Syongari uint16_t sc_lenmask; 352188412Sthompsa}; 353184610Salfred 354215968Syongari#define AXE_IS_178_FAMILY(sc) \ 355215968Syongari ((sc)->sc_flags & (AXE_FLAG_772 | AXE_FLAG_772A | AXE_FLAG_772B | \ 356215968Syongari AXE_FLAG_178)) 357215968Syongari 358215968Syongari#define AXE_IS_772(sc) \ 359215968Syongari ((sc)->sc_flags & (AXE_FLAG_772 | AXE_FLAG_772A | AXE_FLAG_772B)) 360215968Syongari 361188412Sthompsa#define AXE_LOCK(_sc) mtx_lock(&(_sc)->sc_mtx) 362188412Sthompsa#define AXE_UNLOCK(_sc) mtx_unlock(&(_sc)->sc_mtx) 363188412Sthompsa#define AXE_LOCK_ASSERT(_sc, t) mtx_assert(&(_sc)->sc_mtx, t) 364