xhci_pci.c revision 297852 
1/*-
2 * Copyright (c) 2010 Hans Petter Selasky. All rights reserved.
3 *
4 * Redistribution and use in source and binary forms, with or without
5 * modification, are permitted provided that the following conditions
6 * are met:
7 * 1. Redistributions of source code must retain the above copyright
8 *    notice, this list of conditions and the following disclaimer.
9 * 2. Redistributions in binary form must reproduce the above copyright
10 *    notice, this list of conditions and the following disclaimer in the
11 *    documentation and/or other materials provided with the distribution.
12 *
13 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
14 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
15 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
16 * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
17 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
18 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
19 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
20 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
21 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
22 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
23 * SUCH DAMAGE.
24 */
25
26#include <sys/cdefs.h>
27__FBSDID("$FreeBSD: stable/10/sys/dev/usb/controller/xhci_pci.c 297852 2016-04-12 07:54:55Z mav $");
28
29#include <sys/stdint.h>
30#include <sys/stddef.h>
31#include <sys/param.h>
32#include <sys/queue.h>
33#include <sys/types.h>
34#include <sys/systm.h>
35#include <sys/kernel.h>
36#include <sys/bus.h>
37#include <sys/module.h>
38#include <sys/lock.h>
39#include <sys/mutex.h>
40#include <sys/condvar.h>
41#include <sys/sysctl.h>
42#include <sys/sx.h>
43#include <sys/unistd.h>
44#include <sys/callout.h>
45#include <sys/malloc.h>
46#include <sys/priv.h>
47
48#include <dev/usb/usb.h>
49#include <dev/usb/usbdi.h>
50
51#include <dev/usb/usb_core.h>
52#include <dev/usb/usb_busdma.h>
53#include <dev/usb/usb_process.h>
54#include <dev/usb/usb_util.h>
55
56#include <dev/usb/usb_controller.h>
57#include <dev/usb/usb_bus.h>
58#include <dev/usb/usb_pci.h>
59#include <dev/usb/controller/xhci.h>
60#include <dev/usb/controller/xhcireg.h>
61#include "usb_if.h"
62
63static device_probe_t xhci_pci_probe;
64static device_attach_t xhci_pci_attach;
65static device_detach_t xhci_pci_detach;
66static usb_take_controller_t xhci_pci_take_controller;
67
68static device_method_t xhci_device_methods[] = {
69	/* device interface */
70	DEVMETHOD(device_probe, xhci_pci_probe),
71	DEVMETHOD(device_attach, xhci_pci_attach),
72	DEVMETHOD(device_detach, xhci_pci_detach),
73	DEVMETHOD(device_suspend, bus_generic_suspend),
74	DEVMETHOD(device_resume, bus_generic_resume),
75	DEVMETHOD(device_shutdown, bus_generic_shutdown),
76	DEVMETHOD(usb_take_controller, xhci_pci_take_controller),
77
78	DEVMETHOD_END
79};
80
81static driver_t xhci_driver = {
82	.name = "xhci",
83	.methods = xhci_device_methods,
84	.size = sizeof(struct xhci_softc),
85};
86
87static devclass_t xhci_devclass;
88
89DRIVER_MODULE(xhci, pci, xhci_driver, xhci_devclass, NULL, NULL);
90MODULE_DEPEND(xhci, usb, 1, 1, 1);
91
92static const char *
93xhci_pci_match(device_t self)
94{
95	uint32_t device_id = pci_get_devid(self);
96
97	switch (device_id) {
98	case 0x78141022:
99		return ("AMD FCH USB 3.0 controller");
100
101	case 0x01941033:
102		return ("NEC uPD720200 USB 3.0 controller");
103
104	case 0x10001b73:
105		return ("Fresco Logic FL1000G USB 3.0 controller");
106
107	case 0x10421b21:
108		return ("ASMedia ASM1042 USB 3.0 controller");
109	case 0x11421b21:
110		return ("ASMedia ASM1042A USB 3.0 controller");
111
112	case 0x0f358086:
113		return ("Intel BayTrail USB 3.0 controller");
114	case 0x9c318086:
115	case 0x1e318086:
116		return ("Intel Panther Point USB 3.0 controller");
117	case 0x8c318086:
118		return ("Intel Lynx Point USB 3.0 controller");
119	case 0x8cb18086:
120		return ("Intel Wildcat Point USB 3.0 controller");
121	case 0x8d318086:
122		return ("Intel Wellsburg USB 3.0 controller");
123	case 0x9cb18086:
124		return ("Broadwell Integrated PCH-LP chipset USB 3.0 controller");
125
126	case 0xa01b177d:
127		return ("Cavium ThunderX USB 3.0 controller");
128
129	default:
130		break;
131	}
132
133	if ((pci_get_class(self) == PCIC_SERIALBUS)
134	    && (pci_get_subclass(self) == PCIS_SERIALBUS_USB)
135	    && (pci_get_progif(self) == PCIP_SERIALBUS_USB_XHCI)) {
136		return ("XHCI (generic) USB 3.0 controller");
137	}
138	return (NULL);			/* dunno */
139}
140
141static int
142xhci_pci_probe(device_t self)
143{
144	const char *desc = xhci_pci_match(self);
145
146	if (desc) {
147		device_set_desc(self, desc);
148		return (0);
149	} else {
150		return (ENXIO);
151	}
152}
153
154static int xhci_use_msi = 1;
155TUNABLE_INT("hw.usb.xhci.msi", &xhci_use_msi);
156
157static void
158xhci_interrupt_poll(void *_sc)
159{
160	struct xhci_softc *sc = _sc;
161	USB_BUS_UNLOCK(&sc->sc_bus);
162	xhci_interrupt(sc);
163	USB_BUS_LOCK(&sc->sc_bus);
164	usb_callout_reset(&sc->sc_callout, 1, (void *)&xhci_interrupt_poll, sc);
165}
166
167static int
168xhci_pci_port_route(device_t self, uint32_t set, uint32_t clear)
169{
170	uint32_t temp;
171	uint32_t usb3_mask;
172	uint32_t usb2_mask;
173
174	temp = pci_read_config(self, PCI_XHCI_INTEL_USB3_PSSEN, 4) |
175	    pci_read_config(self, PCI_XHCI_INTEL_XUSB2PR, 4);
176
177	temp |= set;
178	temp &= ~clear;
179
180	/* Don't set bits which the hardware doesn't support */
181	usb3_mask = pci_read_config(self, PCI_XHCI_INTEL_USB3PRM, 4);
182	usb2_mask = pci_read_config(self, PCI_XHCI_INTEL_USB2PRM, 4);
183
184	pci_write_config(self, PCI_XHCI_INTEL_USB3_PSSEN, temp & usb3_mask, 4);
185	pci_write_config(self, PCI_XHCI_INTEL_XUSB2PR, temp & usb2_mask, 4);
186
187	device_printf(self, "Port routing mask set to 0x%08x\n", temp);
188
189	return (0);
190}
191
192static int
193xhci_pci_attach(device_t self)
194{
195	struct xhci_softc *sc = device_get_softc(self);
196	int count, err, rid;
197	uint8_t usemsi = 1;
198	uint8_t usedma32 = 0;
199
200	rid = PCI_XHCI_CBMEM;
201	sc->sc_io_res = bus_alloc_resource_any(self, SYS_RES_MEMORY, &rid,
202	    RF_ACTIVE);
203	if (!sc->sc_io_res) {
204		device_printf(self, "Could not map memory\n");
205		return (ENOMEM);
206	}
207	sc->sc_io_tag = rman_get_bustag(sc->sc_io_res);
208	sc->sc_io_hdl = rman_get_bushandle(sc->sc_io_res);
209	sc->sc_io_size = rman_get_size(sc->sc_io_res);
210
211	switch (pci_get_devid(self)) {
212	case 0x01941033:	/* NEC uPD720200 USB 3.0 controller */
213	case 0x00141912:	/* NEC uPD720201 USB 3.0 controller */
214		/* Don't use 64-bit DMA on these controllers. */
215		usedma32 = 1;
216		break;
217	case 0x10001b73:	/* FL1000G */
218		/* Fresco Logic host doesn't support MSI. */
219		usemsi = 0;
220		break;
221	case 0x0f358086:	/* BayTrail */
222	case 0x9c318086:	/* Panther Point */
223	case 0x1e318086:	/* Panther Point */
224	case 0x8c318086:	/* Lynx Point */
225	case 0x8cb18086:	/* Wildcat Point */
226	case 0x9cb18086:	/* Broadwell Mobile Integrated */
227		/*
228		 * On Intel chipsets, reroute ports from EHCI to XHCI
229		 * controller and use a different IMOD value.
230		 */
231		sc->sc_port_route = &xhci_pci_port_route;
232		sc->sc_imod_default = XHCI_IMOD_DEFAULT_LP;
233		break;
234	}
235
236	if (xhci_init(sc, self, usedma32)) {
237		device_printf(self, "Could not initialize softc\n");
238		bus_release_resource(self, SYS_RES_MEMORY, PCI_XHCI_CBMEM,
239		    sc->sc_io_res);
240		return (ENXIO);
241	}
242
243	pci_enable_busmaster(self);
244
245	usb_callout_init_mtx(&sc->sc_callout, &sc->sc_bus.bus_mtx, 0);
246
247	rid = 0;
248	if (xhci_use_msi && usemsi) {
249		count = 1;
250		if (pci_alloc_msi(self, &count) == 0) {
251			if (bootverbose)
252				device_printf(self, "MSI enabled\n");
253			rid = 1;
254		}
255	}
256	sc->sc_irq_res = bus_alloc_resource_any(self, SYS_RES_IRQ, &rid,
257	    RF_ACTIVE | (rid != 0 ? 0 : RF_SHAREABLE));
258	if (sc->sc_irq_res == NULL) {
259		pci_release_msi(self);
260		device_printf(self, "Could not allocate IRQ\n");
261		/* goto error; FALLTHROUGH - use polling */
262	}
263	sc->sc_bus.bdev = device_add_child(self, "usbus", -1);
264	if (sc->sc_bus.bdev == NULL) {
265		device_printf(self, "Could not add USB device\n");
266		goto error;
267	}
268	device_set_ivars(sc->sc_bus.bdev, &sc->sc_bus);
269
270	sprintf(sc->sc_vendor, "0x%04x", pci_get_vendor(self));
271
272	if (sc->sc_irq_res != NULL) {
273		err = bus_setup_intr(self, sc->sc_irq_res, INTR_TYPE_BIO | INTR_MPSAFE,
274		    NULL, (driver_intr_t *)xhci_interrupt, sc, &sc->sc_intr_hdl);
275		if (err != 0) {
276			bus_release_resource(self, SYS_RES_IRQ,
277			    rman_get_rid(sc->sc_irq_res), sc->sc_irq_res);
278			sc->sc_irq_res = NULL;
279			pci_release_msi(self);
280			device_printf(self, "Could not setup IRQ, err=%d\n", err);
281			sc->sc_intr_hdl = NULL;
282		}
283	}
284	if (sc->sc_irq_res == NULL || sc->sc_intr_hdl == NULL) {
285		if (xhci_use_polling() != 0) {
286			device_printf(self, "Interrupt polling at %dHz\n", hz);
287			USB_BUS_LOCK(&sc->sc_bus);
288			xhci_interrupt_poll(sc);
289			USB_BUS_UNLOCK(&sc->sc_bus);
290		} else
291			goto error;
292	}
293
294	xhci_pci_take_controller(self);
295
296	err = xhci_halt_controller(sc);
297
298	if (err == 0)
299		err = xhci_start_controller(sc);
300
301	if (err == 0)
302		err = device_probe_and_attach(sc->sc_bus.bdev);
303
304	if (err) {
305		device_printf(self, "XHCI halt/start/probe failed err=%d\n", err);
306		goto error;
307	}
308	return (0);
309
310error:
311	xhci_pci_detach(self);
312	return (ENXIO);
313}
314
315static int
316xhci_pci_detach(device_t self)
317{
318	struct xhci_softc *sc = device_get_softc(self);
319	device_t bdev;
320
321	if (sc->sc_bus.bdev != NULL) {
322		bdev = sc->sc_bus.bdev;
323		device_detach(bdev);
324		device_delete_child(self, bdev);
325	}
326	/* during module unload there are lots of children leftover */
327	device_delete_children(self);
328
329	usb_callout_drain(&sc->sc_callout);
330	xhci_halt_controller(sc);
331
332	pci_disable_busmaster(self);
333
334	if (sc->sc_irq_res && sc->sc_intr_hdl) {
335		bus_teardown_intr(self, sc->sc_irq_res, sc->sc_intr_hdl);
336		sc->sc_intr_hdl = NULL;
337	}
338	if (sc->sc_irq_res) {
339		bus_release_resource(self, SYS_RES_IRQ,
340		    rman_get_rid(sc->sc_irq_res), sc->sc_irq_res);
341		sc->sc_irq_res = NULL;
342		pci_release_msi(self);
343	}
344	if (sc->sc_io_res) {
345		bus_release_resource(self, SYS_RES_MEMORY, PCI_XHCI_CBMEM,
346		    sc->sc_io_res);
347		sc->sc_io_res = NULL;
348	}
349
350	xhci_uninit(sc);
351
352	return (0);
353}
354
355static int
356xhci_pci_take_controller(device_t self)
357{
358	struct xhci_softc *sc = device_get_softc(self);
359	uint32_t cparams;
360	uint32_t eecp;
361	uint32_t eec;
362	uint16_t to;
363	uint8_t bios_sem;
364
365	cparams = XREAD4(sc, capa, XHCI_HCSPARAMS0);
366
367	eec = -1;
368
369	/* Synchronise with the BIOS if it owns the controller. */
370	for (eecp = XHCI_HCS0_XECP(cparams) << 2; eecp != 0 && XHCI_XECP_NEXT(eec);
371	    eecp += XHCI_XECP_NEXT(eec) << 2) {
372		eec = XREAD4(sc, capa, eecp);
373
374		if (XHCI_XECP_ID(eec) != XHCI_ID_USB_LEGACY)
375			continue;
376		bios_sem = XREAD1(sc, capa, eecp +
377		    XHCI_XECP_BIOS_SEM);
378		if (bios_sem == 0)
379			continue;
380		device_printf(sc->sc_bus.bdev, "waiting for BIOS "
381		    "to give up control\n");
382		XWRITE1(sc, capa, eecp +
383		    XHCI_XECP_OS_SEM, 1);
384		to = 500;
385		while (1) {
386			bios_sem = XREAD1(sc, capa, eecp +
387			    XHCI_XECP_BIOS_SEM);
388			if (bios_sem == 0)
389				break;
390
391			if (--to == 0) {
392				device_printf(sc->sc_bus.bdev,
393				    "timed out waiting for BIOS\n");
394				break;
395			}
396			usb_pause_mtx(NULL, hz / 100);	/* wait 10ms */
397		}
398	}
399	return (0);
400}
401