xhci_pci.c revision 318499 
1/*-
2 * Copyright (c) 2010 Hans Petter Selasky. All rights reserved.
3 *
4 * Redistribution and use in source and binary forms, with or without
5 * modification, are permitted provided that the following conditions
6 * are met:
7 * 1. Redistributions of source code must retain the above copyright
8 *    notice, this list of conditions and the following disclaimer.
9 * 2. Redistributions in binary form must reproduce the above copyright
10 *    notice, this list of conditions and the following disclaimer in the
11 *    documentation and/or other materials provided with the distribution.
12 *
13 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
14 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
15 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
16 * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
17 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
18 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
19 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
20 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
21 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
22 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
23 * SUCH DAMAGE.
24 */
25
26#include <sys/cdefs.h>
27__FBSDID("$FreeBSD: stable/10/sys/dev/usb/controller/xhci_pci.c 318499 2017-05-18 21:09:31Z marius $");
28
29#include <sys/stdint.h>
30#include <sys/stddef.h>
31#include <sys/param.h>
32#include <sys/queue.h>
33#include <sys/types.h>
34#include <sys/systm.h>
35#include <sys/kernel.h>
36#include <sys/bus.h>
37#include <sys/module.h>
38#include <sys/lock.h>
39#include <sys/mutex.h>
40#include <sys/condvar.h>
41#include <sys/sysctl.h>
42#include <sys/sx.h>
43#include <sys/unistd.h>
44#include <sys/callout.h>
45#include <sys/malloc.h>
46#include <sys/priv.h>
47
48#include <dev/usb/usb.h>
49#include <dev/usb/usbdi.h>
50
51#include <dev/usb/usb_core.h>
52#include <dev/usb/usb_busdma.h>
53#include <dev/usb/usb_process.h>
54#include <dev/usb/usb_util.h>
55
56#include <dev/usb/usb_controller.h>
57#include <dev/usb/usb_bus.h>
58#include <dev/usb/usb_pci.h>
59#include <dev/usb/controller/xhci.h>
60#include <dev/usb/controller/xhcireg.h>
61#include "usb_if.h"
62
63static device_probe_t xhci_pci_probe;
64static device_attach_t xhci_pci_attach;
65static device_detach_t xhci_pci_detach;
66static usb_take_controller_t xhci_pci_take_controller;
67
68static device_method_t xhci_device_methods[] = {
69	/* device interface */
70	DEVMETHOD(device_probe, xhci_pci_probe),
71	DEVMETHOD(device_attach, xhci_pci_attach),
72	DEVMETHOD(device_detach, xhci_pci_detach),
73	DEVMETHOD(device_suspend, bus_generic_suspend),
74	DEVMETHOD(device_resume, bus_generic_resume),
75	DEVMETHOD(device_shutdown, bus_generic_shutdown),
76	DEVMETHOD(usb_take_controller, xhci_pci_take_controller),
77
78	DEVMETHOD_END
79};
80
81static driver_t xhci_driver = {
82	.name = "xhci",
83	.methods = xhci_device_methods,
84	.size = sizeof(struct xhci_softc),
85};
86
87static devclass_t xhci_devclass;
88
89DRIVER_MODULE(xhci, pci, xhci_driver, xhci_devclass, NULL, NULL);
90MODULE_DEPEND(xhci, usb, 1, 1, 1);
91
92static const char *
93xhci_pci_match(device_t self)
94{
95	uint32_t device_id = pci_get_devid(self);
96
97	switch (device_id) {
98	case 0x78141022:
99		return ("AMD FCH USB 3.0 controller");
100
101	case 0x01941033:
102		return ("NEC uPD720200 USB 3.0 controller");
103	case 0x00151912:
104		return ("NEC uPD720202 USB 3.0 controller");
105
106	case 0x10001b73:
107		return ("Fresco Logic FL1000G USB 3.0 controller");
108
109	case 0x10421b21:
110		return ("ASMedia ASM1042 USB 3.0 controller");
111	case 0x11421b21:
112		return ("ASMedia ASM1042A USB 3.0 controller");
113
114	case 0x0f358086:
115		return ("Intel BayTrail USB 3.0 controller");
116	case 0x9c318086:
117	case 0x1e318086:
118		return ("Intel Panther Point USB 3.0 controller");
119	case 0x22b58086:
120		return ("Intel Braswell USB 3.0 controller");
121	case 0x5aa88086:
122		return ("Intel Apollo Lake USB 3.0 controller");
123	case 0x8c318086:
124		return ("Intel Lynx Point USB 3.0 controller");
125	case 0x8cb18086:
126		return ("Intel Wildcat Point USB 3.0 controller");
127	case 0x8d318086:
128		return ("Intel Wellsburg USB 3.0 controller");
129	case 0x9cb18086:
130		return ("Broadwell Integrated PCH-LP chipset USB 3.0 controller");
131	case 0x9d2f8086:
132		return ("Intel Sunrise Point-LP USB 3.0 controller");
133	case 0xa12f8086:
134		return ("Intel Sunrise Point USB 3.0 controller");
135
136	case 0xa01b177d:
137		return ("Cavium ThunderX USB 3.0 controller");
138
139	default:
140		break;
141	}
142
143	if ((pci_get_class(self) == PCIC_SERIALBUS)
144	    && (pci_get_subclass(self) == PCIS_SERIALBUS_USB)
145	    && (pci_get_progif(self) == PCIP_SERIALBUS_USB_XHCI)) {
146		return ("XHCI (generic) USB 3.0 controller");
147	}
148	return (NULL);			/* dunno */
149}
150
151static int
152xhci_pci_probe(device_t self)
153{
154	const char *desc = xhci_pci_match(self);
155
156	if (desc) {
157		device_set_desc(self, desc);
158		return (BUS_PROBE_DEFAULT);
159	} else {
160		return (ENXIO);
161	}
162}
163
164static int xhci_use_msi = 1;
165TUNABLE_INT("hw.usb.xhci.msi", &xhci_use_msi);
166
167static void
168xhci_interrupt_poll(void *_sc)
169{
170	struct xhci_softc *sc = _sc;
171	USB_BUS_UNLOCK(&sc->sc_bus);
172	xhci_interrupt(sc);
173	USB_BUS_LOCK(&sc->sc_bus);
174	usb_callout_reset(&sc->sc_callout, 1, (void *)&xhci_interrupt_poll, sc);
175}
176
177static int
178xhci_pci_port_route(device_t self, uint32_t set, uint32_t clear)
179{
180	uint32_t temp;
181	uint32_t usb3_mask;
182	uint32_t usb2_mask;
183
184	temp = pci_read_config(self, PCI_XHCI_INTEL_USB3_PSSEN, 4) |
185	    pci_read_config(self, PCI_XHCI_INTEL_XUSB2PR, 4);
186
187	temp |= set;
188	temp &= ~clear;
189
190	/* Don't set bits which the hardware doesn't support */
191	usb3_mask = pci_read_config(self, PCI_XHCI_INTEL_USB3PRM, 4);
192	usb2_mask = pci_read_config(self, PCI_XHCI_INTEL_USB2PRM, 4);
193
194	pci_write_config(self, PCI_XHCI_INTEL_USB3_PSSEN, temp & usb3_mask, 4);
195	pci_write_config(self, PCI_XHCI_INTEL_XUSB2PR, temp & usb2_mask, 4);
196
197	device_printf(self, "Port routing mask set to 0x%08x\n", temp);
198
199	return (0);
200}
201
202static int
203xhci_pci_attach(device_t self)
204{
205	struct xhci_softc *sc = device_get_softc(self);
206	int count, err, rid;
207	uint8_t usemsi = 1;
208	uint8_t usedma32 = 0;
209
210	rid = PCI_XHCI_CBMEM;
211	sc->sc_io_res = bus_alloc_resource_any(self, SYS_RES_MEMORY, &rid,
212	    RF_ACTIVE);
213	if (!sc->sc_io_res) {
214		device_printf(self, "Could not map memory\n");
215		return (ENOMEM);
216	}
217	sc->sc_io_tag = rman_get_bustag(sc->sc_io_res);
218	sc->sc_io_hdl = rman_get_bushandle(sc->sc_io_res);
219	sc->sc_io_size = rman_get_size(sc->sc_io_res);
220
221	switch (pci_get_devid(self)) {
222	case 0x01941033:	/* NEC uPD720200 USB 3.0 controller */
223	case 0x00141912:	/* NEC uPD720201 USB 3.0 controller */
224		/* Don't use 64-bit DMA on these controllers. */
225		usedma32 = 1;
226		break;
227	case 0x10001b73:	/* FL1000G */
228		/* Fresco Logic host doesn't support MSI. */
229		usemsi = 0;
230		break;
231	case 0x0f358086:	/* BayTrail */
232	case 0x9c318086:	/* Panther Point */
233	case 0x1e318086:	/* Panther Point */
234	case 0x8c318086:	/* Lynx Point */
235	case 0x8cb18086:	/* Wildcat Point */
236	case 0x9cb18086:	/* Broadwell Mobile Integrated */
237		/*
238		 * On Intel chipsets, reroute ports from EHCI to XHCI
239		 * controller and use a different IMOD value.
240		 */
241		sc->sc_port_route = &xhci_pci_port_route;
242		sc->sc_imod_default = XHCI_IMOD_DEFAULT_LP;
243		break;
244	}
245
246	if (xhci_init(sc, self, usedma32)) {
247		device_printf(self, "Could not initialize softc\n");
248		bus_release_resource(self, SYS_RES_MEMORY, PCI_XHCI_CBMEM,
249		    sc->sc_io_res);
250		return (ENXIO);
251	}
252
253	pci_enable_busmaster(self);
254
255	usb_callout_init_mtx(&sc->sc_callout, &sc->sc_bus.bus_mtx, 0);
256
257	rid = 0;
258	if (xhci_use_msi && usemsi) {
259		count = 1;
260		if (pci_alloc_msi(self, &count) == 0) {
261			if (bootverbose)
262				device_printf(self, "MSI enabled\n");
263			rid = 1;
264		}
265	}
266	sc->sc_irq_res = bus_alloc_resource_any(self, SYS_RES_IRQ, &rid,
267	    RF_ACTIVE | (rid != 0 ? 0 : RF_SHAREABLE));
268	if (sc->sc_irq_res == NULL) {
269		pci_release_msi(self);
270		device_printf(self, "Could not allocate IRQ\n");
271		/* goto error; FALLTHROUGH - use polling */
272	}
273	sc->sc_bus.bdev = device_add_child(self, "usbus", -1);
274	if (sc->sc_bus.bdev == NULL) {
275		device_printf(self, "Could not add USB device\n");
276		goto error;
277	}
278	device_set_ivars(sc->sc_bus.bdev, &sc->sc_bus);
279
280	sprintf(sc->sc_vendor, "0x%04x", pci_get_vendor(self));
281
282	if (sc->sc_irq_res != NULL) {
283		err = bus_setup_intr(self, sc->sc_irq_res, INTR_TYPE_BIO | INTR_MPSAFE,
284		    NULL, (driver_intr_t *)xhci_interrupt, sc, &sc->sc_intr_hdl);
285		if (err != 0) {
286			bus_release_resource(self, SYS_RES_IRQ,
287			    rman_get_rid(sc->sc_irq_res), sc->sc_irq_res);
288			sc->sc_irq_res = NULL;
289			pci_release_msi(self);
290			device_printf(self, "Could not setup IRQ, err=%d\n", err);
291			sc->sc_intr_hdl = NULL;
292		}
293	}
294	if (sc->sc_irq_res == NULL || sc->sc_intr_hdl == NULL) {
295		if (xhci_use_polling() != 0) {
296			device_printf(self, "Interrupt polling at %dHz\n", hz);
297			USB_BUS_LOCK(&sc->sc_bus);
298			xhci_interrupt_poll(sc);
299			USB_BUS_UNLOCK(&sc->sc_bus);
300		} else
301			goto error;
302	}
303
304	xhci_pci_take_controller(self);
305
306	err = xhci_halt_controller(sc);
307
308	if (err == 0)
309		err = xhci_start_controller(sc);
310
311	if (err == 0)
312		err = device_probe_and_attach(sc->sc_bus.bdev);
313
314	if (err) {
315		device_printf(self, "XHCI halt/start/probe failed err=%d\n", err);
316		goto error;
317	}
318	return (0);
319
320error:
321	xhci_pci_detach(self);
322	return (ENXIO);
323}
324
325static int
326xhci_pci_detach(device_t self)
327{
328	struct xhci_softc *sc = device_get_softc(self);
329
330	/* during module unload there are lots of children leftover */
331	device_delete_children(self);
332
333	usb_callout_drain(&sc->sc_callout);
334	xhci_halt_controller(sc);
335	xhci_reset_controller(sc);
336
337	pci_disable_busmaster(self);
338
339	if (sc->sc_irq_res && sc->sc_intr_hdl) {
340		bus_teardown_intr(self, sc->sc_irq_res, sc->sc_intr_hdl);
341		sc->sc_intr_hdl = NULL;
342	}
343	if (sc->sc_irq_res) {
344		bus_release_resource(self, SYS_RES_IRQ,
345		    rman_get_rid(sc->sc_irq_res), sc->sc_irq_res);
346		sc->sc_irq_res = NULL;
347		pci_release_msi(self);
348	}
349	if (sc->sc_io_res) {
350		bus_release_resource(self, SYS_RES_MEMORY, PCI_XHCI_CBMEM,
351		    sc->sc_io_res);
352		sc->sc_io_res = NULL;
353	}
354
355	xhci_uninit(sc);
356
357	return (0);
358}
359
360static int
361xhci_pci_take_controller(device_t self)
362{
363	struct xhci_softc *sc = device_get_softc(self);
364	uint32_t cparams;
365	uint32_t eecp;
366	uint32_t eec;
367	uint16_t to;
368	uint8_t bios_sem;
369
370	cparams = XREAD4(sc, capa, XHCI_HCSPARAMS0);
371
372	eec = -1;
373
374	/* Synchronise with the BIOS if it owns the controller. */
375	for (eecp = XHCI_HCS0_XECP(cparams) << 2; eecp != 0 && XHCI_XECP_NEXT(eec);
376	    eecp += XHCI_XECP_NEXT(eec) << 2) {
377		eec = XREAD4(sc, capa, eecp);
378
379		if (XHCI_XECP_ID(eec) != XHCI_ID_USB_LEGACY)
380			continue;
381		bios_sem = XREAD1(sc, capa, eecp +
382		    XHCI_XECP_BIOS_SEM);
383		if (bios_sem == 0)
384			continue;
385		device_printf(sc->sc_bus.bdev, "waiting for BIOS "
386		    "to give up control\n");
387		XWRITE1(sc, capa, eecp +
388		    XHCI_XECP_OS_SEM, 1);
389		to = 500;
390		while (1) {
391			bios_sem = XREAD1(sc, capa, eecp +
392			    XHCI_XECP_BIOS_SEM);
393			if (bios_sem == 0)
394				break;
395
396			if (--to == 0) {
397				device_printf(sc->sc_bus.bdev,
398				    "timed out waiting for BIOS\n");
399				break;
400			}
401			usb_pause_mtx(NULL, hz / 100);	/* wait 10ms */
402		}
403	}
404	return (0);
405}
406