uart.h revision 139749
195753Sdwmalone/*- 295753Sdwmalone * Copyright (c) 2003 Marcel Moolenaar 395753Sdwmalone * All rights reserved. 495753Sdwmalone * 595753Sdwmalone * Redistribution and use in source and binary forms, with or without 695753Sdwmalone * modification, are permitted provided that the following conditions 795753Sdwmalone * are met: 895753Sdwmalone * 995753Sdwmalone * 1. Redistributions of source code must retain the above copyright 1095753Sdwmalone * notice, this list of conditions and the following disclaimer. 1195753Sdwmalone * 2. Redistributions in binary form must reproduce the above copyright 1295753Sdwmalone * notice, this list of conditions and the following disclaimer in the 1395753Sdwmalone * documentation and/or other materials provided with the distribution. 1495753Sdwmalone * 1595753Sdwmalone * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 1695753Sdwmalone * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 1795753Sdwmalone * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 1895753Sdwmalone * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 1995753Sdwmalone * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 2095753Sdwmalone * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 2195753Sdwmalone * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 2295753Sdwmalone * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 2395753Sdwmalone * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 2495753Sdwmalone * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 2595753Sdwmalone * 2695753Sdwmalone * $FreeBSD: head/sys/dev/uart/uart.h 139749 2005-01-06 01:43:34Z imp $ 2795753Sdwmalone */ 2895753Sdwmalone 2995753Sdwmalone#ifndef _DEV_UART_H_ 3095753Sdwmalone#define _DEV_UART_H_ 3195753Sdwmalone 3295753Sdwmalone/* 3395753Sdwmalone * Bus access structure. This structure holds the minimum information needed 3495753Sdwmalone * to access the UART. The rclk field, although not important to actually 3595753Sdwmalone * access the UART, is important for baudrate programming, delay loops and 3695753Sdwmalone * other timing related computations. 3795753Sdwmalone */ 3895753Sdwmalonestruct uart_bas { 3995753Sdwmalone bus_space_tag_t bst; 4095753Sdwmalone bus_space_handle_t bsh; 4195753Sdwmalone u_int chan; 4295753Sdwmalone u_int rclk; 4395753Sdwmalone u_int regshft; 4495753Sdwmalone}; 4595753Sdwmalone 4695753Sdwmalone#define uart_regofs(bas, reg) ((reg) << (bas)->regshft) 4795753Sdwmalone 4895753Sdwmalone#define uart_getreg(bas, reg) \ 4995753Sdwmalone bus_space_read_1((bas)->bst, (bas)->bsh, uart_regofs(bas, reg)) 5095753Sdwmalone#define uart_setreg(bas, reg, value) \ 5195753Sdwmalone bus_space_write_1((bas)->bst, (bas)->bsh, uart_regofs(bas, reg), value) 5295753Sdwmalone 5395753Sdwmalone/* 16-bit I/O (e.g. to divisor latch) */ 5495753Sdwmalone#define uart_getdreg(bas, reg) \ 5595753Sdwmalone bus_space_read_2((bas)->bst, (bas)->bsh, uart_regofs(bas, reg)) 5695753Sdwmalone#define uart_setdreg(bas, reg, value) \ 5795753Sdwmalone bus_space_write_2((bas)->bst, (bas)->bsh, uart_regofs(bas, reg), value) 5895753Sdwmalone 5995753Sdwmalone/* 6095753Sdwmalone * XXX we don't know the length of the bus space address range in use by 6195753Sdwmalone * the UART. Since barriers don't use the length field currently, we put 6295753Sdwmalone * a zero there for now. 6395753Sdwmalone */ 6495753Sdwmalone#define uart_barrier(bas) \ 6595753Sdwmalone bus_space_barrier((bas)->bst, (bas)->bsh, 0, 0, \ 6695753Sdwmalone BUS_SPACE_BARRIER_READ|BUS_SPACE_BARRIER_WRITE) 6795753Sdwmalone 6895753Sdwmalone/* 6995753Sdwmalone * Device flags. 7095753Sdwmalone */ 7195753Sdwmalone#define UART_FLAGS_CONSOLE(f) ((f) & 0x10) 7295753Sdwmalone#define UART_FLAGS_DBGPORT(f) ((f) & 0x80) 7395753Sdwmalone 7495753Sdwmalone/* 7595753Sdwmalone * Data parity values (magical numbers related to ns8250). 7695753Sdwmalone */ 7795753Sdwmalone#define UART_PARITY_NONE 0 7895753Sdwmalone#define UART_PARITY_ODD 1 7995753Sdwmalone#define UART_PARITY_EVEN 3 8095753Sdwmalone#define UART_PARITY_MARK 5 8195753Sdwmalone#define UART_PARITY_SPACE 7 8295753Sdwmalone 8395753Sdwmalone#endif /* _DEV_UART_H_ */ 8495753Sdwmalone