if_txpreg.h revision 151772
1/* $OpenBSD: if_txpreg.h,v 1.30 2001/06/23 04:18:02 jason Exp $ */ 2/* $FreeBSD: head/sys/dev/txp/if_txpreg.h 151772 2005-10-27 21:16:17Z jhb $ */ 3 4/*- 5 * Copyright (c) 2001 Aaron Campbell <aaron@monkey.org>. 6 * All rights reserved. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 3. All advertising materials mentioning features or use of this software 17 * must display the following acknowledgement: 18 * This product includes software developed by Aaron Campbell. 19 * 4. The name of the author may not be used to endorse or promote products 20 * derived from this software without specific prior written permission. 21 * 22 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 23 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 24 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 25 * IN NO EVENT SHALL THE AUTHOR OR HIS RELATIVES BE LIABLE FOR ANY DIRECT, 26 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 27 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 28 * SERVICES; LOSS OF MIND, USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 29 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, 30 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING 31 * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 32 * THE POSSIBILITY OF SUCH DAMAGE. 33 */ 34 35#define TXP_PCI_LOMEM PCIR_BAR(1) /* memory map BAR */ 36#define TXP_PCI_LOIO PCIR_BAR(0) /* IO map BAR */ 37 38/* 39 * Typhoon registers. 40 */ 41#define TXP_SRR 0x00 /* soft reset register */ 42#define TXP_ISR 0x04 /* interrupt status register */ 43#define TXP_IER 0x08 /* interrupt enable register */ 44#define TXP_IMR 0x0c /* interrupt mask register */ 45#define TXP_SIR 0x10 /* self interrupt register */ 46#define TXP_H2A_7 0x14 /* host->arm comm 7 */ 47#define TXP_H2A_6 0x18 /* host->arm comm 6 */ 48#define TXP_H2A_5 0x1c /* host->arm comm 5 */ 49#define TXP_H2A_4 0x20 /* host->arm comm 4 */ 50#define TXP_H2A_3 0x24 /* host->arm comm 3 */ 51#define TXP_H2A_2 0x28 /* host->arm comm 2 */ 52#define TXP_H2A_1 0x2c /* host->arm comm 1 */ 53#define TXP_H2A_0 0x30 /* host->arm comm 0 */ 54#define TXP_A2H_3 0x34 /* arm->host comm 3 */ 55#define TXP_A2H_2 0x38 /* arm->host comm 2 */ 56#define TXP_A2H_1 0x3c /* arm->host comm 1 */ 57#define TXP_A2H_0 0x40 /* arm->host comm 0 */ 58 59/* 60 * interrupt bits (IMR, ISR, IER) 61 */ 62#define TXP_INT_RESERVED 0xffff0000 63#define TXP_INT_A2H_7 0x00008000 /* arm->host comm 7 */ 64#define TXP_INT_A2H_6 0x00004000 /* arm->host comm 6 */ 65#define TXP_INT_A2H_5 0x00002000 /* arm->host comm 5 */ 66#define TXP_INT_A2H_4 0x00001000 /* arm->host comm 4 */ 67#define TXP_INT_SELF 0x00000800 /* self interrupt */ 68#define TXP_INT_PCI_TABORT 0x00000400 /* pci target abort */ 69#define TXP_INT_PCI_MABORT 0x00000200 /* pci master abort */ 70#define TXP_INT_DMA3 0x00000100 /* dma3 done */ 71#define TXP_INT_DMA2 0x00000080 /* dma2 done */ 72#define TXP_INT_DMA1 0x00000040 /* dma1 done */ 73#define TXP_INT_DMA0 0x00000020 /* dma0 done */ 74#define TXP_INT_A2H_3 0x00000010 /* arm->host comm 3 */ 75#define TXP_INT_A2H_2 0x00000008 /* arm->host comm 2 */ 76#define TXP_INT_A2H_1 0x00000004 /* arm->host comm 1 */ 77#define TXP_INT_A2H_0 0x00000002 /* arm->host comm 0 */ 78#define TXP_INT_LATCH 0x00000001 /* interrupt latch */ 79 80/* 81 * soft reset register (SRR) 82 */ 83#define TXP_SRR_ALL 0x0000007f /* full reset */ 84 85/* 86 * Typhoon boot commands. 87 */ 88#define TXP_BOOTCMD_NULL 0x00 89#define TXP_BOOTCMD_DOWNLOAD_COMPLETE 0xfb 90#define TXP_BOOTCMD_SEGMENT_AVAILABLE 0xfc 91#define TXP_BOOTCMD_RUNTIME_IMAGE 0xfd 92#define TXP_BOOTCMD_REGISTER_BOOT_RECORD 0xff 93 94/* 95 * Typhoon runtime commands. 96 */ 97#define TXP_CMD_GLOBAL_RESET 0x00 98#define TXP_CMD_TX_ENABLE 0x01 99#define TXP_CMD_TX_DISABLE 0x02 100#define TXP_CMD_RX_ENABLE 0x03 101#define TXP_CMD_RX_DISABLE 0x04 102#define TXP_CMD_RX_FILTER_WRITE 0x05 103#define TXP_CMD_RX_FILTER_READ 0x06 104#define TXP_CMD_READ_STATISTICS 0x07 105#define TXP_CMD_CYCLE_STATISTICS 0x08 106#define TXP_CMD_CLEAR_STATISTICS 0x09 107#define TXP_CMD_MEMORY_READ 0x0a 108#define TXP_CMD_MEMORY_WRITE_SINGLE 0x0b 109#define TXP_CMD_VARIABLE_SECTION_READ 0x0c 110#define TXP_CMD_VARIABLE_SECTION_WRITE 0x0d 111#define TXP_CMD_STATIC_SECTION_READ 0x0e 112#define TXP_CMD_STATIC_SECTION_WRITE 0x0f 113#define TXP_CMD_IMAGE_SECTION_PROGRAM 0x10 114#define TXP_CMD_NVRAM_PAGE_READ 0x11 115#define TXP_CMD_NVRAM_PAGE_WRITE 0x12 116#define TXP_CMD_XCVR_SELECT 0x13 117#define TXP_CMD_TEST_MUX 0x14 118#define TXP_CMD_PHYLOOPBACK_ENABLE 0x15 119#define TXP_CMD_PHYLOOPBACK_DISABLE 0x16 120#define TXP_CMD_MAC_CONTROL_READ 0x17 121#define TXP_CMD_MAC_CONTROL_WRITE 0x18 122#define TXP_CMD_MAX_PKT_SIZE_READ 0x19 123#define TXP_CMD_MAX_PKT_SIZE_WRITE 0x1a 124#define TXP_CMD_MEDIA_STATUS_READ 0x1b 125#define TXP_CMD_MEDIA_STATUS_WRITE 0x1c 126#define TXP_CMD_NETWORK_DIAGS_READ 0x1d 127#define TXP_CMD_NETWORK_DIAGS_WRITE 0x1e 128#define TXP_CMD_PHY_MGMT_READ 0x1f 129#define TXP_CMD_PHY_MGMT_WRITE 0x20 130#define TXP_CMD_VARIABLE_PARAMETER_READ 0x21 131#define TXP_CMD_VARIABLE_PARAMETER_WRITE 0x22 132#define TXP_CMD_GOTO_SLEEP 0x23 133#define TXP_CMD_FIREWALL_CONTROL 0x24 134#define TXP_CMD_MCAST_HASH_MASK_WRITE 0x25 135#define TXP_CMD_STATION_ADDRESS_WRITE 0x26 136#define TXP_CMD_STATION_ADDRESS_READ 0x27 137#define TXP_CMD_STATION_MASK_WRITE 0x28 138#define TXP_CMD_STATION_MASK_READ 0x29 139#define TXP_CMD_VLAN_ETHER_TYPE_READ 0x2a 140#define TXP_CMD_VLAN_ETHER_TYPE_WRITE 0x2b 141#define TXP_CMD_VLAN_MASK_READ 0x2c 142#define TXP_CMD_VLAN_MASK_WRITE 0x2d 143#define TXP_CMD_BCAST_THROTTLE_WRITE 0x2e 144#define TXP_CMD_BCAST_THROTTLE_READ 0x2f 145#define TXP_CMD_DHCP_PREVENT_WRITE 0x30 146#define TXP_CMD_DHCP_PREVENT_READ 0x31 147#define TXP_CMD_RECV_BUFFER_CONTROL 0x32 148#define TXP_CMD_SOFTWARE_RESET 0x33 149#define TXP_CMD_CREATE_SA 0x34 150#define TXP_CMD_DELETE_SA 0x35 151#define TXP_CMD_ENABLE_RX_IP_OPTION 0x36 152#define TXP_CMD_RANDOM_NUMBER_CONTROL 0x37 153#define TXP_CMD_RANDOM_NUMBER_READ 0x38 154#define TXP_CMD_MATRIX_TABLE_MODE_WRITE 0x39 155#define TXP_CMD_MATRIX_DETAIL_READ 0x3a 156#define TXP_CMD_FILTER_ARRAY_READ 0x3b 157#define TXP_CMD_FILTER_DETAIL_READ 0x3c 158#define TXP_CMD_FILTER_TABLE_MODE_WRITE 0x3d 159#define TXP_CMD_FILTER_TCL_WRITE 0x3e 160#define TXP_CMD_FILTER_TBL_READ 0x3f 161#define TXP_CMD_FILTER_DEFINE 0x45 162#define TXP_CMD_ADD_WAKEUP_PKT 0x46 163#define TXP_CMD_ADD_SLEEP_PKT 0x47 164#define TXP_CMD_ENABLE_SLEEP_EVENTS 0x48 165#define TXP_CMD_ENABLE_WAKEUP_EVENTS 0x49 166#define TXP_CMD_GET_IP_ADDRESS 0x4a 167#define TXP_CMD_READ_PCI_REG 0x4c 168#define TXP_CMD_WRITE_PCI_REG 0x4d 169#define TXP_CMD_OFFLOAD_READ 0x4e 170#define TXP_CMD_OFFLOAD_WRITE 0x4f 171#define TXP_CMD_HELLO_RESPONSE 0x57 172#define TXP_CMD_ENABLE_RX_FILTER 0x58 173#define TXP_CMD_RX_FILTER_CAPABILITY 0x59 174#define TXP_CMD_HALT 0x5d 175#define TXP_CMD_READ_IPSEC_INFO 0x54 176#define TXP_CMD_GET_IPSEC_ENABLE 0x67 177#define TXP_CMD_INVALID 0xffff 178 179#define TXP_FRAGMENT 0x0000 180#define TXP_TXFRAME 0x0001 181#define TXP_COMMAND 0x0002 182#define TXP_OPTION 0x0003 183#define TXP_RECEIVE 0x0004 184#define TXP_RESPONSE 0x0005 185 186#define TXP_TYPE_IPSEC 0x0000 187#define TXP_TYPE_TCPSEGMENT 0x0001 188 189#define TXP_PFLAG_NOCRC 0x0000 190#define TXP_PFLAG_IPCKSUM 0x0001 191#define TXP_PFLAG_TCPCKSUM 0x0002 192#define TXP_PFLAG_TCPSEGMENT 0x0004 193#define TXP_PFLAG_INSERTVLAN 0x0008 194#define TXP_PFLAG_IPSEC 0x0010 195#define TXP_PFLAG_PRIORITY 0x0020 196#define TXP_PFLAG_UDPCKSUM 0x0040 197#define TXP_PFLAG_PADFRAME 0x0080 198 199#define TXP_MISC_FIRSTDESC 0x0000 200#define TXP_MISC_LASTDESC 0x0001 201 202#define TXP_ERR_INTERNAL 0x0000 203#define TXP_ERR_FIFOUNDERRUN 0x0001 204#define TXP_ERR_BADSSD 0x0002 205#define TXP_ERR_RUNT 0x0003 206#define TXP_ERR_CRC 0x0004 207#define TXP_ERR_OVERSIZE 0x0005 208#define TXP_ERR_ALIGNMENT 0x0006 209#define TXP_ERR_DRIBBLEBIT 0x0007 210 211#define TXP_PROTO_UNKNOWN 0x0000 212#define TXP_PROTO_IP 0x0001 213#define TXP_PROTO_IPX 0x0002 214#define TXP_PROTO_RESERVED 0x0003 215 216#define TXP_STAT_PROTO 0x0001 217#define TXP_STAT_VLAN 0x0002 218#define TXP_STAT_IPFRAGMENT 0x0004 219#define TXP_STAT_IPSEC 0x0008 220#define TXP_STAT_IPCKSUMBAD 0x0010 221#define TXP_STAT_TCPCKSUMBAD 0x0020 222#define TXP_STAT_UDPCKSUMBAD 0x0040 223#define TXP_STAT_IPCKSUMGOOD 0x0080 224#define TXP_STAT_TCPCKSUMGOOD 0x0100 225#define TXP_STAT_UDPCKSUMGOOD 0x0200 226 227struct txp_tx_desc { 228 volatile u_int8_t tx_flags; /* type/descriptor flags */ 229 volatile u_int8_t tx_numdesc; /* number of descriptors */ 230 volatile u_int16_t tx_totlen; /* total packet length */ 231 volatile u_int32_t tx_addrlo; /* virt addr low word */ 232 volatile u_int32_t tx_addrhi; /* virt addr high word */ 233 volatile u_int32_t tx_pflags; /* processing flags */ 234}; 235#define TX_FLAGS_TYPE_M 0x07 /* type mask */ 236#define TX_FLAGS_TYPE_FRAG 0x00 /* type: fragment */ 237#define TX_FLAGS_TYPE_DATA 0x01 /* type: data frame */ 238#define TX_FLAGS_TYPE_CMD 0x02 /* type: command frame */ 239#define TX_FLAGS_TYPE_OPT 0x03 /* type: options */ 240#define TX_FLAGS_TYPE_RX 0x04 /* type: command */ 241#define TX_FLAGS_TYPE_RESP 0x05 /* type: response */ 242#define TX_FLAGS_RESP 0x40 /* response requested */ 243#define TX_FLAGS_VALID 0x80 /* valid descriptor */ 244 245#define TX_PFLAGS_DNAC 0x00000001 /* do not add crc */ 246#define TX_PFLAGS_IPCKSUM 0x00000002 /* ip checksum */ 247#define TX_PFLAGS_TCPCKSUM 0x00000004 /* tcp checksum */ 248#define TX_PFLAGS_TCPSEG 0x00000008 /* tcp segmentation */ 249#define TX_PFLAGS_VLAN 0x00000010 /* insert vlan */ 250#define TX_PFLAGS_IPSEC 0x00000020 /* perform ipsec */ 251#define TX_PFLAGS_PRIO 0x00000040 /* priority field valid */ 252#define TX_PFLAGS_UDPCKSUM 0x00000080 /* udp checksum */ 253#define TX_PFLAGS_PADFRAME 0x00000100 /* pad frame */ 254#define TX_PFLAGS_VLANTAG_M 0x0ffff000 /* vlan tag mask */ 255#define TX_PFLAGS_VLANPRI_M 0x00700000 /* vlan priority mask */ 256#define TX_PFLAGS_VLANTAG_S 12 /* amount to shift tag */ 257 258struct txp_rx_desc { 259 volatile u_int8_t rx_flags; /* type/descriptor flags */ 260 volatile u_int8_t rx_numdesc; /* number of descriptors */ 261 volatile u_int16_t rx_len; /* frame length */ 262#ifdef notdef 263 volatile u_int32_t rx_vaddrlo; /* virtual address, lo word */ 264 volatile u_int32_t rx_vaddrhi; /* virtual address, hi word */ 265#endif 266 union { 267 struct txp_swdesc *rx_sd; 268 u_int64_t rx_dummy; 269 } txp_rx_u; 270 volatile u_int32_t rx_stat; /* status */ 271 volatile u_int16_t rx_filter; /* filter status */ 272 volatile u_int16_t rx_hash; /* hash status */ 273 volatile u_int32_t rx_vlan; /* vlan tag/priority */ 274}; 275 276#define rx_sd txp_rx_u.rx_sd 277 278/* txp_rx_desc.rx_flags */ 279#define RX_FLAGS_TYPE_M 0x07 /* type mask */ 280#define RX_FLAGS_TYPE_FRAG 0x00 /* type: fragment */ 281#define RX_FLAGS_TYPE_DATA 0x01 /* type: data frame */ 282#define RX_FLAGS_TYPE_CMD 0x02 /* type: command frame */ 283#define RX_FLAGS_TYPE_OPT 0x03 /* type: options */ 284#define RX_FLAGS_TYPE_RX 0x04 /* type: command */ 285#define RX_FLAGS_TYPE_RESP 0x05 /* type: response */ 286#define RX_FLAGS_RCV_TYPE_M 0x18 /* rcvtype mask */ 287#define RX_FLAGS_RCV_TYPE_RX 0x00 /* rcvtype: receive */ 288#define RX_FLAGS_RCV_TYPE_RSP 0x08 /* rcvtype: response */ 289#define RX_FLAGS_ERROR 0x40 /* error in packet */ 290 291/* txp_rx_desc.rx_stat (if rx_flags & RX_FLAGS_ERROR bit set) */ 292#define RX_ERROR_ADAPTER 0x00000000 /* adapter internal error */ 293#define RX_ERROR_FIFO 0x00000001 /* fifo underrun */ 294#define RX_ERROR_BADSSD 0x00000002 /* bad ssd */ 295#define RX_ERROR_RUNT 0x00000003 /* runt packet */ 296#define RX_ERROR_CRC 0x00000004 /* bad crc */ 297#define RX_ERROR_OVERSIZE 0x00000005 /* oversized packet */ 298#define RX_ERROR_ALIGN 0x00000006 /* alignment error */ 299#define RX_ERROR_DRIBBLE 0x00000007 /* dribble bit */ 300 301/* txp_rx_desc.rx_stat (if rx_flags & RX_FLAGS_ERROR not bit set) */ 302#define RX_STAT_PROTO_M 0x00000003 /* protocol mask */ 303#define RX_STAT_PROTO_UK 0x00000000 /* unknown protocol */ 304#define RX_STAT_PROTO_IPX 0x00000001 /* IPX */ 305#define RX_STAT_PROTO_IP 0x00000002 /* IP */ 306#define RX_STAT_PROTO_RSV 0x00000003 /* reserved */ 307#define RX_STAT_VLAN 0x00000004 /* vlan tag (in rxd) */ 308#define RX_STAT_IPFRAG 0x00000008 /* fragment, ipsec not done */ 309#define RX_STAT_IPSEC 0x00000010 /* ipsec decoded packet */ 310#define RX_STAT_IPCKSUMBAD 0x00000020 /* ip checksum failed */ 311#define RX_STAT_UDPCKSUMBAD 0x00000040 /* udp checksum failed */ 312#define RX_STAT_TCPCKSUMBAD 0x00000080 /* tcp checksum failed */ 313#define RX_STAT_IPCKSUMGOOD 0x00000100 /* ip checksum succeeded */ 314#define RX_STAT_UDPCKSUMGOOD 0x00000200 /* udp checksum succeeded */ 315#define RX_STAT_TCPCKSUMGOOD 0x00000400 /* tcp checksum succeeded */ 316 317 318struct txp_rxbuf_desc { 319 volatile u_int32_t rb_paddrlo; 320 volatile u_int32_t rb_paddrhi; 321#ifdef notdef 322 volatile u_int32_t rb_vaddrlo; 323 volatile u_int32_t rb_vaddrhi; 324#endif 325 union { 326 struct txp_swdesc *rb_sd; 327 u_int64_t rb_dummy; 328 } txp_rb_u; 329}; 330 331#define rb_sd txp_rb_u.rb_sd 332 333/* Extension descriptor */ 334struct txp_ext_desc { 335 volatile u_int32_t ext_1; 336 volatile u_int32_t ext_2; 337 volatile u_int32_t ext_3; 338 volatile u_int32_t ext_4; 339}; 340 341struct txp_cmd_desc { 342 volatile u_int8_t cmd_flags; 343 volatile u_int8_t cmd_numdesc; 344 volatile u_int16_t cmd_id; 345 volatile u_int16_t cmd_seq; 346 volatile u_int16_t cmd_par1; 347 volatile u_int32_t cmd_par2; 348 volatile u_int32_t cmd_par3; 349}; 350#define CMD_FLAGS_TYPE_M 0x07 /* type mask */ 351#define CMD_FLAGS_TYPE_FRAG 0x00 /* type: fragment */ 352#define CMD_FLAGS_TYPE_DATA 0x01 /* type: data frame */ 353#define CMD_FLAGS_TYPE_CMD 0x02 /* type: command frame */ 354#define CMD_FLAGS_TYPE_OPT 0x03 /* type: options */ 355#define CMD_FLAGS_TYPE_RX 0x04 /* type: command */ 356#define CMD_FLAGS_TYPE_RESP 0x05 /* type: response */ 357#define CMD_FLAGS_RESP 0x40 /* response requested */ 358#define CMD_FLAGS_VALID 0x80 /* valid descriptor */ 359 360struct txp_rsp_desc { 361 volatile u_int8_t rsp_flags; 362 volatile u_int8_t rsp_numdesc; 363 volatile u_int16_t rsp_id; 364 volatile u_int16_t rsp_seq; 365 volatile u_int16_t rsp_par1; 366 volatile u_int32_t rsp_par2; 367 volatile u_int32_t rsp_par3; 368}; 369#define RSP_FLAGS_TYPE_M 0x07 /* type mask */ 370#define RSP_FLAGS_TYPE_FRAG 0x00 /* type: fragment */ 371#define RSP_FLAGS_TYPE_DATA 0x01 /* type: data frame */ 372#define RSP_FLAGS_TYPE_CMD 0x02 /* type: command frame */ 373#define RSP_FLAGS_TYPE_OPT 0x03 /* type: options */ 374#define RSP_FLAGS_TYPE_RX 0x04 /* type: command */ 375#define RSP_FLAGS_TYPE_RESP 0x05 /* type: response */ 376#define RSP_FLAGS_ERROR 0x40 /* response error */ 377 378struct txp_frag_desc { 379 volatile u_int8_t frag_flags; /* type/descriptor flags */ 380 volatile u_int8_t frag_rsvd1; 381 volatile u_int16_t frag_len; /* bytes in this fragment */ 382 volatile u_int32_t frag_addrlo; /* phys addr low word */ 383 volatile u_int32_t frag_addrhi; /* phys addr high word */ 384 volatile u_int32_t frag_rsvd2; 385}; 386#define FRAG_FLAGS_TYPE_M 0x07 /* type mask */ 387#define FRAG_FLAGS_TYPE_FRAG 0x00 /* type: fragment */ 388#define FRAG_FLAGS_TYPE_DATA 0x01 /* type: data frame */ 389#define FRAG_FLAGS_TYPE_CMD 0x02 /* type: command frame */ 390#define FRAG_FLAGS_TYPE_OPT 0x03 /* type: options */ 391#define FRAG_FLAGS_TYPE_RX 0x04 /* type: command */ 392#define FRAG_FLAGS_TYPE_RESP 0x05 /* type: response */ 393 394struct txp_opt_desc { 395 u_int8_t opt_desctype:3, 396 opt_rsvd:1, 397 opt_type:4; 398 399 u_int8_t opt_num; 400 u_int16_t opt_dep1; 401 u_int32_t opt_dep2; 402 u_int32_t opt_dep3; 403 u_int32_t opt_dep4; 404}; 405 406struct txp_ipsec_desc { 407 u_int8_t ipsec_desctpe:3, 408 ipsec_rsvd:1, 409 ipsec_type:4; 410 411 u_int8_t ipsec_num; 412 u_int16_t ipsec_flags; 413 u_int16_t ipsec_ah1; 414 u_int16_t ipsec_esp1; 415 u_int16_t ipsec_ah2; 416 u_int16_t ipsec_esp2; 417 u_int32_t ipsec_rsvd1; 418}; 419 420struct txp_tcpseg_desc { 421 u_int8_t tcpseg_desctype:3, 422 tcpseg_rsvd:1, 423 tcpseg_type:4; 424 425 u_int8_t tcpseg_num; 426 427 u_int16_t tcpseg_mss:12, 428 tcpseg_misc:4; 429 430 u_int32_t tcpseg_respaddr; 431 u_int32_t tcpseg_txbytes; 432 u_int32_t tcpseg_lss; 433}; 434 435/* 436 * Transceiver types 437 */ 438#define TXP_XCVR_10_HDX 0 439#define TXP_XCVR_10_FDX 1 440#define TXP_XCVR_100_HDX 2 441#define TXP_XCVR_100_FDX 3 442#define TXP_XCVR_AUTO 4 443 444#define TXP_MEDIA_CRC 0x0004 /* crc strip disable */ 445#define TXP_MEDIA_CD 0x0010 /* collision detection */ 446#define TXP_MEDIA_CS 0x0020 /* carrier sense */ 447#define TXP_MEDIA_POL 0x0400 /* polarity reversed */ 448#define TXP_MEDIA_NOLINK 0x0800 /* 0 = link, 1 = no link */ 449 450/* 451 * receive filter bits (par1 to TXP_CMD_RX_FILTER_{READ|WRITE} 452 */ 453#define TXP_RXFILT_DIRECT 0x0001 /* directed packets */ 454#define TXP_RXFILT_ALLMULTI 0x0002 /* all multicast packets */ 455#define TXP_RXFILT_BROADCAST 0x0004 /* broadcast packets */ 456#define TXP_RXFILT_PROMISC 0x0008 /* promiscuous mode */ 457#define TXP_RXFILT_HASHMULTI 0x0010 /* use multicast filter */ 458 459/* multicast polynomial */ 460#define TXP_POLYNOMIAL 0x04c11db7 461 462/* 463 * boot record (pointers to rings) 464 */ 465struct txp_boot_record { 466 volatile u_int32_t br_hostvar_lo; /* host ring pointer */ 467 volatile u_int32_t br_hostvar_hi; 468 volatile u_int32_t br_txlopri_lo; /* tx low pri ring */ 469 volatile u_int32_t br_txlopri_hi; 470 volatile u_int32_t br_txlopri_siz; 471 volatile u_int32_t br_txhipri_lo; /* tx high pri ring */ 472 volatile u_int32_t br_txhipri_hi; 473 volatile u_int32_t br_txhipri_siz; 474 volatile u_int32_t br_rxlopri_lo; /* rx low pri ring */ 475 volatile u_int32_t br_rxlopri_hi; 476 volatile u_int32_t br_rxlopri_siz; 477 volatile u_int32_t br_rxbuf_lo; /* rx buffer ring */ 478 volatile u_int32_t br_rxbuf_hi; 479 volatile u_int32_t br_rxbuf_siz; 480 volatile u_int32_t br_cmd_lo; /* command ring */ 481 volatile u_int32_t br_cmd_hi; 482 volatile u_int32_t br_cmd_siz; 483 volatile u_int32_t br_resp_lo; /* response ring */ 484 volatile u_int32_t br_resp_hi; 485 volatile u_int32_t br_resp_siz; 486 volatile u_int32_t br_zero_lo; /* zero word */ 487 volatile u_int32_t br_zero_hi; 488 volatile u_int32_t br_rxhipri_lo; /* rx high pri ring */ 489 volatile u_int32_t br_rxhipri_hi; 490 volatile u_int32_t br_rxhipri_siz; 491}; 492 493/* 494 * hostvar structure (shared with typhoon) 495 */ 496struct txp_hostvar { 497 volatile u_int32_t hv_rx_hi_read_idx; /* host->arm */ 498 volatile u_int32_t hv_rx_lo_read_idx; /* host->arm */ 499 volatile u_int32_t hv_rx_buf_write_idx; /* host->arm */ 500 volatile u_int32_t hv_resp_read_idx; /* host->arm */ 501 volatile u_int32_t hv_tx_lo_desc_read_idx; /* arm->host */ 502 volatile u_int32_t hv_tx_hi_desc_read_idx; /* arm->host */ 503 volatile u_int32_t hv_rx_lo_write_idx; /* arm->host */ 504 volatile u_int32_t hv_rx_buf_read_idx; /* arm->host */ 505 volatile u_int32_t hv_cmd_read_idx; /* arm->host */ 506 volatile u_int32_t hv_resp_write_idx; /* arm->host */ 507 volatile u_int32_t hv_rx_hi_write_idx; /* arm->host */ 508}; 509 510/* 511 * TYPHOON status register state (in TXP_A2H_0) 512 */ 513#define STAT_ROM_CODE 0x00000001 514#define STAT_ROM_EEPROM_LOAD 0x00000002 515#define STAT_WAITING_FOR_BOOT 0x00000007 516#define STAT_RUNNING 0x00000009 517#define STAT_WAITING_FOR_HOST_REQUEST 0x0000000d 518#define STAT_WAITING_FOR_SEGMENT 0x00000010 519#define STAT_SLEEPING 0x00000011 520#define STAT_HALTED 0x00000014 521 522#define TX_ENTRIES 256 523#define RX_ENTRIES 128 524#define RXBUF_ENTRIES 256 525#define CMD_ENTRIES 32 526#define RSP_ENTRIES 32 527 528#define OFFLOAD_TCPCKSUM 0x00000002 /* tcp checksum */ 529#define OFFLOAD_UDPCKSUM 0x00000004 /* udp checksum */ 530#define OFFLOAD_IPCKSUM 0x00000008 /* ip checksum */ 531#define OFFLOAD_IPSEC 0x00000010 /* ipsec enable */ 532#define OFFLOAD_BCAST 0x00000020 /* broadcast throttle */ 533#define OFFLOAD_DHCP 0x00000040 /* dhcp prevention */ 534#define OFFLOAD_VLAN 0x00000080 /* vlan enable */ 535#define OFFLOAD_FILTER 0x00000100 /* filter enable */ 536#define OFFLOAD_TCPSEG 0x00000200 /* tcp segmentation */ 537#define OFFLOAD_MASK 0xfffffffe /* mask off low bit */ 538 539/* 540 * Macros for converting array indices to offsets within the descriptor 541 * arrays. The chip operates on offsets, but it's much easier for us 542 * to operate on indices. Assumes descriptor entries are 16 bytes. 543 */ 544#define TXP_IDX2OFFSET(idx) ((idx) << 4) 545#define TXP_OFFSET2IDX(off) ((off) >> 4) 546 547struct txp_cmd_ring { 548 struct txp_cmd_desc *base; 549 u_int32_t lastwrite; 550 u_int32_t size; 551}; 552 553struct txp_rsp_ring { 554 struct txp_rsp_desc *base; 555 u_int32_t lastwrite; 556 u_int32_t size; 557}; 558 559struct txp_tx_ring { 560 struct txp_tx_desc *r_desc; /* base address of descs */ 561 u_int32_t r_reg; /* register to activate */ 562 u_int32_t r_prod; /* producer */ 563 u_int32_t r_cons; /* consumer */ 564 u_int32_t r_cnt; /* # descs in use */ 565 volatile u_int32_t *r_off; /* hostvar index pointer */ 566}; 567 568struct txp_swdesc { 569 struct mbuf * sd_mbuf; 570 bus_dmamap_t sd_map; 571}; 572 573struct txp_rx_ring { 574 struct txp_rx_desc *r_desc; /* base address of descs */ 575 volatile u_int32_t *r_roff; /* hv read offset ptr */ 576 volatile u_int32_t *r_woff; /* hv write offset ptr */ 577}; 578 579struct txp_ldata { 580 struct txp_boot_record txp_boot; 581 struct txp_hostvar txp_hostvar; 582 struct txp_tx_desc txp_txhiring[TX_ENTRIES]; 583 struct txp_tx_desc txp_txloring[TX_ENTRIES]; 584 struct txp_rxbuf_desc txp_rxbufs[RXBUF_ENTRIES]; 585 struct txp_rx_desc txp_rxhiring[RX_ENTRIES]; 586 struct txp_rx_desc txp_rxloring[RX_ENTRIES]; 587 struct txp_cmd_desc txp_cmdring[CMD_ENTRIES]; 588 struct txp_rsp_desc txp_rspring[RSP_ENTRIES]; 589 u_int32_t txp_zero; 590}; 591 592struct txp_softc { 593 struct ifnet *sc_ifp; 594 device_t sc_dev; 595 struct txp_hostvar *sc_hostvar; 596 struct txp_boot_record *sc_boot; 597 bus_space_handle_t sc_bh; /* bus handle (regs) */ 598 bus_space_tag_t sc_bt; /* bus tag (regs) */ 599 struct resource *sc_res; 600 struct resource *sc_irq; 601 void *sc_intrhand; 602 struct mtx sc_mtx; 603 struct txp_ldata *sc_ldata; 604 void *sc_fwbuf; 605 int sc_rxbufprod; 606 struct txp_cmd_ring sc_cmdring; 607 struct txp_rsp_ring sc_rspring; 608 struct txp_swdesc sc_txd[TX_ENTRIES]; 609 struct callout sc_tick; 610 struct ifmedia sc_ifmedia; 611 struct txp_tx_ring sc_txhir, sc_txlor; 612 struct txp_rxbuf_desc *sc_rxbufs; 613 struct txp_rx_ring sc_rxhir, sc_rxlor; 614 u_int16_t sc_xcvr; 615 u_int16_t sc_seq; 616 int sc_cold; 617 u_int32_t sc_rx_capability, sc_tx_capability; 618}; 619 620struct txp_fw_file_header { 621 u_int8_t magicid[8]; /* TYPHOON\0 */ 622 u_int32_t version; 623 u_int32_t nsections; 624 u_int32_t addr; 625}; 626 627struct txp_fw_section_header { 628 u_int32_t nbytes; 629 u_int16_t cksum; 630 u_int16_t reserved; 631 u_int32_t addr; 632}; 633 634#define TXP_MAX_SEGLEN 0xffff 635#define TXP_MAX_PKTLEN 0x0800 636 637#define WRITE_REG(sc,reg,val) \ 638 bus_space_write_4((sc)->sc_bt, (sc)->sc_bh, reg, val) 639#define READ_REG(sc,reg) \ 640 bus_space_read_4((sc)->sc_bt, (sc)->sc_bh, reg) 641 642#define TXP_LOCK(sc) mtx_lock(&(sc)->sc_mtx) 643#define TXP_UNLOCK(sc) mtx_unlock(&(sc)->sc_mtx) 644#define TXP_LOCK_ASSERT(sc) mtx_assert(&(sc)->sc_mtx, MA_OWNED) 645 646/* 647 * 3Com PCI vendor ID. 648 */ 649#define TXP_VENDORID_3COM 0x10B7 650 651/* 652 * 3cR990 device IDs 653 */ 654#define TXP_DEVICEID_3CR990_TX_95 0x9902 655#define TXP_DEVICEID_3CR990_TX_97 0x9903 656#define TXP_DEVICEID_3CR990B_TXM 0x9904 657#define TXP_DEVICEID_3CR990_SRV_95 0x9908 658#define TXP_DEVICEID_3CR990_SRV_97 0x9909 659#define TXP_DEVICEID_3CR990B_SRV 0x990A 660 661struct txp_type { 662 u_int16_t txp_vid; 663 u_int16_t txp_did; 664 char *txp_name; 665}; 666