140804Ssemenu/*- 240804Ssemenu * Copyright (c) 1997 Semen Ustimenko 340804Ssemenu * All rights reserved. 440804Ssemenu * 540804Ssemenu * Redistribution and use in source and binary forms, with or without 640804Ssemenu * modification, are permitted provided that the following conditions 740804Ssemenu * are met: 840804Ssemenu * 1. Redistributions of source code must retain the above copyright 940804Ssemenu * notice, this list of conditions and the following disclaimer. 1040804Ssemenu * 2. Redistributions in binary form must reproduce the above copyright 1140804Ssemenu * notice, this list of conditions and the following disclaimer in the 1240804Ssemenu * documentation and/or other materials provided with the distribution. 1340804Ssemenu * 1440804Ssemenu * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 1540804Ssemenu * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 1640804Ssemenu * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 1740804Ssemenu * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 1840804Ssemenu * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 1940804Ssemenu * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 2040804Ssemenu * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 2140804Ssemenu * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 2240804Ssemenu * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 2340804Ssemenu * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 2440804Ssemenu * SUCH DAMAGE. 25105666Ssemenu * 26105666Ssemenu * $FreeBSD$ 2740804Ssemenu */ 2840804Ssemenu 2981593Ssemenu#define EPIC_MAX_MTU 1600 /* This is experiment-derived value */ 3081593Ssemenu 3159164Ssemenu/* PCI aux configuration registers */ 32119690Sjhb#define PCIR_BASEIO PCIR_BAR(0) /* Base IO Address */ 33119690Sjhb#define PCIR_BASEMEM PCIR_BAR(1) /* Base Memory Address */ 3459164Ssemenu 3540804Ssemenu/* PCI identification */ 3640804Ssemenu#define SMC_VENDORID 0x10B8 3759164Ssemenu#define SMC_DEVICEID_83C170 0x0005 3840804Ssemenu 3940804Ssemenu/* EPIC's registers */ 4040804Ssemenu#define COMMAND 0x0000 4140804Ssemenu#define INTSTAT 0x0004 /* Interrupt status. See below */ 4240804Ssemenu#define INTMASK 0x0008 /* Interrupt mask. See below */ 4340804Ssemenu#define GENCTL 0x000C 4440804Ssemenu#define NVCTL 0x0010 4540804Ssemenu#define EECTL 0x0014 /* EEPROM control **/ 4640804Ssemenu#define TEST1 0x001C /* XXXXX */ 4740804Ssemenu#define CRCCNT 0x0020 /* CRC error counter */ 4840804Ssemenu#define ALICNT 0x0024 /* FrameTooLang error counter */ 4940804Ssemenu#define MPCNT 0x0028 /* MissedFrames error counters */ 5040804Ssemenu#define MIICTL 0x0030 5140804Ssemenu#define MIIDATA 0x0034 5240804Ssemenu#define MIICFG 0x0038 5340804Ssemenu#define IPG 0x003C 5440804Ssemenu#define LAN0 0x0040 /* MAC address */ 5540804Ssemenu#define LAN1 0x0044 /* MAC address */ 5640804Ssemenu#define LAN2 0x0048 /* MAC address */ 5740804Ssemenu#define ID_CHK 0x004C 5840804Ssemenu#define MC0 0x0050 /* Multicast filter table */ 5940804Ssemenu#define MC1 0x0054 /* Multicast filter table */ 6040804Ssemenu#define MC2 0x0058 /* Multicast filter table */ 6140804Ssemenu#define MC3 0x005C /* Multicast filter table */ 6240804Ssemenu#define RXCON 0x0060 /* Rx control register */ 6340804Ssemenu#define TXCON 0x0070 /* Tx control register */ 6440804Ssemenu#define TXSTAT 0x0074 6540804Ssemenu#define PRCDAR 0x0084 /* RxRing bus address */ 6640804Ssemenu#define PRSTAT 0x00A4 6740804Ssemenu#define PRCPTHR 0x00B0 6840804Ssemenu#define PTCDAR 0x00C4 /* TxRing bus address */ 6940804Ssemenu#define ETXTHR 0x00DC 7040804Ssemenu 7140804Ssemenu#define COMMAND_STOP_RX 0x01 7240804Ssemenu#define COMMAND_START_RX 0x02 7340804Ssemenu#define COMMAND_TXQUEUED 0x04 7440804Ssemenu#define COMMAND_RXQUEUED 0x08 7540804Ssemenu#define COMMAND_NEXTFRAME 0x10 7640804Ssemenu#define COMMAND_STOP_TDMA 0x20 7740804Ssemenu#define COMMAND_STOP_RDMA 0x40 7840804Ssemenu#define COMMAND_TXUGO 0x80 7940804Ssemenu 8040804Ssemenu/* Interrupt register bits */ 8140804Ssemenu#define INTSTAT_RCC 0x00000001 8240804Ssemenu#define INTSTAT_HCC 0x00000002 8340804Ssemenu#define INTSTAT_RQE 0x00000004 8440804Ssemenu#define INTSTAT_OVW 0x00000008 8540804Ssemenu#define INTSTAT_RXE 0x00000010 8640804Ssemenu#define INTSTAT_TXC 0x00000020 8740804Ssemenu#define INTSTAT_TCC 0x00000040 8840804Ssemenu#define INTSTAT_TQE 0x00000080 8940804Ssemenu#define INTSTAT_TXU 0x00000100 9040804Ssemenu#define INTSTAT_CNT 0x00000200 9140804Ssemenu#define INTSTAT_PREI 0x00000400 9240804Ssemenu#define INTSTAT_RCT 0x00000800 9340804Ssemenu#define INTSTAT_FATAL 0x00001000 /* One of DPE,APE,PMA,PTA happend */ 9440804Ssemenu#define INTSTAT_UNUSED1 0x00002000 9540804Ssemenu#define INTSTAT_UNUSED2 0x00004000 9640804Ssemenu#define INTSTAT_GP2 0x00008000 /* PHY Event */ 9740804Ssemenu#define INTSTAT_INT_ACTV 0x00010000 9840804Ssemenu#define INTSTAT_RXIDLE 0x00020000 9940804Ssemenu#define INTSTAT_TXIDLE 0x00040000 10040804Ssemenu#define INTSTAT_RCIP 0x00080000 10140804Ssemenu#define INTSTAT_TCIP 0x00100000 10240804Ssemenu#define INTSTAT_RBE 0x00200000 10340804Ssemenu#define INTSTAT_RCTS 0x00400000 10440804Ssemenu#define INTSTAT_RSV 0x00800000 10540804Ssemenu#define INTSTAT_DPE 0x01000000 /* PCI Fatal error */ 10640804Ssemenu#define INTSTAT_APE 0x02000000 /* PCI Fatal error */ 10740804Ssemenu#define INTSTAT_PMA 0x04000000 /* PCI Fatal error */ 10840804Ssemenu#define INTSTAT_PTA 0x08000000 /* PCI Fatal error */ 10940804Ssemenu 11040804Ssemenu#define GENCTL_SOFT_RESET 0x00000001 11140804Ssemenu#define GENCTL_ENABLE_INTERRUPT 0x00000002 11240804Ssemenu#define GENCTL_SOFTWARE_INTERRUPT 0x00000004 11340804Ssemenu#define GENCTL_POWER_DOWN 0x00000008 11440804Ssemenu#define GENCTL_ONECOPY 0x00000010 11540804Ssemenu#define GENCTL_BIG_ENDIAN 0x00000020 11640804Ssemenu#define GENCTL_RECEIVE_DMA_PRIORITY 0x00000040 11740804Ssemenu#define GENCTL_TRANSMIT_DMA_PRIORITY 0x00000080 11840804Ssemenu#define GENCTL_RECEIVE_FIFO_THRESHOLD128 0x00000300 11940804Ssemenu#define GENCTL_RECEIVE_FIFO_THRESHOLD96 0x00000200 12040804Ssemenu#define GENCTL_RECEIVE_FIFO_THRESHOLD64 0x00000100 12140804Ssemenu#define GENCTL_RECEIVE_FIFO_THRESHOLD32 0x00000000 12240804Ssemenu#define GENCTL_MEMORY_READ_LINE 0x00000400 12340804Ssemenu#define GENCTL_MEMORY_READ_MULTIPLE 0x00000800 12440804Ssemenu#define GENCTL_SOFTWARE1 0x00001000 12540804Ssemenu#define GENCTL_SOFTWARE2 0x00002000 12640804Ssemenu#define GENCTL_RESET_PHY 0x00004000 12740804Ssemenu 12840804Ssemenu#define NVCTL_ENABLE_MEMORY_MAP 0x00000001 12940804Ssemenu#define NVCTL_CLOCK_RUN_SUPPORTED 0x00000002 13040804Ssemenu#define NVCTL_GP1_OUTPUT_ENABLE 0x00000004 13140804Ssemenu#define NVCTL_GP2_OUTPUT_ENABLE 0x00000008 13240804Ssemenu#define NVCTL_GP1 0x00000010 13340804Ssemenu#define NVCTL_GP2 0x00000020 13440804Ssemenu#define NVCTL_CARDBUS_MODE 0x00000040 13540804Ssemenu#define NVCTL_IPG_DELAY_MASK(x) ((x&0xF)<<7) 13640804Ssemenu 13740804Ssemenu#define RXCON_SAVE_ERRORED_PACKETS 0x00000001 13840804Ssemenu#define RXCON_RECEIVE_RUNT_FRAMES 0x00000002 13940804Ssemenu#define RXCON_RECEIVE_BROADCAST_FRAMES 0x00000004 14040804Ssemenu#define RXCON_RECEIVE_MULTICAST_FRAMES 0x00000008 14140804Ssemenu#define RXCON_RECEIVE_INVERSE_INDIVIDUAL_ADDRESS_FRAMES 0x00000010 14240804Ssemenu#define RXCON_PROMISCUOUS_MODE 0x00000020 14340804Ssemenu#define RXCON_MONITOR_MODE 0x00000040 14440804Ssemenu#define RXCON_EARLY_RECEIVE_ENABLE 0x00000080 14540804Ssemenu#define RXCON_EXTERNAL_BUFFER_DISABLE 0x00000000 14640804Ssemenu#define RXCON_EXTERNAL_BUFFER_16K 0x00000100 14740804Ssemenu#define RXCON_EXTERNAL_BUFFER_32K 0x00000200 14840804Ssemenu#define RXCON_EXTERNAL_BUFFER_128K 0x00000300 14940804Ssemenu 15040804Ssemenu#define TXCON_EARLY_TRANSMIT_ENABLE 0x00000001 15140804Ssemenu#define TXCON_LOOPBACK_DISABLE 0x00000000 15240804Ssemenu#define TXCON_LOOPBACK_MODE_INT 0x00000002 15340804Ssemenu#define TXCON_LOOPBACK_MODE_PHY 0x00000004 15440804Ssemenu#define TXCON_LOOPBACK_MODE 0x00000006 15540804Ssemenu#define TXCON_FULL_DUPLEX 0x00000006 15640804Ssemenu#define TXCON_SLOT_TIME 0x00000078 15740804Ssemenu 15861906Ssemenu#define MIICFG_SERIAL_ENABLE 0x00000001 15961906Ssemenu#define MIICFG_694_ENABLE 0x00000002 16061906Ssemenu#define MIICFG_694_STATUS 0x00000004 16161906Ssemenu#define MIICFG_PHY_PRESENT 0x00000008 16244737Ssemenu#define MIICFG_SMI_ENABLE 0x00000010 16344737Ssemenu 16444737Ssemenu#define TEST1_CLOCK_TEST 0x00000008 16544737Ssemenu 16659164Ssemenu/* 16759164Ssemenu * Some default values 16859164Ssemenu */ 16940804Ssemenu#define TXCON_DEFAULT (TXCON_SLOT_TIME | TXCON_EARLY_TRANSMIT_ENABLE) 17059164Ssemenu#define TRANSMIT_THRESHOLD 0x300 171105666Ssemenu#define TRANSMIT_THRESHOLD_MAX 0x600 17240804Ssemenu 17395075Ssemenu#define RXCON_DEFAULT (RXCON_RECEIVE_MULTICAST_FRAMES | \ 17495075Ssemenu RXCON_RECEIVE_BROADCAST_FRAMES) 17595075Ssemenu 17695075Ssemenu#define RXCON_EARLY_RX (RXCON_EARLY_RECEIVE_ENABLE | \ 17759164Ssemenu RXCON_SAVE_ERRORED_PACKETS) 17878677Ssemenu/* 17978677Ssemenu * EEPROM structure 18078677Ssemenu * SMC9432* eeprom is organized by words and only first 8 words 18178677Ssemenu * have distinctive meaning (according to datasheet) 18278677Ssemenu */ 18378677Ssemenu#define EEPROM_MAC0 0x0000 /* Byte 0 / Byte 1 */ 18478677Ssemenu#define EEPROM_MAC1 0x0001 /* Byte 2 / Byte 3 */ 18578677Ssemenu#define EEPROM_MAC2 0x0002 /* Byte 4 / Byte 5 */ 18678677Ssemenu#define EEPROM_BID_CSUM 0x0003 /* Board Id / Check Sum */ 18778677Ssemenu#define EEPROM_NVCTL 0x0004 /* NVCTL (bits 0-5) / nothing */ 18878677Ssemenu#define EEPROM_PCI_MGD_MLD 0x0005 /* PCI MinGrant / MaxLatency. Desired */ 18978677Ssemenu#define EEPROM_SSVENDID 0x0006 /* Subsystem Vendor Id */ 19078677Ssemenu#define EEPROM_SSID 0x0006 /* Subsystem Id */ 19140804Ssemenu 19240804Ssemenu/* 193113726Smux * Hardware structures. 19440804Ssemenu */ 19540804Ssemenu 196113726Smux/* 197113726Smux * EPIC's hardware descriptors, must be aligned on dword in memory. 198113726Smux * NB: to make driver happy, this two structures MUST have their sizes 199113726Smux * be divisor of PAGE_SIZE. 200113726Smux */ 20140804Ssemenustruct epic_tx_desc { 20240804Ssemenu volatile u_int16_t status; 20340804Ssemenu volatile u_int16_t txlength; 20440804Ssemenu volatile u_int32_t bufaddr; 20540804Ssemenu volatile u_int16_t buflength; 20640804Ssemenu volatile u_int16_t control; 20740804Ssemenu volatile u_int32_t next; 20840804Ssemenu}; 20940804Ssemenustruct epic_rx_desc { 21040804Ssemenu volatile u_int16_t status; 21140804Ssemenu volatile u_int16_t rxlength; 21240804Ssemenu volatile u_int32_t bufaddr; 21340804Ssemenu volatile u_int32_t buflength; 21440804Ssemenu volatile u_int32_t next; 21540804Ssemenu}; 21640804Ssemenu 217113726Smux/* 218113726Smux * This structure defines EPIC's fragment list, maximum number of frags 219113726Smux * is 63. Let's use the maximum, because size of struct MUST be divisor 220113726Smux * of PAGE_SIZE, and sometimes come mbufs with more then 30 frags. 221113726Smux */ 22240804Ssemenu#define EPIC_MAX_FRAGS 63 22340804Ssemenustruct epic_frag_list { 22440804Ssemenu volatile u_int32_t numfrags; 22540804Ssemenu struct { 22640804Ssemenu volatile u_int32_t fragaddr; 22740804Ssemenu volatile u_int32_t fraglen; 22840804Ssemenu } frag[EPIC_MAX_FRAGS]; 22940804Ssemenu volatile u_int32_t pad; /* align on 256 bytes */ 23040804Ssemenu}; 23140804Ssemenu 23240804Ssemenu/* 23340804Ssemenu * NB: ALIGN OF ABOVE STRUCTURES 23440804Ssemenu * epic_rx_desc, epic_tx_desc, epic_frag_list - must be aligned on dword 23540804Ssemenu */ 23640804Ssemenu 23772134Ssemenu#define SMC9432DMT 0xA010 23872134Ssemenu#define SMC9432TX 0xA011 23972134Ssemenu#define SMC9032TXM 0xA012 24072134Ssemenu#define SMC9032TX 0xA013 24172134Ssemenu#define SMC9432TXPWR 0xA014 24272134Ssemenu#define SMC9432BTX 0xA015 24372134Ssemenu#define SMC9432FTX 0xA016 24472134Ssemenu#define SMC9432FTX_SC 0xA017 24572134Ssemenu#define SMC9432TX_XG_ADHOC 0xA020 24672134Ssemenu#define SMC9434TX_XG_ADHOC 0xA021 24772134Ssemenu#define SMC9432FTX_ADHOC 0xA022 24872134Ssemenu#define SMC9432BTX1 0xA024 249