1193323Sed/*- 2193323Sed * Copyright (c) 1997 Semen Ustimenko 3193323Sed * All rights reserved. 4193323Sed * 5193323Sed * Redistribution and use in source and binary forms, with or without 6193323Sed * modification, are permitted provided that the following conditions 7193323Sed * are met: 8193323Sed * 1. Redistributions of source code must retain the above copyright 9193323Sed * notice, this list of conditions and the following disclaimer. 10193323Sed * 2. Redistributions in binary form must reproduce the above copyright 11193323Sed * notice, this list of conditions and the following disclaimer in the 12193323Sed * documentation and/or other materials provided with the distribution. 13193323Sed * 14193323Sed * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 15193323Sed * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 16193323Sed * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 17193323Sed * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 18193323Sed * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 19193323Sed * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 20193323Sed * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 21193323Sed * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 22249423Sdim * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 23249423Sdim * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 24249423Sdim * SUCH DAMAGE. 25249423Sdim * 26249423Sdim * $FreeBSD$ 27249423Sdim */ 28193323Sed 29193323Sed#define EPIC_MAX_MTU 1600 /* This is experiment-derived value */ 30198090Srdivacky 31198090Srdivacky/* PCI aux configuration registers */ 32249423Sdim#define PCIR_BASEIO PCIR_BAR(0) /* Base IO Address */ 33193323Sed#define PCIR_BASEMEM PCIR_BAR(1) /* Base Memory Address */ 34193323Sed 35193323Sed/* PCI identification */ 36193323Sed#define SMC_VENDORID 0x10B8 37193323Sed#define SMC_DEVICEID_83C170 0x0005 38193323Sed 39193323Sed/* EPIC's registers */ 40193323Sed#define COMMAND 0x0000 41193323Sed#define INTSTAT 0x0004 /* Interrupt status. See below */ 42193323Sed#define INTMASK 0x0008 /* Interrupt mask. See below */ 43234353Sdim#define GENCTL 0x000C 44234353Sdim#define NVCTL 0x0010 45193323Sed#define EECTL 0x0014 /* EEPROM control **/ 46193323Sed#define TEST1 0x001C /* XXXXX */ 47202375Srdivacky#define CRCCNT 0x0020 /* CRC error counter */ 48221345Sdim#define ALICNT 0x0024 /* FrameTooLang error counter */ 49221345Sdim#define MPCNT 0x0028 /* MissedFrames error counters */ 50193323Sed#define MIICTL 0x0030 51193323Sed#define MIIDATA 0x0034 52193323Sed#define MIICFG 0x0038 53193323Sed#define IPG 0x003C 54193323Sed#define LAN0 0x0040 /* MAC address */ 55193323Sed#define LAN1 0x0044 /* MAC address */ 56212904Sdim#define LAN2 0x0048 /* MAC address */ 57212904Sdim#define ID_CHK 0x004C 58212904Sdim#define MC0 0x0050 /* Multicast filter table */ 59212904Sdim#define MC1 0x0054 /* Multicast filter table */ 60212904Sdim#define MC2 0x0058 /* Multicast filter table */ 61212904Sdim#define MC3 0x005C /* Multicast filter table */ 62263508Sdim#define RXCON 0x0060 /* Rx control register */ 63212904Sdim#define TXCON 0x0070 /* Tx control register */ 64212904Sdim#define TXSTAT 0x0074 65212904Sdim#define PRCDAR 0x0084 /* RxRing bus address */ 66212904Sdim#define PRSTAT 0x00A4 67193323Sed#define PRCPTHR 0x00B0 68218893Sdim#define PTCDAR 0x00C4 /* TxRing bus address */ 69193323Sed#define ETXTHR 0x00DC 70193323Sed 71193323Sed#define COMMAND_STOP_RX 0x01 72193323Sed#define COMMAND_START_RX 0x02 73193323Sed#define COMMAND_TXQUEUED 0x04 74193323Sed#define COMMAND_RXQUEUED 0x08 75193323Sed#define COMMAND_NEXTFRAME 0x10 76193323Sed#define COMMAND_STOP_TDMA 0x20 77193323Sed#define COMMAND_STOP_RDMA 0x40 78193323Sed#define COMMAND_TXUGO 0x80 79193323Sed 80193323Sed/* Interrupt register bits */ 81193323Sed#define INTSTAT_RCC 0x00000001 82234353Sdim#define INTSTAT_HCC 0x00000002 83234353Sdim#define INTSTAT_RQE 0x00000004 84234353Sdim#define INTSTAT_OVW 0x00000008 85193323Sed#define INTSTAT_RXE 0x00000010 86193323Sed#define INTSTAT_TXC 0x00000020 87218893Sdim#define INTSTAT_TCC 0x00000040 88218893Sdim#define INTSTAT_TQE 0x00000080 89193323Sed#define INTSTAT_TXU 0x00000100 90193323Sed#define INTSTAT_CNT 0x00000200 91193323Sed#define INTSTAT_PREI 0x00000400 92193323Sed#define INTSTAT_RCT 0x00000800 93193323Sed#define INTSTAT_FATAL 0x00001000 /* One of DPE,APE,PMA,PTA happend */ 94193323Sed#define INTSTAT_UNUSED1 0x00002000 95193323Sed#define INTSTAT_UNUSED2 0x00004000 96193323Sed#define INTSTAT_GP2 0x00008000 /* PHY Event */ 97193323Sed#define INTSTAT_INT_ACTV 0x00010000 98193323Sed#define INTSTAT_RXIDLE 0x00020000 99193323Sed#define INTSTAT_TXIDLE 0x00040000 100193323Sed#define INTSTAT_RCIP 0x00080000 101193323Sed#define INTSTAT_TCIP 0x00100000 102193323Sed#define INTSTAT_RBE 0x00200000 103193323Sed#define INTSTAT_RCTS 0x00400000 104193323Sed#define INTSTAT_RSV 0x00800000 105193323Sed#define INTSTAT_DPE 0x01000000 /* PCI Fatal error */ 106193323Sed#define INTSTAT_APE 0x02000000 /* PCI Fatal error */ 107193323Sed#define INTSTAT_PMA 0x04000000 /* PCI Fatal error */ 108193323Sed#define INTSTAT_PTA 0x08000000 /* PCI Fatal error */ 109202375Srdivacky 110263508Sdim#define GENCTL_SOFT_RESET 0x00000001 111221345Sdim#define GENCTL_ENABLE_INTERRUPT 0x00000002 112221345Sdim#define GENCTL_SOFTWARE_INTERRUPT 0x00000004 113221345Sdim#define GENCTL_POWER_DOWN 0x00000008 114221345Sdim#define GENCTL_ONECOPY 0x00000010 115221345Sdim#define GENCTL_BIG_ENDIAN 0x00000020 116221345Sdim#define GENCTL_RECEIVE_DMA_PRIORITY 0x00000040 117221345Sdim#define GENCTL_TRANSMIT_DMA_PRIORITY 0x00000080 118263508Sdim#define GENCTL_RECEIVE_FIFO_THRESHOLD128 0x00000300 119221345Sdim#define GENCTL_RECEIVE_FIFO_THRESHOLD96 0x00000200 120221345Sdim#define GENCTL_RECEIVE_FIFO_THRESHOLD64 0x00000100 121193323Sed#define GENCTL_RECEIVE_FIFO_THRESHOLD32 0x00000000 122221345Sdim#define GENCTL_MEMORY_READ_LINE 0x00000400 123221345Sdim#define GENCTL_MEMORY_READ_MULTIPLE 0x00000800 124221345Sdim#define GENCTL_SOFTWARE1 0x00001000 125221345Sdim#define GENCTL_SOFTWARE2 0x00002000 126263508Sdim#define GENCTL_RESET_PHY 0x00004000 127226633Sdim 128226633Sdim#define NVCTL_ENABLE_MEMORY_MAP 0x00000001 129226633Sdim#define NVCTL_CLOCK_RUN_SUPPORTED 0x00000002 130226633Sdim#define NVCTL_GP1_OUTPUT_ENABLE 0x00000004 131226633Sdim#define NVCTL_GP2_OUTPUT_ENABLE 0x00000008 132226633Sdim#define NVCTL_GP1 0x00000010 133226633Sdim#define NVCTL_GP2 0x00000020 134226633Sdim#define NVCTL_CARDBUS_MODE 0x00000040 135221345Sdim#define NVCTL_IPG_DELAY_MASK(x) ((x&0xF)<<7) 136221345Sdim 137193323Sed#define RXCON_SAVE_ERRORED_PACKETS 0x00000001 138221345Sdim#define RXCON_RECEIVE_RUNT_FRAMES 0x00000002 139221345Sdim#define RXCON_RECEIVE_BROADCAST_FRAMES 0x00000004 140221345Sdim#define RXCON_RECEIVE_MULTICAST_FRAMES 0x00000008 141221345Sdim#define RXCON_RECEIVE_INVERSE_INDIVIDUAL_ADDRESS_FRAMES 0x00000010 142251662Sdim#define RXCON_PROMISCUOUS_MODE 0x00000020 143221345Sdim#define RXCON_MONITOR_MODE 0x00000040 144221345Sdim#define RXCON_EARLY_RECEIVE_ENABLE 0x00000080 145221345Sdim#define RXCON_EXTERNAL_BUFFER_DISABLE 0x00000000 146221345Sdim#define RXCON_EXTERNAL_BUFFER_16K 0x00000100 147221345Sdim#define RXCON_EXTERNAL_BUFFER_32K 0x00000200 148251662Sdim#define RXCON_EXTERNAL_BUFFER_128K 0x00000300 149221345Sdim 150221345Sdim#define TXCON_EARLY_TRANSMIT_ENABLE 0x00000001 151221345Sdim#define TXCON_LOOPBACK_DISABLE 0x00000000 152221345Sdim#define TXCON_LOOPBACK_MODE_INT 0x00000002 153221345Sdim#define TXCON_LOOPBACK_MODE_PHY 0x00000004 154251662Sdim#define TXCON_LOOPBACK_MODE 0x00000006 155221345Sdim#define TXCON_FULL_DUPLEX 0x00000006 156221345Sdim#define TXCON_SLOT_TIME 0x00000078 157221345Sdim 158221345Sdim#define MIICFG_SERIAL_ENABLE 0x00000001 159221345Sdim#define MIICFG_694_ENABLE 0x00000002 160251662Sdim#define MIICFG_694_STATUS 0x00000004 161221345Sdim#define MIICFG_PHY_PRESENT 0x00000008 162221345Sdim#define MIICFG_SMI_ENABLE 0x00000010 163221345Sdim 164221345Sdim#define TEST1_CLOCK_TEST 0x00000008 165221345Sdim 166251662Sdim/* 167221345Sdim * Some default values 168249423Sdim */ 169249423Sdim#define TXCON_DEFAULT (TXCON_SLOT_TIME | TXCON_EARLY_TRANSMIT_ENABLE) 170249423Sdim#define TRANSMIT_THRESHOLD 0x300 171251662Sdim#define TRANSMIT_THRESHOLD_MAX 0x600 172223017Sdim 173221345Sdim#define RXCON_DEFAULT (RXCON_RECEIVE_MULTICAST_FRAMES | \ 174221345Sdim RXCON_RECEIVE_BROADCAST_FRAMES) 175221345Sdim 176221345Sdim#define RXCON_EARLY_RX (RXCON_EARLY_RECEIVE_ENABLE | \ 177221345Sdim RXCON_SAVE_ERRORED_PACKETS) 178221345Sdim/* 179202375Srdivacky * EEPROM structure 180193323Sed * SMC9432* eeprom is organized by words and only first 8 words 181221345Sdim * have distinctive meaning (according to datasheet) 182221345Sdim */ 183221345Sdim#define EEPROM_MAC0 0x0000 /* Byte 0 / Byte 1 */ 184221345Sdim#define EEPROM_MAC1 0x0001 /* Byte 2 / Byte 3 */ 185221345Sdim#define EEPROM_MAC2 0x0002 /* Byte 4 / Byte 5 */ 186221345Sdim#define EEPROM_BID_CSUM 0x0003 /* Board Id / Check Sum */ 187221345Sdim#define EEPROM_NVCTL 0x0004 /* NVCTL (bits 0-5) / nothing */ 188221345Sdim#define EEPROM_PCI_MGD_MLD 0x0005 /* PCI MinGrant / MaxLatency. Desired */ 189221345Sdim#define EEPROM_SSVENDID 0x0006 /* Subsystem Vendor Id */ 190221345Sdim#define EEPROM_SSID 0x0006 /* Subsystem Id */ 191221345Sdim 192221345Sdim/* 193221345Sdim * Hardware structures. 194221345Sdim */ 195221345Sdim 196221345Sdim/* 197221345Sdim * EPIC's hardware descriptors, must be aligned on dword in memory. 198221345Sdim * NB: to make driver happy, this two structures MUST have their sizes 199221345Sdim * be divisor of PAGE_SIZE. 200221345Sdim */ 201221345Sdimstruct epic_tx_desc { 202221345Sdim volatile u_int16_t status; 203221345Sdim volatile u_int16_t txlength; 204221345Sdim volatile u_int32_t bufaddr; 205263508Sdim volatile u_int16_t buflength; 206221345Sdim volatile u_int16_t control; 207221345Sdim volatile u_int32_t next; 208221345Sdim}; 209221345Sdimstruct epic_rx_desc { 210263508Sdim volatile u_int16_t status; 211221345Sdim volatile u_int16_t rxlength; 212221345Sdim volatile u_int32_t bufaddr; 213221345Sdim volatile u_int32_t buflength; 214221345Sdim volatile u_int32_t next; 215221345Sdim}; 216221345Sdim 217221345Sdim/* 218221345Sdim * This structure defines EPIC's fragment list, maximum number of frags 219221345Sdim * is 63. Let's use the maximum, because size of struct MUST be divisor 220221345Sdim * of PAGE_SIZE, and sometimes come mbufs with more then 30 frags. 221221345Sdim */ 222221345Sdim#define EPIC_MAX_FRAGS 63 223221345Sdimstruct epic_frag_list { 224221345Sdim volatile u_int32_t numfrags; 225221345Sdim struct { 226221345Sdim volatile u_int32_t fragaddr; 227221345Sdim volatile u_int32_t fraglen; 228221345Sdim } frag[EPIC_MAX_FRAGS]; 229221345Sdim volatile u_int32_t pad; /* align on 256 bytes */ 230221345Sdim}; 231221345Sdim 232221345Sdim/* 233221345Sdim * NB: ALIGN OF ABOVE STRUCTURES 234221345Sdim * epic_rx_desc, epic_tx_desc, epic_frag_list - must be aligned on dword 235221345Sdim */ 236221345Sdim 237221345Sdim#define SMC9432DMT 0xA010 238221345Sdim#define SMC9432TX 0xA011 239221345Sdim#define SMC9032TXM 0xA012 240221345Sdim#define SMC9032TX 0xA013 241221345Sdim#define SMC9432TXPWR 0xA014 242221345Sdim#define SMC9432BTX 0xA015 243221345Sdim#define SMC9432FTX 0xA016 244221345Sdim#define SMC9432FTX_SC 0xA017 245221345Sdim#define SMC9432TX_XG_ADHOC 0xA020 246221345Sdim#define SMC9434TX_XG_ADHOC 0xA021 247221345Sdim#define SMC9432FTX_ADHOC 0xA022 248221345Sdim#define SMC9432BTX1 0xA024 249221345Sdim