trm.c revision 315813
1/* 2 * O.S : FreeBSD CAM 3 * FILE NAME : trm.c 4 * BY : C.L. Huang (ching@tekram.com.tw) 5 * Erich Chen (erich@tekram.com.tw) 6 * Description: Device Driver for Tekram SCSI adapters 7 * DC395U/UW/F ,DC315/U(TRM-S1040) 8 * DC395U2D/U2W(TRM-S2080) 9 * PCI SCSI Bus Master Host Adapter 10 * (SCSI chip set used Tekram ASIC TRM-S1040,TRM-S2080) 11 */ 12 13#include <sys/cdefs.h> 14__FBSDID("$FreeBSD: stable/10/sys/dev/trm/trm.c 315813 2017-03-23 06:41:13Z mav $"); 15 16/* 17 * HISTORY: 18 * 19 * REV# DATE NAME DESCRIPTION 20 * 1.05 05/01/1999 ERICH CHEN First released for 3.x.x (CAM) 21 * 1.06 07/29/1999 ERICH CHEN Modify for NEW PCI 22 * 1.07 12/12/1999 ERICH CHEN Modify for 3.3.x ,DCB no free 23 * 1.08 06/12/2000 ERICH CHEN Modify for 4.x.x 24 * 1.09 11/03/2000 ERICH CHEN Modify for 4.1.R ,new sim 25 * 1.10 10/10/2001 Oscar Feng Fixed CAM rescan hang up bug. 26 * 1.11 10/13/2001 Oscar Feng Fixed wrong Async speed display bug. 27 */ 28 29/*- 30 * (C)Copyright 1995-2001 Tekram Technology Co.,Ltd. 31 * 32 * Redistribution and use in source and binary forms, with or without 33 * modification, are permitted provided that the following conditions 34 * are met: 35 * 1. Redistributions of source code must retain the above copyright 36 * notice, this list of conditions and the following disclaimer. 37 * 2. Redistributions in binary form must reproduce the above copyright 38 * notice, this list of conditions and the following disclaimer in the 39 * documentation and/or other materials provided with the distribution. 40 * 3. The name of the author may not be used to endorse or promote products 41 * derived from this software without specific prior written permission. 42 * 43 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 44 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 45 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 46 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 47 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 48 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 49 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 50 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 51 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 52 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 53 * 54 */ 55 56/* 57 * Imported into FreeBSD source repository, and updated to compile under 58 * FreeBSD-3.0-DEVELOPMENT, by Stefan Esser <se@FreeBSD.Org>, 1996-12-17 59 */ 60 61/* 62 * Updated to compile under FreeBSD 5.0-CURRENT by Olivier Houchard 63 * <doginou@ci0.org>, 2002-03-04 64 */ 65 66#include <sys/param.h> 67 68#include <sys/systm.h> 69#include <sys/malloc.h> 70#include <sys/queue.h> 71#if __FreeBSD_version >= 500000 72#include <sys/bio.h> 73#endif 74#include <sys/buf.h> 75#include <sys/bus.h> 76#include <sys/kernel.h> 77#include <sys/module.h> 78 79#include <vm/vm.h> 80#include <vm/pmap.h> 81 82#include <dev/pci/pcivar.h> 83#include <dev/pci/pcireg.h> 84#include <machine/resource.h> 85#include <machine/bus.h> 86#include <sys/rman.h> 87 88#include <cam/cam.h> 89#include <cam/cam_ccb.h> 90#include <cam/cam_sim.h> 91#include <cam/cam_xpt_sim.h> 92#include <cam/cam_debug.h> 93 94#include <cam/scsi/scsi_all.h> 95#include <cam/scsi/scsi_message.h> 96 97#include <dev/trm/trm.h> 98 99#define trm_reg_read8(reg) bus_space_read_1(pACB->tag, pACB->bsh, reg) 100#define trm_reg_read16(reg) bus_space_read_2(pACB->tag, pACB->bsh, reg) 101#define trm_reg_read32(reg) bus_space_read_4(pACB->tag, pACB->bsh, reg) 102#define trm_reg_write8(value,reg) bus_space_write_1(pACB->tag, pACB->bsh,\ 103 reg, value) 104#define trm_reg_write16(value,reg) bus_space_write_2(pACB->tag, pACB->bsh,\ 105 reg, value) 106#define trm_reg_write32(value,reg) bus_space_write_4(pACB->tag, pACB->bsh,\ 107 reg, value) 108 109#define PCI_Vendor_ID_TEKRAM 0x1DE1 110#define PCI_Device_ID_TRM_S1040 0x0391 111#define PCI_DEVICEID_TRMS1040 0x03911DE1 112#define PCI_DEVICEID_TRMS2080 0x03921DE1 113 114#ifdef trm_DEBUG1 115#define TRM_DPRINTF(fmt, arg...) printf("trm: " fmt, ##arg) 116#else 117#define TRM_DPRINTF(fmt, arg...) {} 118#endif /* TRM_DEBUG */ 119 120static void trm_check_eeprom(PNVRAMTYPE pEEpromBuf,PACB pACB); 121static void NVRAM_trm_read_all(PNVRAMTYPE pEEpromBuf,PACB pACB); 122static u_int8_t NVRAM_trm_get_data(PACB pACB, u_int8_t bAddr); 123static void NVRAM_trm_write_all(PNVRAMTYPE pEEpromBuf,PACB pACB); 124static void NVRAM_trm_set_data(PACB pACB, u_int8_t bAddr, u_int8_t bData); 125static void NVRAM_trm_write_cmd(PACB pACB, u_int8_t bCmd, u_int8_t bAddr); 126static void NVRAM_trm_wait_30us(PACB pACB); 127 128static void trm_Interrupt(void *vpACB); 129static void trm_DataOutPhase0(PACB pACB, PSRB pSRB, 130 u_int16_t * pscsi_status); 131static void trm_DataInPhase0(PACB pACB, PSRB pSRB, 132 u_int16_t * pscsi_status); 133static void trm_CommandPhase0(PACB pACB, PSRB pSRB, 134 u_int16_t * pscsi_status); 135static void trm_StatusPhase0(PACB pACB, PSRB pSRB, 136 u_int16_t * pscsi_status); 137static void trm_MsgOutPhase0(PACB pACB, PSRB pSRB, 138 u_int16_t * pscsi_status); 139static void trm_MsgInPhase0(PACB pACB, PSRB pSRB, 140 u_int16_t * pscsi_status); 141static void trm_DataOutPhase1(PACB pACB, PSRB pSRB, 142 u_int16_t * pscsi_status); 143static void trm_DataInPhase1(PACB pACB, PSRB pSRB, 144 u_int16_t * pscsi_status); 145static void trm_CommandPhase1(PACB pACB, PSRB pSRB, 146 u_int16_t * pscsi_status); 147static void trm_StatusPhase1(PACB pACB, PSRB pSRB, 148 u_int16_t * pscsi_status); 149static void trm_MsgOutPhase1(PACB pACB, PSRB pSRB, 150 u_int16_t * pscsi_status); 151static void trm_MsgInPhase1(PACB pACB, PSRB pSRB, 152 u_int16_t * pscsi_status); 153static void trm_Nop0(PACB pACB, PSRB pSRB, u_int16_t * pscsi_status); 154static void trm_Nop1(PACB pACB, PSRB pSRB, u_int16_t * pscsi_status); 155static void trm_SetXferRate(PACB pACB, PSRB pSRB,PDCB pDCB); 156static void trm_DataIO_transfer(PACB pACB, PSRB pSRB, u_int16_t ioDir); 157static void trm_Disconnect(PACB pACB); 158static void trm_Reselect(PACB pACB); 159static void trm_SRBdone(PACB pACB, PDCB pDCB, PSRB pSRB); 160static void trm_DoingSRB_Done(PACB pACB); 161static void trm_ScsiRstDetect(PACB pACB); 162static void trm_ResetSCSIBus(PACB pACB); 163static void trm_RequestSense(PACB pACB, PDCB pDCB, PSRB pSRB); 164static void trm_EnableMsgOutAbort2(PACB pACB, PSRB pSRB); 165static void trm_EnableMsgOutAbort1(PACB pACB, PSRB pSRB); 166static void trm_SendSRB(PACB pACB, PSRB pSRB); 167static int trm_probe(device_t tag); 168static int trm_attach(device_t tag); 169static void trm_reset(PACB pACB); 170 171static u_int16_t trm_StartSCSI(PACB pACB, PDCB pDCB, PSRB pSRB); 172 173static int trm_initAdapter(PACB pACB, u_int16_t unit); 174static void trm_initDCB(PACB pACB, PDCB pDCB, u_int16_t unit, 175 u_int32_t i, u_int32_t j); 176static int trm_initSRB(PACB pACB); 177static void trm_initACB(PACB pACB, u_int8_t adaptType, u_int16_t unit); 178/* CAM SIM entry points */ 179#define ccb_trmsrb_ptr spriv_ptr0 180#define ccb_trmacb_ptr spriv_ptr1 181static void trm_action(struct cam_sim *psim, union ccb *pccb); 182static void trm_poll(struct cam_sim *psim); 183 184 185static void * trm_SCSI_phase0[] = { 186 trm_DataOutPhase0, /* phase:0 */ 187 trm_DataInPhase0, /* phase:1 */ 188 trm_CommandPhase0, /* phase:2 */ 189 trm_StatusPhase0, /* phase:3 */ 190 trm_Nop0, /* phase:4 */ 191 trm_Nop1, /* phase:5 */ 192 trm_MsgOutPhase0, /* phase:6 */ 193 trm_MsgInPhase0, /* phase:7 */ 194}; 195 196/* 197 * 198 * stateV = (void *) trm_SCSI_phase1[phase] 199 * 200 */ 201static void * trm_SCSI_phase1[] = { 202 trm_DataOutPhase1, /* phase:0 */ 203 trm_DataInPhase1, /* phase:1 */ 204 trm_CommandPhase1, /* phase:2 */ 205 trm_StatusPhase1, /* phase:3 */ 206 trm_Nop0, /* phase:4 */ 207 trm_Nop1, /* phase:5 */ 208 trm_MsgOutPhase1, /* phase:6 */ 209 trm_MsgInPhase1, /* phase:7 */ 210}; 211 212 213NVRAMTYPE trm_eepromBuf[TRM_MAX_ADAPTER_NUM]; 214/* 215 *Fast20: 000 50ns, 20.0 Mbytes/s 216 * 001 75ns, 13.3 Mbytes/s 217 * 010 100ns, 10.0 Mbytes/s 218 * 011 125ns, 8.0 Mbytes/s 219 * 100 150ns, 6.6 Mbytes/s 220 * 101 175ns, 5.7 Mbytes/s 221 * 110 200ns, 5.0 Mbytes/s 222 * 111 250ns, 4.0 Mbytes/s 223 * 224 *Fast40: 000 25ns, 40.0 Mbytes/s 225 * 001 50ns, 20.0 Mbytes/s 226 * 010 75ns, 13.3 Mbytes/s 227 * 011 100ns, 10.0 Mbytes/s 228 * 100 125ns, 8.0 Mbytes/s 229 * 101 150ns, 6.6 Mbytes/s 230 * 110 175ns, 5.7 Mbytes/s 231 * 111 200ns, 5.0 Mbytes/s 232 */ 233 /* real period: */ 234u_int8_t dc395x_clock_period[] = { 235 12,/* 48 ns 20 MB/sec */ 236 18,/* 72 ns 13.3 MB/sec */ 237 25,/* 100 ns 10.0 MB/sec */ 238 31,/* 124 ns 8.0 MB/sec */ 239 37,/* 148 ns 6.6 MB/sec */ 240 43,/* 172 ns 5.7 MB/sec */ 241 50,/* 200 ns 5.0 MB/sec */ 242 62 /* 248 ns 4.0 MB/sec */ 243}; 244 245u_int8_t dc395u2x_clock_period[]={ 246 10,/* 25 ns 40.0 MB/sec */ 247 12,/* 48 ns 20.0 MB/sec */ 248 18,/* 72 ns 13.3 MB/sec */ 249 25,/* 100 ns 10.0 MB/sec */ 250 31,/* 124 ns 8.0 MB/sec */ 251 37,/* 148 ns 6.6 MB/sec */ 252 43,/* 172 ns 5.7 MB/sec */ 253 50,/* 200 ns 5.0 MB/sec */ 254}; 255 256#define dc395x_tinfo_period dc395x_clock_period 257#define dc395u2x_tinfo_period dc395u2x_clock_period 258 259static PSRB 260trm_GetSRB(PACB pACB) 261{ 262 int intflag; 263 PSRB pSRB; 264 265 intflag = splcam(); 266 pSRB = pACB->pFreeSRB; 267 if (pSRB) { 268 pACB->pFreeSRB = pSRB->pNextSRB; 269 pSRB->pNextSRB = NULL; 270 } 271 splx(intflag); 272 return (pSRB); 273} 274 275static void 276trm_RewaitSRB0(PDCB pDCB, PSRB pSRB) 277{ 278 PSRB psrb1; 279 int intflag; 280 281 intflag = splcam(); 282 if ((psrb1 = pDCB->pWaitingSRB)) { 283 pSRB->pNextSRB = psrb1; 284 pDCB->pWaitingSRB = pSRB; 285 } else { 286 pSRB->pNextSRB = NULL; 287 pDCB->pWaitingSRB = pSRB; 288 pDCB->pWaitingLastSRB = pSRB; 289 } 290 splx(intflag); 291} 292 293static void 294trm_RewaitSRB(PDCB pDCB, PSRB pSRB) 295{ 296 PSRB psrb1; 297 int intflag; 298 299 intflag = splcam(); 300 pDCB->GoingSRBCnt--; 301 psrb1 = pDCB->pGoingSRB; 302 if (pSRB == psrb1) 303 /* 304 * if this SRB is GoingSRB 305 * remove this SRB from GoingSRB Q 306 */ 307 pDCB->pGoingSRB = psrb1->pNextSRB; 308 else { 309 /* 310 * if this SRB is not current GoingSRB 311 * remove this SRB from GoingSRB Q 312 */ 313 while (pSRB != psrb1->pNextSRB) 314 psrb1 = psrb1->pNextSRB; 315 psrb1->pNextSRB = pSRB->pNextSRB; 316 if (pSRB == pDCB->pGoingLastSRB) 317 pDCB->pGoingLastSRB = psrb1; 318 } 319 if ((psrb1 = pDCB->pWaitingSRB)) { 320 /* 321 * if WaitingSRB Q is not NULL 322 * Q back this SRB into WaitingSRB 323 */ 324 325 pSRB->pNextSRB = psrb1; 326 pDCB->pWaitingSRB = pSRB; 327 } else { 328 pSRB->pNextSRB = NULL; 329 pDCB->pWaitingSRB = pSRB; 330 pDCB->pWaitingLastSRB = pSRB; 331 } 332 splx(intflag); 333} 334 335static void 336trm_DoWaitingSRB(PACB pACB) 337{ 338 int intflag; 339 PDCB ptr, ptr1; 340 PSRB pSRB; 341 342 intflag = splcam(); 343 if (!(pACB->pActiveDCB) && 344 !(pACB->ACBFlag & (RESET_DETECT+RESET_DONE+RESET_DEV))) { 345 ptr = pACB->pDCBRunRobin; 346 if (!ptr) { 347 ptr = pACB->pLinkDCB; 348 pACB->pDCBRunRobin = ptr; 349 } 350 ptr1 = ptr; 351 for (;ptr1 ;) { 352 pACB->pDCBRunRobin = ptr1->pNextDCB; 353 if (!(ptr1->MaxActiveCommandCnt > ptr1->GoingSRBCnt) 354 || !(pSRB = ptr1->pWaitingSRB)) { 355 if (pACB->pDCBRunRobin == ptr) 356 break; 357 ptr1 = ptr1->pNextDCB; 358 } else { 359 if (!trm_StartSCSI(pACB, ptr1, pSRB)) { 360 /* 361 * If trm_StartSCSI return 0 : 362 * current interrupt status is interrupt enable 363 * It's said that SCSI processor is unoccupied 364 */ 365 ptr1->GoingSRBCnt++; 366 if (ptr1->pWaitingLastSRB == pSRB) { 367 ptr1->pWaitingSRB = NULL; 368 ptr1->pWaitingLastSRB = NULL; 369 } else 370 ptr1->pWaitingSRB = pSRB->pNextSRB; 371 pSRB->pNextSRB = NULL; 372 if (ptr1->pGoingSRB) 373 ptr1->pGoingLastSRB->pNextSRB = pSRB; 374 else 375 ptr1->pGoingSRB = pSRB; 376 ptr1->pGoingLastSRB = pSRB; 377 } 378 break; 379 } 380 } 381 } 382 splx(intflag); 383 return; 384} 385 386static void 387trm_SRBwaiting(PDCB pDCB, PSRB pSRB) 388{ 389 390 if (pDCB->pWaitingSRB) { 391 pDCB->pWaitingLastSRB->pNextSRB = pSRB; 392 pDCB->pWaitingLastSRB = pSRB; 393 pSRB->pNextSRB = NULL; 394 } else { 395 pDCB->pWaitingSRB = pSRB; 396 pDCB->pWaitingLastSRB = pSRB; 397 } 398} 399 400static u_int32_t 401trm_get_sense_bufaddr(PACB pACB, PSRB pSRB) 402{ 403 int offset; 404 405 offset = pSRB->TagNumber; 406 return (pACB->sense_busaddr + 407 (offset * sizeof(struct scsi_sense_data))); 408} 409 410static struct scsi_sense_data * 411trm_get_sense_buf(PACB pACB, PSRB pSRB) 412{ 413 int offset; 414 415 offset = pSRB->TagNumber; 416 return (&pACB->sense_buffers[offset]); 417} 418static void 419trm_ExecuteSRB(void *arg, bus_dma_segment_t *dm_segs, int nseg, int error) 420{ 421 int flags; 422 PACB pACB; 423 PSRB pSRB; 424 union ccb *ccb; 425 u_long totalxferlen=0; 426 427 flags = splcam(); 428 pSRB = (PSRB)arg; 429 ccb = pSRB->pccb; 430 pACB = (PACB)ccb->ccb_h.ccb_trmacb_ptr; 431 TRM_DPRINTF("trm_ExecuteSRB..........\n"); 432 if (nseg != 0) { 433 PSEG psg; 434 bus_dma_segment_t *end_seg; 435 int op; 436 437 /* Copy the segments into our SG list */ 438 end_seg = dm_segs + nseg; 439 psg = pSRB->pSRBSGL; 440 while (dm_segs < end_seg) { 441 psg->address = dm_segs->ds_addr; 442 psg->length = (u_long)dm_segs->ds_len; 443 totalxferlen += dm_segs->ds_len; 444 psg++; 445 dm_segs++; 446 } 447 if ((ccb->ccb_h.flags & CAM_DIR_MASK) == CAM_DIR_IN) { 448 op = BUS_DMASYNC_PREREAD; 449 } else { 450 op = BUS_DMASYNC_PREWRITE; 451 } 452 bus_dmamap_sync(pACB->buffer_dmat, pSRB->dmamap, op); 453 } 454 pSRB->RetryCnt = 0; 455 pSRB->SRBTotalXferLength = totalxferlen; 456 pSRB->SRBSGCount = nseg; 457 pSRB->SRBSGIndex = 0; 458 pSRB->AdaptStatus = 0; 459 pSRB->TargetStatus = 0; 460 pSRB->MsgCnt = 0; 461 pSRB->SRBStatus = 0; 462 pSRB->SRBFlag = 0; 463 pSRB->SRBState = 0; 464 pSRB->ScsiPhase = PH_BUS_FREE; /* SCSI bus free Phase */ 465 466 if (ccb->ccb_h.status != CAM_REQ_INPROG) { 467 if (nseg != 0) 468 bus_dmamap_unload(pACB->buffer_dmat, pSRB->dmamap); 469 pSRB->pNextSRB = pACB->pFreeSRB; 470 pACB->pFreeSRB = pSRB; 471 xpt_done(ccb); 472 splx(flags); 473 return; 474 } 475 ccb->ccb_h.status |= CAM_SIM_QUEUED; 476 trm_SendSRB(pACB, pSRB); 477 splx(flags); 478 return; 479} 480 481static void 482trm_SendSRB(PACB pACB, PSRB pSRB) 483{ 484 PDCB pDCB; 485 486 pDCB = pSRB->pSRBDCB; 487 if (!(pDCB->MaxActiveCommandCnt > pDCB->GoingSRBCnt) || (pACB->pActiveDCB) 488 || (pACB->ACBFlag & (RESET_DETECT+RESET_DONE+RESET_DEV))) { 489 TRM_DPRINTF("pDCB->MaxCommand=%d \n",pDCB->MaxActiveCommandCnt); 490 TRM_DPRINTF("pDCB->GoingSRBCnt=%d \n",pDCB->GoingSRBCnt); 491 TRM_DPRINTF("pACB->pActiveDCB=%8x \n",(u_int)pACB->pActiveDCB); 492 TRM_DPRINTF("pACB->ACBFlag=%x \n",pACB->ACBFlag); 493 trm_SRBwaiting(pDCB, pSRB); 494 goto SND_EXIT; 495 } 496 497 if (pDCB->pWaitingSRB) { 498 trm_SRBwaiting(pDCB, pSRB); 499 pSRB = pDCB->pWaitingSRB; 500 pDCB->pWaitingSRB = pSRB->pNextSRB; 501 pSRB->pNextSRB = NULL; 502 } 503 504 if (!trm_StartSCSI(pACB, pDCB, pSRB)) { 505 /* 506 * If trm_StartSCSI return 0 : 507 * current interrupt status is interrupt enable 508 * It's said that SCSI processor is unoccupied 509 */ 510 pDCB->GoingSRBCnt++; /* stack waiting SRB*/ 511 if (pDCB->pGoingSRB) { 512 pDCB->pGoingLastSRB->pNextSRB = pSRB; 513 pDCB->pGoingLastSRB = pSRB; 514 } else { 515 pDCB->pGoingSRB = pSRB; 516 pDCB->pGoingLastSRB = pSRB; 517 } 518 } else { 519 /* 520 * If trm_StartSCSI return 1 : 521 * current interrupt status is interrupt disreenable 522 * It's said that SCSI processor has more one SRB need to do 523 */ 524 trm_RewaitSRB0(pDCB, pSRB); 525 } 526SND_EXIT: 527 return; 528} 529 530 531static void 532trm_action(struct cam_sim *psim, union ccb *pccb) 533{ 534 PACB pACB; 535 int actionflags; 536 u_int target_id,target_lun; 537 538 CAM_DEBUG(pccb->ccb_h.path, CAM_DEBUG_TRACE, ("trm_action\n")); 539 540 actionflags = splcam(); 541 pACB = (PACB) cam_sim_softc(psim); 542 target_id = pccb->ccb_h.target_id; 543 target_lun = pccb->ccb_h.target_lun; 544 545 switch (pccb->ccb_h.func_code) { 546 case XPT_NOOP: 547 TRM_DPRINTF(" XPT_NOOP \n"); 548 pccb->ccb_h.status = CAM_REQ_INVALID; 549 xpt_done(pccb); 550 break; 551 /* 552 * Execute the requested I/O operation 553 */ 554 case XPT_SCSI_IO: { 555 PDCB pDCB = NULL; 556 PSRB pSRB; 557 struct ccb_scsiio *pcsio; 558 int error; 559 560 pcsio = &pccb->csio; 561 TRM_DPRINTF(" XPT_SCSI_IO \n"); 562 TRM_DPRINTF("trm: target_id= %d target_lun= %d \n" 563 ,target_id, target_lun); 564 TRM_DPRINTF( 565 "pACB->scan_devices[target_id][target_lun]= %d \n" 566 ,pACB->scan_devices[target_id][target_lun]); 567 if ((pccb->ccb_h.status & CAM_STATUS_MASK) != 568 CAM_REQ_INPROG) { 569 xpt_done(pccb); 570 splx(actionflags); 571 return; 572 } 573 pDCB = &pACB->DCBarray[target_id][target_lun]; 574 if (!(pDCB->DCBstatus & DS_IN_QUEUE)) { 575 pACB->scan_devices[target_id][target_lun] = 1; 576 trm_initDCB(pACB, pDCB, pACB->AdapterUnit, 577 target_id, target_lun); 578 } 579 /* 580 * Assign an SRB and connect it with this ccb. 581 */ 582 pSRB = trm_GetSRB(pACB); 583 if (!pSRB) { 584 /* Freeze SIMQ */ 585 pccb->ccb_h.status = CAM_RESRC_UNAVAIL; 586 xpt_done(pccb); 587 splx(actionflags); 588 return; 589 } 590 pSRB->pSRBDCB = pDCB; 591 pccb->ccb_h.ccb_trmsrb_ptr = pSRB; 592 pccb->ccb_h.ccb_trmacb_ptr = pACB; 593 pSRB->pccb = pccb; 594 pSRB->ScsiCmdLen = pcsio->cdb_len; 595 /* 596 * move layer of CAM command block to layer of SCSI 597 * Request Block for SCSI processor command doing 598 */ 599 if ((pccb->ccb_h.flags & CAM_CDB_POINTER) != 0) { 600 if ((pccb->ccb_h.flags & CAM_CDB_PHYS) == 0) { 601 bcopy(pcsio->cdb_io.cdb_ptr,pSRB->CmdBlock 602 ,pcsio->cdb_len); 603 } else { 604 pccb->ccb_h.status = CAM_REQ_INVALID; 605 pSRB->pNextSRB = pACB->pFreeSRB; 606 pACB->pFreeSRB= pSRB; 607 xpt_done(pccb); 608 splx(actionflags); 609 return; 610 } 611 } else 612 bcopy(pcsio->cdb_io.cdb_bytes, 613 pSRB->CmdBlock, pcsio->cdb_len); 614 error = bus_dmamap_load_ccb(pACB->buffer_dmat, 615 pSRB->dmamap, 616 pccb, 617 trm_ExecuteSRB, 618 pSRB, 619 0); 620 if (error == EINPROGRESS) { 621 xpt_freeze_simq(pACB->psim, 1); 622 pccb->ccb_h.status |= CAM_RELEASE_SIMQ; 623 } 624 break; 625 } 626 case XPT_GDEV_TYPE: 627 TRM_DPRINTF(" XPT_GDEV_TYPE \n"); 628 pccb->ccb_h.status = CAM_REQ_INVALID; 629 xpt_done(pccb); 630 break; 631 case XPT_GDEVLIST: 632 TRM_DPRINTF(" XPT_GDEVLIST \n"); 633 pccb->ccb_h.status = CAM_REQ_INVALID; 634 xpt_done(pccb); 635 break; 636 /* 637 * Path routing inquiry 638 * Path Inquiry CCB 639 */ 640 case XPT_PATH_INQ: { 641 struct ccb_pathinq *cpi = &pccb->cpi; 642 643 TRM_DPRINTF(" XPT_PATH_INQ \n"); 644 cpi->version_num = 1; 645 cpi->hba_inquiry = PI_SDTR_ABLE|PI_TAG_ABLE|PI_WIDE_16; 646 cpi->target_sprt = 0; 647 cpi->hba_misc = 0; 648 cpi->hba_eng_cnt = 0; 649 cpi->max_target = 15 ; 650 cpi->max_lun = pACB->max_lun; /* 7 or 0 */ 651 cpi->initiator_id = pACB->AdaptSCSIID; 652 cpi->bus_id = cam_sim_bus(psim); 653 cpi->base_transfer_speed = 3300; 654 strlcpy(cpi->sim_vid, "FreeBSD", SIM_IDLEN); 655 strlcpy(cpi->hba_vid, "Tekram_TRM", HBA_IDLEN); 656 strlcpy(cpi->dev_name, cam_sim_name(psim), DEV_IDLEN); 657 cpi->unit_number = cam_sim_unit(psim); 658 cpi->transport = XPORT_SPI; 659 cpi->transport_version = 2; 660 cpi->protocol = PROTO_SCSI; 661 cpi->protocol_version = SCSI_REV_2; 662 cpi->ccb_h.status = CAM_REQ_CMP; 663 xpt_done(pccb); 664 } 665 break; 666 /* 667 * Release a frozen SIM queue 668 * Release SIM Queue 669 */ 670 case XPT_REL_SIMQ: 671 TRM_DPRINTF(" XPT_REL_SIMQ \n"); 672 pccb->ccb_h.status = CAM_REQ_INVALID; 673 xpt_done(pccb); 674 break; 675 /* 676 * Set Asynchronous Callback Parameters 677 * Set Asynchronous Callback CCB 678 */ 679 case XPT_SASYNC_CB: 680 TRM_DPRINTF(" XPT_SASYNC_CB \n"); 681 pccb->ccb_h.status = CAM_REQ_INVALID; 682 xpt_done(pccb); 683 break; 684 /* 685 * Set device type information 686 * Set Device Type CCB 687 */ 688 case XPT_SDEV_TYPE: 689 TRM_DPRINTF(" XPT_SDEV_TYPE \n"); 690 pccb->ccb_h.status = CAM_REQ_INVALID; 691 xpt_done(pccb); 692 break; 693 /* 694 * Get EDT entries matching the given pattern 695 */ 696 case XPT_DEV_MATCH: 697 TRM_DPRINTF(" XPT_DEV_MATCH \n"); 698 pccb->ccb_h.status = CAM_REQ_INVALID; 699 xpt_done(pccb); 700 break; 701 /* 702 * Turn on debugging for a bus, target or lun 703 */ 704 case XPT_DEBUG: 705 TRM_DPRINTF(" XPT_DEBUG \n"); 706 pccb->ccb_h.status = CAM_REQ_INVALID; 707 xpt_done(pccb); 708 break; 709 /* 710 * XPT_ABORT = 0x10, Abort the specified CCB 711 * Abort XPT request CCB 712 */ 713 case XPT_ABORT: 714 TRM_DPRINTF(" XPT_ABORT \n"); 715 pccb->ccb_h.status = CAM_REQ_INVALID; 716 xpt_done(pccb); 717 break; 718 /* 719 * Reset the specified SCSI bus 720 * Reset SCSI Bus CCB 721 */ 722 case XPT_RESET_BUS: { 723 int i; 724 725 TRM_DPRINTF(" XPT_RESET_BUS \n"); 726 trm_reset(pACB); 727 pACB->ACBFlag=0; 728 for (i=0; i<500; i++) 729 DELAY(1000); 730 pccb->ccb_h.status = CAM_REQ_CMP; 731 xpt_done(pccb); 732 } 733 break; 734 /* 735 * Bus Device Reset the specified SCSI device 736 * Reset SCSI Device CCB 737 */ 738 case XPT_RESET_DEV: 739 /* 740 * Don't (yet?) support vendor 741 * specific commands. 742 */ 743 TRM_DPRINTF(" XPT_RESET_DEV \n"); 744 pccb->ccb_h.status = CAM_REQ_INVALID; 745 xpt_done(pccb); 746 break; 747 /* 748 * Terminate the I/O process 749 * Terminate I/O Process Request CCB 750 */ 751 case XPT_TERM_IO: 752 TRM_DPRINTF(" XPT_TERM_IO \n"); 753 pccb->ccb_h.status = CAM_REQ_INVALID; 754 xpt_done(pccb); 755 break; 756 /* 757 * Get/Set transfer rate/width/disconnection/tag queueing 758 * settings 759 * (GET) default/user transfer settings for the target 760 */ 761 case XPT_GET_TRAN_SETTINGS: { 762 struct ccb_trans_settings *cts = &pccb->cts; 763 int intflag; 764 struct trm_transinfo *tinfo; 765 PDCB pDCB; 766 struct ccb_trans_settings_scsi *scsi = 767 &cts->proto_specific.scsi; 768 struct ccb_trans_settings_spi *spi = 769 &cts->xport_specific.spi; 770 771 cts->protocol = PROTO_SCSI; 772 cts->protocol_version = SCSI_REV_2; 773 cts->transport = XPORT_SPI; 774 cts->transport_version = 2; 775 776 TRM_DPRINTF(" XPT_GET_TRAN_SETTINGS \n"); 777 pDCB = &pACB->DCBarray[target_id][target_lun]; 778 intflag = splcam(); 779 /* 780 * disable interrupt 781 */ 782 if (cts->type == CTS_TYPE_CURRENT_SETTINGS) { 783 /* current transfer settings */ 784 if (pDCB->tinfo.disc_tag & TRM_CUR_DISCENB) 785 spi->flags = CTS_SPI_FLAGS_DISC_ENB; 786 else 787 spi->flags = 0;/* no tag & disconnect */ 788 if (pDCB->tinfo.disc_tag & TRM_CUR_TAGENB) 789 scsi->flags |= CTS_SCSI_FLAGS_TAG_ENB; 790 tinfo = &pDCB->tinfo.current; 791 TRM_DPRINTF("CURRENT: cts->flags= %2x \n", 792 cts->flags); 793 } else { 794 /* default(user) transfer settings */ 795 if (pDCB->tinfo.disc_tag & TRM_USR_DISCENB) 796 spi->flags = CTS_SPI_FLAGS_DISC_ENB; 797 else 798 spi->flags = 0; 799 if (pDCB->tinfo.disc_tag & TRM_USR_TAGENB) 800 scsi->flags |= CTS_SCSI_FLAGS_TAG_ENB; 801 tinfo = &pDCB->tinfo.user; 802 TRM_DPRINTF("USER: cts->flags= %2x \n", 803 cts->flags); 804 } 805 spi->sync_period = tinfo->period; 806 spi->sync_offset = tinfo->offset; 807 spi->bus_width = tinfo->width; 808 TRM_DPRINTF("pDCB->SyncPeriod: %d \n", 809 pDCB->SyncPeriod); 810 TRM_DPRINTF("period: %d \n", tinfo->period); 811 TRM_DPRINTF("offset: %d \n", tinfo->offset); 812 TRM_DPRINTF("width: %d \n", tinfo->width); 813 814 splx(intflag); 815 spi->valid = CTS_SPI_VALID_SYNC_RATE | 816 CTS_SPI_VALID_SYNC_OFFSET | 817 CTS_SPI_VALID_BUS_WIDTH | 818 CTS_SPI_VALID_DISC; 819 scsi->valid = CTS_SCSI_VALID_TQ; 820 pccb->ccb_h.status = CAM_REQ_CMP; 821 xpt_done(pccb); 822 } 823 break; 824 /* 825 * Get/Set transfer rate/width/disconnection/tag queueing 826 * settings 827 * (Set) transfer rate/width negotiation settings 828 */ 829 case XPT_SET_TRAN_SETTINGS: { 830 struct ccb_trans_settings *cts = &pccb->cts; 831 u_int update_type; 832 int intflag; 833 PDCB pDCB; 834 struct ccb_trans_settings_scsi *scsi = 835 &cts->proto_specific.scsi; 836 struct ccb_trans_settings_spi *spi = 837 &cts->xport_specific.spi; 838 839 TRM_DPRINTF(" XPT_SET_TRAN_SETTINGS \n"); 840 update_type = 0; 841 if (cts->type == CTS_TYPE_CURRENT_SETTINGS) 842 update_type |= TRM_TRANS_GOAL; 843 if (cts->type == CTS_TYPE_USER_SETTINGS) 844 update_type |= TRM_TRANS_USER; 845 intflag = splcam(); 846 pDCB = &pACB->DCBarray[target_id][target_lun]; 847 848 if ((spi->valid & CTS_SPI_VALID_DISC) != 0) { 849 /*ccb disc enables */ 850 if (update_type & TRM_TRANS_GOAL) { 851 if ((spi->flags & CTS_SPI_FLAGS_DISC_ENB) 852 != 0) 853 pDCB->tinfo.disc_tag 854 |= TRM_CUR_DISCENB; 855 else 856 pDCB->tinfo.disc_tag &= 857 ~TRM_CUR_DISCENB; 858 } 859 if (update_type & TRM_TRANS_USER) { 860 if ((spi->flags & CTS_SPI_FLAGS_DISC_ENB) 861 != 0) 862 pDCB->tinfo.disc_tag 863 |= TRM_USR_DISCENB; 864 else 865 pDCB->tinfo.disc_tag &= 866 ~TRM_USR_DISCENB; 867 } 868 } 869 if ((scsi->valid & CTS_SCSI_VALID_TQ) != 0) { 870 /* if ccb tag q active */ 871 if (update_type & TRM_TRANS_GOAL) { 872 if ((scsi->flags & CTS_SCSI_FLAGS_TAG_ENB) 873 != 0) 874 pDCB->tinfo.disc_tag |= 875 TRM_CUR_TAGENB; 876 else 877 pDCB->tinfo.disc_tag &= 878 ~TRM_CUR_TAGENB; 879 } 880 if (update_type & TRM_TRANS_USER) { 881 if ((scsi->flags & CTS_SCSI_FLAGS_TAG_ENB) 882 != 0) 883 pDCB->tinfo.disc_tag |= 884 TRM_USR_TAGENB; 885 else 886 pDCB->tinfo.disc_tag &= 887 ~TRM_USR_TAGENB; 888 } 889 } 890 /* Minimum sync period factor */ 891 892 if ((spi->valid & CTS_SPI_VALID_SYNC_RATE) != 0) { 893 /* if ccb sync active */ 894 /* TRM-S1040 MinSyncPeriod = 4 clocks/byte */ 895 if ((spi->sync_period != 0) && 896 (spi->sync_period < 125)) 897 spi->sync_period = 125; 898 /* 1/(125*4) minsync 2 MByte/sec */ 899 if ((spi->valid & CTS_SPI_VALID_SYNC_OFFSET) 900 != 0) { 901 if (spi->sync_offset == 0) 902 spi->sync_period = 0; 903 /* TRM-S1040 MaxSyncOffset = 15 bytes*/ 904 if (spi->sync_offset > 15) 905 spi->sync_offset = 15; 906 } 907 } 908 if ((update_type & TRM_TRANS_USER) != 0) { 909 pDCB->tinfo.user.period = spi->sync_period; 910 pDCB->tinfo.user.offset = spi->sync_offset; 911 pDCB->tinfo.user.width = spi->bus_width; 912 } 913 if ((update_type & TRM_TRANS_GOAL) != 0) { 914 pDCB->tinfo.goal.period = spi->sync_period; 915 pDCB->tinfo.goal.offset = spi->sync_offset; 916 pDCB->tinfo.goal.width = spi->bus_width; 917 } 918 splx(intflag); 919 pccb->ccb_h.status = CAM_REQ_CMP; 920 xpt_done(pccb); 921 break; 922 } 923 /* 924 * Calculate the geometry parameters for a device give 925 * the sector size and volume size. 926 */ 927 case XPT_CALC_GEOMETRY: 928 TRM_DPRINTF(" XPT_CALC_GEOMETRY \n"); 929 cam_calc_geometry(&pccb->ccg, /*extended*/1); 930 xpt_done(pccb); 931 break; 932 case XPT_ENG_INQ: 933 TRM_DPRINTF(" XPT_ENG_INQ \n"); 934 pccb->ccb_h.status = CAM_REQ_INVALID; 935 xpt_done(pccb); 936 break; 937 /* 938 * HBA execute engine request 939 * This structure must match SCSIIO size 940 */ 941 case XPT_ENG_EXEC: 942 TRM_DPRINTF(" XPT_ENG_EXEC \n"); 943 pccb->ccb_h.status = CAM_REQ_INVALID; 944 xpt_done(pccb); 945 break; 946 /* 947 * XPT_EN_LUN = 0x30, Enable LUN as a target 948 * Target mode structures. 949 */ 950 case XPT_EN_LUN: 951 /* 952 * Don't (yet?) support vendor 953 * specific commands. 954 */ 955 TRM_DPRINTF(" XPT_EN_LUN \n"); 956 pccb->ccb_h.status = CAM_REQ_INVALID; 957 xpt_done(pccb); 958 break; 959 /* 960 * Execute target I/O request 961 */ 962 case XPT_TARGET_IO: 963 /* 964 * Don't (yet?) support vendor 965 * specific commands. 966 */ 967 TRM_DPRINTF(" XPT_TARGET_IO \n"); 968 pccb->ccb_h.status = CAM_REQ_INVALID; 969 xpt_done(pccb); 970 break; 971 /* 972 * Accept Host Target Mode CDB 973 */ 974 case XPT_ACCEPT_TARGET_IO: 975 /* 976 * Don't (yet?) support vendor 977 * specific commands. 978 */ 979 TRM_DPRINTF(" XPT_ACCEPT_TARGET_IO \n"); 980 pccb->ccb_h.status = CAM_REQ_INVALID; 981 xpt_done(pccb); 982 break; 983 /* 984 * Continue Host Target I/O Connection 985 */ 986 case XPT_CONT_TARGET_IO: 987 /* 988 * Don't (yet?) support vendor 989 * specific commands. 990 */ 991 TRM_DPRINTF(" XPT_CONT_TARGET_IO \n"); 992 pccb->ccb_h.status = CAM_REQ_INVALID; 993 xpt_done(pccb); 994 break; 995 /* 996 * Notify Host Target driver of event 997 */ 998 case XPT_IMMED_NOTIFY: 999 TRM_DPRINTF(" XPT_IMMED_NOTIFY \n"); 1000 pccb->ccb_h.status = CAM_REQ_INVALID; 1001 xpt_done(pccb); 1002 break; 1003 /* 1004 * Acknowledgement of event 1005 */ 1006 case XPT_NOTIFY_ACK: 1007 TRM_DPRINTF(" XPT_NOTIFY_ACK \n"); 1008 pccb->ccb_h.status = CAM_REQ_INVALID; 1009 xpt_done(pccb); 1010 break; 1011 /* 1012 * XPT_VUNIQUE = 0x80 1013 */ 1014 case XPT_VUNIQUE: 1015 pccb->ccb_h.status = CAM_REQ_INVALID; 1016 xpt_done(pccb); 1017 break; 1018 default: 1019 pccb->ccb_h.status = CAM_REQ_INVALID; 1020 xpt_done(pccb); 1021 break; 1022 } 1023 splx(actionflags); 1024} 1025 1026static void 1027trm_poll(struct cam_sim *psim) 1028{ 1029 trm_Interrupt(cam_sim_softc(psim)); 1030} 1031 1032static void 1033trm_ResetDevParam(PACB pACB) 1034{ 1035 PDCB pDCB, pdcb; 1036 PNVRAMTYPE pEEpromBuf; 1037 u_int8_t PeriodIndex; 1038 1039 pDCB = pACB->pLinkDCB; 1040 if (pDCB == NULL) 1041 return; 1042 pdcb = pDCB; 1043 do { 1044 pDCB->SyncMode &= ~(SYNC_NEGO_DONE+ WIDE_NEGO_DONE); 1045 pDCB->SyncPeriod = 0; 1046 pDCB->SyncOffset = 0; 1047 pEEpromBuf = &trm_eepromBuf[pACB->AdapterUnit]; 1048 pDCB->DevMode = 1049 pEEpromBuf->NvramTarget[pDCB->TargetID].NvmTarCfg0; 1050 pDCB->AdpMode = pEEpromBuf->NvramChannelCfg; 1051 PeriodIndex = 1052 pEEpromBuf->NvramTarget[pDCB->TargetID].NvmTarPeriod & 0x07; 1053 if (pACB->AdaptType == 1) /* is U2? */ 1054 pDCB->MaxNegoPeriod = dc395u2x_clock_period[PeriodIndex]; 1055 else 1056 pDCB->MaxNegoPeriod = dc395x_clock_period[PeriodIndex]; 1057 if ((pDCB->DevMode & NTC_DO_WIDE_NEGO) && 1058 (pACB->Config & HCC_WIDE_CARD)) 1059 pDCB->SyncMode |= WIDE_NEGO_ENABLE; 1060 pDCB = pDCB->pNextDCB; 1061 } 1062 while (pdcb != pDCB); 1063} 1064 1065static void 1066trm_RecoverSRB(PACB pACB) 1067{ 1068 PDCB pDCB, pdcb; 1069 PSRB psrb, psrb2; 1070 u_int16_t cnt, i; 1071 1072 pDCB = pACB->pLinkDCB; 1073 if (pDCB == NULL) 1074 return; 1075 pdcb = pDCB; 1076 do { 1077 cnt = pdcb->GoingSRBCnt; 1078 psrb = pdcb->pGoingSRB; 1079 for (i = 0; i < cnt; i++) { 1080 psrb2 = psrb; 1081 psrb = psrb->pNextSRB; 1082 if (pdcb->pWaitingSRB) { 1083 psrb2->pNextSRB = pdcb->pWaitingSRB; 1084 pdcb->pWaitingSRB = psrb2; 1085 } else { 1086 pdcb->pWaitingSRB = psrb2; 1087 pdcb->pWaitingLastSRB = psrb2; 1088 psrb2->pNextSRB = NULL; 1089 } 1090 } 1091 pdcb->GoingSRBCnt = 0; 1092 pdcb->pGoingSRB = NULL; 1093 pdcb = pdcb->pNextDCB; 1094 } 1095 while (pdcb != pDCB); 1096} 1097 1098static void 1099trm_reset(PACB pACB) 1100{ 1101 int intflag; 1102 u_int16_t i; 1103 1104 TRM_DPRINTF("trm: RESET"); 1105 intflag = splcam(); 1106 trm_reg_write8(0x00, TRMREG_DMA_INTEN); 1107 trm_reg_write8(0x00, TRMREG_SCSI_INTEN); 1108 1109 trm_ResetSCSIBus(pACB); 1110 for (i = 0; i < 500; i++) 1111 DELAY(1000); 1112 trm_reg_write8(0x7F, TRMREG_SCSI_INTEN); 1113 /* Enable DMA interrupt */ 1114 trm_reg_write8(EN_SCSIINTR, TRMREG_DMA_INTEN); 1115 /* Clear DMA FIFO */ 1116 trm_reg_write8(CLRXFIFO, TRMREG_DMA_CONTROL); 1117 /* Clear SCSI FIFO */ 1118 trm_reg_write16(DO_CLRFIFO,TRMREG_SCSI_CONTROL); 1119 trm_ResetDevParam(pACB); 1120 trm_DoingSRB_Done(pACB); 1121 pACB->pActiveDCB = NULL; 1122 pACB->ACBFlag = 0;/* RESET_DETECT, RESET_DONE ,RESET_DEV */ 1123 trm_DoWaitingSRB(pACB); 1124 /* Tell the XPT layer that a bus reset occured */ 1125 if (pACB->ppath != NULL) 1126 xpt_async(AC_BUS_RESET, pACB->ppath, NULL); 1127 splx(intflag); 1128 return; 1129} 1130 1131static u_int16_t 1132trm_StartSCSI(PACB pACB, PDCB pDCB, PSRB pSRB) 1133{ 1134 u_int16_t return_code; 1135 u_int8_t scsicommand, i,command,identify_message; 1136 u_int8_t * ptr; 1137 union ccb *pccb; 1138 struct ccb_scsiio *pcsio; 1139 1140 pccb = pSRB->pccb; 1141 pcsio = &pccb->csio; 1142 1143 trm_reg_write8(pACB->AdaptSCSIID, TRMREG_SCSI_HOSTID); 1144 trm_reg_write8(pDCB->TargetID, TRMREG_SCSI_TARGETID); 1145 trm_reg_write8(pDCB->SyncPeriod, TRMREG_SCSI_SYNC); 1146 trm_reg_write8(pDCB->SyncOffset, TRMREG_SCSI_OFFSET); 1147 pSRB->ScsiPhase = PH_BUS_FREE;/* initial phase */ 1148 /* Flush FIFO */ 1149 trm_reg_write16(DO_CLRFIFO, TRMREG_SCSI_CONTROL); 1150 1151 identify_message = pDCB->IdentifyMsg; 1152 1153 if ((pSRB->CmdBlock[0] == INQUIRY) || 1154 (pSRB->CmdBlock[0] == REQUEST_SENSE) || 1155 (pSRB->SRBFlag & AUTO_REQSENSE)) { 1156 if (((pDCB->SyncMode & WIDE_NEGO_ENABLE) && 1157 !(pDCB->SyncMode & WIDE_NEGO_DONE)) 1158 || ((pDCB->SyncMode & SYNC_NEGO_ENABLE) && 1159 !(pDCB->SyncMode & SYNC_NEGO_DONE))) { 1160 if (!(pDCB->IdentifyMsg & 7) || 1161 (pSRB->CmdBlock[0] != INQUIRY)) { 1162 scsicommand = SCMD_SEL_ATNSTOP; 1163 pSRB->SRBState = SRB_MSGOUT; 1164 goto polling; 1165 } 1166 } 1167 /* 1168 * Send identify message 1169 */ 1170 trm_reg_write8((identify_message & 0xBF) ,TRMREG_SCSI_FIFO); 1171 scsicommand = SCMD_SEL_ATN; 1172 pSRB->SRBState = SRB_START_; 1173 } else { 1174 /* not inquiry,request sense,auto request sense */ 1175 /* 1176 * Send identify message 1177 */ 1178 trm_reg_write8(identify_message,TRMREG_SCSI_FIFO); 1179 scsicommand = SCMD_SEL_ATN; 1180 pSRB->SRBState = SRB_START_; 1181 if (pDCB->SyncMode & EN_TAG_QUEUING) { 1182 /* Send Tag message */ 1183 trm_reg_write8(MSG_SIMPLE_QTAG, TRMREG_SCSI_FIFO); 1184 trm_reg_write8(pSRB->TagNumber, TRMREG_SCSI_FIFO); 1185 scsicommand = SCMD_SEL_ATN3; 1186 } 1187 } 1188polling: 1189 /* 1190 * Send CDB ..command block ......... 1191 */ 1192 if (pSRB->SRBFlag & AUTO_REQSENSE) { 1193 trm_reg_write8(REQUEST_SENSE, TRMREG_SCSI_FIFO); 1194 trm_reg_write8((pDCB->IdentifyMsg << 5), TRMREG_SCSI_FIFO); 1195 trm_reg_write8(0, TRMREG_SCSI_FIFO); 1196 trm_reg_write8(0, TRMREG_SCSI_FIFO); 1197 trm_reg_write8(pcsio->sense_len, TRMREG_SCSI_FIFO); 1198 trm_reg_write8(0, TRMREG_SCSI_FIFO); 1199 } else { 1200 ptr = (u_int8_t *) pSRB->CmdBlock; 1201 for (i = 0; i < pSRB->ScsiCmdLen ; i++) { 1202 command = *ptr++; 1203 trm_reg_write8(command,TRMREG_SCSI_FIFO); 1204 } 1205 } 1206 if (trm_reg_read16(TRMREG_SCSI_STATUS) & SCSIINTERRUPT) { 1207 /* 1208 * If trm_StartSCSI return 1 : 1209 * current interrupt status is interrupt disreenable 1210 * It's said that SCSI processor has more one SRB need to do, 1211 * SCSI processor has been occupied by one SRB. 1212 */ 1213 pSRB->SRBState = SRB_READY; 1214 return_code = 1; 1215 } else { 1216 /* 1217 * If trm_StartSCSI return 0 : 1218 * current interrupt status is interrupt enable 1219 * It's said that SCSI processor is unoccupied 1220 */ 1221 pSRB->ScsiPhase = SCSI_NOP1; /* SCSI bus free Phase */ 1222 pACB->pActiveDCB = pDCB; 1223 pDCB->pActiveSRB = pSRB; 1224 return_code = 0; 1225 trm_reg_write16(DO_DATALATCH | DO_HWRESELECT, 1226 TRMREG_SCSI_CONTROL);/* it's important for atn stop*/ 1227 /* 1228 * SCSI cammand 1229 */ 1230 trm_reg_write8(scsicommand,TRMREG_SCSI_COMMAND); 1231 } 1232 return (return_code); 1233} 1234 1235static void 1236trm_Interrupt(vpACB) 1237void *vpACB; 1238{ 1239 PACB pACB; 1240 PDCB pDCB; 1241 PSRB pSRB; 1242 u_int16_t phase; 1243 void (*stateV)(PACB, PSRB, u_int16_t *); 1244 u_int16_t scsi_status=0; 1245 u_int8_t scsi_intstatus; 1246 1247 pACB = vpACB; 1248 1249 scsi_status = trm_reg_read16(TRMREG_SCSI_STATUS); 1250 if (!(scsi_status & SCSIINTERRUPT)) { 1251 TRM_DPRINTF("trm_Interrupt: TRMREG_SCSI_STATUS scsi_status = NULL ,return......"); 1252 return; 1253 } 1254 TRM_DPRINTF("scsi_status=%2x,",scsi_status); 1255 1256 scsi_intstatus = trm_reg_read8(TRMREG_SCSI_INTSTATUS); 1257 1258 TRM_DPRINTF("scsi_intstatus=%2x,",scsi_intstatus); 1259 1260 if (scsi_intstatus & (INT_SELTIMEOUT | INT_DISCONNECT)) { 1261 trm_Disconnect(pACB); 1262 return; 1263 } 1264 1265 if (scsi_intstatus & INT_RESELECTED) { 1266 trm_Reselect(pACB); 1267 return; 1268 } 1269 if (scsi_intstatus & INT_SCSIRESET) { 1270 trm_ScsiRstDetect(pACB); 1271 return; 1272 } 1273 1274 if (scsi_intstatus & (INT_BUSSERVICE | INT_CMDDONE)) { 1275 pDCB = pACB->pActiveDCB; 1276 KASSERT(pDCB != NULL, ("no active DCB")); 1277 pSRB = pDCB->pActiveSRB; 1278 if (pDCB->DCBFlag & ABORT_DEV_) 1279 trm_EnableMsgOutAbort1(pACB, pSRB); 1280 phase = (u_int16_t) pSRB->ScsiPhase; /* phase: */ 1281 stateV = (void *) trm_SCSI_phase0[phase]; 1282 stateV(pACB, pSRB, &scsi_status); 1283 pSRB->ScsiPhase = scsi_status & PHASEMASK; 1284 /* phase:0,1,2,3,4,5,6,7 */ 1285 phase = (u_int16_t) scsi_status & PHASEMASK; 1286 stateV = (void *) trm_SCSI_phase1[phase]; 1287 stateV(pACB, pSRB, &scsi_status); 1288 } 1289} 1290 1291static void 1292trm_MsgOutPhase0(PACB pACB, PSRB pSRB, u_int16_t *pscsi_status) 1293{ 1294 1295 if (pSRB->SRBState & (SRB_UNEXPECT_RESEL+SRB_ABORT_SENT)) 1296 *pscsi_status = PH_BUS_FREE; 1297 /*.. initial phase*/ 1298} 1299 1300static void 1301trm_MsgOutPhase1(PACB pACB, PSRB pSRB, u_int16_t *pscsi_status) 1302{ 1303 u_int8_t bval; 1304 u_int16_t i, cnt; 1305 u_int8_t * ptr; 1306 PDCB pDCB; 1307 1308 trm_reg_write16(DO_CLRFIFO, TRMREG_SCSI_CONTROL); 1309 pDCB = pACB->pActiveDCB; 1310 if (!(pSRB->SRBState & SRB_MSGOUT)) { 1311 cnt = pSRB->MsgCnt; 1312 if (cnt) { 1313 ptr = (u_int8_t *) pSRB->MsgOutBuf; 1314 for (i = 0; i < cnt; i++) { 1315 trm_reg_write8(*ptr, TRMREG_SCSI_FIFO); 1316 ptr++; 1317 } 1318 pSRB->MsgCnt = 0; 1319 if ((pDCB->DCBFlag & ABORT_DEV_) && 1320 (pSRB->MsgOutBuf[0] == MSG_ABORT)) { 1321 pSRB->SRBState = SRB_ABORT_SENT; 1322 } 1323 } else { 1324 bval = MSG_ABORT; 1325 if ((pSRB->CmdBlock[0] == INQUIRY) || 1326 (pSRB->CmdBlock[0] == REQUEST_SENSE) || 1327 (pSRB->SRBFlag & AUTO_REQSENSE)) { 1328 if (pDCB->SyncMode & SYNC_NEGO_ENABLE) { 1329 goto mop1; 1330 } 1331 } 1332 trm_reg_write8(bval, TRMREG_SCSI_FIFO); 1333 } 1334 } else { 1335mop1: /* message out phase */ 1336 if (!(pSRB->SRBState & SRB_DO_WIDE_NEGO) 1337 && (pDCB->SyncMode & WIDE_NEGO_ENABLE)) { 1338 /* 1339 * WIDE DATA TRANSFER REQUEST code (03h) 1340 */ 1341 pDCB->SyncMode &= ~(SYNC_NEGO_DONE | EN_ATN_STOP); 1342 trm_reg_write8((pDCB->IdentifyMsg & 0xBF), 1343 TRMREG_SCSI_FIFO); 1344 trm_reg_write8(MSG_EXTENDED,TRMREG_SCSI_FIFO); 1345 /* (01h) */ 1346 trm_reg_write8(2,TRMREG_SCSI_FIFO); 1347 /* Message length (02h) */ 1348 trm_reg_write8(3,TRMREG_SCSI_FIFO); 1349 /* wide data xfer (03h) */ 1350 trm_reg_write8(1,TRMREG_SCSI_FIFO); 1351 /* width:0(8bit),1(16bit),2(32bit) */ 1352 pSRB->SRBState |= SRB_DO_WIDE_NEGO; 1353 } else if (!(pSRB->SRBState & SRB_DO_SYNC_NEGO) 1354 && (pDCB->SyncMode & SYNC_NEGO_ENABLE)) { 1355 /* 1356 * SYNCHRONOUS DATA TRANSFER REQUEST code (01h) 1357 */ 1358 if (!(pDCB->SyncMode & WIDE_NEGO_DONE)) 1359 trm_reg_write8((pDCB->IdentifyMsg & 0xBF), 1360 TRMREG_SCSI_FIFO); 1361 trm_reg_write8(MSG_EXTENDED,TRMREG_SCSI_FIFO); 1362 /* (01h) */ 1363 trm_reg_write8(3,TRMREG_SCSI_FIFO); 1364 /* Message length (03h) */ 1365 trm_reg_write8(1,TRMREG_SCSI_FIFO); 1366 /* SYNCHRONOUS DATA TRANSFER REQUEST code (01h) */ 1367 trm_reg_write8(pDCB->MaxNegoPeriod,TRMREG_SCSI_FIFO); 1368 /* Transfer peeriod factor */ 1369 trm_reg_write8((pACB->AdaptType == 1) ? 31 : 15, 1370 TRMREG_SCSI_FIFO); 1371 /* REQ/ACK offset */ 1372 pSRB->SRBState |= SRB_DO_SYNC_NEGO; 1373 } 1374 } 1375 trm_reg_write16(DO_DATALATCH, TRMREG_SCSI_CONTROL); 1376 /* it's important for atn stop */ 1377 /* 1378 * SCSI cammand 1379 */ 1380 trm_reg_write8(SCMD_FIFO_OUT, TRMREG_SCSI_COMMAND); 1381} 1382 1383static void 1384trm_CommandPhase0(PACB pACB, PSRB pSRB, u_int16_t *pscsi_status) 1385{ 1386 1387} 1388 1389static void 1390trm_CommandPhase1(PACB pACB, PSRB pSRB, u_int16_t *pscsi_status) 1391{ 1392 PDCB pDCB; 1393 u_int8_t * ptr; 1394 u_int16_t i, cnt; 1395 union ccb *pccb; 1396 struct ccb_scsiio *pcsio; 1397 1398 pccb = pSRB->pccb; 1399 pcsio = &pccb->csio; 1400 1401 trm_reg_write16(DO_CLRATN | DO_CLRFIFO , TRMREG_SCSI_CONTROL); 1402 if (!(pSRB->SRBFlag & AUTO_REQSENSE)) { 1403 cnt = (u_int16_t) pSRB->ScsiCmdLen; 1404 ptr = (u_int8_t *) pSRB->CmdBlock; 1405 for (i = 0; i < cnt; i++) { 1406 trm_reg_write8(*ptr, TRMREG_SCSI_FIFO); 1407 ptr++; 1408 } 1409 } else { 1410 trm_reg_write8(REQUEST_SENSE, TRMREG_SCSI_FIFO); 1411 pDCB = pACB->pActiveDCB; 1412 /* target id */ 1413 trm_reg_write8((pDCB->IdentifyMsg << 5), TRMREG_SCSI_FIFO); 1414 trm_reg_write8(0, TRMREG_SCSI_FIFO); 1415 trm_reg_write8(0, TRMREG_SCSI_FIFO); 1416 /* sizeof(struct scsi_sense_data) */ 1417 trm_reg_write8(pcsio->sense_len, TRMREG_SCSI_FIFO); 1418 trm_reg_write8(0, TRMREG_SCSI_FIFO); 1419 } 1420 pSRB->SRBState = SRB_COMMAND; 1421 trm_reg_write16(DO_DATALATCH, TRMREG_SCSI_CONTROL); 1422 /* it's important for atn stop*/ 1423 /* 1424 * SCSI cammand 1425 */ 1426 trm_reg_write8(SCMD_FIFO_OUT, TRMREG_SCSI_COMMAND); 1427} 1428 1429static void 1430trm_DataOutPhase0(PACB pACB, PSRB pSRB, u_int16_t *pscsi_status) 1431{ 1432 PDCB pDCB; 1433 u_int8_t TempDMAstatus,SGIndexTemp; 1434 u_int16_t scsi_status; 1435 PSEG pseg; 1436 u_long TempSRBXferredLength,dLeftCounter=0; 1437 1438 pDCB = pSRB->pSRBDCB; 1439 scsi_status = *pscsi_status; 1440 1441 if (!(pSRB->SRBState & SRB_XFERPAD)) { 1442 if (scsi_status & PARITYERROR) 1443 pSRB->SRBStatus |= PARITY_ERROR; 1444 if (!(scsi_status & SCSIXFERDONE)) { 1445 /* 1446 * when data transfer from DMA FIFO to SCSI FIFO 1447 * if there was some data left in SCSI FIFO 1448 */ 1449 dLeftCounter = (u_long) 1450 (trm_reg_read8(TRMREG_SCSI_FIFOCNT) & 0x3F); 1451 if (pDCB->SyncPeriod & WIDE_SYNC) { 1452 /* 1453 * if WIDE scsi SCSI FIFOCNT unit is word 1454 * so need to * 2 1455 */ 1456 dLeftCounter <<= 1; 1457 } 1458 } 1459 /* 1460 * caculate all the residue data that not yet tranfered 1461 * SCSI transfer counter + left in SCSI FIFO data 1462 * 1463 * .....TRM_SCSI_COUNTER (24bits) 1464 * The counter always decrement by one for every SCSI byte 1465 *transfer. 1466 * .....TRM_SCSI_FIFOCNT (5bits) 1467 * The counter is SCSI FIFO offset counter 1468 */ 1469 dLeftCounter += trm_reg_read32(TRMREG_SCSI_COUNTER); 1470 if (dLeftCounter == 1) { 1471 dLeftCounter = 0; 1472 trm_reg_write16(DO_CLRFIFO,TRMREG_SCSI_CONTROL); 1473 } 1474 if ((dLeftCounter == 0) || 1475 (scsi_status & SCSIXFERCNT_2_ZERO)) { 1476 TempDMAstatus = trm_reg_read8(TRMREG_DMA_STATUS); 1477 while (!(TempDMAstatus & DMAXFERCOMP)) { 1478 TempDMAstatus = 1479 trm_reg_read8(TRMREG_DMA_STATUS); 1480 } 1481 pSRB->SRBTotalXferLength = 0; 1482 } else { 1483 /* Update SG list */ 1484 /* 1485 * if transfer not yet complete 1486 * there were some data residue in SCSI FIFO or 1487 * SCSI transfer counter not empty 1488 */ 1489 if (pSRB->SRBTotalXferLength != dLeftCounter) { 1490 /* 1491 * data that had transferred length 1492 */ 1493 TempSRBXferredLength = 1494 pSRB->SRBTotalXferLength - dLeftCounter; 1495 /* 1496 * next time to be transferred length 1497 */ 1498 pSRB->SRBTotalXferLength = dLeftCounter; 1499 /* 1500 * parsing from last time disconnect SRBSGIndex 1501 */ 1502 pseg = 1503 pSRB->pSRBSGL + pSRB->SRBSGIndex; 1504 for (SGIndexTemp = pSRB->SRBSGIndex; 1505 SGIndexTemp < pSRB->SRBSGCount; 1506 SGIndexTemp++) { 1507 /* 1508 * find last time which SG transfer be 1509 * disconnect 1510 */ 1511 if (TempSRBXferredLength >= 1512 pseg->length) 1513 TempSRBXferredLength -= 1514 pseg->length; 1515 else { 1516 /* 1517 * update last time disconnected SG 1518 * list 1519 */ 1520 pseg->length -= 1521 TempSRBXferredLength; 1522 /* residue data length */ 1523 pseg->address += 1524 TempSRBXferredLength; 1525 /* residue data pointer */ 1526 pSRB->SRBSGIndex = SGIndexTemp; 1527 break; 1528 } 1529 pseg++; 1530 } 1531 } 1532 } 1533 } 1534 trm_reg_write8(STOPDMAXFER ,TRMREG_DMA_CONTROL); 1535} 1536 1537 1538static void 1539trm_DataOutPhase1(PACB pACB, PSRB pSRB, u_int16_t *pscsi_status) 1540{ 1541 u_int16_t ioDir; 1542 /* 1543 * do prepare befor transfer when data out phase 1544 */ 1545 1546 ioDir = XFERDATAOUT; 1547 trm_DataIO_transfer(pACB, pSRB, ioDir); 1548} 1549 1550static void 1551trm_DataInPhase0(PACB pACB, PSRB pSRB, u_int16_t *pscsi_status) 1552{ 1553 u_int8_t TempDMAstatus, SGIndexTemp; 1554 u_int16_t scsi_status; 1555 PSEG pseg; 1556 u_long TempSRBXferredLength,dLeftCounter = 0; 1557 1558 scsi_status = *pscsi_status; 1559 if (!(pSRB->SRBState & SRB_XFERPAD)) { 1560 if (scsi_status & PARITYERROR) 1561 pSRB->SRBStatus |= PARITY_ERROR; 1562 dLeftCounter += trm_reg_read32(TRMREG_SCSI_COUNTER); 1563 if ((dLeftCounter == 0) || (scsi_status & SCSIXFERCNT_2_ZERO)) { 1564 TempDMAstatus = trm_reg_read8(TRMREG_DMA_STATUS); 1565 while (!(TempDMAstatus & DMAXFERCOMP)) 1566 TempDMAstatus = trm_reg_read8(TRMREG_DMA_STATUS); 1567 pSRB->SRBTotalXferLength = 0; 1568 } else { 1569 /* 1570 * parsing the case: 1571 * when a transfer not yet complete 1572 * but be disconnected by uper layer 1573 * if transfer not yet complete 1574 * there were some data residue in SCSI FIFO or 1575 * SCSI transfer counter not empty 1576 */ 1577 if (pSRB->SRBTotalXferLength != dLeftCounter) { 1578 /* 1579 * data that had transferred length 1580 */ 1581 TempSRBXferredLength = 1582 pSRB->SRBTotalXferLength - dLeftCounter; 1583 /* 1584 * next time to be transferred length 1585 */ 1586 pSRB->SRBTotalXferLength = dLeftCounter; 1587 /* 1588 * parsing from last time disconnect SRBSGIndex 1589 */ 1590 pseg = pSRB->pSRBSGL + pSRB->SRBSGIndex; 1591 for (SGIndexTemp = pSRB->SRBSGIndex; 1592 SGIndexTemp < pSRB->SRBSGCount; 1593 SGIndexTemp++) { 1594 /* 1595 * find last time which SG transfer be disconnect 1596 */ 1597 if (TempSRBXferredLength >= pseg->length) 1598 TempSRBXferredLength -= pseg->length; 1599 else { 1600 /* 1601 * update last time disconnected SG list 1602 */ 1603 pseg->length -= TempSRBXferredLength; 1604 /* residue data length */ 1605 pseg->address += TempSRBXferredLength; 1606 /* residue data pointer */ 1607 pSRB->SRBSGIndex = SGIndexTemp; 1608 break; 1609 } 1610 pseg++; 1611 } 1612 } 1613 } 1614 } 1615} 1616 1617static void 1618trm_DataInPhase1(PACB pACB, PSRB pSRB, u_int16_t *pscsi_status) 1619{ 1620 u_int16_t ioDir; 1621 /* 1622 * do prepare befor transfer when data in phase 1623 */ 1624 1625 ioDir = XFERDATAIN; 1626 trm_DataIO_transfer(pACB, pSRB, ioDir); 1627} 1628 1629static void 1630trm_DataIO_transfer(PACB pACB, PSRB pSRB, u_int16_t ioDir) 1631{ 1632 u_int8_t bval; 1633 PDCB pDCB; 1634 1635 pDCB = pSRB->pSRBDCB; 1636 if (pSRB->SRBSGIndex < pSRB->SRBSGCount) { 1637 if (pSRB->SRBTotalXferLength != 0) { 1638 /* 1639 * load what physical address of Scatter/Gather list 1640 table want to be transfer 1641 */ 1642 TRM_DPRINTF(" SG->address=%8x \n",pSRB->pSRBSGL->address); 1643 TRM_DPRINTF(" SG->length=%8x \n",pSRB->pSRBSGL->length); 1644 TRM_DPRINTF(" pDCB->SyncPeriod=%x \n",pDCB->SyncPeriod); 1645 TRM_DPRINTF(" pSRB->pSRBSGL=%8x \n",(unsigned int)pSRB->pSRBSGL); 1646 TRM_DPRINTF(" pSRB->SRBSGPhyAddr=%8x \n",pSRB->SRBSGPhyAddr); 1647 TRM_DPRINTF(" pSRB->SRBSGIndex=%d \n",pSRB->SRBSGIndex); 1648 TRM_DPRINTF(" pSRB->SRBSGCount=%d \n",pSRB->SRBSGCount); 1649 TRM_DPRINTF(" pSRB->SRBTotalXferLength=%d \n",pSRB->SRBTotalXferLength); 1650 1651 pSRB->SRBState = SRB_DATA_XFER; 1652 trm_reg_write32(0, TRMREG_DMA_XHIGHADDR); 1653 trm_reg_write32( 1654 (pSRB->SRBSGPhyAddr + 1655 ((u_long)pSRB->SRBSGIndex << 3)), 1656 TRMREG_DMA_XLOWADDR); 1657 /* 1658 * load how many bytes in the Scatter/Gather 1659 * list table 1660 */ 1661 trm_reg_write32( 1662 ((u_long)(pSRB->SRBSGCount - pSRB->SRBSGIndex) << 3), 1663 TRMREG_DMA_XCNT); 1664 /* 1665 * load total transfer length (24bits) max value 1666 * 16Mbyte 1667 */ 1668 trm_reg_write32(pSRB->SRBTotalXferLength, 1669 TRMREG_SCSI_COUNTER); 1670 /* Start DMA transfer */ 1671 trm_reg_write16(ioDir, TRMREG_DMA_COMMAND); 1672 /* Start SCSI transfer */ 1673 trm_reg_write16(DO_DATALATCH, TRMREG_SCSI_CONTROL); 1674 /* it's important for atn stop */ 1675 /* 1676 * SCSI cammand 1677 */ 1678 bval = (ioDir == XFERDATAOUT) ? 1679 SCMD_DMA_OUT : SCMD_DMA_IN; 1680 trm_reg_write8(bval, TRMREG_SCSI_COMMAND); 1681 } else { 1682 /* xfer pad */ 1683 if (pSRB->SRBSGCount) { 1684 pSRB->AdaptStatus = H_OVER_UNDER_RUN; 1685 pSRB->SRBStatus |= OVER_RUN; 1686 } 1687 if (pDCB->SyncPeriod & WIDE_SYNC) 1688 trm_reg_write32(2,TRMREG_SCSI_COUNTER); 1689 else 1690 trm_reg_write32(1,TRMREG_SCSI_COUNTER); 1691 if (ioDir == XFERDATAOUT) 1692 trm_reg_write16(0, TRMREG_SCSI_FIFO); 1693 else 1694 trm_reg_read16(TRMREG_SCSI_FIFO); 1695 pSRB->SRBState |= SRB_XFERPAD; 1696 trm_reg_write16(DO_DATALATCH, TRMREG_SCSI_CONTROL); 1697 /* it's important for atn stop */ 1698 /* 1699 * SCSI cammand 1700 */ 1701 bval = (ioDir == XFERDATAOUT) ? 1702 SCMD_FIFO_OUT : SCMD_FIFO_IN; 1703 trm_reg_write8(bval, TRMREG_SCSI_COMMAND); 1704 } 1705 } 1706} 1707 1708static void 1709trm_StatusPhase0(PACB pACB, PSRB pSRB, u_int16_t *pscsi_status) 1710{ 1711 1712 pSRB->TargetStatus = trm_reg_read8(TRMREG_SCSI_FIFO); 1713 pSRB->SRBState = SRB_COMPLETED; 1714 *pscsi_status = PH_BUS_FREE; 1715 /*.. initial phase*/ 1716 trm_reg_write16(DO_DATALATCH, TRMREG_SCSI_CONTROL); 1717 /* it's important for atn stop */ 1718 /* 1719 * SCSI cammand 1720 */ 1721 trm_reg_write8(SCMD_MSGACCEPT, TRMREG_SCSI_COMMAND); 1722} 1723 1724 1725 1726static void 1727trm_StatusPhase1(PACB pACB, PSRB pSRB, u_int16_t *pscsi_status) 1728{ 1729 1730 if (trm_reg_read16(TRMREG_DMA_COMMAND) & 0x0001) { 1731 if (!(trm_reg_read8(TRMREG_SCSI_FIFOCNT) & 0x40)) 1732 trm_reg_write16(DO_CLRFIFO, TRMREG_SCSI_CONTROL); 1733 if (!(trm_reg_read16(TRMREG_DMA_FIFOCNT) & 0x8000)) 1734 trm_reg_write8(CLRXFIFO, TRMREG_DMA_CONTROL); 1735 } else { 1736 if (!(trm_reg_read16(TRMREG_DMA_FIFOCNT) & 0x8000)) 1737 trm_reg_write8(CLRXFIFO, TRMREG_DMA_CONTROL); 1738 if (!(trm_reg_read8(TRMREG_SCSI_FIFOCNT) & 0x40)) 1739 trm_reg_write16(DO_CLRFIFO, TRMREG_SCSI_CONTROL); 1740 } 1741 pSRB->SRBState = SRB_STATUS; 1742 trm_reg_write16(DO_DATALATCH, TRMREG_SCSI_CONTROL); 1743 /* it's important for atn stop */ 1744 /* 1745 * SCSI cammand 1746 */ 1747 trm_reg_write8(SCMD_COMP, TRMREG_SCSI_COMMAND); 1748} 1749 1750/* 1751 *scsiiom 1752 * trm_MsgInPhase0: one of trm_SCSI_phase0[] vectors 1753 * stateV = (void *) trm_SCSI_phase0[phase] 1754 * if phase =7 1755 * extended message codes: 1756 * 1757 * code description 1758 * 1759 * 02h Reserved 1760 * 00h MODIFY DATA POINTER 1761 * 01h SYNCHRONOUS DATA TRANSFER REQUEST 1762 * 03h WIDE DATA TRANSFER REQUEST 1763 * 04h - 7Fh Reserved 1764 * 80h - FFh Vendor specific 1765 * 1766 */ 1767 1768static void 1769trm_MsgInPhase0(PACB pACB, PSRB pSRB, u_int16_t *pscsi_status) 1770{ 1771 u_int8_t message_in_code,bIndex,message_in_tag_id; 1772 PDCB pDCB; 1773 PSRB pSRBTemp; 1774 1775 pDCB = pACB->pActiveDCB; 1776 1777 message_in_code = trm_reg_read8(TRMREG_SCSI_FIFO); 1778 if (!(pSRB->SRBState & SRB_EXTEND_MSGIN)) { 1779 if (message_in_code == MSG_DISCONNECT) { 1780 pSRB->SRBState = SRB_DISCONNECT; 1781 *pscsi_status = PH_BUS_FREE; /* .. initial phase */ 1782 /* it's important for atn stop */ 1783 trm_reg_write16(DO_DATALATCH, TRMREG_SCSI_CONTROL); 1784 /* 1785 * SCSI command 1786 */ 1787 trm_reg_write8(SCMD_MSGACCEPT, TRMREG_SCSI_COMMAND); 1788 return; 1789 } else if (message_in_code == MSG_SAVE_PTR) { 1790 *pscsi_status = PH_BUS_FREE; /* .. initial phase */ 1791 /* it's important for atn stop */ 1792 trm_reg_write16(DO_DATALATCH, TRMREG_SCSI_CONTROL); 1793 /* 1794 * SCSI command 1795 */ 1796 trm_reg_write8(SCMD_MSGACCEPT, TRMREG_SCSI_COMMAND); 1797 return; 1798 } else if ((message_in_code == MSG_EXTENDED) || 1799 ((message_in_code >= MSG_SIMPLE_QTAG) && 1800 (message_in_code <= MSG_ORDER_QTAG))) { 1801 pSRB->SRBState |= SRB_EXTEND_MSGIN; 1802 pSRB->MsgInBuf[0] = message_in_code; 1803 /* extended message (01h) */ 1804 pSRB->MsgCnt = 1; 1805 pSRB->pMsgPtr = &pSRB->MsgInBuf[1]; 1806 /* extended message length (n) */ 1807 *pscsi_status = PH_BUS_FREE; /* .. initial phase */ 1808 /* it's important for atn stop */ 1809 trm_reg_write16(DO_DATALATCH, TRMREG_SCSI_CONTROL); 1810 /* 1811 * SCSI command 1812 */ 1813 trm_reg_write8(SCMD_MSGACCEPT, TRMREG_SCSI_COMMAND); 1814 return; 1815 } else if (message_in_code == MSG_REJECT_) { 1816 /* Reject message */ 1817 if (pDCB->SyncMode & WIDE_NEGO_ENABLE) { 1818 /* do wide nego reject */ 1819 pDCB = pSRB->pSRBDCB; 1820 pDCB->SyncMode |= WIDE_NEGO_DONE; 1821 pDCB->SyncMode &= ~(SYNC_NEGO_DONE | 1822 EN_ATN_STOP | WIDE_NEGO_ENABLE); 1823 pSRB->SRBState &= ~(SRB_DO_WIDE_NEGO+SRB_MSGIN); 1824 if ((pDCB->SyncMode & SYNC_NEGO_ENABLE) 1825 && !(pDCB->SyncMode & SYNC_NEGO_DONE)) { 1826 /* Set ATN, in case ATN was clear */ 1827 pSRB->SRBState |= SRB_MSGOUT; 1828 trm_reg_write16( 1829 DO_SETATN, 1830 TRMREG_SCSI_CONTROL); 1831 } else { 1832 /* Clear ATN */ 1833 trm_reg_write16( 1834 DO_CLRATN, 1835 TRMREG_SCSI_CONTROL); 1836 } 1837 } else if (pDCB->SyncMode & SYNC_NEGO_ENABLE) { 1838 /* do sync nego reject */ 1839 trm_reg_write16(DO_CLRATN,TRMREG_SCSI_CONTROL); 1840 if (pSRB->SRBState & SRB_DO_SYNC_NEGO) { 1841 pDCB = pSRB->pSRBDCB; 1842 pDCB->SyncMode &= 1843 ~(SYNC_NEGO_ENABLE+SYNC_NEGO_DONE); 1844 pDCB->SyncPeriod = 0; 1845 pDCB->SyncOffset = 0; 1846 /* 1847 * 1848 * program SCSI control register 1849 * 1850 */ 1851 trm_reg_write8(pDCB->SyncPeriod, 1852 TRMREG_SCSI_SYNC); 1853 trm_reg_write8(pDCB->SyncOffset, 1854 TRMREG_SCSI_OFFSET); 1855 trm_SetXferRate(pACB,pSRB,pDCB); 1856 } 1857 } 1858 *pscsi_status = PH_BUS_FREE; /* .. initial phase */ 1859 /* it's important for atn stop */ 1860 trm_reg_write16(DO_DATALATCH, TRMREG_SCSI_CONTROL); 1861 /* 1862 * SCSI command 1863 */ 1864 trm_reg_write8(SCMD_MSGACCEPT, TRMREG_SCSI_COMMAND); 1865 return; 1866 } else if (message_in_code == MSG_IGNOREWIDE) { 1867 trm_reg_write32(1, TRMREG_SCSI_COUNTER); 1868 trm_reg_read8(TRMREG_SCSI_FIFO); 1869 *pscsi_status = PH_BUS_FREE; /* .. initial phase */ 1870 /* it's important for atn stop */ 1871 trm_reg_write16(DO_DATALATCH, TRMREG_SCSI_CONTROL); 1872 /* 1873 * SCSI command 1874 */ 1875 trm_reg_write8(SCMD_MSGACCEPT, TRMREG_SCSI_COMMAND); 1876 return; 1877 } else { 1878 /* Restore data pointer message */ 1879 /* Save data pointer message */ 1880 /* Completion message */ 1881 /* NOP message */ 1882 *pscsi_status = PH_BUS_FREE; /* .. initial phase */ 1883 /* it's important for atn stop */ 1884 trm_reg_write16(DO_DATALATCH, TRMREG_SCSI_CONTROL); 1885 /* 1886 * SCSI command 1887 */ 1888 trm_reg_write8(SCMD_MSGACCEPT, TRMREG_SCSI_COMMAND); 1889 return; 1890 } 1891 } else { 1892 /* 1893 * Parsing incomming extented messages 1894 */ 1895 *pSRB->pMsgPtr = message_in_code; 1896 pSRB->MsgCnt++; 1897 pSRB->pMsgPtr++; 1898 TRM_DPRINTF("pSRB->MsgInBuf[0]=%2x \n ",pSRB->MsgInBuf[0]); 1899 TRM_DPRINTF("pSRB->MsgInBuf[1]=%2x \n ",pSRB->MsgInBuf[1]); 1900 TRM_DPRINTF("pSRB->MsgInBuf[2]=%2x \n ",pSRB->MsgInBuf[2]); 1901 TRM_DPRINTF("pSRB->MsgInBuf[3]=%2x \n ",pSRB->MsgInBuf[3]); 1902 TRM_DPRINTF("pSRB->MsgInBuf[4]=%2x \n ",pSRB->MsgInBuf[4]); 1903 if ((pSRB->MsgInBuf[0] >= MSG_SIMPLE_QTAG) 1904 && (pSRB->MsgInBuf[0] <= MSG_ORDER_QTAG)) { 1905 /* 1906 * is QUEUE tag message : 1907 * 1908 * byte 0: 1909 * HEAD QUEUE TAG (20h) 1910 * ORDERED QUEUE TAG (21h) 1911 * SIMPLE QUEUE TAG (22h) 1912 * byte 1: 1913 * Queue tag (00h - FFh) 1914 */ 1915 if (pSRB->MsgCnt == 2) { 1916 pSRB->SRBState = 0; 1917 message_in_tag_id = pSRB->MsgInBuf[1]; 1918 pSRB = pDCB->pGoingSRB; 1919 pSRBTemp = pDCB->pGoingLastSRB; 1920 if (pSRB) { 1921 for (;;) { 1922 if (pSRB->TagNumber != 1923 message_in_tag_id) { 1924 if (pSRB == pSRBTemp) { 1925 goto mingx0; 1926 } 1927 pSRB = pSRB->pNextSRB; 1928 } else 1929 break; 1930 } 1931 if (pDCB->DCBFlag & ABORT_DEV_) { 1932 pSRB->SRBState = SRB_ABORT_SENT; 1933 trm_EnableMsgOutAbort1( 1934 pACB, pSRB); 1935 } 1936 if (!(pSRB->SRBState & SRB_DISCONNECT)) { 1937 TRM_DPRINTF("SRB not yet disconnect........ \n "); 1938 goto mingx0; 1939 } 1940 pDCB->pActiveSRB = pSRB; 1941 pSRB->SRBState = SRB_DATA_XFER; 1942 } else { 1943mingx0: 1944 pSRB = &pACB->TmpSRB; 1945 pSRB->SRBState = SRB_UNEXPECT_RESEL; 1946 pDCB->pActiveSRB = pSRB; 1947 pSRB->MsgOutBuf[0] = MSG_ABORT_TAG; 1948 trm_EnableMsgOutAbort2( 1949 pACB, 1950 pSRB); 1951 } 1952 } 1953 *pscsi_status = PH_BUS_FREE; 1954 /* .. initial phase */ 1955 trm_reg_write16(DO_DATALATCH, TRMREG_SCSI_CONTROL); 1956 /* it's important for atn stop */ 1957 /* 1958 * SCSI command 1959 */ 1960 trm_reg_write8(SCMD_MSGACCEPT, TRMREG_SCSI_COMMAND); 1961 return; 1962 } else if ((pSRB->MsgInBuf[0] == MSG_EXTENDED) && 1963 (pSRB->MsgInBuf[2] == 3) && (pSRB->MsgCnt == 4)) { 1964 /* 1965 * is Wide data xfer Extended message : 1966 * ====================================== 1967 * WIDE DATA TRANSFER REQUEST 1968 * ====================================== 1969 * byte 0 : Extended message (01h) 1970 * byte 1 : Extended message length (02h) 1971 * byte 2 : WIDE DATA TRANSFER code (03h) 1972 * byte 3 : Transfer width exponent 1973 */ 1974 pDCB = pSRB->pSRBDCB; 1975 pSRB->SRBState &= ~(SRB_EXTEND_MSGIN+SRB_DO_WIDE_NEGO); 1976 if ((pSRB->MsgInBuf[1] != 2)) { 1977 /* Length is wrong, reject it */ 1978 pDCB->SyncMode &= 1979 ~(WIDE_NEGO_ENABLE+WIDE_NEGO_DONE); 1980 pSRB->MsgCnt = 1; 1981 pSRB->MsgInBuf[0] = MSG_REJECT_; 1982 trm_reg_write16(DO_SETATN, TRMREG_SCSI_CONTROL); 1983 *pscsi_status = PH_BUS_FREE; /* .. initial phase */ 1984 /* it's important for atn stop */ 1985 trm_reg_write16(DO_DATALATCH, TRMREG_SCSI_CONTROL); 1986 /* 1987 * SCSI command 1988 */ 1989 trm_reg_write8(SCMD_MSGACCEPT, TRMREG_SCSI_COMMAND); 1990 return; 1991 } 1992 if (pDCB->SyncMode & WIDE_NEGO_ENABLE) { 1993 /* Do wide negoniation */ 1994 if (pSRB->MsgInBuf[3] > 2) { 1995 /* > 32 bit */ 1996 /* reject_msg: */ 1997 pDCB->SyncMode &= 1998 ~(WIDE_NEGO_ENABLE+WIDE_NEGO_DONE); 1999 pSRB->MsgCnt = 1; 2000 pSRB->MsgInBuf[0] = MSG_REJECT_; 2001 trm_reg_write16(DO_SETATN, 2002 TRMREG_SCSI_CONTROL); 2003 *pscsi_status = PH_BUS_FREE; /* .. initial phase */ 2004 /* it's important for atn stop */ 2005 trm_reg_write16(DO_DATALATCH, TRMREG_SCSI_CONTROL); 2006 /* 2007 * SCSI command 2008 */ 2009 trm_reg_write8(SCMD_MSGACCEPT, TRMREG_SCSI_COMMAND); 2010 return; 2011 } 2012 if (pSRB->MsgInBuf[3] == 2) { 2013 pSRB->MsgInBuf[3] = 1; 2014 /* do 16 bits */ 2015 } else { 2016 if (!(pDCB->SyncMode 2017 & WIDE_NEGO_DONE)) { 2018 pSRB->SRBState &= 2019 ~(SRB_DO_WIDE_NEGO+SRB_MSGIN); 2020 pDCB->SyncMode |= 2021 WIDE_NEGO_DONE; 2022 pDCB->SyncMode &= 2023 ~(SYNC_NEGO_DONE | 2024 EN_ATN_STOP | 2025 WIDE_NEGO_ENABLE); 2026 if (pSRB->MsgInBuf[3] != 0) { 2027 /* is Wide data xfer */ 2028 pDCB->SyncPeriod |= 2029 WIDE_SYNC; 2030 pDCB->tinfo.current.width 2031 = MSG_EXT_WDTR_BUS_16_BIT; 2032 pDCB->tinfo.goal.width 2033 = MSG_EXT_WDTR_BUS_16_BIT; 2034 } 2035 } 2036 } 2037 } else 2038 pSRB->MsgInBuf[3] = 0; 2039 pSRB->SRBState |= SRB_MSGOUT; 2040 trm_reg_write16(DO_SETATN,TRMREG_SCSI_CONTROL); 2041 *pscsi_status = PH_BUS_FREE; /* .. initial phase */ 2042 /* it's important for atn stop */ 2043 trm_reg_write16(DO_DATALATCH, TRMREG_SCSI_CONTROL); 2044 /* 2045 * SCSI command 2046 */ 2047 trm_reg_write8(SCMD_MSGACCEPT, TRMREG_SCSI_COMMAND); 2048 return; 2049 } else if ((pSRB->MsgInBuf[0] == MSG_EXTENDED) && 2050 (pSRB->MsgInBuf[2] == 1) && (pSRB->MsgCnt == 5)) { 2051 /* 2052 * is 8bit transfer Extended message : 2053 * ================================= 2054 * SYNCHRONOUS DATA TRANSFER REQUEST 2055 * ================================= 2056 * byte 0 : Extended message (01h) 2057 * byte 1 : Extended message length (03) 2058 * byte 2 : SYNCHRONOUS DATA TRANSFER code (01h) 2059 * byte 3 : Transfer period factor 2060 * byte 4 : REQ/ACK offset 2061 */ 2062 pSRB->SRBState &= ~(SRB_EXTEND_MSGIN+SRB_DO_SYNC_NEGO); 2063 if ((pSRB->MsgInBuf[1] != 3) || 2064 (pSRB->MsgInBuf[2] != 1)) { 2065 /* reject_msg: */ 2066 pSRB->MsgCnt = 1; 2067 pSRB->MsgInBuf[0] = MSG_REJECT_; 2068 trm_reg_write16(DO_SETATN, TRMREG_SCSI_CONTROL); 2069 *pscsi_status = PH_BUS_FREE; 2070 /* .. initial phase */ 2071 trm_reg_write16(DO_DATALATCH, TRMREG_SCSI_CONTROL); 2072 /* it's important for atn stop */ 2073 /* 2074 * SCSI cammand 2075 */ 2076 trm_reg_write8(SCMD_MSGACCEPT, TRMREG_SCSI_COMMAND); 2077 return; 2078 } else if (!(pSRB->MsgInBuf[3]) || !(pSRB->MsgInBuf[4])) { 2079 /* set async */ 2080 pDCB = pSRB->pSRBDCB; 2081 /* disable sync & sync nego */ 2082 pDCB->SyncMode &= 2083 ~(SYNC_NEGO_ENABLE+SYNC_NEGO_DONE); 2084 pDCB->SyncPeriod = 0; 2085 pDCB->SyncOffset = 0; 2086 pDCB->tinfo.goal.period = 0; 2087 pDCB->tinfo.goal.offset = 0; 2088 pDCB->tinfo.current.period = 0; 2089 pDCB->tinfo.current.offset = 0; 2090 pDCB->tinfo.current.width = 2091 MSG_EXT_WDTR_BUS_8_BIT; 2092 /* 2093 * 2094 * program SCSI control register 2095 * 2096 */ 2097 trm_reg_write8(pDCB->SyncPeriod,TRMREG_SCSI_SYNC); 2098 trm_reg_write8(pDCB->SyncOffset,TRMREG_SCSI_OFFSET); 2099 trm_SetXferRate(pACB,pSRB,pDCB); 2100 *pscsi_status = PH_BUS_FREE; 2101 /* .. initial phase */ 2102 trm_reg_write16(DO_DATALATCH, TRMREG_SCSI_CONTROL); 2103 /* it's important for atn stop */ 2104 /* 2105 * SCSI cammand 2106 */ 2107 trm_reg_write8(SCMD_MSGACCEPT, TRMREG_SCSI_COMMAND); 2108 return; 2109 } else { 2110 /* set sync */ 2111 pDCB = pSRB->pSRBDCB; 2112 pDCB->SyncMode |= 2113 SYNC_NEGO_ENABLE+SYNC_NEGO_DONE; 2114 pDCB->MaxNegoPeriod = pSRB->MsgInBuf[3]; 2115 /* Transfer period factor */ 2116 pDCB->SyncOffset = pSRB->MsgInBuf[4]; 2117 /* REQ/ACK offset */ 2118 if (pACB->AdaptType == 1) { 2119 for(bIndex = 0; bIndex < 7; bIndex++) { 2120 if (pSRB->MsgInBuf[3] <= 2121 dc395u2x_clock_period[bIndex]) { 2122 pDCB->tinfo.goal.period = 2123 dc395u2x_tinfo_period[bIndex]; 2124 pDCB->tinfo.current.period = 2125 dc395u2x_tinfo_period[bIndex]; 2126 pDCB->tinfo.goal.offset = 2127 pDCB->SyncOffset; 2128 pDCB->tinfo.current.offset = 2129 pDCB->SyncOffset; 2130 pDCB->SyncPeriod |= (bIndex|LVDS_SYNC); 2131 break; 2132 } 2133 } 2134 } else { 2135 for(bIndex = 0; bIndex < 7; bIndex++) { 2136 if (pSRB->MsgInBuf[3] <= 2137 dc395x_clock_period[bIndex]) { 2138 pDCB->tinfo.goal.period = 2139 dc395x_tinfo_period[bIndex]; 2140 pDCB->tinfo.current.period = 2141 dc395x_tinfo_period[bIndex]; 2142 pDCB->tinfo.goal.offset = 2143 pDCB->SyncOffset; 2144 pDCB->tinfo.current.offset = 2145 pDCB->SyncOffset; 2146 pDCB->SyncPeriod |= 2147 (bIndex|ALT_SYNC); 2148 break; 2149 } 2150 } 2151 } 2152 /* 2153 * 2154 * program SCSI control register 2155 * 2156 */ 2157 trm_reg_write8(pDCB->SyncPeriod, 2158 TRMREG_SCSI_SYNC); 2159 trm_reg_write8(pDCB->SyncOffset, 2160 TRMREG_SCSI_OFFSET); 2161 trm_SetXferRate(pACB,pSRB,pDCB); 2162 *pscsi_status=PH_BUS_FREE;/*.. initial phase*/ 2163 trm_reg_write16(DO_DATALATCH,TRMREG_SCSI_CONTROL);/* it's important for atn stop*/ 2164 /* 2165 ** SCSI command 2166 */ 2167 trm_reg_write8(SCMD_MSGACCEPT,TRMREG_SCSI_COMMAND); 2168 return; 2169 } 2170 } 2171 *pscsi_status = PH_BUS_FREE; 2172 /* .. initial phase */ 2173 trm_reg_write16(DO_DATALATCH, TRMREG_SCSI_CONTROL); 2174 /* it's important for atn stop */ 2175 /* 2176 * SCSI cammand 2177 */ 2178 trm_reg_write8(SCMD_MSGACCEPT, TRMREG_SCSI_COMMAND); 2179 } 2180} 2181 2182static void 2183trm_MsgInPhase1(PACB pACB, PSRB pSRB, u_int16_t *pscsi_status) 2184{ 2185 2186 trm_reg_write16(DO_CLRFIFO, TRMREG_SCSI_CONTROL); 2187 trm_reg_write32(1,TRMREG_SCSI_COUNTER); 2188 if (!(pSRB->SRBState & SRB_MSGIN)) { 2189 pSRB->SRBState &= SRB_DISCONNECT; 2190 pSRB->SRBState |= SRB_MSGIN; 2191 } 2192 trm_reg_write16(DO_DATALATCH, TRMREG_SCSI_CONTROL); 2193 /* it's important for atn stop*/ 2194 /* 2195 * SCSI cammand 2196 */ 2197 trm_reg_write8(SCMD_FIFO_IN, TRMREG_SCSI_COMMAND); 2198} 2199 2200static void 2201trm_Nop0(PACB pACB, PSRB pSRB, u_int16_t *pscsi_status) 2202{ 2203 2204} 2205 2206static void 2207trm_Nop1(PACB pACB, PSRB pSRB, u_int16_t *pscsi_status) 2208{ 2209 2210} 2211 2212static void 2213trm_SetXferRate(PACB pACB,PSRB pSRB, PDCB pDCB) 2214{ 2215 union ccb *pccb; 2216 struct ccb_trans_settings neg; 2217 u_int16_t cnt, i; 2218 u_int8_t bval; 2219 PDCB pDCBTemp; 2220 2221 /* 2222 * set all lun device's period , offset 2223 */ 2224 TRM_DPRINTF("trm_SetXferRate\n"); 2225 pccb = pSRB->pccb; 2226 memset(&neg, 0, sizeof (neg)); 2227 neg.xport_specific.spi.sync_period = pDCB->tinfo.goal.period; 2228 neg.xport_specific.spi.sync_offset = pDCB->tinfo.goal.offset; 2229 neg.xport_specific.spi.valid = 2230 CTS_SPI_VALID_SYNC_RATE | CTS_SPI_VALID_SYNC_OFFSET; 2231 xpt_setup_ccb(&neg.ccb_h, pccb->ccb_h.path, /* priority */1); 2232 xpt_async(AC_TRANSFER_NEG, pccb->ccb_h.path, &neg); 2233 if (!(pDCB->IdentifyMsg & 0x07)) { 2234 pDCBTemp = pACB->pLinkDCB; 2235 cnt = pACB->DeviceCnt; 2236 bval = pDCB->TargetID; 2237 for (i = 0; i < cnt; i++) { 2238 if (pDCBTemp->TargetID == bval) { 2239 pDCBTemp->SyncPeriod = pDCB->SyncPeriod; 2240 pDCBTemp->SyncOffset = pDCB->SyncOffset; 2241 pDCBTemp->SyncMode = pDCB->SyncMode; 2242 } 2243 pDCBTemp = pDCBTemp->pNextDCB; 2244 } 2245 } 2246 return; 2247} 2248 2249/* 2250 * scsiiom 2251 * trm_Interrupt 2252 * 2253 * 2254 * ---SCSI bus phase 2255 * 2256 * PH_DATA_OUT 0x00 Data out phase 2257 * PH_DATA_IN 0x01 Data in phase 2258 * PH_COMMAND 0x02 Command phase 2259 * PH_STATUS 0x03 Status phase 2260 * PH_BUS_FREE 0x04 Invalid phase used as bus free 2261 * PH_BUS_FREE 0x05 Invalid phase used as bus free 2262 * PH_MSG_OUT 0x06 Message out phase 2263 * PH_MSG_IN 0x07 Message in phase 2264 * 2265 */ 2266static void 2267trm_Disconnect(PACB pACB) 2268{ 2269 PDCB pDCB; 2270 PSRB pSRB, psrb; 2271 u_int16_t i,j, cnt; 2272 u_int target_id,target_lun; 2273 2274 TRM_DPRINTF("trm_Disconnect...............\n "); 2275 2276 pDCB = pACB->pActiveDCB; 2277 if (!pDCB) { 2278 TRM_DPRINTF(" Exception Disconnect DCB=NULL..............\n "); 2279 j = 400; 2280 while (--j) 2281 DELAY(1); 2282 /* 1 msec */ 2283 trm_reg_write16((DO_CLRFIFO | DO_HWRESELECT), 2284 TRMREG_SCSI_CONTROL); 2285 return; 2286 } 2287 pSRB = pDCB->pActiveSRB; 2288 /* bug pSRB=0 */ 2289 target_id = pSRB->pccb->ccb_h.target_id; 2290 target_lun = pSRB->pccb->ccb_h.target_lun; 2291 TRM_DPRINTF(":pDCB->pActiveSRB= %8x \n ",(u_int) pDCB->pActiveSRB); 2292 pACB->pActiveDCB = 0; 2293 pSRB->ScsiPhase = PH_BUS_FREE; 2294 /* SCSI bus free Phase */ 2295 trm_reg_write16((DO_CLRFIFO | DO_HWRESELECT), TRMREG_SCSI_CONTROL); 2296 if (pSRB->SRBState & SRB_UNEXPECT_RESEL) { 2297 pSRB->SRBState = 0; 2298 trm_DoWaitingSRB(pACB); 2299 } else if (pSRB->SRBState & SRB_ABORT_SENT) { 2300 pDCB->DCBFlag = 0; 2301 cnt = pDCB->GoingSRBCnt; 2302 pDCB->GoingSRBCnt = 0; 2303 pSRB = pDCB->pGoingSRB; 2304 for (i = 0; i < cnt; i++) { 2305 psrb = pSRB->pNextSRB; 2306 pSRB->pNextSRB = pACB->pFreeSRB; 2307 pACB->pFreeSRB = pSRB; 2308 pSRB = psrb; 2309 } 2310 pDCB->pGoingSRB = 0; 2311 trm_DoWaitingSRB(pACB); 2312 } else { 2313 if ((pSRB->SRBState & (SRB_START_+SRB_MSGOUT)) || 2314 !(pSRB->SRBState & (SRB_DISCONNECT+SRB_COMPLETED))) { 2315 /* Selection time out */ 2316 if (!(pACB->scan_devices[target_id][target_lun]) && 2317 pSRB->CmdBlock[0] != 0x00 && /* TEST UNIT READY */ 2318 pSRB->CmdBlock[0] != INQUIRY) { 2319 pSRB->SRBState = SRB_READY; 2320 trm_RewaitSRB(pDCB, pSRB); 2321 } else { 2322 pSRB->TargetStatus = SCSI_STAT_SEL_TIMEOUT; 2323 goto disc1; 2324 } 2325 } else if (pSRB->SRBState & SRB_DISCONNECT) { 2326 /* 2327 * SRB_DISCONNECT 2328 */ 2329 trm_DoWaitingSRB(pACB); 2330 } else if (pSRB->SRBState & SRB_COMPLETED) { 2331disc1: 2332 /* 2333 * SRB_COMPLETED 2334 */ 2335 pDCB->pActiveSRB = 0; 2336 pSRB->SRBState = SRB_FREE; 2337 trm_SRBdone(pACB, pDCB, pSRB); 2338 } 2339 } 2340 return; 2341} 2342 2343static void 2344trm_Reselect(PACB pACB) 2345{ 2346 PDCB pDCB; 2347 PSRB pSRB; 2348 u_int16_t RselTarLunId; 2349 2350 TRM_DPRINTF("trm_Reselect................. \n"); 2351 pDCB = pACB->pActiveDCB; 2352 if (pDCB) { 2353 /* Arbitration lost but Reselection win */ 2354 pSRB = pDCB->pActiveSRB; 2355 pSRB->SRBState = SRB_READY; 2356 trm_RewaitSRB(pDCB, pSRB); 2357 } 2358 /* Read Reselected Target Id and LUN */ 2359 RselTarLunId = trm_reg_read16(TRMREG_SCSI_TARGETID) & 0x1FFF; 2360 pDCB = pACB->pLinkDCB; 2361 while (RselTarLunId != *((u_int16_t *) &pDCB->TargetID)) { 2362 /* get pDCB of the reselect id */ 2363 pDCB = pDCB->pNextDCB; 2364 } 2365 2366 pACB->pActiveDCB = pDCB; 2367 if (pDCB->SyncMode & EN_TAG_QUEUING) { 2368 pSRB = &pACB->TmpSRB; 2369 pDCB->pActiveSRB = pSRB; 2370 } else { 2371 pSRB = pDCB->pActiveSRB; 2372 if (!pSRB || !(pSRB->SRBState & SRB_DISCONNECT)) { 2373 /* 2374 * abort command 2375 */ 2376 pSRB = &pACB->TmpSRB; 2377 pSRB->SRBState = SRB_UNEXPECT_RESEL; 2378 pDCB->pActiveSRB = pSRB; 2379 trm_EnableMsgOutAbort1(pACB, pSRB); 2380 } else { 2381 if (pDCB->DCBFlag & ABORT_DEV_) { 2382 pSRB->SRBState = SRB_ABORT_SENT; 2383 trm_EnableMsgOutAbort1(pACB, pSRB); 2384 } else 2385 pSRB->SRBState = SRB_DATA_XFER; 2386 } 2387 } 2388 pSRB->ScsiPhase = PH_BUS_FREE; 2389 /* SCSI bus free Phase */ 2390 /* 2391 * Program HA ID, target ID, period and offset 2392 */ 2393 trm_reg_write8((u_int8_t) RselTarLunId,TRMREG_SCSI_TARGETID); 2394 /* target ID */ 2395 trm_reg_write8(pACB->AdaptSCSIID,TRMREG_SCSI_HOSTID); 2396 /* host ID */ 2397 trm_reg_write8(pDCB->SyncPeriod,TRMREG_SCSI_SYNC); 2398 /* period */ 2399 trm_reg_write8(pDCB->SyncOffset,TRMREG_SCSI_OFFSET); 2400 /* offset */ 2401 trm_reg_write16(DO_DATALATCH, TRMREG_SCSI_CONTROL); 2402 /* it's important for atn stop*/ 2403 /* 2404 * SCSI cammand 2405 */ 2406 trm_reg_write8(SCMD_MSGACCEPT, TRMREG_SCSI_COMMAND); 2407 /* to rls the /ACK signal */ 2408} 2409 2410static void 2411trm_SRBdone(PACB pACB, PDCB pDCB, PSRB pSRB) 2412{ 2413 PSRB psrb; 2414 u_int8_t bval, bval1,status; 2415 union ccb *pccb; 2416 struct ccb_scsiio *pcsio; 2417 PSCSI_INQDATA ptr; 2418 int intflag; 2419 u_int target_id,target_lun; 2420 PDCB pTempDCB; 2421 2422 pccb = pSRB->pccb; 2423 if (pccb == NULL) 2424 return; 2425 pcsio = &pccb->csio; 2426 target_id = pSRB->pccb->ccb_h.target_id; 2427 target_lun = pSRB->pccb->ccb_h.target_lun; 2428 if ((pccb->ccb_h.flags & CAM_DIR_MASK) != CAM_DIR_NONE) { 2429 bus_dmasync_op_t op; 2430 if ((pccb->ccb_h.flags & CAM_DIR_MASK) == CAM_DIR_IN) 2431 op = BUS_DMASYNC_POSTREAD; 2432 else 2433 op = BUS_DMASYNC_POSTWRITE; 2434 bus_dmamap_sync(pACB->buffer_dmat, pSRB->dmamap, op); 2435 bus_dmamap_unload(pACB->buffer_dmat, pSRB->dmamap); 2436 } 2437 /* 2438 * 2439 * target status 2440 * 2441 */ 2442 status = pSRB->TargetStatus; 2443 pcsio->scsi_status=SCSI_STAT_GOOD; 2444 pccb->ccb_h.status = CAM_REQ_CMP; 2445 if (pSRB->SRBFlag & AUTO_REQSENSE) { 2446 /* 2447 * status of auto request sense 2448 */ 2449 pSRB->SRBFlag &= ~AUTO_REQSENSE; 2450 pSRB->AdaptStatus = 0; 2451 pSRB->TargetStatus = SCSI_STATUS_CHECK_COND; 2452 2453 if (status == SCSI_STATUS_CHECK_COND) { 2454 pccb->ccb_h.status = CAM_SEL_TIMEOUT; 2455 goto ckc_e; 2456 } 2457 *((u_long *) &(pSRB->CmdBlock[0])) = pSRB->Segment0[0]; 2458 *((u_long *) &(pSRB->CmdBlock[4])) = pSRB->Segment0[1]; 2459 pSRB->SRBTotalXferLength = pSRB->Segment1[1]; 2460 pSRB->pSRBSGL->address = pSRB->SgSenseTemp.address; 2461 pSRB->pSRBSGL->length = pSRB->SgSenseTemp.length; 2462 pcsio->scsi_status = SCSI_STATUS_CHECK_COND; 2463 bcopy(trm_get_sense_buf(pACB, pSRB), &pcsio->sense_data, 2464 pcsio->sense_len); 2465 pcsio->ccb_h.status = CAM_SCSI_STATUS_ERROR 2466 | CAM_AUTOSNS_VALID; 2467 goto ckc_e; 2468 } 2469 /* 2470 * target status 2471 */ 2472 if (status) { 2473 if (status == SCSI_STATUS_CHECK_COND) { 2474 if ((pcsio->ccb_h.flags & CAM_DIS_AUTOSENSE) == 0) { 2475 TRM_DPRINTF("trm_RequestSense..................\n"); 2476 trm_RequestSense(pACB, pDCB, pSRB); 2477 return; 2478 } 2479 pcsio->scsi_status = SCSI_STATUS_CHECK_COND; 2480 pccb->ccb_h.status = CAM_SCSI_STATUS_ERROR; 2481 goto ckc_e; 2482 } else if (status == SCSI_STAT_QUEUEFULL) { 2483 bval = (u_int8_t) pDCB->GoingSRBCnt; 2484 bval--; 2485 pDCB->MaxActiveCommandCnt = bval; 2486 trm_RewaitSRB(pDCB, pSRB); 2487 pSRB->AdaptStatus = 0; 2488 pSRB->TargetStatus = 0; 2489 return; 2490 } else if (status == SCSI_STAT_SEL_TIMEOUT) { 2491 pSRB->AdaptStatus = H_SEL_TIMEOUT; 2492 pSRB->TargetStatus = 0; 2493 pcsio->scsi_status = SCSI_STAT_SEL_TIMEOUT; 2494 pccb->ccb_h.status = CAM_SEL_TIMEOUT; 2495 } else if (status == SCSI_STAT_BUSY) { 2496 TRM_DPRINTF("trm: target busy at %s %d\n", 2497 __FILE__, __LINE__); 2498 pcsio->scsi_status = SCSI_STAT_BUSY; 2499 pccb->ccb_h.status = CAM_SCSI_BUSY; 2500 return; 2501 /* The device busy, try again later? */ 2502 } else if (status == SCSI_STAT_RESCONFLICT) { 2503 TRM_DPRINTF("trm: target reserved at %s %d\n", 2504 __FILE__, __LINE__); 2505 pcsio->scsi_status = SCSI_STAT_RESCONFLICT; 2506 pccb->ccb_h.status = CAM_SCSI_STATUS_ERROR; /*XXX*/ 2507 return; 2508 } else { 2509 pSRB->AdaptStatus = 0; 2510 if (pSRB->RetryCnt) { 2511 pSRB->RetryCnt--; 2512 pSRB->TargetStatus = 0; 2513 pSRB->SRBSGIndex = 0; 2514 if (trm_StartSCSI(pACB, pDCB, pSRB)) { 2515 /* 2516 * If trm_StartSCSI return 1 : 2517 * current interrupt status is interrupt 2518 * disreenable 2519 * It's said that SCSI processor has more 2520 * one SRB need to do 2521 */ 2522 trm_RewaitSRB(pDCB, pSRB); 2523 } 2524 return; 2525 } else { 2526 TRM_DPRINTF("trm: driver stuffup at %s %d\n", 2527 __FILE__, __LINE__); 2528 pccb->ccb_h.status = CAM_SCSI_STATUS_ERROR; 2529 } 2530 } 2531 } else { 2532 /* 2533 * process initiator status.......................... 2534 * Adapter (initiator) status 2535 */ 2536 status = pSRB->AdaptStatus; 2537 if (status & H_OVER_UNDER_RUN) { 2538 pSRB->TargetStatus = 0; 2539 pccb->ccb_h.status = CAM_DATA_RUN_ERR; 2540 /* Illegal length (over/under run) */ 2541 } else if (pSRB->SRBStatus & PARITY_ERROR) { 2542 TRM_DPRINTF("trm: driver stuffup %s %d\n", 2543 __FILE__, __LINE__); 2544 pDCB->tinfo.goal.period = 0; 2545 pDCB->tinfo.goal.offset = 0; 2546 /* Driver failed to perform operation */ 2547 pccb->ccb_h.status = CAM_UNCOR_PARITY; 2548 } else { 2549 /* no error */ 2550 pSRB->AdaptStatus = 0; 2551 pSRB->TargetStatus = 0; 2552 pccb->ccb_h.status = CAM_REQ_CMP; 2553 /* there is no error, (sense is invalid) */ 2554 } 2555 } 2556ckc_e: 2557 if (pACB->scan_devices[target_id][target_lun]) { 2558 /* 2559 * if SCSI command in "scan devices" duty 2560 */ 2561 if (pSRB->CmdBlock[0] == TEST_UNIT_READY) 2562 pACB->scan_devices[target_id][target_lun] = 0; 2563 /* SCSI command phase :test unit ready */ 2564 else if (pSRB->CmdBlock[0] == INQUIRY) { 2565 /* 2566 * SCSI command phase :inquiry scsi device data 2567 * (type,capacity,manufacture.... 2568 */ 2569 if (pccb->ccb_h.status == CAM_SEL_TIMEOUT) 2570 goto NO_DEV; 2571 ptr = (PSCSI_INQDATA) pcsio->data_ptr; 2572 /* page fault */ 2573 TRM_DPRINTF("trm_SRBdone..PSCSI_INQDATA:%2x \n", 2574 ptr->DevType); 2575 bval1 = ptr->DevType & SCSI_DEVTYPE; 2576 if (bval1 == SCSI_NODEV) { 2577NO_DEV: 2578 TRM_DPRINTF("trm_SRBdone NO Device:target_id= %d ,target_lun= %d \n", 2579 target_id, 2580 target_lun); 2581 intflag = splcam(); 2582 pACB->scan_devices[target_id][target_lun] = 0; 2583 /* no device set scan device flag =0*/ 2584 /* pDCB Q link */ 2585 /* move the head of DCB to tempDCB*/ 2586 pTempDCB=pACB->pLinkDCB; 2587 /* search current DCB for pass link */ 2588 while (pTempDCB->pNextDCB != pDCB) { 2589 pTempDCB = pTempDCB->pNextDCB; 2590 } 2591 /* 2592 * when the current DCB found than connect 2593 * current DCB tail 2594 */ 2595 /* to the DCB tail that before current DCB */ 2596 pTempDCB->pNextDCB = pDCB->pNextDCB; 2597 /* 2598 * if there was only one DCB ,connect his tail 2599 * to his head 2600 */ 2601 if (pACB->pLinkDCB == pDCB) 2602 pACB->pLinkDCB = pTempDCB->pNextDCB; 2603 if (pACB->pDCBRunRobin == pDCB) 2604 pACB->pDCBRunRobin = pTempDCB->pNextDCB; 2605 pDCB->DCBstatus &= ~DS_IN_QUEUE; 2606 pACB->DeviceCnt--; 2607 if (pACB->DeviceCnt == 0) { 2608 pACB->pLinkDCB = NULL; 2609 pACB->pDCBRunRobin = NULL; 2610 } 2611 splx(intflag); 2612 } else { 2613#ifdef trm_DEBUG1 2614 int j; 2615 for (j = 0; j < 28; j++) { 2616 TRM_DPRINTF("ptr=%2x ", 2617 ((u_int8_t *)ptr)[j]); 2618 } 2619#endif 2620 pDCB->DevType = bval1; 2621 if (bval1 == SCSI_DASD || 2622 bval1 == SCSI_OPTICAL) { 2623 if ((((ptr->Vers & 0x07) >= 2) || 2624 ((ptr->RDF & 0x0F) == 2)) && 2625 (ptr->Flags & SCSI_INQ_CMDQUEUE) && 2626 (pDCB->DevMode & TAG_QUEUING_) && 2627 (pDCB->DevMode & EN_DISCONNECT_)) { 2628 if (pDCB->DevMode & 2629 TAG_QUEUING_) { 2630 pDCB-> 2631 MaxActiveCommandCnt = 2632 pACB->TagMaxNum; 2633 pDCB->SyncMode |= 2634 EN_TAG_QUEUING; 2635 pDCB->tinfo.disc_tag |= 2636 TRM_CUR_TAGENB; 2637 } else { 2638 pDCB->SyncMode |= 2639 EN_ATN_STOP; 2640 pDCB->tinfo.disc_tag &= 2641 ~TRM_CUR_TAGENB; 2642 } 2643 } 2644 } 2645 } 2646 /* pSRB->CmdBlock[0] == INQUIRY */ 2647 } 2648 /* pACB->scan_devices[target_id][target_lun] */ 2649 } 2650 intflag = splcam(); 2651 /* ReleaseSRB(pDCB, pSRB); */ 2652 if (pSRB == pDCB->pGoingSRB) 2653 pDCB->pGoingSRB = pSRB->pNextSRB; 2654 else { 2655 psrb = pDCB->pGoingSRB; 2656 while (psrb->pNextSRB != pSRB) { 2657 psrb = psrb->pNextSRB; 2658 } 2659 psrb->pNextSRB = pSRB->pNextSRB; 2660 if (pSRB == pDCB->pGoingLastSRB) { 2661 pDCB->pGoingLastSRB = psrb; 2662 } 2663 } 2664 pSRB->pNextSRB = pACB->pFreeSRB; 2665 pACB->pFreeSRB = pSRB; 2666 pDCB->GoingSRBCnt--; 2667 trm_DoWaitingSRB(pACB); 2668 2669 splx(intflag); 2670 /* Notify cmd done */ 2671 xpt_done (pccb); 2672} 2673 2674static void 2675trm_DoingSRB_Done(PACB pACB) 2676{ 2677 PDCB pDCB, pdcb; 2678 PSRB psrb, psrb2; 2679 u_int16_t cnt, i; 2680 union ccb *pccb; 2681 2682 pDCB = pACB->pLinkDCB; 2683 if (pDCB == NULL) 2684 return; 2685 pdcb = pDCB; 2686 do { 2687 cnt = pdcb->GoingSRBCnt; 2688 psrb = pdcb->pGoingSRB; 2689 for (i = 0; i < cnt; i++) { 2690 psrb2 = psrb->pNextSRB; 2691 pccb = psrb->pccb; 2692 pccb->ccb_h.status = CAM_SEL_TIMEOUT; 2693 /* ReleaseSRB(pDCB, pSRB); */ 2694 psrb->pNextSRB = pACB->pFreeSRB; 2695 pACB->pFreeSRB = psrb; 2696 xpt_done(pccb); 2697 psrb = psrb2; 2698 } 2699 pdcb->GoingSRBCnt = 0; 2700 pdcb->pGoingSRB = NULL; 2701 pdcb = pdcb->pNextDCB; 2702 } 2703 while (pdcb != pDCB); 2704} 2705 2706static void 2707trm_ResetSCSIBus(PACB pACB) 2708{ 2709 int intflag; 2710 2711 intflag = splcam(); 2712 pACB->ACBFlag |= RESET_DEV; 2713 2714 trm_reg_write16(DO_RSTSCSI,TRMREG_SCSI_CONTROL); 2715 while (!(trm_reg_read16(TRMREG_SCSI_INTSTATUS) & INT_SCSIRESET)); 2716 splx(intflag); 2717 return; 2718} 2719 2720static void 2721trm_ScsiRstDetect(PACB pACB) 2722{ 2723 int intflag; 2724 u_long wlval; 2725 2726 TRM_DPRINTF("trm_ScsiRstDetect \n"); 2727 wlval = 1000; 2728 while (--wlval) 2729 DELAY(1000); 2730 intflag = splcam(); 2731 trm_reg_write8(STOPDMAXFER,TRMREG_DMA_CONTROL); 2732 2733 trm_reg_write16(DO_CLRFIFO,TRMREG_SCSI_CONTROL); 2734 2735 if (pACB->ACBFlag & RESET_DEV) 2736 pACB->ACBFlag |= RESET_DONE; 2737 else { 2738 pACB->ACBFlag |= RESET_DETECT; 2739 trm_ResetDevParam(pACB); 2740 /* trm_DoingSRB_Done(pACB); ???? */ 2741 trm_RecoverSRB(pACB); 2742 pACB->pActiveDCB = NULL; 2743 pACB->ACBFlag = 0; 2744 trm_DoWaitingSRB(pACB); 2745 } 2746 splx(intflag); 2747 return; 2748} 2749 2750static void 2751trm_RequestSense(PACB pACB, PDCB pDCB, PSRB pSRB) 2752{ 2753 union ccb *pccb; 2754 struct ccb_scsiio *pcsio; 2755 2756 pccb = pSRB->pccb; 2757 pcsio = &pccb->csio; 2758 2759 pSRB->SRBFlag |= AUTO_REQSENSE; 2760 pSRB->Segment0[0] = *((u_long *) &(pSRB->CmdBlock[0])); 2761 pSRB->Segment0[1] = *((u_long *) &(pSRB->CmdBlock[4])); 2762 pSRB->Segment1[0] = (u_long) ((pSRB->ScsiCmdLen << 8) + 2763 pSRB->SRBSGCount); 2764 pSRB->Segment1[1] = pSRB->SRBTotalXferLength; /* ?????????? */ 2765 2766 /* $$$$$$ Status of initiator/target $$$$$$$$ */ 2767 pSRB->AdaptStatus = 0; 2768 pSRB->TargetStatus = 0; 2769 /* $$$$$$ Status of initiator/target $$$$$$$$ */ 2770 2771 pSRB->SRBTotalXferLength = sizeof(pcsio->sense_data); 2772 pSRB->SgSenseTemp.address = pSRB->pSRBSGL->address; 2773 pSRB->SgSenseTemp.length = pSRB->pSRBSGL->length; 2774 pSRB->pSRBSGL->address = trm_get_sense_bufaddr(pACB, pSRB); 2775 pSRB->pSRBSGL->length = (u_long) sizeof(struct scsi_sense_data); 2776 pSRB->SRBSGCount = 1; 2777 pSRB->SRBSGIndex = 0; 2778 2779 *((u_long *) &(pSRB->CmdBlock[0])) = 0x00000003; 2780 pSRB->CmdBlock[1] = pDCB->IdentifyMsg << 5; 2781 *((u_int16_t *) &(pSRB->CmdBlock[4])) = pcsio->sense_len; 2782 pSRB->ScsiCmdLen = 6; 2783 2784 if (trm_StartSCSI(pACB, pDCB, pSRB)) 2785 /* 2786 * If trm_StartSCSI return 1 : 2787 * current interrupt status is interrupt disreenable 2788 * It's said that SCSI processor has more one SRB need to do 2789 */ 2790 trm_RewaitSRB(pDCB, pSRB); 2791} 2792 2793static void 2794trm_EnableMsgOutAbort2(PACB pACB, PSRB pSRB) 2795{ 2796 2797 pSRB->MsgCnt = 1; 2798 trm_reg_write16(DO_SETATN, TRMREG_SCSI_CONTROL); 2799} 2800 2801static void 2802trm_EnableMsgOutAbort1(PACB pACB, PSRB pSRB) 2803{ 2804 2805 pSRB->MsgOutBuf[0] = MSG_ABORT; 2806 trm_EnableMsgOutAbort2(pACB, pSRB); 2807} 2808 2809static void 2810trm_initDCB(PACB pACB, PDCB pDCB, u_int16_t unit,u_int32_t i,u_int32_t j) 2811{ 2812 PNVRAMTYPE pEEpromBuf; 2813 u_int8_t bval,PeriodIndex; 2814 u_int target_id,target_lun; 2815 PDCB pTempDCB; 2816 int intflag; 2817 2818 target_id = i; 2819 target_lun = j; 2820 2821 /* 2822 * Using the lun 0 device to init other DCB first, if the device 2823 * has been initialized. 2824 * I don't want init sync arguments one by one, it is the same. 2825 */ 2826 if (target_lun != 0 && 2827 (pACB->DCBarray[target_id][0].DCBstatus & DS_IN_QUEUE)) 2828 bcopy(&pACB->DCBarray[target_id][0], pDCB, 2829 sizeof(TRM_DCB)); 2830 intflag = splcam(); 2831 if (pACB->pLinkDCB == 0) { 2832 pACB->pLinkDCB = pDCB; 2833 /* 2834 * RunRobin impersonate the role 2835 * that let each device had good proportion 2836 * about SCSI command proceeding 2837 */ 2838 pACB->pDCBRunRobin = pDCB; 2839 pDCB->pNextDCB = pDCB; 2840 } else { 2841 pTempDCB=pACB->pLinkDCB; 2842 /* search the last nod of DCB link */ 2843 while (pTempDCB->pNextDCB != pACB->pLinkDCB) 2844 pTempDCB = pTempDCB->pNextDCB; 2845 /* connect current DCB with last DCB tail */ 2846 pTempDCB->pNextDCB = pDCB; 2847 /* connect current DCB tail to this DCB Q head */ 2848 pDCB->pNextDCB=pACB->pLinkDCB; 2849 } 2850 splx(intflag); 2851 2852 pACB->DeviceCnt++; 2853 pDCB->TargetID = target_id; 2854 pDCB->TargetLUN = target_lun; 2855 pDCB->pWaitingSRB = NULL; 2856 pDCB->pGoingSRB = NULL; 2857 pDCB->GoingSRBCnt = 0; 2858 pDCB->pActiveSRB = NULL; 2859 pDCB->MaxActiveCommandCnt = 1; 2860 pDCB->DCBFlag = 0; 2861 pDCB->DCBstatus |= DS_IN_QUEUE; 2862 /* $$$$$$$ */ 2863 pEEpromBuf = &trm_eepromBuf[unit]; 2864 pDCB->DevMode = pEEpromBuf->NvramTarget[target_id].NvmTarCfg0; 2865 pDCB->AdpMode = pEEpromBuf->NvramChannelCfg; 2866 /* $$$$$$$ */ 2867 /* 2868 * disconnect enable ? 2869 */ 2870 if (pDCB->DevMode & NTC_DO_DISCONNECT) { 2871 bval = 0xC0; 2872 pDCB->tinfo.disc_tag |= TRM_USR_DISCENB ; 2873 } else { 2874 bval = 0x80; 2875 pDCB->tinfo.disc_tag &= ~(TRM_USR_DISCENB); 2876 } 2877 bval |= target_lun; 2878 pDCB->IdentifyMsg = bval; 2879 if (target_lun != 0 && 2880 (pACB->DCBarray[target_id][0].DCBstatus & DS_IN_QUEUE)) 2881 return; 2882 /* $$$$$$$ */ 2883 /* 2884 * tag Qing enable ? 2885 */ 2886 if (pDCB->DevMode & TAG_QUEUING_) { 2887 pDCB->tinfo.disc_tag |= TRM_USR_TAGENB ; 2888 } else 2889 pDCB->tinfo.disc_tag &= ~(TRM_USR_TAGENB); 2890 /* $$$$$$$ */ 2891 /* 2892 * wide nego ,sync nego enable ? 2893 */ 2894 pDCB->SyncPeriod = 0; 2895 pDCB->SyncOffset = 0; 2896 PeriodIndex = pEEpromBuf->NvramTarget[target_id].NvmTarPeriod & 0x07; 2897 if (pACB->AdaptType==1) {/* is U2? */ 2898 pDCB->MaxNegoPeriod=dc395u2x_clock_period[ PeriodIndex ]; 2899 pDCB->tinfo.user.period=pDCB->MaxNegoPeriod; 2900 pDCB->tinfo.user.offset=(pDCB->SyncMode & SYNC_NEGO_ENABLE) ? 31 : 0; 2901 } else { 2902 pDCB->MaxNegoPeriod=dc395x_clock_period[ PeriodIndex ]; 2903 pDCB->tinfo.user.period=pDCB->MaxNegoPeriod; 2904 pDCB->tinfo.user.offset=(pDCB->SyncMode & SYNC_NEGO_ENABLE) ? 15 : 0; 2905 } 2906 pDCB->SyncMode = 0; 2907 if ((pDCB->DevMode & NTC_DO_WIDE_NEGO) && 2908 (pACB->Config & HCC_WIDE_CARD)) 2909 pDCB->SyncMode |= WIDE_NEGO_ENABLE; 2910 /* enable wide nego */ 2911 if (pDCB->DevMode & NTC_DO_SYNC_NEGO) 2912 pDCB->SyncMode |= SYNC_NEGO_ENABLE; 2913 /* enable sync nego */ 2914 /* $$$$$$$ */ 2915 /* 2916 * Fill in tinfo structure. 2917 */ 2918 pDCB->tinfo.user.width = (pDCB->SyncMode & WIDE_NEGO_ENABLE) ? 2919 MSG_EXT_WDTR_BUS_16_BIT : MSG_EXT_WDTR_BUS_8_BIT; 2920 2921 pDCB->tinfo.current.period = 0; 2922 pDCB->tinfo.current.offset = 0; 2923 pDCB->tinfo.current.width = MSG_EXT_WDTR_BUS_8_BIT; 2924} 2925 2926static void 2927trm_srbmapSG(void *arg, bus_dma_segment_t *segs, int nseg, int error) 2928{ 2929 PSRB pSRB; 2930 2931 pSRB=(PSRB) arg; 2932 pSRB->SRBSGPhyAddr=segs->ds_addr; 2933 return; 2934} 2935 2936static void 2937trm_destroySRB(PACB pACB) 2938{ 2939 PSRB pSRB; 2940 2941 pSRB = pACB->pFreeSRB; 2942 while (pSRB) { 2943 if (pSRB->sg_dmamap) { 2944 bus_dmamap_unload(pACB->sg_dmat, pSRB->sg_dmamap); 2945 bus_dmamem_free(pACB->sg_dmat, pSRB->pSRBSGL, 2946 pSRB->sg_dmamap); 2947 bus_dmamap_destroy(pACB->sg_dmat, pSRB->sg_dmamap); 2948 } 2949 if (pSRB->dmamap) 2950 bus_dmamap_destroy(pACB->buffer_dmat, pSRB->dmamap); 2951 pSRB = pSRB->pNextSRB; 2952 } 2953} 2954 2955static int 2956trm_initSRB(PACB pACB) 2957{ 2958 u_int16_t i; 2959 PSRB pSRB; 2960 int error; 2961 2962 for (i = 0; i < TRM_MAX_SRB_CNT; i++) { 2963 pSRB = (PSRB)&pACB->pFreeSRB[i]; 2964 2965 if (bus_dmamem_alloc(pACB->sg_dmat, (void **)&pSRB->pSRBSGL, 2966 BUS_DMA_NOWAIT, &pSRB->sg_dmamap) !=0 ) { 2967 return ENXIO; 2968 } 2969 bus_dmamap_load(pACB->sg_dmat, pSRB->sg_dmamap, pSRB->pSRBSGL, 2970 TRM_MAX_SG_LISTENTRY * sizeof(SGentry), 2971 trm_srbmapSG, pSRB, /*flags*/0); 2972 if (i != TRM_MAX_SRB_CNT - 1) { 2973 /* 2974 * link all SRB 2975 */ 2976 pSRB->pNextSRB = &pACB->pFreeSRB[i+1]; 2977 } else { 2978 /* 2979 * load NULL to NextSRB of the last SRB 2980 */ 2981 pSRB->pNextSRB = NULL; 2982 } 2983 pSRB->TagNumber = i; 2984 2985 /* 2986 * Create the dmamap. This is no longer optional! 2987 */ 2988 if ((error = bus_dmamap_create(pACB->buffer_dmat, 0, 2989 &pSRB->dmamap)) != 0) 2990 return (error); 2991 2992 } 2993 return (0); 2994} 2995 2996 2997 2998 2999static void 3000trm_initACB(PACB pACB, u_int8_t adaptType, u_int16_t unit) 3001{ 3002 PNVRAMTYPE pEEpromBuf; 3003 3004 pEEpromBuf = &trm_eepromBuf[unit]; 3005 pACB->max_id = 15; 3006 3007 if (pEEpromBuf->NvramChannelCfg & NAC_SCANLUN) 3008 pACB->max_lun = 7; 3009 else 3010 pACB->max_lun = 0; 3011 3012 TRM_DPRINTF("trm: pACB->max_id= %d pACB->max_lun= %d \n", 3013 pACB->max_id, pACB->max_lun); 3014 pACB->pLinkDCB = NULL; 3015 pACB->pDCBRunRobin = NULL; 3016 pACB->pActiveDCB = NULL; 3017 pACB->AdapterUnit = (u_int8_t)unit; 3018 pACB->AdaptSCSIID = pEEpromBuf->NvramScsiId; 3019 pACB->AdaptSCSILUN = 0; 3020 pACB->DeviceCnt = 0; 3021 pACB->AdaptType = adaptType; 3022 pACB->TagMaxNum = 2 << pEEpromBuf->NvramMaxTag; 3023 pACB->ACBFlag = 0; 3024 return; 3025} 3026 3027static void 3028NVRAM_trm_write_all(PNVRAMTYPE pEEpromBuf,PACB pACB) 3029{ 3030 u_int8_t *bpEeprom = (u_int8_t *) pEEpromBuf; 3031 u_int8_t bAddr; 3032 3033 /* Enable SEEPROM */ 3034 trm_reg_write8((trm_reg_read8(TRMREG_GEN_CONTROL) | EN_EEPROM), 3035 TRMREG_GEN_CONTROL); 3036 /* 3037 * Write enable 3038 */ 3039 NVRAM_trm_write_cmd(pACB, 0x04, 0xFF); 3040 trm_reg_write8(0, TRMREG_GEN_NVRAM); 3041 NVRAM_trm_wait_30us(pACB); 3042 for (bAddr = 0; bAddr < 128; bAddr++, bpEeprom++) { 3043 NVRAM_trm_set_data(pACB, bAddr, *bpEeprom); 3044 } 3045 /* 3046 * Write disable 3047 */ 3048 NVRAM_trm_write_cmd(pACB, 0x04, 0x00); 3049 trm_reg_write8(0 , TRMREG_GEN_NVRAM); 3050 NVRAM_trm_wait_30us(pACB); 3051 /* Disable SEEPROM */ 3052 trm_reg_write8((trm_reg_read8(TRMREG_GEN_CONTROL) & ~EN_EEPROM), 3053 TRMREG_GEN_CONTROL); 3054 return; 3055} 3056 3057static void 3058NVRAM_trm_set_data(PACB pACB, u_int8_t bAddr, u_int8_t bData) 3059{ 3060 int i; 3061 u_int8_t bSendData; 3062 /* 3063 * Send write command & address 3064 */ 3065 3066 NVRAM_trm_write_cmd(pACB, 0x05, bAddr); 3067 /* 3068 * Write data 3069 */ 3070 for (i = 0; i < 8; i++, bData <<= 1) { 3071 bSendData = NVR_SELECT; 3072 if (bData & 0x80) 3073 /* Start from bit 7 */ 3074 bSendData |= NVR_BITOUT; 3075 trm_reg_write8(bSendData , TRMREG_GEN_NVRAM); 3076 NVRAM_trm_wait_30us(pACB); 3077 trm_reg_write8((bSendData | NVR_CLOCK), TRMREG_GEN_NVRAM); 3078 NVRAM_trm_wait_30us(pACB); 3079 } 3080 trm_reg_write8(NVR_SELECT , TRMREG_GEN_NVRAM); 3081 NVRAM_trm_wait_30us(pACB); 3082 /* 3083 * Disable chip select 3084 */ 3085 trm_reg_write8(0 , TRMREG_GEN_NVRAM); 3086 NVRAM_trm_wait_30us(pACB); 3087 trm_reg_write8(NVR_SELECT ,TRMREG_GEN_NVRAM); 3088 NVRAM_trm_wait_30us(pACB); 3089 /* 3090 * Wait for write ready 3091 */ 3092 while (1) { 3093 trm_reg_write8((NVR_SELECT | NVR_CLOCK), TRMREG_GEN_NVRAM); 3094 NVRAM_trm_wait_30us(pACB); 3095 trm_reg_write8(NVR_SELECT, TRMREG_GEN_NVRAM); 3096 NVRAM_trm_wait_30us(pACB); 3097 if (trm_reg_read8(TRMREG_GEN_NVRAM) & NVR_BITIN) { 3098 break; 3099 } 3100 } 3101 /* 3102 * Disable chip select 3103 */ 3104 trm_reg_write8(0, TRMREG_GEN_NVRAM); 3105 return; 3106} 3107 3108static void 3109NVRAM_trm_read_all(PNVRAMTYPE pEEpromBuf, PACB pACB) 3110{ 3111 u_int8_t *bpEeprom = (u_int8_t*) pEEpromBuf; 3112 u_int8_t bAddr; 3113 3114 /* 3115 * Enable SEEPROM 3116 */ 3117 trm_reg_write8((trm_reg_read8(TRMREG_GEN_CONTROL) | EN_EEPROM), 3118 TRMREG_GEN_CONTROL); 3119 for (bAddr = 0; bAddr < 128; bAddr++, bpEeprom++) 3120 *bpEeprom = NVRAM_trm_get_data(pACB, bAddr); 3121 /* 3122 * Disable SEEPROM 3123 */ 3124 trm_reg_write8((trm_reg_read8(TRMREG_GEN_CONTROL) & ~EN_EEPROM), 3125 TRMREG_GEN_CONTROL); 3126 return; 3127} 3128 3129static u_int8_t 3130NVRAM_trm_get_data(PACB pACB, u_int8_t bAddr) 3131{ 3132 int i; 3133 u_int8_t bReadData, bData = 0; 3134 /* 3135 * Send read command & address 3136 */ 3137 3138 NVRAM_trm_write_cmd(pACB, 0x06, bAddr); 3139 3140 for (i = 0; i < 8; i++) { 3141 /* 3142 * Read data 3143 */ 3144 trm_reg_write8((NVR_SELECT | NVR_CLOCK) , TRMREG_GEN_NVRAM); 3145 NVRAM_trm_wait_30us(pACB); 3146 trm_reg_write8(NVR_SELECT , TRMREG_GEN_NVRAM); 3147 /* 3148 * Get data bit while falling edge 3149 */ 3150 bReadData = trm_reg_read8(TRMREG_GEN_NVRAM); 3151 bData <<= 1; 3152 if (bReadData & NVR_BITIN) { 3153 bData |= 1; 3154 } 3155 NVRAM_trm_wait_30us(pACB); 3156 } 3157 /* 3158 * Disable chip select 3159 */ 3160 trm_reg_write8(0, TRMREG_GEN_NVRAM); 3161 return (bData); 3162} 3163 3164static void 3165NVRAM_trm_wait_30us(PACB pACB) 3166{ 3167 3168 /* ScsiPortStallExecution(30); wait 30 us */ 3169 trm_reg_write8(5, TRMREG_GEN_TIMER); 3170 while (!(trm_reg_read8(TRMREG_GEN_STATUS) & GTIMEOUT)); 3171 return; 3172} 3173 3174static void 3175NVRAM_trm_write_cmd(PACB pACB, u_int8_t bCmd, u_int8_t bAddr) 3176{ 3177 int i; 3178 u_int8_t bSendData; 3179 3180 for (i = 0; i < 3; i++, bCmd <<= 1) { 3181 /* 3182 * Program SB+OP code 3183 */ 3184 bSendData = NVR_SELECT; 3185 if (bCmd & 0x04) 3186 bSendData |= NVR_BITOUT; 3187 /* start from bit 2 */ 3188 trm_reg_write8(bSendData, TRMREG_GEN_NVRAM); 3189 NVRAM_trm_wait_30us(pACB); 3190 trm_reg_write8((bSendData | NVR_CLOCK), TRMREG_GEN_NVRAM); 3191 NVRAM_trm_wait_30us(pACB); 3192 } 3193 for (i = 0; i < 7; i++, bAddr <<= 1) { 3194 /* 3195 * Program address 3196 */ 3197 bSendData = NVR_SELECT; 3198 if (bAddr & 0x40) 3199 /* Start from bit 6 */ 3200 bSendData |= NVR_BITOUT; 3201 trm_reg_write8(bSendData , TRMREG_GEN_NVRAM); 3202 NVRAM_trm_wait_30us(pACB); 3203 trm_reg_write8((bSendData | NVR_CLOCK), TRMREG_GEN_NVRAM); 3204 NVRAM_trm_wait_30us(pACB); 3205 } 3206 trm_reg_write8(NVR_SELECT, TRMREG_GEN_NVRAM); 3207 NVRAM_trm_wait_30us(pACB); 3208} 3209 3210static void 3211trm_check_eeprom(PNVRAMTYPE pEEpromBuf, PACB pACB) 3212{ 3213 u_int16_t *wpEeprom = (u_int16_t *) pEEpromBuf; 3214 u_int16_t wAddr, wCheckSum; 3215 u_long dAddr, *dpEeprom; 3216 3217 NVRAM_trm_read_all(pEEpromBuf,pACB); 3218 wCheckSum = 0; 3219 for (wAddr = 0, wpEeprom = (u_int16_t *) pEEpromBuf; 3220 wAddr < 64; wAddr++, wpEeprom++) { 3221 wCheckSum += *wpEeprom; 3222 } 3223 if (wCheckSum != 0x1234) { 3224 /* 3225 * Checksum error, load default 3226 */ 3227 pEEpromBuf->NvramSubVendorID[0] = (u_int8_t) PCI_Vendor_ID_TEKRAM; 3228 pEEpromBuf->NvramSubVendorID[1] = 3229 (u_int8_t) (PCI_Vendor_ID_TEKRAM >> 8); 3230 pEEpromBuf->NvramSubSysID[0] = (u_int8_t) PCI_Device_ID_TRM_S1040; 3231 pEEpromBuf->NvramSubSysID[1] = 3232 (u_int8_t) (PCI_Device_ID_TRM_S1040 >> 8); 3233 pEEpromBuf->NvramSubClass = 0x00; 3234 pEEpromBuf->NvramVendorID[0] = (u_int8_t) PCI_Vendor_ID_TEKRAM; 3235 pEEpromBuf->NvramVendorID[1] = 3236 (u_int8_t) (PCI_Vendor_ID_TEKRAM >> 8); 3237 pEEpromBuf->NvramDeviceID[0] = (u_int8_t) PCI_Device_ID_TRM_S1040; 3238 pEEpromBuf->NvramDeviceID[1] = 3239 (u_int8_t) (PCI_Device_ID_TRM_S1040 >> 8); 3240 pEEpromBuf->NvramReserved = 0x00; 3241 3242 for (dAddr = 0, dpEeprom = (u_long *) pEEpromBuf->NvramTarget; 3243 dAddr < 16; dAddr++, dpEeprom++) { 3244 *dpEeprom = 0x00000077; 3245 /* NvmTarCfg3,NvmTarCfg2,NvmTarPeriod,NvmTarCfg0 */ 3246 } 3247 3248 *dpEeprom++ = 0x04000F07; 3249 /* NvramMaxTag,NvramDelayTime,NvramChannelCfg,NvramScsiId */ 3250 *dpEeprom++ = 0x00000015; 3251 /* NvramReserved1,NvramBootLun,NvramBootTarget,NvramReserved0 */ 3252 for (dAddr = 0; dAddr < 12; dAddr++, dpEeprom++) 3253 *dpEeprom = 0x00; 3254 pEEpromBuf->NvramCheckSum = 0x00; 3255 for (wAddr = 0, wCheckSum = 0, wpEeprom = (u_int16_t *) pEEpromBuf; 3256 wAddr < 63; wAddr++, wpEeprom++) 3257 wCheckSum += *wpEeprom; 3258 *wpEeprom = 0x1234 - wCheckSum; 3259 NVRAM_trm_write_all(pEEpromBuf,pACB); 3260 } 3261 return; 3262} 3263static int 3264trm_initAdapter(PACB pACB, u_int16_t unit) 3265{ 3266 PNVRAMTYPE pEEpromBuf; 3267 u_int16_t wval; 3268 u_int8_t bval; 3269 3270 pEEpromBuf = &trm_eepromBuf[unit]; 3271 3272 /* 250ms selection timeout */ 3273 trm_reg_write8(SEL_TIMEOUT, TRMREG_SCSI_TIMEOUT); 3274 /* Mask all the interrupt */ 3275 trm_reg_write8(0x00, TRMREG_DMA_INTEN); 3276 trm_reg_write8(0x00, TRMREG_SCSI_INTEN); 3277 /* Reset SCSI module */ 3278 trm_reg_write16(DO_RSTMODULE, TRMREG_SCSI_CONTROL); 3279 /* program configuration 0 */ 3280 pACB->Config = HCC_AUTOTERM | HCC_PARITY; 3281 if (trm_reg_read8(TRMREG_GEN_STATUS) & WIDESCSI) 3282 pACB->Config |= HCC_WIDE_CARD; 3283 if (pEEpromBuf->NvramChannelCfg & NAC_POWERON_SCSI_RESET) 3284 pACB->Config |= HCC_SCSI_RESET; 3285 if (pACB->Config & HCC_PARITY) 3286 bval = PHASELATCH | INITIATOR | BLOCKRST | PARITYCHECK; 3287 else 3288 bval = PHASELATCH | INITIATOR | BLOCKRST ; 3289 trm_reg_write8(bval,TRMREG_SCSI_CONFIG0); 3290 /* program configuration 1 */ 3291 trm_reg_write8(0x13, TRMREG_SCSI_CONFIG1); 3292 /* program Host ID */ 3293 bval = pEEpromBuf->NvramScsiId; 3294 trm_reg_write8(bval, TRMREG_SCSI_HOSTID); 3295 /* set ansynchronous transfer */ 3296 trm_reg_write8(0x00, TRMREG_SCSI_OFFSET); 3297 /* Trun LED control off*/ 3298 wval = trm_reg_read16(TRMREG_GEN_CONTROL) & 0x7F; 3299 trm_reg_write16(wval, TRMREG_GEN_CONTROL); 3300 /* DMA config */ 3301 wval = trm_reg_read16(TRMREG_DMA_CONFIG) | DMA_ENHANCE; 3302 trm_reg_write16(wval, TRMREG_DMA_CONFIG); 3303 /* Clear pending interrupt status */ 3304 trm_reg_read8(TRMREG_SCSI_INTSTATUS); 3305 /* Enable SCSI interrupt */ 3306 trm_reg_write8(0x7F, TRMREG_SCSI_INTEN); 3307 trm_reg_write8(EN_SCSIINTR, TRMREG_DMA_INTEN); 3308 return (0); 3309} 3310 3311static void 3312trm_mapSRB(void *arg, bus_dma_segment_t *segs, int nseg, int error) 3313{ 3314 PACB pACB; 3315 3316 pACB = (PACB)arg; 3317 pACB->srb_physbase = segs->ds_addr; 3318} 3319 3320static void 3321trm_dmamap_cb(void *arg, bus_dma_segment_t *segs, int nseg, int error) 3322{ 3323 bus_addr_t *baddr; 3324 3325 baddr = (bus_addr_t *)arg; 3326 *baddr = segs->ds_addr; 3327} 3328 3329static PACB 3330trm_init(u_int16_t unit, device_t dev) 3331{ 3332 PACB pACB; 3333 int rid = PCIR_BAR(0), i = 0, j = 0; 3334 u_int16_t adaptType = 0; 3335 3336 pACB = (PACB) device_get_softc(dev); 3337 if (!pACB) { 3338 printf("trm%d: cannot allocate ACB !\n", unit); 3339 return (NULL); 3340 } 3341 pACB->iores = bus_alloc_resource_any(dev, SYS_RES_IOPORT, 3342 &rid, RF_ACTIVE); 3343 if (pACB->iores == NULL) { 3344 printf("trm_init: bus_alloc_resource failed!\n"); 3345 return (NULL); 3346 } 3347 switch (pci_get_devid(dev)) { 3348 case PCI_DEVICEID_TRMS1040: 3349 adaptType = 0; 3350 break; 3351 case PCI_DEVICEID_TRMS2080: 3352 adaptType = 1; 3353 break; 3354 default: 3355 printf("trm_init %d: unknown adapter type!\n", unit); 3356 goto bad; 3357 } 3358 pACB->dev = dev; 3359 pACB->tag = rman_get_bustag(pACB->iores); 3360 pACB->bsh = rman_get_bushandle(pACB->iores); 3361 if (bus_dma_tag_create( 3362 /*parent_dmat*/ bus_get_dma_tag(dev), 3363 /*alignment*/ 1, 3364 /*boundary*/ 0, 3365 /*lowaddr*/ BUS_SPACE_MAXADDR, 3366 /*highaddr*/ BUS_SPACE_MAXADDR, 3367 /*filter*/ NULL, 3368 /*filterarg*/ NULL, 3369 /*maxsize*/ BUS_SPACE_MAXSIZE_32BIT, 3370 /*nsegments*/ BUS_SPACE_UNRESTRICTED, 3371 /*maxsegsz*/ BUS_SPACE_MAXSIZE_32BIT, 3372 /*flags*/ 0, 3373 /*lockfunc*/ NULL, 3374 /*lockarg*/ NULL, 3375 /* dmat */ &pACB->parent_dmat) != 0) 3376 goto bad; 3377 if (bus_dma_tag_create( 3378 /*parent_dmat*/ pACB->parent_dmat, 3379 /*alignment*/ 1, 3380 /*boundary*/ 0, 3381 /*lowaddr*/ BUS_SPACE_MAXADDR, 3382 /*highaddr*/ BUS_SPACE_MAXADDR, 3383 /*filter*/ NULL, 3384 /*filterarg*/ NULL, 3385 /*maxsize*/ TRM_MAXPHYS, 3386 /*nsegments*/ TRM_NSEG, 3387 /*maxsegsz*/ TRM_MAXTRANSFER_SIZE, 3388 /*flags*/ BUS_DMA_ALLOCNOW, 3389 /*lockfunc*/ busdma_lock_mutex, 3390 /*lockarg*/ &Giant, 3391 /* dmat */ &pACB->buffer_dmat) != 0) 3392 goto bad; 3393 /* DMA tag for our ccb structures */ 3394 if (bus_dma_tag_create( 3395 /*parent_dmat*/pACB->parent_dmat, 3396 /*alignment*/ 1, 3397 /*boundary*/ 0, 3398 /*lowaddr*/ BUS_SPACE_MAXADDR, 3399 /*highaddr*/ BUS_SPACE_MAXADDR, 3400 /*filter*/ NULL, 3401 /*filterarg*/ NULL, 3402 /*maxsize*/ TRM_MAX_SRB_CNT * sizeof(TRM_SRB), 3403 /*nsegments*/ 1, 3404 /*maxsegsz*/ TRM_MAXTRANSFER_SIZE, 3405 /*flags*/ 0, 3406 /*lockfunc*/ busdma_lock_mutex, 3407 /*lockarg*/ &Giant, 3408 /*dmat*/ &pACB->srb_dmat) != 0) { 3409 printf("trm_init %d: bus_dma_tag_create SRB failure\n", unit); 3410 goto bad; 3411 } 3412 if (bus_dmamem_alloc(pACB->srb_dmat, (void **)&pACB->pFreeSRB, 3413 BUS_DMA_NOWAIT, &pACB->srb_dmamap) != 0) { 3414 printf("trm_init %d: bus_dmamem_alloc SRB failure\n", unit); 3415 goto bad; 3416 } 3417 bus_dmamap_load(pACB->srb_dmat, pACB->srb_dmamap, pACB->pFreeSRB, 3418 TRM_MAX_SRB_CNT * sizeof(TRM_SRB), trm_mapSRB, pACB, 3419 /* flags */0); 3420 /* Create, allocate, and map DMA buffers for autosense data */ 3421 if (bus_dma_tag_create( 3422 /*parent_dmat*/pACB->parent_dmat, 3423 /*alignment*/1, 3424 /*boundary*/0, 3425 /*lowaddr*/BUS_SPACE_MAXADDR_32BIT, 3426 /*highaddr*/BUS_SPACE_MAXADDR, 3427 /*filter*/NULL, /*filterarg*/NULL, 3428 sizeof(struct scsi_sense_data) * TRM_MAX_SRB_CNT, 3429 /*nsegments*/1, 3430 /*maxsegsz*/TRM_MAXTRANSFER_SIZE, 3431 /*flags*/0, /*lockfunc*/busdma_lock_mutex, 3432 /*lockarg*/&Giant, &pACB->sense_dmat) != 0) { 3433 if (bootverbose) 3434 device_printf(dev, "cannot create sense buffer dmat\n"); 3435 goto bad; 3436 } 3437 3438 if (bus_dmamem_alloc(pACB->sense_dmat, (void **)&pACB->sense_buffers, 3439 BUS_DMA_NOWAIT, &pACB->sense_dmamap) != 0) 3440 goto bad; 3441 3442 bus_dmamap_load(pACB->sense_dmat, pACB->sense_dmamap, 3443 pACB->sense_buffers, 3444 sizeof(struct scsi_sense_data) * TRM_MAX_SRB_CNT, 3445 trm_dmamap_cb, &pACB->sense_busaddr, /*flags*/0); 3446 3447 trm_check_eeprom(&trm_eepromBuf[unit],pACB); 3448 trm_initACB(pACB, adaptType, unit); 3449 for (i = 0; i < (pACB->max_id + 1); i++) { 3450 if (pACB->AdaptSCSIID == i) 3451 continue; 3452 for(j = 0; j < (pACB->max_lun + 1); j++) { 3453 pACB->scan_devices[i][j] = 1; 3454 /* we assume we need to scan all devices */ 3455 trm_initDCB(pACB, &pACB->DCBarray[i][j], unit, i, j); 3456 } 3457 } 3458 bzero(pACB->pFreeSRB, TRM_MAX_SRB_CNT * sizeof(TRM_SRB)); 3459 if (bus_dma_tag_create( 3460 /*parent_dmat*/pACB->parent_dmat, 3461 /*alignment*/ 1, 3462 /*boundary*/ 0, 3463 /*lowaddr*/ BUS_SPACE_MAXADDR, 3464 /*highaddr*/ BUS_SPACE_MAXADDR, 3465 /*filter*/ NULL, 3466 /*filterarg*/ NULL, 3467 /*maxsize*/ TRM_MAX_SG_LISTENTRY * sizeof(SGentry), 3468 /*nsegments*/ 1, 3469 /*maxsegsz*/ TRM_MAXTRANSFER_SIZE, 3470 /*flags*/ 0, 3471 /*lockfunc*/ busdma_lock_mutex, 3472 /*lockarg*/ &Giant, 3473 /*dmat*/ &pACB->sg_dmat) != 0) 3474 goto bad; 3475 3476 if (trm_initSRB(pACB)) { 3477 printf("trm_initSRB: error\n"); 3478 goto bad; 3479 } 3480 if (trm_initAdapter(pACB, unit)) { 3481 printf("trm_initAdapter: initial ERROR\n"); 3482 goto bad; 3483 } 3484 return (pACB); 3485bad: 3486 if (pACB->iores) 3487 bus_release_resource(dev, SYS_RES_IOPORT, PCIR_BAR(0), 3488 pACB->iores); 3489 if (pACB->sense_dmamap) { 3490 bus_dmamap_unload(pACB->sense_dmat, pACB->sense_dmamap); 3491 bus_dmamem_free(pACB->sense_dmat, pACB->sense_buffers, 3492 pACB->sense_dmamap); 3493 bus_dmamap_destroy(pACB->sense_dmat, pACB->sense_dmamap); 3494 } 3495 if (pACB->sense_dmat) 3496 bus_dma_tag_destroy(pACB->sense_dmat); 3497 if (pACB->sg_dmat) { 3498 trm_destroySRB(pACB); 3499 bus_dma_tag_destroy(pACB->sg_dmat); 3500 } 3501 if (pACB->srb_dmamap) { 3502 bus_dmamap_unload(pACB->srb_dmat, pACB->srb_dmamap); 3503 bus_dmamem_free(pACB->srb_dmat, pACB->pFreeSRB, 3504 pACB->srb_dmamap); 3505 bus_dmamap_destroy(pACB->srb_dmat, pACB->srb_dmamap); 3506 } 3507 if (pACB->srb_dmat) 3508 bus_dma_tag_destroy(pACB->srb_dmat); 3509 if (pACB->buffer_dmat) 3510 bus_dma_tag_destroy(pACB->buffer_dmat); 3511 if (pACB->parent_dmat) 3512 bus_dma_tag_destroy(pACB->parent_dmat); 3513 return (NULL); 3514} 3515 3516static int 3517trm_attach(device_t dev) 3518{ 3519 struct cam_devq *device_Q; 3520 u_long device_id; 3521 PACB pACB = 0; 3522 int rid = 0; 3523 int unit = device_get_unit(dev); 3524 3525 device_id = pci_get_devid(dev); 3526 /* 3527 * These cards do not allow memory mapped accesses 3528 */ 3529 if ((pACB = trm_init((u_int16_t) unit, 3530 dev)) == NULL) { 3531 printf("trm%d: trm_init error!\n",unit); 3532 return (ENXIO); 3533 } 3534 /* After setting up the adapter, map our interrupt */ 3535 /* 3536 * Now let the CAM generic SCSI layer find the SCSI devices on the bus 3537 * start queue to reset to the idle loop. 3538 * Create device queue of SIM(s) 3539 * (MAX_START_JOB - 1) : max_sim_transactions 3540 */ 3541 pACB->irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid, 3542 RF_SHAREABLE | RF_ACTIVE); 3543 if (pACB->irq == NULL || 3544 bus_setup_intr(dev, pACB->irq, 3545 INTR_TYPE_CAM, NULL, trm_Interrupt, pACB, &pACB->ih)) { 3546 printf("trm%d: register Interrupt handler error!\n", unit); 3547 goto bad; 3548 } 3549 device_Q = cam_simq_alloc(TRM_MAX_START_JOB); 3550 if (device_Q == NULL){ 3551 printf("trm%d: device_Q == NULL !\n",unit); 3552 goto bad; 3553 } 3554 /* 3555 * Now tell the generic SCSI layer 3556 * about our bus. 3557 * If this is the xpt layer creating a sim, then it's OK 3558 * to wait for an allocation. 3559 * XXX Should we pass in a flag to indicate that wait is OK? 3560 * 3561 * SIM allocation 3562 * 3563 * SCSI Interface Modules 3564 * The sim driver creates a sim for each controller. The sim device 3565 * queue is separately created in order to allow resource sharing betwee 3566 * sims. For instance, a driver may create one sim for each channel of 3567 * a multi-channel controller and use the same queue for each channel. 3568 * In this way, the queue resources are shared across all the channels 3569 * of the multi-channel controller. 3570 * trm_action : sim_action_func 3571 * trm_poll : sim_poll_func 3572 * "trm" : sim_name ,if sim_name = "xpt" ..M_DEVBUF,M_WAITOK 3573 * pACB : *softc if sim_name <> "xpt" ..M_DEVBUF,M_NOWAIT 3574 * pACB->unit : unit 3575 * 1 : max_dev_transactions 3576 * MAX_TAGS : max_tagged_dev_transactions 3577 * 3578 * *******Construct our first channel SIM entry 3579 */ 3580 pACB->psim = cam_sim_alloc(trm_action, 3581 trm_poll, 3582 "trm", 3583 pACB, 3584 unit, 3585 &Giant, 3586 1, 3587 TRM_MAX_TAGS_CMD_QUEUE, 3588 device_Q); 3589 if (pACB->psim == NULL) { 3590 printf("trm%d: SIM allocate fault !\n",unit); 3591 cam_simq_free(device_Q); /* SIM allocate fault*/ 3592 goto bad; 3593 } 3594 if (xpt_bus_register(pACB->psim, dev, 0) != CAM_SUCCESS) { 3595 printf("trm%d: xpt_bus_register fault !\n",unit); 3596 goto bad; 3597 } 3598 if (xpt_create_path(&pACB->ppath, 3599 NULL, 3600 cam_sim_path(pACB->psim), 3601 CAM_TARGET_WILDCARD, 3602 CAM_LUN_WILDCARD) != CAM_REQ_CMP) { 3603 printf("trm%d: xpt_create_path fault !\n",unit); 3604 xpt_bus_deregister(cam_sim_path(pACB->psim)); 3605 goto bad; 3606 } 3607 return (0); 3608bad: 3609 if (pACB->iores) 3610 bus_release_resource(dev, SYS_RES_IOPORT, PCIR_BAR(0), 3611 pACB->iores); 3612 if (pACB->sg_dmat) { 3613 trm_destroySRB(pACB); 3614 bus_dma_tag_destroy(pACB->sg_dmat); 3615 } 3616 3617 if (pACB->srb_dmamap) { 3618 bus_dmamap_unload(pACB->srb_dmat, pACB->srb_dmamap); 3619 bus_dmamem_free(pACB->srb_dmat, pACB->pFreeSRB, 3620 pACB->srb_dmamap); 3621 bus_dmamap_destroy(pACB->srb_dmat, pACB->srb_dmamap); 3622 } 3623 if (pACB->srb_dmat) 3624 bus_dma_tag_destroy(pACB->srb_dmat); 3625 if (pACB->sense_dmamap) { 3626 bus_dmamap_unload(pACB->sense_dmat, pACB->sense_dmamap); 3627 bus_dmamem_free(pACB->sense_dmat, pACB->sense_buffers, 3628 pACB->sense_dmamap); 3629 bus_dmamap_destroy(pACB->sense_dmat, pACB->sense_dmamap); 3630 } 3631 if (pACB->sense_dmat) 3632 bus_dma_tag_destroy(pACB->sense_dmat); 3633 if (pACB->buffer_dmat) 3634 bus_dma_tag_destroy(pACB->buffer_dmat); 3635 if (pACB->ih) 3636 bus_teardown_intr(dev, pACB->irq, pACB->ih); 3637 if (pACB->irq) 3638 bus_release_resource(dev, SYS_RES_IRQ, 0, pACB->irq); 3639 if (pACB->psim) 3640 cam_sim_free(pACB->psim, TRUE); 3641 3642 return (ENXIO); 3643 3644} 3645 3646/* 3647* pci_device 3648* trm_probe (device_t tag, pcidi_t type) 3649* 3650*/ 3651static int 3652trm_probe(device_t dev) 3653{ 3654 switch (pci_get_devid(dev)) { 3655 case PCI_DEVICEID_TRMS1040: 3656 device_set_desc(dev, 3657 "Tekram DC395U/UW/F DC315/U Fast20 Wide SCSI Adapter"); 3658 return (BUS_PROBE_DEFAULT); 3659 case PCI_DEVICEID_TRMS2080: 3660 device_set_desc(dev, 3661 "Tekram DC395U2D/U2W Fast40 Wide SCSI Adapter"); 3662 return (BUS_PROBE_DEFAULT); 3663 default: 3664 return (ENXIO); 3665 } 3666} 3667 3668static int 3669trm_detach(device_t dev) 3670{ 3671 PACB pACB = device_get_softc(dev); 3672 3673 bus_release_resource(dev, SYS_RES_IOPORT, PCIR_BAR(0), pACB->iores); 3674 trm_destroySRB(pACB); 3675 bus_dma_tag_destroy(pACB->sg_dmat); 3676 bus_dmamap_unload(pACB->srb_dmat, pACB->srb_dmamap); 3677 bus_dmamem_free(pACB->srb_dmat, pACB->pFreeSRB, 3678 pACB->srb_dmamap); 3679 bus_dmamap_destroy(pACB->srb_dmat, pACB->srb_dmamap); 3680 bus_dma_tag_destroy(pACB->srb_dmat); 3681 bus_dmamap_unload(pACB->sense_dmat, pACB->sense_dmamap); 3682 bus_dmamem_free(pACB->sense_dmat, pACB->sense_buffers, 3683 pACB->sense_dmamap); 3684 bus_dmamap_destroy(pACB->sense_dmat, pACB->sense_dmamap); 3685 bus_dma_tag_destroy(pACB->sense_dmat); 3686 bus_dma_tag_destroy(pACB->buffer_dmat); 3687 bus_teardown_intr(dev, pACB->irq, pACB->ih); 3688 bus_release_resource(dev, SYS_RES_IRQ, 0, pACB->irq); 3689 xpt_async(AC_LOST_DEVICE, pACB->ppath, NULL); 3690 xpt_free_path(pACB->ppath); 3691 xpt_bus_deregister(cam_sim_path(pACB->psim)); 3692 cam_sim_free(pACB->psim, TRUE); 3693 return (0); 3694} 3695static device_method_t trm_methods[] = { 3696 /* Device interface */ 3697 DEVMETHOD(device_probe, trm_probe), 3698 DEVMETHOD(device_attach, trm_attach), 3699 DEVMETHOD(device_detach, trm_detach), 3700 { 0, 0 } 3701}; 3702 3703static driver_t trm_driver = { 3704 "trm", trm_methods, sizeof(struct _ACB) 3705}; 3706 3707static devclass_t trm_devclass; 3708DRIVER_MODULE(trm, pci, trm_driver, trm_devclass, 0, 0); 3709MODULE_DEPEND(trm, pci, 1, 1, 1); 3710MODULE_DEPEND(trm, cam, 1, 1, 1); 3711