1139825Simp/*- 236270Swpaul * Copyright (c) 1997, 1998 336270Swpaul * Bill Paul <wpaul@ctr.columbia.edu>. All rights reserved. 436270Swpaul * 536270Swpaul * Redistribution and use in source and binary forms, with or without 636270Swpaul * modification, are permitted provided that the following conditions 736270Swpaul * are met: 836270Swpaul * 1. Redistributions of source code must retain the above copyright 936270Swpaul * notice, this list of conditions and the following disclaimer. 1036270Swpaul * 2. Redistributions in binary form must reproduce the above copyright 1136270Swpaul * notice, this list of conditions and the following disclaimer in the 1236270Swpaul * documentation and/or other materials provided with the distribution. 1336270Swpaul * 3. All advertising materials mentioning features or use of this software 1436270Swpaul * must display the following acknowledgement: 1536270Swpaul * This product includes software developed by Bill Paul. 1636270Swpaul * 4. Neither the name of the author nor the names of any co-contributors 1736270Swpaul * may be used to endorse or promote products derived from this software 1836270Swpaul * without specific prior written permission. 1936270Swpaul * 2036270Swpaul * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 2136270Swpaul * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 2236270Swpaul * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 2336270Swpaul * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 2436270Swpaul * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 2536270Swpaul * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 2636270Swpaul * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 2736270Swpaul * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 2836270Swpaul * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 2936270Swpaul * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 3036270Swpaul * THE POSSIBILITY OF SUCH DAMAGE. 3136270Swpaul * 3250477Speter * $FreeBSD$ 3336270Swpaul */ 3436270Swpaul 3536270Swpaulstruct tl_type { 3636270Swpaul u_int16_t tl_vid; 3736270Swpaul u_int16_t tl_did; 38226995Smarius const char *tl_name; 3936270Swpaul}; 4036270Swpaul 4136270Swpaul/* 4236270Swpaul * ThunderLAN TX/RX list format. The TX and RX lists are pretty much 4336270Swpaul * identical: the list begins with a 32-bit forward pointer which points 4436270Swpaul * at the next list in the chain, followed by 16 bits for the total 4536270Swpaul * frame size, and a 16 bit status field. This is followed by a series 4636270Swpaul * of 10 32-bit data count/data address pairs that point to the fragments 4736270Swpaul * that make up the complete frame. 4836270Swpaul */ 4936270Swpaul 5036270Swpaul#define TL_MAXFRAGS 10 5151439Swpaul#define TL_RX_LIST_CNT 64 5251439Swpaul#define TL_TX_LIST_CNT 128 5336270Swpaul#define TL_MIN_FRAMELEN 64 5436270Swpaul 5536270Swpaulstruct tl_frag { 5636270Swpaul u_int32_t tlist_dcnt; 5736270Swpaul u_int32_t tlist_dadr; 5836270Swpaul}; 5936270Swpaul 6036270Swpaulstruct tl_list { 6136270Swpaul u_int32_t tlist_fptr; /* phys address of next list */ 6236270Swpaul u_int16_t tlist_cstat; /* status word */ 6336270Swpaul u_int16_t tlist_frsize; /* size of data in frame */ 6436270Swpaul struct tl_frag tl_frag[TL_MAXFRAGS]; 6536270Swpaul}; 6636270Swpaul 6736270Swpaul/* 6836270Swpaul * This is a special case of an RX list. By setting the One_Frag 6936270Swpaul * bit in the NETCONFIG register, the driver can force the ThunderLAN 7036270Swpaul * chip to use only one fragment when DMAing RX frames. 7136270Swpaul */ 7236270Swpaul 7336270Swpaulstruct tl_list_onefrag { 7436270Swpaul u_int32_t tlist_fptr; 7536270Swpaul u_int16_t tlist_cstat; 7636270Swpaul u_int16_t tlist_frsize; 7736270Swpaul struct tl_frag tl_frag; 7836270Swpaul}; 7936270Swpaul 8036270Swpaulstruct tl_list_data { 8136270Swpaul struct tl_list_onefrag tl_rx_list[TL_RX_LIST_CNT]; 8236270Swpaul struct tl_list tl_tx_list[TL_TX_LIST_CNT]; 8336270Swpaul unsigned char tl_pad[TL_MIN_FRAMELEN]; 8436270Swpaul}; 8536270Swpaul 8636270Swpaulstruct tl_chain { 8736270Swpaul struct tl_list *tl_ptr; 8836270Swpaul struct mbuf *tl_mbuf; 8936270Swpaul struct tl_chain *tl_next; 9036270Swpaul}; 9136270Swpaul 9237626Swpaulstruct tl_chain_onefrag { 9337626Swpaul struct tl_list_onefrag *tl_ptr; 9437626Swpaul struct mbuf *tl_mbuf; 9537626Swpaul struct tl_chain_onefrag *tl_next; 9637626Swpaul}; 9737626Swpaul 9836270Swpaulstruct tl_chain_data { 9937626Swpaul struct tl_chain_onefrag tl_rx_chain[TL_RX_LIST_CNT]; 10036270Swpaul struct tl_chain tl_tx_chain[TL_TX_LIST_CNT]; 10136270Swpaul 10237626Swpaul struct tl_chain_onefrag *tl_rx_head; 10337626Swpaul struct tl_chain_onefrag *tl_rx_tail; 10436270Swpaul 10536270Swpaul struct tl_chain *tl_tx_head; 10636270Swpaul struct tl_chain *tl_tx_tail; 10736270Swpaul struct tl_chain *tl_tx_free; 10836270Swpaul}; 10936270Swpaul 11036270Swpaulstruct tl_softc { 111147256Sbrooks struct ifnet *tl_ifp; 112162317Sru device_t tl_dev; 11336270Swpaul struct ifmedia ifmedia; /* media info */ 11448992Swpaul void *tl_intrhand; 11548992Swpaul struct resource *tl_irq; 11648992Swpaul struct resource *tl_res; 11750462Swpaul device_t tl_miibus; 11839583Swpaul u_int8_t tl_eeaddr; 11936270Swpaul struct tl_list_data *tl_ldata; /* TX/RX lists and mbufs */ 12036270Swpaul struct tl_chain_data tl_cdata; 12145155Swpaul u_int8_t tl_txeoc; 12245155Swpaul u_int8_t tl_bitrate; 12350462Swpaul int tl_if_flags; 124150171Sjhb struct callout tl_stat_callout; 12567087Swpaul struct mtx tl_mtx; 126199560Sjhb int tl_timer; 12736270Swpaul}; 12836270Swpaul 12972200Sbmilekic#define TL_LOCK(_sc) mtx_lock(&(_sc)->tl_mtx) 13072200Sbmilekic#define TL_UNLOCK(_sc) mtx_unlock(&(_sc)->tl_mtx) 131122689Ssam#define TL_LOCK_ASSERT(_sc) mtx_assert(&(_sc)->tl_mtx, MA_OWNED) 13267087Swpaul 13337626Swpaul/* 13437626Swpaul * Transmit interrupt threshold. 13537626Swpaul */ 13640795Swpaul#define TX_THR 0x00000004 13736270Swpaul 13836270Swpaul/* 13936270Swpaul * General constants that are fun to know. 14036270Swpaul * 14136270Swpaul * The ThunderLAN controller is made by Texas Instruments. The 14236270Swpaul * manual indicates that if the EEPROM checksum fails, the PCI 14336270Swpaul * vendor and device ID registers will be loaded with TI-specific 14436270Swpaul * values. 14536270Swpaul */ 14636270Swpaul#define TI_VENDORID 0x104C 14736270Swpaul#define TI_DEVICEID_THUNDERLAN 0x0500 14836270Swpaul 14936270Swpaul/* 15036270Swpaul * These are the PCI vendor and device IDs for Compaq ethernet 15136270Swpaul * adapters based on the ThunderLAN controller. 15236270Swpaul */ 15336270Swpaul#define COMPAQ_VENDORID 0x0E11 15436270Swpaul#define COMPAQ_DEVICEID_NETEL_10_100 0xAE32 15539583Swpaul#define COMPAQ_DEVICEID_NETEL_UNKNOWN 0xAE33 15636270Swpaul#define COMPAQ_DEVICEID_NETEL_10 0xAE34 15736270Swpaul#define COMPAQ_DEVICEID_NETFLEX_3P_INTEGRATED 0xAE35 15836270Swpaul#define COMPAQ_DEVICEID_NETEL_10_100_DUAL 0xAE40 15936270Swpaul#define COMPAQ_DEVICEID_NETEL_10_100_PROLIANT 0xAE43 16037626Swpaul#define COMPAQ_DEVICEID_NETEL_10_100_EMBEDDED 0xB011 16137626Swpaul#define COMPAQ_DEVICEID_NETEL_10_T2_UTP_COAX 0xB012 16237626Swpaul#define COMPAQ_DEVICEID_NETEL_10_100_TX_UTP 0xB030 16336270Swpaul#define COMPAQ_DEVICEID_NETFLEX_3P 0xF130 16436270Swpaul#define COMPAQ_DEVICEID_NETFLEX_3P_BNC 0xF150 16536270Swpaul 16639583Swpaul/* 16739583Swpaul * These are the PCI vendor and device IDs for Olicom 16839583Swpaul * adapters based on the ThunderLAN controller. 16939583Swpaul */ 17037626Swpaul#define OLICOM_VENDORID 0x108D 17137626Swpaul#define OLICOM_DEVICEID_OC2183 0x0013 17237626Swpaul#define OLICOM_DEVICEID_OC2325 0x0012 17337626Swpaul#define OLICOM_DEVICEID_OC2326 0x0014 17437626Swpaul 17536270Swpaul/* 17636270Swpaul * PCI low memory base and low I/O base 17736270Swpaul */ 17836270Swpaul#define TL_PCI_LOIO 0x10 17936270Swpaul#define TL_PCI_LOMEM 0x14 18036270Swpaul 18136270Swpaul/* 18239583Swpaul * PCI latency timer (it's actually 0x0D, but we want a value 18339583Swpaul * that's longword aligned). 18436270Swpaul */ 18539583Swpaul#define TL_PCI_LATENCY_TIMER 0x0C 18636270Swpaul 18736270Swpaul#define TL_DIO_ADDR_INC 0x8000 /* Increment addr on each read */ 18836270Swpaul#define TL_DIO_RAM_SEL 0x4000 /* RAM address select */ 18936270Swpaul#define TL_DIO_ADDR_MASK 0x3FFF /* address bits mask */ 19036270Swpaul 19136270Swpaul/* 19236270Swpaul * Interrupt types 19336270Swpaul */ 19436270Swpaul#define TL_INTR_INVALID 0x0 19536270Swpaul#define TL_INTR_TXEOF 0x1 19636270Swpaul#define TL_INTR_STATOFLOW 0x2 19736270Swpaul#define TL_INTR_RXEOF 0x3 19836270Swpaul#define TL_INTR_DUMMY 0x4 19936270Swpaul#define TL_INTR_TXEOC 0x5 20036270Swpaul#define TL_INTR_ADCHK 0x6 20136270Swpaul#define TL_INTR_RXEOC 0x7 20236270Swpaul 20336270Swpaul#define TL_INT_MASK 0x001C 20436270Swpaul#define TL_VEC_MASK 0x1FE0 205226995Smarius 20636270Swpaul/* 20736270Swpaul * Host command register bits 20836270Swpaul */ 20936270Swpaul#define TL_CMD_GO 0x80000000 21036270Swpaul#define TL_CMD_STOP 0x40000000 21136270Swpaul#define TL_CMD_ACK 0x20000000 21236270Swpaul#define TL_CMD_CHSEL7 0x10000000 21336270Swpaul#define TL_CMD_CHSEL6 0x08000000 21436270Swpaul#define TL_CMD_CHSEL5 0x04000000 21536270Swpaul#define TL_CMD_CHSEL4 0x02000000 21636270Swpaul#define TL_CMD_CHSEL3 0x01000000 21736270Swpaul#define TL_CMD_CHSEL2 0x00800000 21836270Swpaul#define TL_CMD_CHSEL1 0x00400000 21936270Swpaul#define TL_CMD_CHSEL0 0x00200000 22036270Swpaul#define TL_CMD_EOC 0x00100000 22136270Swpaul#define TL_CMD_RT 0x00080000 22236270Swpaul#define TL_CMD_NES 0x00040000 22336270Swpaul#define TL_CMD_ZERO0 0x00020000 22436270Swpaul#define TL_CMD_ZERO1 0x00010000 22536270Swpaul#define TL_CMD_ADRST 0x00008000 22636270Swpaul#define TL_CMD_LDTMR 0x00004000 22736270Swpaul#define TL_CMD_LDTHR 0x00002000 22836270Swpaul#define TL_CMD_REQINT 0x00001000 22936270Swpaul#define TL_CMD_INTSOFF 0x00000800 23036270Swpaul#define TL_CMD_INTSON 0x00000400 23136270Swpaul#define TL_CMD_RSVD0 0x00000200 23236270Swpaul#define TL_CMD_RSVD1 0x00000100 23336270Swpaul#define TL_CMD_ACK7 0x00000080 23436270Swpaul#define TL_CMD_ACK6 0x00000040 23536270Swpaul#define TL_CMD_ACK5 0x00000020 23636270Swpaul#define TL_CMD_ACK4 0x00000010 23736270Swpaul#define TL_CMD_ACK3 0x00000008 23836270Swpaul#define TL_CMD_ACK2 0x00000004 23936270Swpaul#define TL_CMD_ACK1 0x00000002 24036270Swpaul#define TL_CMD_ACK0 0x00000001 24136270Swpaul 24236270Swpaul#define TL_CMD_CHSEL_MASK 0x01FE0000 24336270Swpaul#define TL_CMD_ACK_MASK 0xFF 24436270Swpaul 24536270Swpaul/* 24636270Swpaul * EEPROM address where station address resides. 24736270Swpaul */ 24836270Swpaul#define TL_EEPROM_EADDR 0x83 24936270Swpaul#define TL_EEPROM_EADDR2 0x99 25036270Swpaul#define TL_EEPROM_EADDR3 0xAF 25137626Swpaul#define TL_EEPROM_EADDR_OC 0xF8 /* Olicom cards use a different 25237626Swpaul address than Compaqs. */ 25336270Swpaul/* 25436270Swpaul * ThunderLAN host command register offsets. 25536270Swpaul * (Can be accessed either by IO ports or memory map.) 25636270Swpaul */ 25736270Swpaul#define TL_HOSTCMD 0x00 25836270Swpaul#define TL_CH_PARM 0x04 25936270Swpaul#define TL_DIO_ADDR 0x08 26036270Swpaul#define TL_HOST_INT 0x0A 26136270Swpaul#define TL_DIO_DATA 0x0C 26236270Swpaul 26336270Swpaul/* 26436270Swpaul * ThunderLAN internal registers 26536270Swpaul */ 26636270Swpaul#define TL_NETCMD 0x00 26736270Swpaul#define TL_NETSIO 0x01 26836270Swpaul#define TL_NETSTS 0x02 26936270Swpaul#define TL_NETMASK 0x03 27036270Swpaul 27136270Swpaul#define TL_NETCONFIG 0x04 27236270Swpaul#define TL_MANTEST 0x06 27336270Swpaul 27436270Swpaul#define TL_VENID_LSB 0x08 27536270Swpaul#define TL_VENID_MSB 0x09 27636270Swpaul#define TL_DEVID_LSB 0x0A 27736270Swpaul#define TL_DEVID_MSB 0x0B 27836270Swpaul 27936270Swpaul#define TL_REVISION 0x0C 28036270Swpaul#define TL_SUBCLASS 0x0D 28136270Swpaul#define TL_MINLAT 0x0E 28236270Swpaul#define TL_MAXLAT 0x0F 28336270Swpaul 28436270Swpaul#define TL_AREG0_B5 0x10 28536270Swpaul#define TL_AREG0_B4 0x11 28636270Swpaul#define TL_AREG0_B3 0x12 28736270Swpaul#define TL_AREG0_B2 0x13 28836270Swpaul 28936270Swpaul#define TL_AREG0_B1 0x14 29036270Swpaul#define TL_AREG0_B0 0x15 29136270Swpaul#define TL_AREG1_B5 0x16 29236270Swpaul#define TL_AREG1_B4 0x17 29336270Swpaul 29436270Swpaul#define TL_AREG1_B3 0x18 29536270Swpaul#define TL_AREG1_B2 0x19 29636270Swpaul#define TL_AREG1_B1 0x1A 29736270Swpaul#define TL_AREG1_B0 0x1B 29836270Swpaul 29936270Swpaul#define TL_AREG2_B5 0x1C 30036270Swpaul#define TL_AREG2_B4 0x1D 30136270Swpaul#define TL_AREG2_B3 0x1E 30236270Swpaul#define TL_AREG2_B2 0x1F 30336270Swpaul 30436270Swpaul#define TL_AREG2_B1 0x20 30536270Swpaul#define TL_AREG2_B0 0x21 30636270Swpaul#define TL_AREG3_B5 0x22 30736270Swpaul#define TL_AREG3_B4 0x23 30836270Swpaul 30936270Swpaul#define TL_AREG3_B3 0x24 31036270Swpaul#define TL_AREG3_B2 0x25 31136270Swpaul#define TL_AREG3_B1 0x26 31236270Swpaul#define TL_AREG3_B0 0x27 31336270Swpaul 31436270Swpaul#define TL_HASH1 0x28 31536270Swpaul#define TL_HASH2 0x2C 31636270Swpaul#define TL_TXGOODFRAMES 0x30 31736270Swpaul#define TL_TXUNDERRUN 0x33 31836270Swpaul#define TL_RXGOODFRAMES 0x34 31936270Swpaul#define TL_RXOVERRUN 0x37 32036270Swpaul#define TL_DEFEREDTX 0x38 32136270Swpaul#define TL_CRCERROR 0x3A 32236270Swpaul#define TL_CODEERROR 0x3B 32336270Swpaul#define TL_MULTICOLTX 0x3C 32436270Swpaul#define TL_SINGLECOLTX 0x3E 32536270Swpaul#define TL_EXCESSIVECOL 0x40 32636270Swpaul#define TL_LATECOL 0x41 32736270Swpaul#define TL_CARRIERLOSS 0x42 32836270Swpaul#define TL_ACOMMIT 0x43 32936270Swpaul#define TL_LDREG 0x44 33036270Swpaul#define TL_BSIZEREG 0x45 33136270Swpaul#define TL_MAXRX 0x46 33236270Swpaul 33336270Swpaul/* 33436270Swpaul * ThunderLAN SIO register bits 33536270Swpaul */ 33636270Swpaul#define TL_SIO_MINTEN 0x80 33736270Swpaul#define TL_SIO_ECLOK 0x40 33836270Swpaul#define TL_SIO_ETXEN 0x20 33936270Swpaul#define TL_SIO_EDATA 0x10 34036270Swpaul#define TL_SIO_NMRST 0x08 34136270Swpaul#define TL_SIO_MCLK 0x04 34236270Swpaul#define TL_SIO_MTXEN 0x02 34336270Swpaul#define TL_SIO_MDATA 0x01 34436270Swpaul 34536270Swpaul/* 34636270Swpaul * Thunderlan NETCONFIG bits 34736270Swpaul */ 34836270Swpaul#define TL_CFG_RCLKTEST 0x8000 34936270Swpaul#define TL_CFG_TCLKTEST 0x4000 35036270Swpaul#define TL_CFG_BITRATE 0x2000 35136270Swpaul#define TL_CFG_RXCRC 0x1000 35236270Swpaul#define TL_CFG_PEF 0x0800 35336270Swpaul#define TL_CFG_ONEFRAG 0x0400 35436270Swpaul#define TL_CFG_ONECHAN 0x0200 35536270Swpaul#define TL_CFG_MTEST 0x0100 35636270Swpaul#define TL_CFG_PHYEN 0x0080 35736270Swpaul#define TL_CFG_MACSEL6 0x0040 35836270Swpaul#define TL_CFG_MACSEL5 0x0020 35936270Swpaul#define TL_CFG_MACSEL4 0x0010 36036270Swpaul#define TL_CFG_MACSEL3 0x0008 36136270Swpaul#define TL_CFG_MACSEL2 0x0004 36236270Swpaul#define TL_CFG_MACSEL1 0x0002 36336270Swpaul#define TL_CFG_MACSEL0 0x0001 36436270Swpaul 36536270Swpaul/* 36636270Swpaul * ThunderLAN NETSTS bits 36736270Swpaul */ 36836270Swpaul#define TL_STS_MIRQ 0x80 36936270Swpaul#define TL_STS_HBEAT 0x40 37036270Swpaul#define TL_STS_TXSTOP 0x20 37136270Swpaul#define TL_STS_RXSTOP 0x10 37236270Swpaul 37336270Swpaul/* 37436270Swpaul * ThunderLAN NETCMD bits 37536270Swpaul */ 37636270Swpaul#define TL_CMD_NRESET 0x80 37736270Swpaul#define TL_CMD_NWRAP 0x40 37836270Swpaul#define TL_CMD_CSF 0x20 37936270Swpaul#define TL_CMD_CAF 0x10 38036270Swpaul#define TL_CMD_NOBRX 0x08 38136270Swpaul#define TL_CMD_DUPLEX 0x04 38236270Swpaul#define TL_CMD_TRFRAM 0x02 38336270Swpaul#define TL_CMD_TXPACE 0x01 38436270Swpaul 38536270Swpaul/* 38636270Swpaul * ThunderLAN NETMASK bits 38736270Swpaul */ 38836270Swpaul#define TL_MASK_MASK7 0x80 38936270Swpaul#define TL_MASK_MASK6 0x40 39036270Swpaul#define TL_MASK_MASK5 0x20 39136270Swpaul#define TL_MASK_MASK4 0x10 39236270Swpaul 39336270Swpaul#define TL_LAST_FRAG 0x80000000 39436270Swpaul#define TL_CSTAT_UNUSED 0x8000 39536270Swpaul#define TL_CSTAT_FRAMECMP 0x4000 39636270Swpaul#define TL_CSTAT_READY 0x3000 39736270Swpaul#define TL_CSTAT_UNUSED13 0x2000 39836270Swpaul#define TL_CSTAT_UNUSED12 0x1000 39936270Swpaul#define TL_CSTAT_EOC 0x0800 40036270Swpaul#define TL_CSTAT_RXERROR 0x0400 40136270Swpaul#define TL_CSTAT_PASSCRC 0x0200 40236270Swpaul#define TL_CSTAT_DPRIO 0x0100 40336270Swpaul 40436270Swpaul#define TL_FRAME_MASK 0x00FFFFFF 40536270Swpaul#define tl_tx_goodframes(x) (x.tl_txstat & TL_FRAME_MASK) 40636270Swpaul#define tl_tx_underrun(x) ((x.tl_txstat & ~TL_FRAME_MASK) >> 24) 40736270Swpaul#define tl_rx_goodframes(x) (x.tl_rxstat & TL_FRAME_MASK) 40836270Swpaul#define tl_rx_overrun(x) ((x.tl_rxstat & ~TL_FRAME_MASK) >> 24) 40936270Swpaul 41036270Swpaulstruct tl_stats { 41136270Swpaul u_int32_t tl_txstat; 41236270Swpaul u_int32_t tl_rxstat; 41336270Swpaul u_int16_t tl_deferred; 41436270Swpaul u_int8_t tl_crc_errors; 41536270Swpaul u_int8_t tl_code_errors; 41636270Swpaul u_int16_t tl_tx_multi_collision; 41736270Swpaul u_int16_t tl_tx_single_collision; 41836270Swpaul u_int8_t tl_excessive_collision; 41936270Swpaul u_int8_t tl_late_collision; 42036270Swpaul u_int8_t tl_carrier_loss; 42136270Swpaul u_int8_t acommit; 42236270Swpaul}; 42336270Swpaul 42436270Swpaul/* 42545155Swpaul * ACOMMIT register bits. These are used only when a bitrate 42645155Swpaul * PHY is selected ('bitrate' bit in netconfig register is set). 42745155Swpaul */ 42845155Swpaul#define TL_AC_MTXER 0x01 /* reserved */ 42945155Swpaul#define TL_AC_MTXD1 0x02 /* 0 == 10baseT 1 == AUI */ 43045155Swpaul#define TL_AC_MTXD2 0x04 /* loopback disable */ 43145155Swpaul#define TL_AC_MTXD3 0x08 /* full duplex disable */ 43245155Swpaul 43351439Swpaul#define TL_AC_TXTHRESH 0xF0 43451439Swpaul#define TL_AC_TXTHRESH_16LONG 0x00 43551439Swpaul#define TL_AC_TXTHRESH_32LONG 0x10 43651439Swpaul#define TL_AC_TXTHRESH_64LONG 0x20 43751439Swpaul#define TL_AC_TXTHRESH_128LONG 0x30 43851439Swpaul#define TL_AC_TXTHRESH_256LONG 0x40 43951439Swpaul#define TL_AC_TXTHRESH_WHOLEPKT 0x50 44051439Swpaul 44145155Swpaul/* 44251439Swpaul * PCI burst size register (TL_BSIZEREG). 44351439Swpaul */ 44451439Swpaul#define TL_RXBURST 0x0F 44551439Swpaul#define TL_TXBURST 0xF0 44651439Swpaul 44751439Swpaul#define TL_RXBURST_4LONG 0x00 44851439Swpaul#define TL_RXBURST_8LONG 0x01 44951439Swpaul#define TL_RXBURST_16LONG 0x02 45051439Swpaul#define TL_RXBURST_32LONG 0x03 45151439Swpaul#define TL_RXBURST_64LONG 0x04 45251439Swpaul#define TL_RXBURST_128LONG 0x05 45351439Swpaul 45451439Swpaul#define TL_TXBURST_4LONG 0x00 45551439Swpaul#define TL_TXBURST_8LONG 0x10 45651439Swpaul#define TL_TXBURST_16LONG 0x20 45751439Swpaul#define TL_TXBURST_32LONG 0x30 45851439Swpaul#define TL_TXBURST_64LONG 0x40 45951439Swpaul#define TL_TXBURST_128LONG 0x50 46051439Swpaul 46151439Swpaul/* 46239583Swpaul * register space access macros 46339583Swpaul */ 464199414Sjhb#define CSR_WRITE_4(sc, reg, val) bus_write_4(sc->tl_res, reg, val) 465199414Sjhb#define CSR_WRITE_2(sc, reg, val) bus_write_2(sc->tl_res, reg, val) 466199414Sjhb#define CSR_WRITE_1(sc, reg, val) bus_write_1(sc->tl_res, reg, val) 46739583Swpaul 468199414Sjhb#define CSR_READ_4(sc, reg) bus_read_4(sc->tl_res, reg) 469199414Sjhb#define CSR_READ_2(sc, reg) bus_read_2(sc->tl_res, reg) 470199414Sjhb#define CSR_READ_1(sc, reg) bus_read_1(sc->tl_res, reg) 47139583Swpaul 472226995Smarius#define CSR_BARRIER(sc, reg, length, flags) \ 473226995Smarius bus_barrier(sc->tl_res, reg, length, flags) 474226995Smarius 47539583Swpaul#define CMD_PUT(sc, x) CSR_WRITE_4(sc, TL_HOSTCMD, x) 47639583Swpaul#define CMD_SET(sc, x) \ 47739583Swpaul CSR_WRITE_4(sc, TL_HOSTCMD, CSR_READ_4(sc, TL_HOSTCMD) | (x)) 47839583Swpaul#define CMD_CLR(sc, x) \ 47939583Swpaul CSR_WRITE_4(sc, TL_HOSTCMD, CSR_READ_4(sc, TL_HOSTCMD) & ~(x)) 48039583Swpaul 48139583Swpaul/* 48239583Swpaul * ThunderLAN adapters typically have a serial EEPROM containing 48339583Swpaul * configuration information. The main reason we're interested in 48439583Swpaul * it is because it also contains the adapters's station address. 48539583Swpaul * 48639583Swpaul * Access to the EEPROM is a bit goofy since it is a serial device: 48739583Swpaul * you have to do reads and writes one bit at a time. The state of 48839583Swpaul * the DATA bit can only change while the CLOCK line is held low. 48939583Swpaul * Transactions work basically like this: 49039583Swpaul * 49139583Swpaul * 1) Send the EEPROM_START sequence to prepare the EEPROM for 49239583Swpaul * accepting commands. This pulls the clock high, sets 49339583Swpaul * the data bit to 0, enables transmission to the EEPROM, 49439583Swpaul * pulls the data bit up to 1, then pulls the clock low. 49539583Swpaul * The idea is to do a 0 to 1 transition of the data bit 49639583Swpaul * while the clock pin is held high. 49739583Swpaul * 49839583Swpaul * 2) To write a bit to the EEPROM, set the TXENABLE bit, then 49939583Swpaul * set the EDATA bit to send a 1 or clear it to send a 0. 50039583Swpaul * Finally, set and then clear ECLOK. Strobing the clock 50139583Swpaul * transmits the bit. After 8 bits have been written, the 50239583Swpaul * EEPROM should respond with an ACK, which should be read. 50339583Swpaul * 50439583Swpaul * 3) To read a bit from the EEPROM, clear the TXENABLE bit, 50539583Swpaul * then set ECLOK. The bit can then be read by reading EDATA. 50639583Swpaul * ECLOCK should then be cleared again. This can be repeated 50739583Swpaul * 8 times to read a whole byte, after which the 50839583Swpaul * 50939583Swpaul * 4) We need to send the address byte to the EEPROM. For this 51039583Swpaul * we have to send the write control byte to the EEPROM to 51139583Swpaul * tell it to accept data. The byte is 0xA0. The EEPROM should 51239583Swpaul * ack this. The address byte can be send after that. 51339583Swpaul * 51439583Swpaul * 5) Now we have to tell the EEPROM to send us data. For that we 51539583Swpaul * have to transmit the read control byte, which is 0xA1. This 51639583Swpaul * byte should also be acked. We can then read the data bits 51739583Swpaul * from the EEPROM. 51839583Swpaul * 51939583Swpaul * 6) When we're all finished, send the EEPROM_STOP sequence. 52039583Swpaul * 52139583Swpaul * Note that we use the ThunderLAN's NetSio register to access the 52239583Swpaul * EEPROM, however there is an alternate method. There is a PCI NVRAM 52339583Swpaul * register at PCI offset 0xB4 which can also be used with minor changes. 52439583Swpaul * The difference is that access to PCI registers via pci_conf_read() 52539583Swpaul * and pci_conf_write() is done using programmed I/O, which we want to 52639583Swpaul * avoid. 52739583Swpaul */ 52839583Swpaul 52939583Swpaul/* 53039583Swpaul * Note that EEPROM_START leaves transmission enabled. 53139583Swpaul */ 53239583Swpaul#define EEPROM_START \ 53339583Swpaul tl_dio_setbit(sc, TL_NETSIO, TL_SIO_ECLOK); /* Pull clock pin high */\ 53439583Swpaul tl_dio_setbit(sc, TL_NETSIO, TL_SIO_EDATA); /* Set DATA bit to 1 */ \ 53539583Swpaul tl_dio_setbit(sc, TL_NETSIO, TL_SIO_ETXEN); /* Enable xmit to write bit */\ 53639583Swpaul tl_dio_clrbit(sc, TL_NETSIO, TL_SIO_EDATA); /* Pull DATA bit to 0 again */\ 53739583Swpaul tl_dio_clrbit(sc, TL_NETSIO, TL_SIO_ECLOK); /* Pull clock low again */ 53839583Swpaul 53939583Swpaul/* 54039583Swpaul * EEPROM_STOP ends access to the EEPROM and clears the ETXEN bit so 54139583Swpaul * that no further data can be written to the EEPROM I/O pin. 54239583Swpaul */ 54339583Swpaul#define EEPROM_STOP \ 54439583Swpaul tl_dio_clrbit(sc, TL_NETSIO, TL_SIO_ETXEN); /* Disable xmit */ \ 54539583Swpaul tl_dio_clrbit(sc, TL_NETSIO, TL_SIO_EDATA); /* Pull DATA to 0 */ \ 54639583Swpaul tl_dio_setbit(sc, TL_NETSIO, TL_SIO_ECLOK); /* Pull clock high */ \ 54739583Swpaul tl_dio_setbit(sc, TL_NETSIO, TL_SIO_ETXEN); /* Enable xmit */ \ 54839583Swpaul tl_dio_setbit(sc, TL_NETSIO, TL_SIO_EDATA); /* Toggle DATA to 1 */ \ 54939583Swpaul tl_dio_clrbit(sc, TL_NETSIO, TL_SIO_ETXEN); /* Disable xmit. */ \ 55039583Swpaul tl_dio_clrbit(sc, TL_NETSIO, TL_SIO_ECLOK); /* Pull clock low again */ 55139583Swpaul 55239583Swpaul 55339583Swpaul/* 55436270Swpaul * Microchip Technology 24Cxx EEPROM control bytes 55536270Swpaul */ 55636270Swpaul#define EEPROM_CTL_READ 0xA1 /* 0101 0001 */ 55736270Swpaul#define EEPROM_CTL_WRITE 0xA0 /* 0101 0000 */ 558