1160641Syongari/* $NetBSD: if_stgereg.h,v 1.3 2003/02/10 21:10:07 christos Exp $ */ 2160641Syongari 3160641Syongari/*- 4160641Syongari * Copyright (c) 2001 The NetBSD Foundation, Inc. 5160641Syongari * All rights reserved. 6160641Syongari * 7160641Syongari * This code is derived from software contributed to The NetBSD Foundation 8160641Syongari * by Jason R. Thorpe. 9160641Syongari * 10160641Syongari * Redistribution and use in source and binary forms, with or without 11160641Syongari * modification, are permitted provided that the following conditions 12160641Syongari * are met: 13160641Syongari * 1. Redistributions of source code must retain the above copyright 14160641Syongari * notice, this list of conditions and the following disclaimer. 15160641Syongari * 2. Redistributions in binary form must reproduce the above copyright 16160641Syongari * notice, this list of conditions and the following disclaimer in the 17160641Syongari * documentation and/or other materials provided with the distribution. 18160641Syongari * 19160641Syongari * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 20160641Syongari * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 21160641Syongari * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 22160641Syongari * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 23160641Syongari * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 24160641Syongari * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 25160641Syongari * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 26160641Syongari * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 27160641Syongari * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 28160641Syongari * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 29160641Syongari * POSSIBILITY OF SUCH DAMAGE. 30160641Syongari */ 31160641Syongari 32160641Syongari/* $FreeBSD$ */ 33160641Syongari 34160641Syongari/* 35160641Syongari * Sundance Technology PCI vendor ID 36160641Syongari */ 37160641Syongari#define VENDOR_SUNDANCETI 0x13f0 38160641Syongari 39160641Syongari/* 40160641Syongari * Tamarack Microelectronics PCI vendor ID 41160641Syongari */ 42160641Syongari#define VENDOR_TAMARACK 0x143d 43160641Syongari 44160641Syongari/* 45160641Syongari * D-Link Systems PCI vendor ID 46160641Syongari */ 47160641Syongari#define VENDOR_DLINK 0x1186 48160641Syongari 49160641Syongari/* 50160641Syongari * Antares Microsystems PCI vendor ID 51160641Syongari */ 52160641Syongari#define VENDOR_ANTARES 0x1754 53160641Syongari 54160641Syongari/* 55160641Syongari * Sundance Technology device ID 56160641Syongari */ 57160641Syongari#define DEVICEID_SUNDANCETI_ST1023 0x1023 58160641Syongari#define DEVICEID_SUNDANCETI_ST2021 0x2021 59160641Syongari#define DEVICEID_TAMARACK_TC9021 0x1021 60160641Syongari#define DEVICEID_TAMARACK_TC9021_ALT 0x9021 61160641Syongari 62160641Syongari/* 63160641Syongari * D-Link Systems device ID 64160641Syongari */ 65160641Syongari#define DEVICEID_DLINK_DL4000 0x4000 66160641Syongari 67160641Syongari/* 68160641Syongari * Antares Microsystems device ID 69160641Syongari */ 70160641Syongari#define DEVICEID_ANTARES_TC9021 0x1021 71160641Syongari 72160641Syongari/* 73160641Syongari * Register description for the Sundance Tech. TC9021 10/100/1000 74160641Syongari * Ethernet controller. 75160641Syongari * 76160641Syongari * Note that while DMA addresses are all in 64-bit fields, only 77160641Syongari * the lower 40 bits of a DMA address are valid. 78160641Syongari */ 79160641Syongari#if (BUS_SPACE_MAXADDR < 0xFFFFFFFFFF) 80160641Syongari#define STGE_DMA_MAXADDR BUS_SPACE_MAXADDR 81160641Syongari#else 82160641Syongari#define STGE_DMA_MAXADDR 0xFFFFFFFFFF 83160641Syongari#endif 84160641Syongari 85160641Syongari/* 86160641Syongari * Register access macros 87160641Syongari */ 88160641Syongari#define CSR_WRITE_4(_sc, reg, val) \ 89160641Syongari bus_write_4((_sc)->sc_res[0], (reg), (val)) 90160641Syongari#define CSR_WRITE_2(_sc, reg, val) \ 91160641Syongari bus_write_2((_sc)->sc_res[0], (reg), (val)) 92160641Syongari#define CSR_WRITE_1(_sc, reg, val) \ 93160641Syongari bus_write_1((_sc)->sc_res[0], (reg), (val)) 94160641Syongari 95160641Syongari#define CSR_READ_4(_sc, reg) \ 96160641Syongari bus_read_4((_sc)->sc_res[0], (reg)) 97160641Syongari#define CSR_READ_2(_sc, reg) \ 98160641Syongari bus_read_2((_sc)->sc_res[0], (reg)) 99160641Syongari#define CSR_READ_1(_sc, reg) \ 100160641Syongari bus_read_1((_sc)->sc_res[0], (reg)) 101160641Syongari 102226995Smarius#define CSR_BARRIER(_sc, reg, length, flags) \ 103226995Smarius bus_barrier((_sc)->sc_res[0], reg, length, flags) 104226995Smarius 105160641Syongari/* 106160641Syongari * TC9021 buffer fragment descriptor. 107160641Syongari */ 108160641Syongaristruct stge_frag { 109160641Syongari uint64_t frag_word0; /* address, length */ 110160641Syongari}; 111160641Syongari 112160641Syongari#define FRAG_ADDR(x) (((uint64_t)(x)) << 0) 113160641Syongari#define FRAG_ADDR_MASK FRAG_ADDR(0xfffffffffULL) 114160641Syongari#define FRAG_LEN(x) (((uint64_t)(x)) << 48) 115160641Syongari#define FRAG_LEN_MASK FRAG_LEN(0xffffULL) 116160641Syongari 117160641Syongari/* 118160641Syongari * TC9021 Transmit Frame Descriptor. Note the number of fragments 119160641Syongari * here is arbitrary, but we can't have any more than 15. 120160641Syongari */ 121160641Syongari#define STGE_NTXFRAGS 15 122160641Syongaristruct stge_tfd { 123160641Syongari uint64_t tfd_next; /* next TFD in list */ 124160641Syongari uint64_t tfd_control; /* control bits */ 125160641Syongari /* the buffer fragments */ 126160641Syongari struct stge_frag tfd_frags[STGE_NTXFRAGS]; 127160641Syongari}; 128160641Syongari 129160641Syongari#define TFD_FrameId(x) ((x) << 0) 130160641Syongari#define TFD_FrameId_MAX 0xffff 131160641Syongari#define TFD_WordAlign(x) ((x) << 16) 132160641Syongari#define TFD_WordAlign_dword 0 /* align to dword in TxFIFO */ 133160641Syongari#define TFD_WordAlign_word 2 /* align to word in TxFIFO */ 134160641Syongari#define TFD_WordAlign_disable 1 /* disable alignment */ 135160641Syongari#define TFD_TCPChecksumEnable (1ULL << 18) 136160641Syongari#define TFD_UDPChecksumEnable (1ULL << 19) 137160641Syongari#define TFD_IPChecksumEnable (1ULL << 20) 138160641Syongari#define TFD_FcsAppendDisable (1ULL << 21) 139160641Syongari#define TFD_TxIndicate (1ULL << 22) 140160641Syongari#define TFD_TxDMAIndicate (1ULL << 23) 141160641Syongari#define TFD_FragCount(x) ((x) << 24) 142160641Syongari#define TFD_VLANTagInsert (1ULL << 28) 143160641Syongari#define TFD_TFDDone (1ULL << 31) 144160641Syongari#define TFD_VID(x) (((uint64_t)(x)) << 32) 145160641Syongari#define TFD_CFI (1ULL << 44) 146160641Syongari#define TFD_UserPriority(x) (((uint64_t)(x)) << 45) 147160641Syongari 148160641Syongari/* 149160641Syongari * TC9021 Receive Frame Descriptor. Each RFD has a single fragment 150160641Syongari * in it, and the chip tells us the beginning and end of the frame. 151160641Syongari */ 152160641Syongaristruct stge_rfd { 153160641Syongari uint64_t rfd_next; /* next RFD in list */ 154160641Syongari uint64_t rfd_status; /* status bits */ 155160641Syongari struct stge_frag rfd_frag; /* the buffer */ 156160641Syongari}; 157160641Syongari 158160641Syongari/* Low word of rfd_status */ 159160641Syongari#define RFD_RxStatus(x) ((x) & 0xffffffff) 160160641Syongari#define RFD_RxDMAFrameLen(x) ((x) & 0xffff) 161160641Syongari#define RFD_RxFIFOOverrun 0x00010000 162160641Syongari#define RFD_RxRuntFrame 0x00020000 163160641Syongari#define RFD_RxAlignmentError 0x00040000 164160641Syongari#define RFD_RxFCSError 0x00080000 165160641Syongari#define RFD_RxOversizedFrame 0x00100000 166160641Syongari#define RFD_RxLengthError 0x00200000 167160641Syongari#define RFD_VLANDetected 0x00400000 168160641Syongari#define RFD_TCPDetected 0x00800000 169160641Syongari#define RFD_TCPError 0x01000000 170160641Syongari#define RFD_UDPDetected 0x02000000 171160641Syongari#define RFD_UDPError 0x04000000 172160641Syongari#define RFD_IPDetected 0x08000000 173160641Syongari#define RFD_IPError 0x10000000 174160641Syongari#define RFD_FrameStart 0x20000000 175160641Syongari#define RFD_FrameEnd 0x40000000 176160641Syongari#define RFD_RFDDone 0x80000000 177160641Syongari/* High word of rfd_status */ 178160641Syongari#define RFD_TCI(x) ((((uint64_t)(x)) >> 32) & 0xffff) 179160641Syongari 180160641Syongari/* 181160641Syongari * EEPROM offsets. 182160641Syongari */ 183160641Syongari#define STGE_EEPROM_ConfigParam 0x00 184160641Syongari#define STGE_EEPROM_AsicCtrl 0x01 185160641Syongari#define STGE_EEPROM_SubSystemVendorId 0x02 186160641Syongari#define STGE_EEPROM_SubSystemId 0x03 187160641Syongari#define STGE_EEPROM_LEDMode 0x06 188160641Syongari#define STGE_EEPROM_StationAddress0 0x10 189160641Syongari#define STGE_EEPROM_StationAddress1 0x11 190160641Syongari#define STGE_EEPROM_StationAddress2 0x12 191160641Syongari 192160641Syongari/* 193160641Syongari * The TC9021 register space. 194160641Syongari */ 195160641Syongari 196160641Syongari#define STGE_DMACtrl 0x00 197160641Syongari#define DMAC_RxDMAComplete (1U << 3) 198160641Syongari#define DMAC_RxDMAPollNow (1U << 4) 199160641Syongari#define DMAC_TxDMAComplete (1U << 11) 200160641Syongari#define DMAC_TxDMAPollNow (1U << 12) 201160641Syongari#define DMAC_TxDMAInProg (1U << 15) 202160641Syongari#define DMAC_RxEarlyDisable (1U << 16) 203160641Syongari#define DMAC_MWIDisable (1U << 18) 204160641Syongari#define DMAC_TxWriteBackDisable (1U << 19) 205160641Syongari#define DMAC_TxBurstLimit(x) ((x) << 20) 206160641Syongari#define DMAC_TargetAbort (1U << 30) 207160641Syongari#define DMAC_MasterAbort (1U << 31) 208160641Syongari 209160641Syongari#define STGE_RxDMAStatus 0x08 210160641Syongari 211160641Syongari#define STGE_TFDListPtrLo 0x10 212160641Syongari 213160641Syongari#define STGE_TFDListPtrHi 0x14 214160641Syongari 215160641Syongari#define STGE_TxDMABurstThresh 0x18 /* 8-bit */ 216160641Syongari 217160641Syongari#define STGE_TxDMAUrgentThresh 0x19 /* 8-bit */ 218160641Syongari 219160641Syongari#define STGE_TxDMAPollPeriod 0x1a /* 8-bit, 320ns increments */ 220160641Syongari 221160641Syongari#define STGE_RFDListPtrLo 0x1c 222160641Syongari 223160641Syongari#define STGE_RFDListPtrHi 0x20 224160641Syongari 225160641Syongari#define STGE_RxDMABurstThresh 0x24 /* 8-bit */ 226160641Syongari 227160641Syongari#define STGE_RxDMAUrgentThresh 0x25 /* 8-bit */ 228160641Syongari 229160641Syongari#define STGE_RxDMAPollPeriod 0x26 /* 8-bit, 320ns increments */ 230160641Syongari 231160641Syongari#define STGE_RxDMAIntCtrl 0x28 232160641Syongari#define RDIC_RxFrameCount(x) ((x) & 0xff) 233160641Syongari#define RDIC_PriorityThresh(x) ((x) << 10) 234160641Syongari#define RDIC_RxDMAWaitTime(x) ((x) << 16) 235160641Syongari/* 236160641Syongari * Number of receive frames transferred via DMA before a Rx interrupt is issued. 237160641Syongari */ 238160641Syongari#define STGE_RXINT_NFRAME_DEFAULT 8 239160641Syongari#define STGE_RXINT_NFRAME_MIN 1 240160641Syongari#define STGE_RXINT_NFRAME_MAX 255 241160641Syongari/* 242160641Syongari * Maximum amount of time (in 64ns increments) to wait before issuing a Rx 243160641Syongari * interrupt if number of frames recevied is less than STGE_RXINT_NFRAME 244160641Syongari * (STGE_RXINT_NFRAME_MIN <= STGE_RXINT_NFRAME <= STGE_RXINT_NFRAME_MAX) 245160641Syongari */ 246160641Syongari#define STGE_RXINT_DMAWAIT_DEFAULT 30 /* 30us */ 247160641Syongari#define STGE_RXINT_DMAWAIT_MIN 0 248160641Syongari#define STGE_RXINT_DMAWAIT_MAX 4194 249160641Syongari#define STGE_RXINT_USECS2TICK(x) (((x) * 1000)/64) 250160641Syongari 251160641Syongari#define STGE_DebugCtrl 0x2c /* 16-bit */ 252160641Syongari#define DC_GPIO0Ctrl (1U << 0) 253160641Syongari#define DC_GPIO1Ctrl (1U << 1) 254160641Syongari#define DC_GPIO0 (1U << 2) 255160641Syongari#define DC_GPIO1 (1U << 3) 256160641Syongari 257160641Syongari#define STGE_AsicCtrl 0x30 258160641Syongari#define AC_ExpRomDisable (1U << 0) 259160641Syongari#define AC_ExpRomSize (1U << 1) 260160641Syongari#define AC_PhySpeed10 (1U << 4) 261160641Syongari#define AC_PhySpeed100 (1U << 5) 262160641Syongari#define AC_PhySpeed1000 (1U << 6) 263160641Syongari#define AC_PhyMedia (1U << 7) 264160641Syongari#define AC_ForcedConfig(x) ((x) << 8) 265160641Syongari#define AC_ForcedConfig_MASK AC_ForcedConfig(7) 266160641Syongari#define AC_D3ResetDisable (1U << 11) 267160641Syongari#define AC_SpeedupMode (1U << 13) 268160641Syongari#define AC_LEDMode (1U << 14) 269160641Syongari#define AC_RstOutPolarity (1U << 15) 270160641Syongari#define AC_GlobalReset (1U << 16) 271160641Syongari#define AC_RxReset (1U << 17) 272160641Syongari#define AC_TxReset (1U << 18) 273160641Syongari#define AC_DMA (1U << 19) 274160641Syongari#define AC_FIFO (1U << 20) 275160641Syongari#define AC_Network (1U << 21) 276160641Syongari#define AC_Host (1U << 22) 277160641Syongari#define AC_AutoInit (1U << 23) 278160641Syongari#define AC_RstOut (1U << 24) 279160641Syongari#define AC_InterruptRequest (1U << 25) 280160641Syongari#define AC_ResetBusy (1U << 26) 281160641Syongari#define AC_LEDSpeed (1U << 27) 282160641Syongari#define AC_LEDModeBit1 (1U << 29) 283160641Syongari 284160641Syongari#define STGE_FIFOCtrl 0x38 /* 16-bit */ 285160641Syongari#define FC_RAMTestMode (1U << 0) 286160641Syongari#define FC_Transmitting (1U << 14) 287160641Syongari#define FC_Receiving (1U << 15) 288160641Syongari 289160641Syongari#define STGE_RxEarlyThresh 0x3a /* 16-bit */ 290160641Syongari 291160641Syongari#define STGE_FlowOffThresh 0x3c /* 16-bit */ 292160641Syongari 293160641Syongari#define STGE_FlowOnTresh 0x3e /* 16-bit */ 294160641Syongari 295160641Syongari#define STGE_TxStartThresh 0x44 /* 16-bit */ 296160641Syongari 297160641Syongari#define STGE_EepromData 0x48 /* 16-bit */ 298160641Syongari 299160641Syongari#define STGE_EepromCtrl 0x4a /* 16-bit */ 300160641Syongari#define EC_EepromAddress(x) ((x) & 0xff) 301160641Syongari#define EC_EepromOpcode(x) ((x) << 8) 302160641Syongari#define EC_OP_WE 0 303160641Syongari#define EC_OP_WR 1 304160641Syongari#define EC_OP_RR 2 305160641Syongari#define EC_OP_ER 3 306160641Syongari#define EC_EepromBusy (1U << 15) 307160641Syongari 308160641Syongari#define STGE_ExpRomAddr 0x4c 309160641Syongari 310160641Syongari#define STGE_ExpRomData 0x50 /* 8-bit */ 311160641Syongari 312160641Syongari#define STGE_WakeEvent 0x51 /* 8-bit */ 313175315Syongari#define WE_WakePktEnable (1U << 0) 314175315Syongari#define WE_MagicPktEnable (1U << 1) 315175315Syongari#define WE_LinkEventEnable (1U << 2) 316175315Syongari#define WE_WakePolarity (1U << 3) 317175315Syongari#define WE_WakePktEvent (1U << 4) 318175315Syongari#define WE_MagicPktEvent (1U << 5) 319175315Syongari#define WE_LinkEvent (1U << 6) 320175315Syongari#define WE_WakeOnLanEnable (1U << 7) 321160641Syongari 322160641Syongari#define STGE_Countdown 0x54 323160641Syongari#define CD_Count(x) ((x) & 0xffff) 324160641Syongari#define CD_CountdownSpeed (1U << 24) 325160641Syongari#define CD_CountdownMode (1U << 25) 326160641Syongari#define CD_CountdownIntEnabled (1U << 26) 327160641Syongari 328160641Syongari#define STGE_IntStatusAck 0x5a /* 16-bit */ 329160641Syongari 330160641Syongari#define STGE_IntEnable 0x5c /* 16-bit */ 331160641Syongari 332160641Syongari#define STGE_IntStatus 0x5e /* 16-bit */ 333160641Syongari 334160641Syongari#define IS_InterruptStatus (1U << 0) 335160641Syongari#define IS_HostError (1U << 1) 336160641Syongari#define IS_TxComplete (1U << 2) 337160641Syongari#define IS_MACControlFrame (1U << 3) 338160641Syongari#define IS_RxComplete (1U << 4) 339160641Syongari#define IS_RxEarly (1U << 5) 340160641Syongari#define IS_InRequested (1U << 6) 341160641Syongari#define IS_UpdateStats (1U << 7) 342160641Syongari#define IS_LinkEvent (1U << 8) 343160641Syongari#define IS_TxDMAComplete (1U << 9) 344160641Syongari#define IS_RxDMAComplete (1U << 10) 345160641Syongari#define IS_RFDListEnd (1U << 11) 346160641Syongari#define IS_RxDMAPriority (1U << 12) 347160641Syongari 348160641Syongari#define STGE_TxStatus 0x60 349160641Syongari#define TS_TxError (1U << 0) 350160641Syongari#define TS_LateCollision (1U << 2) 351160641Syongari#define TS_MaxCollisions (1U << 3) 352160641Syongari#define TS_TxUnderrun (1U << 4) 353160641Syongari#define TS_TxIndicateReqd (1U << 6) 354160641Syongari#define TS_TxComplete (1U << 7) 355160641Syongari#define TS_TxFrameId_get(x) ((x) >> 16) 356160641Syongari 357160641Syongari#define STGE_MACCtrl 0x6c 358160641Syongari#define MC_IFSSelect(x) ((x) & 3) 359160641Syongari#define MC_IFS96bit 0 360160641Syongari#define MC_IFS1024bit 1 361160641Syongari#define MC_IFS1792bit 2 362160641Syongari#define MC_IFS4352bit 3 363160641Syongari 364160641Syongari#define MC_DuplexSelect (1U << 5) 365160641Syongari#define MC_RcvLargeFrames (1U << 6) 366160641Syongari#define MC_TxFlowControlEnable (1U << 7) 367160641Syongari#define MC_RxFlowControlEnable (1U << 8) 368160641Syongari#define MC_RcvFCS (1U << 9) 369160641Syongari#define MC_FIFOLoopback (1U << 10) 370160641Syongari#define MC_MACLoopback (1U << 11) 371160641Syongari#define MC_AutoVLANtagging (1U << 12) 372160641Syongari#define MC_AutoVLANuntagging (1U << 13) 373160641Syongari#define MC_CollisionDetect (1U << 16) 374160641Syongari#define MC_CarrierSense (1U << 17) 375160641Syongari#define MC_StatisticsEnable (1U << 21) 376160641Syongari#define MC_StatisticsDisable (1U << 22) 377160641Syongari#define MC_StatisticsEnabled (1U << 23) 378160641Syongari#define MC_TxEnable (1U << 24) 379160641Syongari#define MC_TxDisable (1U << 25) 380160641Syongari#define MC_TxEnabled (1U << 26) 381160641Syongari#define MC_RxEnable (1U << 27) 382160641Syongari#define MC_RxDisable (1U << 28) 383160641Syongari#define MC_RxEnabled (1U << 29) 384160641Syongari#define MC_Paused (1U << 30) 385160641Syongari#define MC_MASK 0x7fe33fa3 386160641Syongari 387160641Syongari#define STGE_VLANTag 0x70 388160641Syongari 389160641Syongari#define STGE_PhySet 0x75 /* 8-bit */ 390160641Syongari#define PS_MemLenb9b (1U << 0) 391160641Syongari#define PS_MemLen (1U << 1) 392160641Syongari#define PS_NonCompdet (1U << 2) 393160641Syongari 394160641Syongari#define STGE_PhyCtrl 0x76 /* 8-bit */ 395160641Syongari#define PC_MgmtClk (1U << 0) 396160641Syongari#define PC_MgmtData (1U << 1) 397160641Syongari#define PC_MgmtDir (1U << 2) /* MAC->PHY */ 398160641Syongari#define PC_PhyDuplexPolarity (1U << 3) 399160641Syongari#define PC_PhyDuplexStatus (1U << 4) 400160641Syongari#define PC_PhyLnkPolarity (1U << 5) 401160641Syongari#define PC_LinkSpeed(x) (((x) >> 6) & 3) 402160641Syongari#define PC_LinkSpeed_Down 0 403160641Syongari#define PC_LinkSpeed_10 1 404160641Syongari#define PC_LinkSpeed_100 2 405160641Syongari#define PC_LinkSpeed_1000 3 406160641Syongari 407160641Syongari#define STGE_StationAddress0 0x78 /* 16-bit */ 408160641Syongari 409160641Syongari#define STGE_StationAddress1 0x7a /* 16-bit */ 410160641Syongari 411160641Syongari#define STGE_StationAddress2 0x7c /* 16-bit */ 412160641Syongari 413160641Syongari#define STGE_VLANHashTable 0x7e /* 16-bit */ 414160641Syongari 415160641Syongari#define STGE_VLANId 0x80 416160641Syongari 417160641Syongari#define STGE_MaxFrameSize 0x86 418160641Syongari 419160641Syongari#define STGE_ReceiveMode 0x88 /* 16-bit */ 420160641Syongari#define RM_ReceiveUnicast (1U << 0) 421160641Syongari#define RM_ReceiveMulticast (1U << 1) 422160641Syongari#define RM_ReceiveBroadcast (1U << 2) 423160641Syongari#define RM_ReceiveAllFrames (1U << 3) 424160641Syongari#define RM_ReceiveMulticastHash (1U << 4) 425160641Syongari#define RM_ReceiveIPMulticast (1U << 5) 426160641Syongari#define RM_ReceiveVLANMatch (1U << 8) 427160641Syongari#define RM_ReceiveVLANHash (1U << 9) 428160641Syongari 429160641Syongari#define STGE_HashTable0 0x8c 430160641Syongari 431160641Syongari#define STGE_HashTable1 0x90 432160641Syongari 433160641Syongari#define STGE_RMONStatisticsMask 0x98 /* set to disable */ 434160641Syongari 435160641Syongari#define STGE_StatisticsMask 0x9c /* set to disable */ 436160641Syongari 437160641Syongari#define STGE_RxJumboFrames 0xbc /* 16-bit */ 438160641Syongari 439160641Syongari#define STGE_TCPCheckSumErrors 0xc0 /* 16-bit */ 440160641Syongari 441160641Syongari#define STGE_IPCheckSumErrors 0xc2 /* 16-bit */ 442160641Syongari 443160641Syongari#define STGE_UDPCheckSumErrors 0xc4 /* 16-bit */ 444160641Syongari 445160641Syongari#define STGE_TxJumboFrames 0xf4 /* 16-bit */ 446160641Syongari 447160641Syongari/* 448160641Syongari * TC9021 statistics. Available memory and I/O mapped. 449160641Syongari */ 450160641Syongari 451160641Syongari#define STGE_OctetRcvOk 0xa8 452160641Syongari 453160641Syongari#define STGE_McstOctetRcvdOk 0xac 454160641Syongari 455160641Syongari#define STGE_BcstOctetRcvdOk 0xb0 456160641Syongari 457160641Syongari#define STGE_FramesRcvdOk 0xb4 458160641Syongari 459160641Syongari#define STGE_McstFramesRcvdOk 0xb8 460160641Syongari 461160641Syongari#define STGE_BcstFramesRcvdOk 0xbe /* 16-bit */ 462160641Syongari 463160641Syongari#define STGE_MacControlFramesRcvd 0xc6 /* 16-bit */ 464160641Syongari 465160641Syongari#define STGE_FrameTooLongErrors 0xc8 /* 16-bit */ 466160641Syongari 467160641Syongari#define STGE_InRangeLengthErrors 0xca /* 16-bit */ 468160641Syongari 469160641Syongari#define STGE_FramesCheckSeqErrors 0xcc /* 16-bit */ 470160641Syongari 471160641Syongari#define STGE_FramesLostRxErrors 0xce /* 16-bit */ 472160641Syongari 473160641Syongari#define STGE_OctetXmtdOk 0xd0 474160641Syongari 475160641Syongari#define STGE_McstOctetXmtdOk 0xd4 476160641Syongari 477160641Syongari#define STGE_BcstOctetXmtdOk 0xd8 478160641Syongari 479160641Syongari#define STGE_FramesXmtdOk 0xdc 480160641Syongari 481160641Syongari#define STGE_McstFramesXmtdOk 0xe0 482160641Syongari 483160641Syongari#define STGE_FramesWDeferredXmt 0xe4 484160641Syongari 485160641Syongari#define STGE_LateCollisions 0xe8 486160641Syongari 487160641Syongari#define STGE_MultiColFrames 0xec 488160641Syongari 489160641Syongari#define STGE_SingleColFrames 0xf0 490160641Syongari 491160641Syongari#define STGE_BcstFramesXmtdOk 0xf6 /* 16-bit */ 492160641Syongari 493160641Syongari#define STGE_CarrierSenseErrors 0xf8 /* 16-bit */ 494160641Syongari 495160641Syongari#define STGE_MacControlFramesXmtd 0xfa /* 16-bit */ 496160641Syongari 497160641Syongari#define STGE_FramesAbortXSColls 0xfc /* 16-bit */ 498160641Syongari 499160641Syongari#define STGE_FramesWEXDeferal 0xfe /* 16-bit */ 500160641Syongari 501160641Syongari/* 502160641Syongari * RMON-compatible statistics. Only accessible if memory-mapped. 503160641Syongari */ 504160641Syongari 505160641Syongari#define STGE_EtherStatsCollisions 0x100 506160641Syongari 507160641Syongari#define STGE_EtherStatsOctetsTransmit 0x104 508160641Syongari 509160641Syongari#define STGE_EtherStatsPktsTransmit 0x108 510160641Syongari 511160641Syongari#define STGE_EtherStatsPkts64OctetsTransmit 0x10c 512160641Syongari 513160641Syongari#define STGE_EtherStatsPkts64to127OctetsTransmit 0x110 514160641Syongari 515160641Syongari#define STGE_EtherStatsPkts128to255OctetsTransmit 0x114 516160641Syongari 517160641Syongari#define STGE_EtherStatsPkts256to511OctetsTransmit 0x118 518160641Syongari 519160641Syongari#define STGE_EtherStatsPkts512to1023OctetsTransmit 0x11c 520160641Syongari 521160641Syongari#define STGE_EtherStatsPkts1024to1518OctetsTransmit 0x120 522160641Syongari 523160641Syongari#define STGE_EtherStatsCRCAlignErrors 0x124 524160641Syongari 525160641Syongari#define STGE_EtherStatsUndersizePkts 0x128 526160641Syongari 527160641Syongari#define STGE_EtherStatsFragments 0x12c 528160641Syongari 529160641Syongari#define STGE_EtherStatsJabbers 0x130 530160641Syongari 531160641Syongari#define STGE_EtherStatsOctets 0x134 532160641Syongari 533160641Syongari#define STGE_EtherStatsPkts 0x138 534160641Syongari 535160641Syongari#define STGE_EtherStatsPkts64Octets 0x13c 536160641Syongari 537160641Syongari#define STGE_EtherStatsPkts65to127Octets 0x140 538160641Syongari 539160641Syongari#define STGE_EtherStatsPkts128to255Octets 0x144 540160641Syongari 541160641Syongari#define STGE_EtherStatsPkts256to511Octets 0x148 542160641Syongari 543160641Syongari#define STGE_EtherStatsPkts512to1023Octets 0x14c 544160641Syongari 545160641Syongari#define STGE_EtherStatsPkts1024to1518Octets 0x150 546160641Syongari 547160641Syongari/* 548160641Syongari * Transmit descriptor list size. 549160641Syongari */ 550160641Syongari#define STGE_TX_RING_CNT 256 551160641Syongari#define STGE_TX_LOWAT (STGE_TX_RING_CNT/32) 552160641Syongari#define STGE_TX_HIWAT (STGE_TX_RING_CNT - STGE_TX_LOWAT) 553160641Syongari 554160641Syongari/* 555160641Syongari * Receive descriptor list size. 556160641Syongari */ 557160641Syongari#define STGE_RX_RING_CNT 256 558160641Syongari 559160641Syongari#define STGE_MAXTXSEGS STGE_NTXFRAGS 560160641Syongari 561160641Syongari#define STGE_JUMBO_FRAMELEN 9022 562160641Syongari#define STGE_JUMBO_MTU \ 563160641Syongari (STGE_JUMBO_FRAMELEN - ETHER_HDR_LEN - ETHER_CRC_LEN) 564160641Syongari 565160641Syongaristruct stge_txdesc { 566160641Syongari struct mbuf *tx_m; /* head of our mbuf chain */ 567160641Syongari bus_dmamap_t tx_dmamap; /* our DMA map */ 568160641Syongari STAILQ_ENTRY(stge_txdesc) tx_q; 569160641Syongari}; 570160641Syongari 571160641SyongariSTAILQ_HEAD(stge_txdq, stge_txdesc); 572160641Syongari 573160641Syongaristruct stge_rxdesc { 574160641Syongari struct mbuf *rx_m; 575160641Syongari bus_dmamap_t rx_dmamap; 576160641Syongari}; 577160641Syongari 578160641Syongari#define STGE_ADDR_LO(x) ((u_int64_t) (x) & 0xffffffff) 579160641Syongari#define STGE_ADDR_HI(x) ((u_int64_t) (x) >> 32) 580160641Syongari 581160641Syongari#define STGE_RING_ALIGN 8 582160641Syongari 583160641Syongaristruct stge_chain_data{ 584160641Syongari bus_dma_tag_t stge_parent_tag; 585160641Syongari bus_dma_tag_t stge_tx_tag; 586160641Syongari struct stge_txdesc stge_txdesc[STGE_TX_RING_CNT]; 587160641Syongari struct stge_txdq stge_txfreeq; 588160641Syongari struct stge_txdq stge_txbusyq; 589160641Syongari bus_dma_tag_t stge_rx_tag; 590160641Syongari struct stge_rxdesc stge_rxdesc[STGE_RX_RING_CNT]; 591160641Syongari bus_dma_tag_t stge_tx_ring_tag; 592160641Syongari bus_dmamap_t stge_tx_ring_map; 593160641Syongari bus_dma_tag_t stge_rx_ring_tag; 594160641Syongari bus_dmamap_t stge_rx_ring_map; 595160641Syongari bus_dmamap_t stge_rx_sparemap; 596160641Syongari 597160641Syongari int stge_tx_prod; 598160641Syongari int stge_tx_cons; 599160641Syongari int stge_tx_cnt; 600160641Syongari int stge_rx_cons; 601160641Syongari#ifdef DEVICE_POLLING 602160641Syongari int stge_rxcycles; 603160641Syongari#endif 604160641Syongari int stge_rxlen; 605160641Syongari struct mbuf *stge_rxhead; 606160641Syongari struct mbuf *stge_rxtail; 607160641Syongari}; 608160641Syongari 609160641Syongaristruct stge_ring_data { 610160641Syongari struct stge_tfd *stge_tx_ring; 611160641Syongari bus_addr_t stge_tx_ring_paddr; 612160641Syongari struct stge_rfd *stge_rx_ring; 613160641Syongari bus_addr_t stge_rx_ring_paddr; 614160641Syongari}; 615160641Syongari 616160641Syongari#define STGE_TX_RING_ADDR(sc, i) \ 617160641Syongari ((sc)->sc_rdata.stge_tx_ring_paddr + sizeof(struct stge_tfd) * (i)) 618160641Syongari#define STGE_RX_RING_ADDR(sc, i) \ 619160641Syongari ((sc)->sc_rdata.stge_rx_ring_paddr + sizeof(struct stge_rfd) * (i)) 620160641Syongari 621160641Syongari#define STGE_TX_RING_SZ \ 622160641Syongari (sizeof(struct stge_tfd) * STGE_TX_RING_CNT) 623160641Syongari#define STGE_RX_RING_SZ \ 624160641Syongari (sizeof(struct stge_rfd) * STGE_RX_RING_CNT) 625160641Syongari 626160641Syongari/* 627160641Syongari * Software state per device. 628160641Syongari */ 629160641Syongaristruct stge_softc { 630160641Syongari struct ifnet *sc_ifp; /* interface info */ 631160641Syongari device_t sc_dev; 632160641Syongari device_t sc_miibus; 633160641Syongari struct resource *sc_res[2]; 634160641Syongari struct resource_spec *sc_spec; 635160641Syongari void *sc_ih; /* interrupt cookie */ 636160641Syongari int sc_rev; /* silicon revision */ 637160641Syongari 638160641Syongari struct callout sc_tick_ch; /* tick callout */ 639160641Syongari 640160641Syongari struct stge_chain_data sc_cdata; 641160641Syongari struct stge_ring_data sc_rdata; 642160641Syongari int sc_if_flags; 643160641Syongari int sc_if_framesize; 644160641Syongari int sc_txthresh; /* Tx threshold */ 645160641Syongari uint32_t sc_usefiber:1; /* if we're fiber */ 646160641Syongari uint32_t sc_stge1023:1; /* are we a 1023 */ 647160641Syongari uint32_t sc_DMACtrl; /* prototype DMACtrl reg. */ 648160641Syongari uint32_t sc_MACCtrl; /* prototype MacCtrl reg. */ 649160641Syongari uint16_t sc_IntEnable; /* prototype IntEnable reg. */ 650160641Syongari uint16_t sc_led; /* LED conf. from EEPROM */ 651160641Syongari uint8_t sc_PhyCtrl; /* prototype PhyCtrl reg. */ 652160641Syongari int sc_suspended; 653160641Syongari int sc_detach; 654160641Syongari 655160641Syongari int sc_rxint_nframe; 656160641Syongari int sc_rxint_dmawait; 657160641Syongari int sc_nerr; 658169157Syongari int sc_watchdog_timer; 659169158Syongari int sc_link; 660160641Syongari 661160641Syongari struct task sc_link_task; 662160641Syongari struct mtx sc_mii_mtx; /* MII mutex */ 663160641Syongari struct mtx sc_mtx; 664160641Syongari}; 665160641Syongari 666160641Syongari#define STGE_LOCK(_sc) mtx_lock(&(_sc)->sc_mtx) 667160641Syongari#define STGE_UNLOCK(_sc) mtx_unlock(&(_sc)->sc_mtx) 668160641Syongari#define STGE_LOCK_ASSERT(_sc) mtx_assert(&(_sc)->sc_mtx, MA_OWNED) 669160641Syongari#define STGE_MII_LOCK(_sc) mtx_lock(&(_sc)->sc_mii_mtx) 670160641Syongari#define STGE_MII_UNLOCK(_sc) mtx_unlock(&(_sc)->sc_mii_mtx) 671160641Syongari 672160641Syongari#define STGE_MAXERR 5 673160641Syongari 674160641Syongari#define STGE_RXCHAIN_RESET(_sc) \ 675160641Syongarido { \ 676160641Syongari (_sc)->sc_cdata.stge_rxhead = NULL; \ 677160641Syongari (_sc)->sc_cdata.stge_rxtail = NULL; \ 678160641Syongari (_sc)->sc_cdata.stge_rxlen = 0; \ 679160641Syongari} while (/*CONSTCOND*/0) 680160641Syongari 681160641Syongari#define STGE_TIMEOUT 1000 682160641Syongari 683160641Syongari#define STGE_RESET_NONE 0x00 684160641Syongari#define STGE_RESET_TX 0x01 685160641Syongari#define STGE_RESET_RX 0x02 686160641Syongari#define STGE_RESET_FULL 0x04 687