1230401Spfg/* $FreeBSD$ */ 2230401Spfg/*- 3230401Spfg * Copyright (c) 1996-2008, 4Front Technologies 4230401Spfg * Copyright (C) 1992-2000 Don Kim (don.kim@esstech.com) 5230401Spfg * All rights reserved. 6230401Spfg * 7230401Spfg * Redistribution and use in source and binary forms, with or without 8230401Spfg * modification, are permitted provided that the following conditions 9230401Spfg * are met: 10230401Spfg * 1. Redistributions of source code must retain the above copyright 11230401Spfg * notice, this list of conditions and the following disclaimer. 12230401Spfg * 2. Redistributions in binary form must reproduce the above copyright 13230401Spfg * notice, this list of conditions and the following disclaimer in the 14230401Spfg * documentation and/or other materials provided with the distribution. 15230401Spfg * 16230401Spfg * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 17230401Spfg * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 18230401Spfg * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 19230401Spfg * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 20230401Spfg * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 21230401Spfg * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 22230401Spfg * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 23230401Spfg * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHERIN CONTRACT, STRICT 24230401Spfg * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25230401Spfg * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26230401Spfg * SUCH DAMAGE. 27230401Spfg * 28230401Spfg */ 29230401Spfg 30230401Spfg/*--------------------------------------------------------------------------- 31230401Spfg * Copyright (C) 1997-1999, ESS Technology, Inc. 32230401Spfg * This source code, its compiled object code, and its associated data sets 33230401Spfg * are copyright (C) 1997-1999 ESS Technology, Inc. 34230401Spfg *--------------------------------------------------------------------------- 35230401Spfg * This header contains data structures and registers taken from the 36230401Spfg * 4Front OSS Allegro BSD licensed driver (in the Attic/ directory). 37230401Spfg * Files used for this header include: 38230401Spfg * hardware.h 39230401Spfg * kernel.h and hckernel.h 40230401Spfg * srcmgr.h 41230401Spfg *--------------------------------------------------------------------------- 42230401Spfg */ 43230401Spfg 44230401Spfg#ifndef _DEV_SOUND_PCI_ALLEGRO_REG_H 45230401Spfg#define _DEV_SOUND_PCI_ALLEGRO_REG_H 46230401Spfg 47230401Spfg/* Allegro PCI configuration registers */ 48230401Spfg#define PCI_LEGACY_AUDIO_CTRL 0x40 49230401Spfg#define SOUND_BLASTER_ENABLE 0x00000001 50230401Spfg#define FM_SYNTHESIS_ENABLE 0x00000002 51230401Spfg#define GAME_PORT_ENABLE 0x00000004 52230401Spfg#define MPU401_IO_ENABLE 0x00000008 53230401Spfg#define MPU401_IRQ_ENABLE 0x00000010 54230401Spfg#define ALIAS_10BIT_IO 0x00000020 55230401Spfg#define SB_DMA_MASK 0x000000C0 56230401Spfg#define SB_DMA_0 0x00000040 57230401Spfg#define SB_DMA_1 0x00000040 58230401Spfg#define SB_DMA_R 0x00000080 59230401Spfg#define SB_DMA_3 0x000000C0 60230401Spfg#define SB_IRQ_MASK 0x00000700 61230401Spfg#define SB_IRQ_5 0x00000000 62230401Spfg#define SB_IRQ_7 0x00000100 63230401Spfg#define SB_IRQ_9 0x00000200 64230401Spfg#define SB_IRQ_10 0x00000300 65230401Spfg#define MIDI_IRQ_MASK 0x00003800 66230401Spfg#define SERIAL_IRQ_ENABLE 0x00004000 67230401Spfg#define DISABLE_LEGACY 0x00008000 68230401Spfg 69230401Spfg#define PCI_ALLEGRO_CONFIG 0x50 70230401Spfg#define SB_ADDR_240 0x00000004 71230401Spfg#define MPU_ADDR_MASK 0x00000018 72230401Spfg#define MPU_ADDR_330 0x00000000 73230401Spfg#define MPU_ADDR_300 0x00000008 74230401Spfg#define MPU_ADDR_320 0x00000010 75230401Spfg#define MPU_ADDR_340 0x00000018 76230401Spfg#define USE_PCI_TIMING 0x00000040 77230401Spfg#define POSTED_WRITE_ENABLE 0x00000080 78230401Spfg#define DMA_POLICY_MASK 0x00000700 79230401Spfg#define DMA_DDMA 0x00000000 80230401Spfg#define DMA_TDMA 0x00000100 81230401Spfg#define DMA_PCPCI 0x00000200 82230401Spfg#define DMA_WBDMA16 0x00000400 83230401Spfg#define DMA_WBDMA4 0x00000500 84230401Spfg#define DMA_WBDMA2 0x00000600 85230401Spfg#define DMA_WBDMA1 0x00000700 86230401Spfg#define DMA_SAFE_GUARD 0x00000800 87230401Spfg#define HI_PERF_GP_ENABLE 0x00001000 88230401Spfg#define PIC_SNOOP_MODE_0 0x00002000 89230401Spfg#define PIC_SNOOP_MODE_1 0x00004000 90230401Spfg#define SOUNDBLASTER_IRQ_MASK 0x00008000 91230401Spfg#define RING_IN_ENABLE 0x00010000 92230401Spfg#define SPDIF_TEST_MODE 0x00020000 93230401Spfg#define CLK_MULT_MODE_SELECT_2 0x00040000 94230401Spfg#define EEPROM_WRITE_ENABLE 0x00080000 95230401Spfg#define CODEC_DIR_IN 0x00100000 96230401Spfg#define HV_BUTTON_FROM_GD 0x00200000 97230401Spfg#define REDUCED_DEBOUNCE 0x00400000 98230401Spfg#define HV_CTRL_ENABLE 0x00800000 99230401Spfg#define SPDIF_ENABLE 0x01000000 100230401Spfg#define CLK_DIV_SELECT 0x06000000 101230401Spfg#define CLK_DIV_BY_48 0x00000000 102230401Spfg#define CLK_DIV_BY_49 0x02000000 103230401Spfg#define CLK_DIV_BY_50 0x04000000 104230401Spfg#define CLK_DIV_RESERVED 0x06000000 105230401Spfg#define PM_CTRL_ENABLE 0x08000000 106230401Spfg#define CLK_MULT_MODE_SELECT 0x30000000 107230401Spfg#define CLK_MULT_MODE_SHIFT 28 108230401Spfg#define CLK_MULT_MODE_0 0x00000000 109230401Spfg#define CLK_MULT_MODE_1 0x10000000 110230401Spfg#define CLK_MULT_MODE_2 0x20000000 111230401Spfg#define CLK_MULT_MODE_3 0x30000000 112230401Spfg#define INT_CLK_SELECT 0x40000000 113230401Spfg#define INT_CLK_MULT_RESET 0x80000000 114230401Spfg 115230401Spfg/* M3 */ 116230401Spfg#define INT_CLK_SRC_NOT_PCI 0x00100000 117230401Spfg#define INT_CLK_MULT_ENABLE 0x80000000 118230401Spfg 119230401Spfg#define PCI_ACPI_CONTROL 0x54 120230401Spfg#define PCI_ACPI_D0 0x00000000 121230401Spfg#define PCI_ACPI_D1 0xB4F70000 122230401Spfg#define PCI_ACPI_D2 0xB4F7B4F7 123230401Spfg 124230401Spfg#define PCI_USER_CONFIG 0x58 125230401Spfg#define EXT_PCI_MASTER_ENABLE 0x00000001 126230401Spfg#define SPDIF_OUT_SELECT 0x00000002 127230401Spfg#define TEST_PIN_DIR_CTRL 0x00000004 128230401Spfg#define AC97_CODEC_TEST 0x00000020 129230401Spfg#define TRI_STATE_BUFFER 0x00000080 130230401Spfg#define IN_CLK_12MHZ_SELECT 0x00000100 131230401Spfg#define MULTI_FUNC_DISABLE 0x00000200 132230401Spfg#define EXT_MASTER_PAIR_SEL 0x00000400 133230401Spfg#define PCI_MASTER_SUPPORT 0x00000800 134230401Spfg#define STOP_CLOCK_ENABLE 0x00001000 135230401Spfg#define EAPD_DRIVE_ENABLE 0x00002000 136230401Spfg#define REQ_TRI_STATE_ENABLE 0x00004000 137230401Spfg#define REQ_LOW_ENABLE 0x00008000 138230401Spfg#define MIDI_1_ENABLE 0x00010000 139230401Spfg#define MIDI_2_ENABLE 0x00020000 140230401Spfg#define SB_AUDIO_SYNC 0x00040000 141230401Spfg#define HV_CTRL_TEST 0x00100000 142230401Spfg#define SOUNDBLASTER_TEST 0x00400000 143230401Spfg 144230401Spfg#define PCI_USER_CONFIG_C 0x5C 145230401Spfg 146230401Spfg#define PCI_DDMA_CTRL 0x60 147230401Spfg#define DDMA_ENABLE 0x00000001 148230401Spfg 149230401Spfg 150230401Spfg/* Allegro registers */ 151230401Spfg#define HOST_INT_CTRL 0x18 152230401Spfg#define SB_INT_ENABLE 0x0001 153230401Spfg#define MPU401_INT_ENABLE 0x0002 154230401Spfg#define ASSP_INT_ENABLE 0x0010 155230401Spfg#define RING_INT_ENABLE 0x0020 156230401Spfg#define HV_INT_ENABLE 0x0040 157230401Spfg#define CLKRUN_GEN_ENABLE 0x0100 158230401Spfg#define HV_CTRL_TO_PME 0x0400 159230401Spfg#define SOFTWARE_RESET_ENABLE 0x8000 160230401Spfg 161230401Spfg#define HOST_INT_STATUS 0x1A 162230401Spfg#define SB_INT_PENDING 0x01 163230401Spfg#define MPU401_INT_PENDING 0x02 164230401Spfg#define ASSP_INT_PENDING 0x10 165230401Spfg#define RING_INT_PENDING 0x20 166230401Spfg#define HV_INT_PENDING 0x40 167230401Spfg 168230401Spfg#define HARDWARE_VOL_CTRL 0x1B 169230401Spfg#define SHADOW_MIX_REG_VOICE 0x1C 170230401Spfg#define HW_VOL_COUNTER_VOICE 0x1D 171230401Spfg#define SHADOW_MIX_REG_MASTER 0x1E 172230401Spfg#define HW_VOL_COUNTER_MASTER 0x1F 173230401Spfg 174230401Spfg#define CODEC_COMMAND 0x30 175230401Spfg#define CODEC_READ_B 0x80 176230401Spfg 177230401Spfg#define CODEC_STATUS 0x30 178230401Spfg#define CODEC_BUSY_B 0x01 179230401Spfg 180230401Spfg#define CODEC_DATA 0x32 181230401Spfg 182230401Spfg/* AC97 registers */ 183230401Spfg#ifndef M3_MODEL 184230401Spfg#define AC97_RESET 0x00 185230401Spfg#endif 186230401Spfg 187230401Spfg#define AC97_VOL_MUTE_B 0x8000 188230401Spfg#define AC97_VOL_M 0x1F 189230401Spfg#define AC97_LEFT_VOL_S 8 190230401Spfg 191230401Spfg#define AC97_MASTER_VOL 0x02 192230401Spfg#define AC97_LINE_LEVEL_VOL 0x04 193230401Spfg#define AC97_MASTER_MONO_VOL 0x06 194230401Spfg#define AC97_PC_BEEP_VOL 0x0A 195230401Spfg#define AC97_PC_BEEP_VOL_M 0x0F 196230401Spfg#define AC97_SROUND_MASTER_VOL 0x38 197230401Spfg#define AC97_PC_BEEP_VOL_S 1 198230401Spfg 199230401Spfg#ifndef M3_MODEL 200230401Spfg#define AC97_PHONE_VOL 0x0C 201230401Spfg#define AC97_MIC_VOL 0x0E 202230401Spfg#endif 203230401Spfg#define AC97_MIC_20DB_ENABLE 0x40 204230401Spfg 205230401Spfg#ifndef M3_MODEL 206230401Spfg#define AC97_LINEIN_VOL 0x10 207230401Spfg#define AC97_CD_VOL 0x12 208230401Spfg#define AC97_VIDEO_VOL 0x14 209230401Spfg#define AC97_AUX_VOL 0x16 210230401Spfg#endif 211230401Spfg#define AC97_PCM_OUT_VOL 0x18 212230401Spfg#ifndef M3_MODEL 213230401Spfg#define AC97_RECORD_SELECT 0x1A 214230401Spfg#endif 215230401Spfg#define AC97_RECORD_MIC 0x00 216230401Spfg#define AC97_RECORD_CD 0x01 217230401Spfg#define AC97_RECORD_VIDEO 0x02 218230401Spfg#define AC97_RECORD_AUX 0x03 219230401Spfg#define AC97_RECORD_MONO_MUX 0x02 220230401Spfg#define AC97_RECORD_DIGITAL 0x03 221230401Spfg#define AC97_RECORD_LINE 0x04 222230401Spfg#define AC97_RECORD_STEREO 0x05 223230401Spfg#define AC97_RECORD_MONO 0x06 224230401Spfg#define AC97_RECORD_PHONE 0x07 225230401Spfg 226230401Spfg#ifndef M3_MODEL 227230401Spfg#define AC97_RECORD_GAIN 0x1C 228230401Spfg#endif 229230401Spfg#define AC97_RECORD_VOL_M 0x0F 230230401Spfg 231230401Spfg#ifndef M3_MODEL 232230401Spfg#define AC97_GENERAL_PURPOSE 0x20 233230401Spfg#endif 234230401Spfg#define AC97_POWER_DOWN_CTRL 0x26 235230401Spfg#define AC97_ADC_READY 0x0001 236230401Spfg#define AC97_DAC_READY 0x0002 237230401Spfg#define AC97_ANALOG_READY 0x0004 238230401Spfg#define AC97_VREF_ON 0x0008 239230401Spfg#define AC97_PR0 0x0100 240230401Spfg#define AC97_PR1 0x0200 241230401Spfg#define AC97_PR2 0x0400 242230401Spfg#define AC97_PR3 0x0800 243230401Spfg#define AC97_PR4 0x1000 244230401Spfg 245230401Spfg#define AC97_RESERVED1 0x28 246230401Spfg 247230401Spfg#define AC97_VENDOR_TEST 0x5A 248230401Spfg 249230401Spfg#define AC97_CLOCK_DELAY 0x5C 250230401Spfg#define AC97_LINEOUT_MUX_SEL 0x0001 251230401Spfg#define AC97_MONO_MUX_SEL 0x0002 252230401Spfg#define AC97_CLOCK_DELAY_SEL 0x1F 253230401Spfg#define AC97_DAC_CDS_SHIFT 6 254230401Spfg#define AC97_ADC_CDS_SHIFT 11 255230401Spfg 256230401Spfg#define AC97_MULTI_CHANNEL_SEL 0x74 257230401Spfg 258230401Spfg#ifndef M3_MODEL 259230401Spfg#define AC97_VENDOR_ID1 0x7C 260230401Spfg#define AC97_VENDOR_ID2 0x7E 261230401Spfg#endif 262230401Spfg 263230401Spfg#define RING_BUS_CTRL_A 0x36 264230401Spfg#define RAC_PME_ENABLE 0x0100 265230401Spfg#define RAC_SDFS_ENABLE 0x0200 266230401Spfg#define LAC_PME_ENABLE 0x0400 267230401Spfg#define LAC_SDFS_ENABLE 0x0800 268230401Spfg#define SERIAL_AC_LINK_ENABLE 0x1000 269230401Spfg#define IO_SRAM_ENABLE 0x2000 270230401Spfg#define IIS_INPUT_ENABLE 0x8000 271230401Spfg 272230401Spfg#define RING_BUS_CTRL_B 0x38 273230401Spfg#define SECOND_CODEC_ID_MASK 0x0003 274230401Spfg#define SPDIF_FUNC_ENABLE 0x0010 275230401Spfg#define SECOND_AC_ENABLE 0x0020 276230401Spfg#define SB_MODULE_INTF_ENABLE 0x0040 277230401Spfg#define SSPE_ENABLE 0x0040 278230401Spfg#define M3I_DOCK_ENABLE 0x0080 279230401Spfg 280230401Spfg#define SDO_OUT_DEST_CTRL 0x3A 281230401Spfg#define COMMAND_ADDR_OUT 0x0003 282230401Spfg#define PCM_LR_OUT_LOCAL 0x0000 283230401Spfg#define PCM_LR_OUT_REMOTE 0x0004 284230401Spfg#define PCM_LR_OUT_MUTE 0x0008 285230401Spfg#define PCM_LR_OUT_BOTH 0x000C 286230401Spfg#define LINE1_DAC_OUT_LOCAL 0x0000 287230401Spfg#define LINE1_DAC_OUT_REMOTE 0x0010 288230401Spfg#define LINE1_DAC_OUT_MUTE 0x0020 289230401Spfg#define LINE1_DAC_OUT_BOTH 0x0030 290230401Spfg#define PCM_CLS_OUT_LOCAL 0x0000 291230401Spfg#define PCM_CLS_OUT_REMOTE 0x0040 292230401Spfg#define PCM_CLS_OUT_MUTE 0x0080 293230401Spfg#define PCM_CLS_OUT_BOTH 0x00C0 294230401Spfg#define PCM_RLF_OUT_LOCAL 0x0000 295230401Spfg#define PCM_RLF_OUT_REMOTE 0x0100 296230401Spfg#define PCM_RLF_OUT_MUTE 0x0200 297230401Spfg#define PCM_RLF_OUT_BOTH 0x0300 298230401Spfg#define LINE2_DAC_OUT_LOCAL 0x0000 299230401Spfg#define LINE2_DAC_OUT_REMOTE 0x0400 300230401Spfg#define LINE2_DAC_OUT_MUTE 0x0800 301230401Spfg#define LINE2_DAC_OUT_BOTH 0x0C00 302230401Spfg#define HANDSET_OUT_LOCAL 0x0000 303230401Spfg#define HANDSET_OUT_REMOTE 0x1000 304230401Spfg#define HANDSET_OUT_MUTE 0x2000 305230401Spfg#define HANDSET_OUT_BOTH 0x3000 306230401Spfg#define IO_CTRL_OUT_LOCAL 0x0000 307230401Spfg#define IO_CTRL_OUT_REMOTE 0x4000 308230401Spfg#define IO_CTRL_OUT_MUTE 0x8000 309230401Spfg#define IO_CTRL_OUT_BOTH 0xC000 310230401Spfg 311230401Spfg#define SDO_IN_DEST_CTRL 0x3C 312230401Spfg#define STATUS_ADDR_IN 0x0003 313230401Spfg#define PCM_LR_IN_LOCAL 0x0000 314230401Spfg#define PCM_LR_IN_REMOTE 0x0004 315230401Spfg#define PCM_LR_RESERVED 0x0008 316230401Spfg#define PCM_LR_IN_BOTH 0x000C 317230401Spfg#define LINE1_ADC_IN_LOCAL 0x0000 318230401Spfg#define LINE1_ADC_IN_REMOTE 0x0010 319230401Spfg#define LINE1_ADC_IN_MUTE 0x0020 320230401Spfg#define MIC_ADC_IN_LOCAL 0x0000 321230401Spfg#define MIC_ADC_IN_REMOTE 0x0040 322230401Spfg#define MIC_ADC_IN_MUTE 0x0080 323230401Spfg#define LINE2_DAC_IN_LOCAL 0x0000 324230401Spfg#define LINE2_DAC_IN_REMOTE 0x0400 325230401Spfg#define LINE2_DAC_IN_MUTE 0x0800 326230401Spfg#define HANDSET_IN_LOCAL 0x0000 327230401Spfg#define HANDSET_IN_REMOTE 0x1000 328230401Spfg#define HANDSET_IN_MUTE 0x2000 329230401Spfg#define IO_STATUS_IN_LOCAL 0x0000 330230401Spfg#define IO_STATUS_IN_REMOTE 0x4000 331230401Spfg 332230401Spfg#define SPDIF_IN_CTRL 0x3E 333230401Spfg#define SPDIF_IN_ENABLE 0x0001 334230401Spfg 335230401Spfg#define GPIO_DATA 0x60 336230401Spfg#define GPIO_DATA_MASK 0x0FFF 337230401Spfg#define GPIO_HV_STATUS 0x3000 338230401Spfg#define GPIO_PME_STATUS 0x4000 339230401Spfg 340230401Spfg#define GPIO_MASK 0x64 341230401Spfg#define GPIO_DIRECTION 0x68 342230401Spfg#define GPO_PRIMARY_AC97 0x0001 343230401Spfg#define GPI_LINEOUT_SENSE 0x0004 344230401Spfg#define GPO_SECONDARY_AC97 0x0008 345230401Spfg#define GPI_VOL_DOWN 0x0010 346230401Spfg#define GPI_VOL_UP 0x0020 347230401Spfg#define GPI_IIS_CLK 0x0040 348230401Spfg#define GPI_IIS_LRCLK 0x0080 349230401Spfg#define GPI_IIS_DATA 0x0100 350230401Spfg#define GPI_DOCKING_STATUS 0x0100 351230401Spfg#define GPI_HEADPHONE_SENSE 0x0200 352230401Spfg#define GPO_EXT_AMP_SHUTDOWN 0x1000 353230401Spfg 354230401Spfg/* M3 */ 355230401Spfg#define GPO_M3_EXT_AMP_SHUTDN 0x0002 356230401Spfg 357230401Spfg#define ASSP_INDEX_PORT 0x80 358230401Spfg#define ASSP_MEMORY_PORT 0x82 359230401Spfg#define ASSP_DATA_PORT 0x84 360230401Spfg 361230401Spfg#define MPU401_DATA_PORT 0x98 362230401Spfg#define MPU401_STATUS_PORT 0x99 363230401Spfg 364230401Spfg#define CLK_MULT_DATA_PORT 0x9C 365230401Spfg 366230401Spfg#define ASSP_CONTROL_A 0xA2 367230401Spfg#define ASSP_0_WS_ENABLE 0x01 368230401Spfg#define ASSP_CTRL_A_RESERVED1 0x02 369230401Spfg#define ASSP_CTRL_A_RESERVED2 0x04 370230401Spfg#define ASSP_CLK_49MHZ_SELECT 0x08 371230401Spfg#define FAST_PLU_ENABLE 0x10 372230401Spfg#define ASSP_CTRL_A_RESERVED3 0x20 373230401Spfg#define DSP_CLK_36MHZ_SELECT 0x40 374230401Spfg 375230401Spfg#define ASSP_CONTROL_B 0xA4 376230401Spfg#define RESET_ASSP 0x00 377230401Spfg#define RUN_ASSP 0x01 378230401Spfg#define ENABLE_ASSP_CLOCK 0x00 379230401Spfg#define STOP_ASSP_CLOCK 0x10 380230401Spfg#define RESET_TOGGLE 0x40 381230401Spfg 382230401Spfg#define ASSP_CONTROL_C 0xA6 383230401Spfg#define ASSP_HOST_INT_ENABLE 0x01 384230401Spfg#define FM_ADDR_REMAP_DISABLE 0x02 385230401Spfg#define HOST_WRITE_PORT_ENABLE 0x08 386230401Spfg 387230401Spfg#define ASSP_HOST_INT_STATUS 0xAC 388230401Spfg#define DSP2HOST_REQ_PIORECORD 0x01 389230401Spfg#define DSP2HOST_REQ_I2SRATE 0x02 390230401Spfg#define DSP2HOST_REQ_TIMER 0x04 391230401Spfg 392230401Spfg/* 393230401Spfg * DSP memory map 394230401Spfg */ 395230401Spfg 396230401Spfg#define REV_A_CODE_MEMORY_BEGIN 0x0000 397230401Spfg#define REV_A_CODE_MEMORY_END 0x0FFF 398230401Spfg#define REV_A_CODE_MEMORY_UNIT_LENGTH 0x0040 399230401Spfg#define REV_A_CODE_MEMORY_LENGTH (REV_A_CODE_MEMORY_END - REV_A_CODE_MEMORY_BEGIN + 1) 400230401Spfg 401230401Spfg#define REV_B_CODE_MEMORY_BEGIN 0x0000 402230401Spfg#define REV_B_CODE_MEMORY_END 0x0BFF 403230401Spfg#define REV_B_CODE_MEMORY_UNIT_LENGTH 0x0040 404230401Spfg#define REV_B_CODE_MEMORY_LENGTH (REV_B_CODE_MEMORY_END - REV_B_CODE_MEMORY_BEGIN + 1) 405230401Spfg 406230401Spfg#if (REV_A_CODE_MEMORY_LENGTH % REV_A_CODE_MEMORY_UNIT_LENGTH) 407230401Spfg#error Assumption about code memory unit length failed. 408230401Spfg#endif 409230401Spfg#if (REV_B_CODE_MEMORY_LENGTH % REV_B_CODE_MEMORY_UNIT_LENGTH) 410230401Spfg#error Assumption about code memory unit length failed. 411230401Spfg#endif 412230401Spfg 413230401Spfg#define REV_A_DATA_MEMORY_BEGIN 0x1000 414230401Spfg#define REV_A_DATA_MEMORY_END 0x2FFF 415230401Spfg#define REV_A_DATA_MEMORY_UNIT_LENGTH 0x0080 416230401Spfg#define REV_A_DATA_MEMORY_LENGTH (REV_A_DATA_MEMORY_END - REV_A_DATA_MEMORY_BEGIN + 1) 417230401Spfg 418230401Spfg#define REV_B_DATA_MEMORY_BEGIN 0x1000 419230401Spfg/*#define REV_B_DATA_MEMORY_END 0x23FF */ 420230401Spfg#define REV_B_DATA_MEMORY_END 0x2BFF 421230401Spfg#define REV_B_DATA_MEMORY_UNIT_LENGTH 0x0080 422230401Spfg#define REV_B_DATA_MEMORY_LENGTH (REV_B_DATA_MEMORY_END - REV_B_DATA_MEMORY_BEGIN + 1) 423230401Spfg 424230401Spfg#if (REV_A_DATA_MEMORY_LENGTH % REV_A_DATA_MEMORY_UNIT_LENGTH) 425230401Spfg#error Assumption about data memory unit length failed. 426230401Spfg#endif 427230401Spfg#if (REV_B_DATA_MEMORY_LENGTH % REV_B_DATA_MEMORY_UNIT_LENGTH) 428230401Spfg#error Assumption about data memory unit length failed. 429230401Spfg#endif 430230401Spfg 431230401Spfg#define CODE_MEMORY_MAP_LENGTH (64 + 1) 432230401Spfg#define DATA_MEMORY_MAP_LENGTH (64 + 1) 433230401Spfg 434230401Spfg#if (CODE_MEMORY_MAP_LENGTH < ((REV_A_CODE_MEMORY_LENGTH / REV_A_CODE_MEMORY_UNIT_LENGTH) + 1)) 435230401Spfg#error Code memory map length too short. 436230401Spfg#endif 437230401Spfg#if (DATA_MEMORY_MAP_LENGTH < ((REV_A_DATA_MEMORY_LENGTH / REV_A_DATA_MEMORY_UNIT_LENGTH) + 1)) 438230401Spfg#error Data memory map length too short. 439230401Spfg#endif 440230401Spfg#if (CODE_MEMORY_MAP_LENGTH < ((REV_B_CODE_MEMORY_LENGTH / REV_B_CODE_MEMORY_UNIT_LENGTH) + 1)) 441230401Spfg#error Code memory map length too short. 442230401Spfg#endif 443230401Spfg#if (DATA_MEMORY_MAP_LENGTH < ((REV_B_DATA_MEMORY_LENGTH / REV_B_DATA_MEMORY_UNIT_LENGTH) + 1)) 444230401Spfg#error Data memory map length too short. 445230401Spfg#endif 446230401Spfg 447230401Spfg 448230401Spfg/* 449230401Spfg * Kernel code memory definition 450230401Spfg */ 451230401Spfg 452230401Spfg#define KCODE_VECTORS_BEGIN 0x0000 453230401Spfg#define KCODE_VECTORS_END 0x002F 454230401Spfg#define KCODE_VECTORS_UNIT_LENGTH 0x0002 455230401Spfg#define KCODE_VECTORS_LENGTH (KCODE_VECTORS_END - KCODE_VECTORS_BEGIN + 1) 456230401Spfg 457230401Spfg 458230401Spfg/* 459230401Spfg * Kernel data memory definition 460230401Spfg */ 461230401Spfg 462230401Spfg#define KDATA_BASE_ADDR 0x1000 463230401Spfg#define KDATA_BASE_ADDR2 0x1080 464230401Spfg 465230401Spfg#define KDATA_TASK0 (KDATA_BASE_ADDR + 0x0000) 466230401Spfg#define KDATA_TASK1 (KDATA_BASE_ADDR + 0x0001) 467230401Spfg#define KDATA_TASK2 (KDATA_BASE_ADDR + 0x0002) 468230401Spfg#define KDATA_TASK3 (KDATA_BASE_ADDR + 0x0003) 469230401Spfg#define KDATA_TASK4 (KDATA_BASE_ADDR + 0x0004) 470230401Spfg#define KDATA_TASK5 (KDATA_BASE_ADDR + 0x0005) 471230401Spfg#define KDATA_TASK6 (KDATA_BASE_ADDR + 0x0006) 472230401Spfg#define KDATA_TASK7 (KDATA_BASE_ADDR + 0x0007) 473230401Spfg#define KDATA_TASK_ENDMARK (KDATA_BASE_ADDR + 0x0008) 474230401Spfg 475230401Spfg#define KDATA_CURRENT_TASK (KDATA_BASE_ADDR + 0x0009) 476230401Spfg#define KDATA_TASK_SWITCH (KDATA_BASE_ADDR + 0x000A) 477230401Spfg 478230401Spfg#define KDATA_INSTANCE0_POS3D (KDATA_BASE_ADDR + 0x000B) 479230401Spfg#define KDATA_INSTANCE1_POS3D (KDATA_BASE_ADDR + 0x000C) 480230401Spfg#define KDATA_INSTANCE2_POS3D (KDATA_BASE_ADDR + 0x000D) 481230401Spfg#define KDATA_INSTANCE3_POS3D (KDATA_BASE_ADDR + 0x000E) 482230401Spfg#define KDATA_INSTANCE4_POS3D (KDATA_BASE_ADDR + 0x000F) 483230401Spfg#define KDATA_INSTANCE5_POS3D (KDATA_BASE_ADDR + 0x0010) 484230401Spfg#define KDATA_INSTANCE6_POS3D (KDATA_BASE_ADDR + 0x0011) 485230401Spfg#define KDATA_INSTANCE7_POS3D (KDATA_BASE_ADDR + 0x0012) 486230401Spfg#define KDATA_INSTANCE8_POS3D (KDATA_BASE_ADDR + 0x0013) 487230401Spfg#define KDATA_INSTANCE_POS3D_ENDMARK (KDATA_BASE_ADDR + 0x0014) 488230401Spfg 489230401Spfg#define KDATA_INSTANCE0_SPKVIRT (KDATA_BASE_ADDR + 0x0015) 490230401Spfg#define KDATA_INSTANCE_SPKVIRT_ENDMARK (KDATA_BASE_ADDR + 0x0016) 491230401Spfg 492230401Spfg#define KDATA_INSTANCE0_SPDIF (KDATA_BASE_ADDR + 0x0017) 493230401Spfg#define KDATA_INSTANCE_SPDIF_ENDMARK (KDATA_BASE_ADDR + 0x0018) 494230401Spfg 495230401Spfg#define KDATA_INSTANCE0_MODEM (KDATA_BASE_ADDR + 0x0019) 496230401Spfg#define KDATA_INSTANCE_MODEM_ENDMARK (KDATA_BASE_ADDR + 0x001A) 497230401Spfg 498230401Spfg#define KDATA_INSTANCE0_SRC (KDATA_BASE_ADDR + 0x001B) 499230401Spfg#define KDATA_INSTANCE1_SRC (KDATA_BASE_ADDR + 0x001C) 500230401Spfg#define KDATA_INSTANCE_SRC_ENDMARK (KDATA_BASE_ADDR + 0x001D) 501230401Spfg 502230401Spfg#define KDATA_INSTANCE0_MINISRC (KDATA_BASE_ADDR + 0x001E) 503230401Spfg#define KDATA_INSTANCE1_MINISRC (KDATA_BASE_ADDR + 0x001F) 504230401Spfg#define KDATA_INSTANCE2_MINISRC (KDATA_BASE_ADDR + 0x0020) 505230401Spfg#define KDATA_INSTANCE3_MINISRC (KDATA_BASE_ADDR + 0x0021) 506230401Spfg#define KDATA_INSTANCE_MINISRC_ENDMARK (KDATA_BASE_ADDR + 0x0022) 507230401Spfg 508230401Spfg#define KDATA_INSTANCE0_CPYTHRU (KDATA_BASE_ADDR + 0x0023) 509230401Spfg#define KDATA_INSTANCE1_CPYTHRU (KDATA_BASE_ADDR + 0x0024) 510230401Spfg#define KDATA_INSTANCE_CPYTHRU_ENDMARK (KDATA_BASE_ADDR + 0x0025) 511230401Spfg 512230401Spfg#define KDATA_CURRENT_DMA (KDATA_BASE_ADDR + 0x0026) 513230401Spfg#define KDATA_DMA_SWITCH (KDATA_BASE_ADDR + 0x0027) 514230401Spfg#define KDATA_DMA_ACTIVE (KDATA_BASE_ADDR + 0x0028) 515230401Spfg 516230401Spfg#define KDATA_DMA_XFER0 (KDATA_BASE_ADDR + 0x0029) 517230401Spfg#define KDATA_DMA_XFER1 (KDATA_BASE_ADDR + 0x002A) 518230401Spfg#define KDATA_DMA_XFER2 (KDATA_BASE_ADDR + 0x002B) 519230401Spfg#define KDATA_DMA_XFER3 (KDATA_BASE_ADDR + 0x002C) 520230401Spfg#define KDATA_DMA_XFER4 (KDATA_BASE_ADDR + 0x002D) 521230401Spfg#define KDATA_DMA_XFER5 (KDATA_BASE_ADDR + 0x002E) 522230401Spfg#define KDATA_DMA_XFER6 (KDATA_BASE_ADDR + 0x002F) 523230401Spfg#define KDATA_DMA_XFER7 (KDATA_BASE_ADDR + 0x0030) 524230401Spfg#define KDATA_DMA_XFER8 (KDATA_BASE_ADDR + 0x0031) 525230401Spfg#define KDATA_DMA_XFER_ENDMARK (KDATA_BASE_ADDR + 0x0032) 526230401Spfg 527230401Spfg#define KDATA_I2S_SAMPLE_COUNT (KDATA_BASE_ADDR + 0x0033) 528230401Spfg#define KDATA_I2S_INT_METER (KDATA_BASE_ADDR + 0x0034) 529230401Spfg#define KDATA_I2S_ACTIVE (KDATA_BASE_ADDR + 0x0035) 530230401Spfg 531230401Spfg#define KDATA_TIMER_COUNT_RELOAD (KDATA_BASE_ADDR + 0x0036) 532230401Spfg#define KDATA_TIMER_COUNT_CURRENT (KDATA_BASE_ADDR + 0x0037) 533230401Spfg 534230401Spfg#define KDATA_HALT_SYNCH_CLIENT (KDATA_BASE_ADDR + 0x0038) 535230401Spfg#define KDATA_HALT_SYNCH_DMA (KDATA_BASE_ADDR + 0x0039) 536230401Spfg#define KDATA_HALT_ACKNOWLEDGE (KDATA_BASE_ADDR + 0x003A) 537230401Spfg 538230401Spfg#define KDATA_ADC1_XFER0 (KDATA_BASE_ADDR + 0x003B) 539230401Spfg#define KDATA_ADC1_XFER_ENDMARK (KDATA_BASE_ADDR + 0x003C) 540230401Spfg#define KDATA_ADC1_LEFT_VOLUME (KDATA_BASE_ADDR + 0x003D) 541230401Spfg#define KDATA_ADC1_RIGHT_VOLUME (KDATA_BASE_ADDR + 0x003E) 542230401Spfg#define KDATA_ADC1_LEFT_SUR_VOL (KDATA_BASE_ADDR + 0x003F) 543230401Spfg#define KDATA_ADC1_RIGHT_SUR_VOL (KDATA_BASE_ADDR + 0x0040) 544230401Spfg 545230401Spfg#define KDATA_ADC2_XFER0 (KDATA_BASE_ADDR + 0x0041) 546230401Spfg#define KDATA_ADC2_XFER_ENDMARK (KDATA_BASE_ADDR + 0x0042) 547230401Spfg#define KDATA_ADC2_LEFT_VOLUME (KDATA_BASE_ADDR + 0x0043) 548230401Spfg#define KDATA_ADC2_RIGHT_VOLUME (KDATA_BASE_ADDR + 0x0044) 549230401Spfg#define KDATA_ADC2_LEFT_SUR_VOL (KDATA_BASE_ADDR + 0x0045) 550230401Spfg#define KDATA_ADC2_RIGHT_SUR_VOL (KDATA_BASE_ADDR + 0x0046) 551230401Spfg 552230401Spfg#define KDATA_CD_XFER0 (KDATA_BASE_ADDR + 0x0047) 553230401Spfg#define KDATA_CD_XFER_ENDMARK (KDATA_BASE_ADDR + 0x0048) 554230401Spfg#define KDATA_CD_LEFT_VOLUME (KDATA_BASE_ADDR + 0x0049) 555230401Spfg#define KDATA_CD_RIGHT_VOLUME (KDATA_BASE_ADDR + 0x004A) 556230401Spfg#define KDATA_CD_LEFT_SUR_VOL (KDATA_BASE_ADDR + 0x004B) 557230401Spfg#define KDATA_CD_RIGHT_SUR_VOL (KDATA_BASE_ADDR + 0x004C) 558230401Spfg 559230401Spfg#define KDATA_MIC_XFER0 (KDATA_BASE_ADDR + 0x004D) 560230401Spfg#define KDATA_MIC_XFER_ENDMARK (KDATA_BASE_ADDR + 0x004E) 561230401Spfg#define KDATA_MIC_VOLUME (KDATA_BASE_ADDR + 0x004F) 562230401Spfg#define KDATA_MIC_SUR_VOL (KDATA_BASE_ADDR + 0x0050) 563230401Spfg 564230401Spfg#define KDATA_I2S_XFER0 (KDATA_BASE_ADDR + 0x0051) 565230401Spfg#define KDATA_I2S_XFER_ENDMARK (KDATA_BASE_ADDR + 0x0052) 566230401Spfg 567230401Spfg#define KDATA_CHI_XFER0 (KDATA_BASE_ADDR + 0x0053) 568230401Spfg#define KDATA_CHI_XFER_ENDMARK (KDATA_BASE_ADDR + 0x0054) 569230401Spfg 570230401Spfg#define KDATA_SPDIF_XFER (KDATA_BASE_ADDR + 0x0055) 571230401Spfg#define KDATA_SPDIF_CURRENT_FRAME (KDATA_BASE_ADDR + 0x0056) 572230401Spfg#define KDATA_SPDIF_FRAME0 (KDATA_BASE_ADDR + 0x0057) 573230401Spfg#define KDATA_SPDIF_FRAME1 (KDATA_BASE_ADDR + 0x0058) 574230401Spfg#define KDATA_SPDIF_FRAME2 (KDATA_BASE_ADDR + 0x0059) 575230401Spfg 576230401Spfg#define KDATA_SPDIF_REQUEST (KDATA_BASE_ADDR + 0x005A) 577230401Spfg#define KDATA_SPDIF_TEMP (KDATA_BASE_ADDR + 0x005B) 578230401Spfg 579230401Spfg/*AY SPDIF IN */ 580230401Spfg#define KDATA_SPDIFIN_XFER0 (KDATA_BASE_ADDR + 0x005C) 581230401Spfg#define KDATA_SPDIFIN_XFER_ENDMARK (KDATA_BASE_ADDR + 0x005D) 582230401Spfg#define KDATA_SPDIFIN_INT_METER (KDATA_BASE_ADDR + 0x005E) 583230401Spfg 584230401Spfg#define KDATA_DSP_RESET_COUNT (KDATA_BASE_ADDR + 0x005F) 585230401Spfg#define KDATA_DEBUG_OUTPUT (KDATA_BASE_ADDR + 0x0060) 586230401Spfg 587230401Spfg#define KDATA_KERNEL_ISR_LIST (KDATA_BASE_ADDR + 0x0061) 588230401Spfg 589230401Spfg#define KDATA_KERNEL_ISR_CBSR1 (KDATA_BASE_ADDR + 0x0062) 590230401Spfg#define KDATA_KERNEL_ISR_CBER1 (KDATA_BASE_ADDR + 0x0063) 591230401Spfg#define KDATA_KERNEL_ISR_CBCR (KDATA_BASE_ADDR + 0x0064) 592230401Spfg#define KDATA_KERNEL_ISR_AR0 (KDATA_BASE_ADDR + 0x0065) 593230401Spfg#define KDATA_KERNEL_ISR_AR1 (KDATA_BASE_ADDR + 0x0066) 594230401Spfg#define KDATA_KERNEL_ISR_AR2 (KDATA_BASE_ADDR + 0x0067) 595230401Spfg#define KDATA_KERNEL_ISR_AR3 (KDATA_BASE_ADDR + 0x0068) 596230401Spfg#define KDATA_KERNEL_ISR_AR4 (KDATA_BASE_ADDR + 0x0069) 597230401Spfg#define KDATA_KERNEL_ISR_AR5 (KDATA_BASE_ADDR + 0x006A) 598230401Spfg#define KDATA_KERNEL_ISR_BRCR (KDATA_BASE_ADDR + 0x006B) 599230401Spfg#define KDATA_KERNEL_ISR_PASR (KDATA_BASE_ADDR + 0x006C) 600230401Spfg#define KDATA_KERNEL_ISR_PAER (KDATA_BASE_ADDR + 0x006D) 601230401Spfg 602230401Spfg#define KDATA_CLIENT_SCRATCH0 (KDATA_BASE_ADDR + 0x006E) 603230401Spfg#define KDATA_CLIENT_SCRATCH1 (KDATA_BASE_ADDR + 0x006F) 604230401Spfg#define KDATA_KERNEL_SCRATCH (KDATA_BASE_ADDR + 0x0070) 605230401Spfg#define KDATA_KERNEL_ISR_SCRATCH (KDATA_BASE_ADDR + 0x0071) 606230401Spfg 607230401Spfg#define KDATA_OUEUE_LEFT (KDATA_BASE_ADDR + 0x0072) 608230401Spfg#define KDATA_QUEUE_RIGHT (KDATA_BASE_ADDR + 0x0073) 609230401Spfg 610230401Spfg#define KDATA_ADC1_REQUEST (KDATA_BASE_ADDR + 0x0074) 611230401Spfg#define KDATA_ADC2_REQUEST (KDATA_BASE_ADDR + 0x0075) 612230401Spfg#define KDATA_CD_REQUEST (KDATA_BASE_ADDR + 0x0076) 613230401Spfg#define KDATA_MIC_REQUEST (KDATA_BASE_ADDR + 0x0077) 614230401Spfg 615230401Spfg#define KDATA_ADC1_MIXER_REQUEST (KDATA_BASE_ADDR + 0x0078) 616230401Spfg#define KDATA_ADC2_MIXER_REQUEST (KDATA_BASE_ADDR + 0x0079) 617230401Spfg#define KDATA_CD_MIXER_REQUEST (KDATA_BASE_ADDR + 0x007A) 618230401Spfg#define KDATA_MIC_MIXER_REQUEST (KDATA_BASE_ADDR + 0x007B) 619230401Spfg#define KDATA_MIC_SYNC_COUNTER (KDATA_BASE_ADDR + 0x007C) 620230401Spfg 621230401Spfg/* 622230401Spfg * second segment 623230401Spfg */ 624230401Spfg 625230401Spfg/* smart mixer buffer */ 626230401Spfg 627230401Spfg#define KDATA_MIXER_WORD0 (KDATA_BASE_ADDR2 + 0x0000) 628230401Spfg#define KDATA_MIXER_WORD1 (KDATA_BASE_ADDR2 + 0x0001) 629230401Spfg#define KDATA_MIXER_WORD2 (KDATA_BASE_ADDR2 + 0x0002) 630230401Spfg#define KDATA_MIXER_WORD3 (KDATA_BASE_ADDR2 + 0x0003) 631230401Spfg#define KDATA_MIXER_WORD4 (KDATA_BASE_ADDR2 + 0x0004) 632230401Spfg#define KDATA_MIXER_WORD5 (KDATA_BASE_ADDR2 + 0x0005) 633230401Spfg#define KDATA_MIXER_WORD6 (KDATA_BASE_ADDR2 + 0x0006) 634230401Spfg#define KDATA_MIXER_WORD7 (KDATA_BASE_ADDR2 + 0x0007) 635230401Spfg#define KDATA_MIXER_WORD8 (KDATA_BASE_ADDR2 + 0x0008) 636230401Spfg#define KDATA_MIXER_WORD9 (KDATA_BASE_ADDR2 + 0x0009) 637230401Spfg#define KDATA_MIXER_WORDA (KDATA_BASE_ADDR2 + 0x000A) 638230401Spfg#define KDATA_MIXER_WORDB (KDATA_BASE_ADDR2 + 0x000B) 639230401Spfg#define KDATA_MIXER_WORDC (KDATA_BASE_ADDR2 + 0x000C) 640230401Spfg#define KDATA_MIXER_WORDD (KDATA_BASE_ADDR2 + 0x000D) 641230401Spfg#define KDATA_MIXER_WORDE (KDATA_BASE_ADDR2 + 0x000E) 642230401Spfg#define KDATA_MIXER_WORDF (KDATA_BASE_ADDR2 + 0x000F) 643230401Spfg 644230401Spfg#define KDATA_MIXER_XFER0 (KDATA_BASE_ADDR2 + 0x0010) 645230401Spfg#define KDATA_MIXER_XFER1 (KDATA_BASE_ADDR2 + 0x0011) 646230401Spfg#define KDATA_MIXER_XFER2 (KDATA_BASE_ADDR2 + 0x0012) 647230401Spfg#define KDATA_MIXER_XFER3 (KDATA_BASE_ADDR2 + 0x0013) 648230401Spfg#define KDATA_MIXER_XFER4 (KDATA_BASE_ADDR2 + 0x0014) 649230401Spfg#define KDATA_MIXER_XFER5 (KDATA_BASE_ADDR2 + 0x0015) 650230401Spfg#define KDATA_MIXER_XFER6 (KDATA_BASE_ADDR2 + 0x0016) 651230401Spfg#define KDATA_MIXER_XFER7 (KDATA_BASE_ADDR2 + 0x0017) 652230401Spfg#define KDATA_MIXER_XFER8 (KDATA_BASE_ADDR2 + 0x0018) 653230401Spfg#define KDATA_MIXER_XFER9 (KDATA_BASE_ADDR2 + 0x0019) 654230401Spfg#define KDATA_MIXER_XFER_ENDMARK (KDATA_BASE_ADDR2 + 0x001A) 655230401Spfg 656230401Spfg#define KDATA_MIXER_TASK_NUMBER (KDATA_BASE_ADDR2 + 0x001B) 657230401Spfg#define KDATA_CURRENT_MIXER (KDATA_BASE_ADDR2 + 0x001C) 658230401Spfg#define KDATA_MIXER_ACTIVE (KDATA_BASE_ADDR2 + 0x001D) 659230401Spfg#define KDATA_MIXER_BANK_STATUS (KDATA_BASE_ADDR2 + 0x001E) 660230401Spfg#define KDATA_DAC_LEFT_VOLUME (KDATA_BASE_ADDR2 + 0x001F) 661230401Spfg#define KDATA_DAC_RIGHT_VOLUME (KDATA_BASE_ADDR2 + 0x0020) 662230401Spfg 663230401Spfg/* 664230401Spfg * Client data memory definition 665230401Spfg */ 666230401Spfg 667230401Spfg#define CDATA_INSTANCE_READY 0x00 668230401Spfg 669230401Spfg#define CDATA_HOST_SRC_ADDRL 0x01 670230401Spfg#define CDATA_HOST_SRC_ADDRH 0x02 671230401Spfg#define CDATA_HOST_SRC_END_PLUS_1L 0x03 672230401Spfg#define CDATA_HOST_SRC_END_PLUS_1H 0x04 673230401Spfg#define CDATA_HOST_SRC_CURRENTL 0x05 674230401Spfg#define CDATA_HOST_SRC_CURRENTH 0x06 675230401Spfg 676230401Spfg#define CDATA_IN_BUF_CONNECT 0x07 677230401Spfg#define CDATA_OUT_BUF_CONNECT 0x08 678230401Spfg 679230401Spfg#define CDATA_IN_BUF_BEGIN 0x09 680230401Spfg#define CDATA_IN_BUF_END_PLUS_1 0x0A 681230401Spfg#define CDATA_IN_BUF_HEAD 0x0B 682230401Spfg#define CDATA_IN_BUF_TAIL 0x0C 683230401Spfg 684230401Spfg#define CDATA_OUT_BUF_BEGIN 0x0D 685230401Spfg#define CDATA_OUT_BUF_END_PLUS_1 0x0E 686230401Spfg#define CDATA_OUT_BUF_HEAD 0x0F 687230401Spfg#define CDATA_OUT_BUF_TAIL 0x10 688230401Spfg 689230401Spfg#define CDATA_DMA_CONTROL 0x11 690230401Spfg#define CDATA_RESERVED 0x12 691230401Spfg 692230401Spfg#define CDATA_FREQUENCY 0x13 693230401Spfg#define CDATA_LEFT_VOLUME 0x14 694230401Spfg#define CDATA_RIGHT_VOLUME 0x15 695230401Spfg#define CDATA_LEFT_SUR_VOL 0x16 696230401Spfg#define CDATA_RIGHT_SUR_VOL 0x17 697230401Spfg 698230401Spfg/* These are from Allegro hckernel.h */ 699230401Spfg#define CDATA_HEADER_LEN 0x18 700230401Spfg#define SRC3_DIRECTION_OFFSET CDATA_HEADER_LEN 701230401Spfg#define SRC3_MODE_OFFSET CDATA_HEADER_LEN + 1 702230401Spfg#define SRC3_WORD_LENGTH_OFFSET CDATA_HEADER_LEN + 2 703230401Spfg#define SRC3_PARAMETER_OFFSET CDATA_HEADER_LEN + 3 704230401Spfg#define SRC3_COEFF_ADDR_OFFSET CDATA_HEADER_LEN + 8 705230401Spfg#define SRC3_FILTAP_ADDR_OFFSET CDATA_HEADER_LEN + 10 706230401Spfg#define SRC3_TEMP_INBUF_ADDR_OFFSET CDATA_HEADER_LEN + 16 707230401Spfg#define SRC3_TEMP_OUTBUF_ADDR_OFFSET CDATA_HEADER_LEN + 17 708230401Spfg#define FOR_FUTURE_USE 10 /* for storing temporary variable in future */ 709230401Spfg 710230401Spfg/* 711230401Spfg * DMA control definition 712230401Spfg */ 713230401Spfg 714230401Spfg#define DMACONTROL_BLOCK_MASK 0x000F 715230401Spfg#define DMAC_BLOCK0_SELECTOR 0x0000 716230401Spfg#define DMAC_BLOCK1_SELECTOR 0x0001 717230401Spfg#define DMAC_BLOCK2_SELECTOR 0x0002 718230401Spfg#define DMAC_BLOCK3_SELECTOR 0x0003 719230401Spfg#define DMAC_BLOCK4_SELECTOR 0x0004 720230401Spfg#define DMAC_BLOCK5_SELECTOR 0x0005 721230401Spfg#define DMAC_BLOCK6_SELECTOR 0x0006 722230401Spfg#define DMAC_BLOCK7_SELECTOR 0x0007 723230401Spfg#define DMAC_BLOCK8_SELECTOR 0x0008 724230401Spfg#define DMAC_BLOCK9_SELECTOR 0x0009 725230401Spfg#define DMAC_BLOCKA_SELECTOR 0x000A 726230401Spfg#define DMAC_BLOCKB_SELECTOR 0x000B 727230401Spfg#define DMAC_BLOCKC_SELECTOR 0x000C 728230401Spfg#define DMAC_BLOCKD_SELECTOR 0x000D 729230401Spfg#define DMAC_BLOCKE_SELECTOR 0x000E 730230401Spfg#define DMAC_BLOCKF_SELECTOR 0x000F 731230401Spfg#define DMACONTROL_PAGE_MASK 0x00F0 732230401Spfg#define DMAC_PAGE0_SELECTOR 0x0030 733230401Spfg#define DMAC_PAGE1_SELECTOR 0x0020 734230401Spfg#define DMAC_PAGE2_SELECTOR 0x0010 735230401Spfg#define DMAC_PAGE3_SELECTOR 0x0000 736230401Spfg#define DMACONTROL_AUTOREPEAT 0x1000 737230401Spfg#define DMACONTROL_STOPPED 0x2000 738230401Spfg#define DMACONTROL_DIRECTION 0x0100 739230401Spfg 740230401Spfg/* 741230401Spfg * Kernel/client memory allocation 742230401Spfg */ 743230401Spfg 744230401Spfg#define NUM_UNITS_KERNEL_CODE 16 745230401Spfg#define NUM_UNITS_KERNEL_DATA 2 746230401Spfg 747230401Spfg#define NUM_UNITS_KERNEL_CODE_WITH_HSP 16 748230401Spfg#ifdef M3_MODEL 749230401Spfg#define NUM_UNITS_KERNEL_DATA_WITH_HSP 5 750230401Spfg#else 751230401Spfg#define NUM_UNITS_KERNEL_DATA_WITH_HSP 4 752230401Spfg#endif 753230401Spfg 754230401Spfg#define NUM_UNITS( BYTES, UNITLEN ) ((((BYTES+1)>>1) + (UNITLEN-1)) / UNITLEN) 755230401Spfg 756230401Spfg/* 757230401Spfg * DSP hardware 758230401Spfg */ 759230401Spfg 760230401Spfg#define DSP_PORT_TIMER_COUNT 0x06 761230401Spfg#define DSP_PORT_MEMORY_INDEX 0x80 762230401Spfg#define DSP_PORT_MEMORY_TYPE 0x82 763230401Spfg#define DSP_PORT_MEMORY_DATA 0x84 764230401Spfg#define DSP_PORT_CONTROL_REG_A 0xA2 765230401Spfg#define DSP_PORT_CONTROL_REG_B 0xA4 766230401Spfg#define DSP_PORT_CONTROL_REG_C 0xA6 767230401Spfg 768230401Spfg#define MEMTYPE_INTERNAL_CODE 0x0002 769230401Spfg#define MEMTYPE_INTERNAL_DATA 0x0003 770230401Spfg#define MEMTYPE_MASK 0x0003 771230401Spfg 772230401Spfg#define REGB_ENABLE_RESET 0x01 773230401Spfg#define REGB_STOP_CLOCK 0x10 774230401Spfg 775230401Spfg#define REGC_DISABLE_FM_MAPPING 0x02 776230401Spfg 777230401Spfg#define DP_SHIFT_COUNT 7 778230401Spfg 779230401Spfg#define DMA_BLOCK_LENGTH 32 780230401Spfg 781230401Spfg/* These are from Allegro srcmgr.h */ 782230401Spfg#define MINISRC_BIQUAD_STAGE 2 783230401Spfg#define MINISRC_IN_BUFFER_SIZE ( 0x50 * 2 ) 784230401Spfg#define MINISRC_OUT_BUFFER_SIZE ( 0x50 * 2 * 2) 785230401Spfg#define MINISRC_TMP_BUFFER_SIZE ( 112 + ( MINISRC_BIQUAD_STAGE * 3 + 4 ) * 2 * 2 ) 786230401Spfg#define MINISRC_BIQUAD_STAGE 2 787230401Spfg/* M. SRC LPF coefficient could be changed in the DSP code */ 788230401Spfg#define MINISRC_COEF_LOC 0X175 789230401Spfg 790230401Spfg#endif /* !_DEV_SOUND_PCI_ALLEGRO_REG_H */ 791