1139749Simp/*- 2139749Simp * Copyright (c) 1999 Doug Rabson 3166427Sjoel * Copyright (c) 1997 Luigi Rizzo 4139749Simp * All rights reserved. 5139749Simp * 6139749Simp * Redistribution and use in source and binary forms, with or without 7139749Simp * modification, are permitted provided that the following conditions 8139749Simp * are met: 9139749Simp * 1. Redistributions of source code must retain the above copyright 10139749Simp * notice, this list of conditions and the following disclaimer. 11139749Simp * 2. Redistributions in binary form must reproduce the above copyright 12139749Simp * notice, this list of conditions and the following disclaimer in the 13139749Simp * documentation and/or other materials provided with the distribution. 14139749Simp * 15139749Simp * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 16139749Simp * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 17139749Simp * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 18139749Simp * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 19139749Simp * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 20139749Simp * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 21139749Simp * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 22139749Simp * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 23139749Simp * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 24139749Simp * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 25139749Simp * SUCH DAMAGE. 26139749Simp * 27139749Simp * $FreeBSD$ 28139749Simp */ 29139749Simp 3029415Sjmg/* 31166426Sjoel * This file contains information and macro definitions for 32166426Sjoel * AD1848-compatible devices, used in the MSS/WSS compatible boards. 33166426Sjoel */ 34166426Sjoel 35166426Sjoel/* 3629415Sjmg * 3729415Sjmg 3829415SjmgThe codec part of the board is seen as a set of 4 registers mapped 3929415Sjmgat the base address for the board (default 0x534). Note that some 4029415Sjmg(early) boards implemented 4 additional registers 4 location before 4129415Sjmg(usually 0x530) to store configuration information. This is a source 4229415Sjmgof confusion in that one never knows what address to specify. The 4329415Sjmg(current) convention is to use the old address (0x530) in the kernel 4429415Sjmgconfiguration file and consider MSS registers start four location 4529415Sjmgahead. 4629415Sjmg 4729415Sjmg * 4829415Sjmg */ 4929415Sjmg 5074763Scgstruct mixer_def { 5174763Scg u_int regno:7; 5274763Scg u_int polarity:1; /* 1 means reversed */ 5374763Scg u_int bitoffs:4; 5474763Scg u_int nbits:4; 5574763Scg}; 5674763Scgtypedef struct mixer_def mixer_ent; 5774763Scgtypedef struct mixer_def mixer_tab[32][2]; 5874763Scg 5974763Scg#define MIX_ENT(name, reg_l, pol_l, pos_l, len_l, reg_r, pol_r, pos_r, len_r) \ 6074763Scg {{reg_l, pol_l, pos_l, len_l}, {reg_r, pol_r, pos_r, len_r}} 6174763Scg 6274763Scg#define PMIX_ENT(name, reg_l, pos_l, len_l, reg_r, pos_r, len_r) \ 6374763Scg {{reg_l, 0, pos_l, len_l}, {reg_r, 0, pos_r, len_r}} 6474763Scg 6574763Scg#define MIX_NONE(name) MIX_ENT(name, 0,0,0,0, 0,0,0,0) 6674763Scg 6729415Sjmg/* 6829415Sjmg * The four visible registers of the MSS : 6929415Sjmg * 7029415Sjmg */ 7129415Sjmg 7250723Scg#define MSS_INDEX (0 + 4) 7350723Scg#define MSS_IDXBUSY 0x80 /* readonly, set when busy */ 7450723Scg#define MSS_MCE 0x40 /* the MCE bit. */ 7529415Sjmg /* 7629415Sjmg * the MCE bit must be set whenever the current mode of the 7729415Sjmg * codec is changed; this in particular is true for the 7829415Sjmg * Data Format (I8, I28) and Interface Config(I9) registers. 7929415Sjmg * Only exception are CEN and PEN which can be changed on the fly. 8029415Sjmg * The DAC output is muted when MCE is set. 8129415Sjmg */ 8250723Scg#define MSS_TRD 0x20 /* Transfer request disable */ 8329415Sjmg /* 8429415Sjmg * When TRD is set, DMA transfers cease when the INT bit in 8529415Sjmg * the MSS status reg is set. Must be cleared for automode 8629415Sjmg * DMA, set otherwise. 8729415Sjmg */ 8850723Scg#define MSS_IDXMASK 0x1f /* mask for indirect address */ 8929415Sjmg 9050723Scg#define MSS_IDATA (1 + 4) 9129415Sjmg /* 9229415Sjmg * data to be transferred to the indirect register addressed 9329415Sjmg * by index addr. During init and sw. powerdown, cannot be 9429415Sjmg * written to, and is always read as 0x80 (consistent with the 9529415Sjmg * busy flag). 9629415Sjmg */ 9729415Sjmg 9850723Scg#define MSS_STATUS (2 + 4) 9929415Sjmg 10029415Sjmg#define IS_CUL 0x80 /* capture upper/lower */ 10129415Sjmg#define IS_CLR 0x40 /* capture left/right */ 10229415Sjmg#define IS_CRDY 0x20 /* capture ready for programmed i/o */ 10329415Sjmg#define IS_SER 0x10 /* sample error (overrun/underrun) */ 10429415Sjmg#define IS_PUL 0x08 /* playback upper/lower */ 10529415Sjmg#define IS_PLR 0x04 /* playback left/right */ 10629415Sjmg#define IS_PRDY 0x02 /* playback ready for programmed i/o */ 10729415Sjmg#define IS_INT 0x01 /* int status (1 = active) */ 10829415Sjmg /* 10929415Sjmg * IS_INT is clreared by any write to the status register. 11029415Sjmg */ 11150723Scg#if 0 11229415Sjmg#define io_Polled_IO(d) ((d)->io_base+3+4) 11329415Sjmg /* 11429415Sjmg * this register is used in case of polled i/o 11529415Sjmg */ 11650723Scg#endif 11729415Sjmg 11829415Sjmg/* 11929415Sjmg * The MSS has a set of 16 (or 32 depending on the model) indirect 12029415Sjmg * registers accessible through the data port by specifying the 12129415Sjmg * appropriate address in the address register. 12229415Sjmg * 12329415Sjmg * The 16 low registers are uniformly handled in AD1848/CS4248 compatible 12429415Sjmg * mode (often called MODE1). For the upper 16 registers there are 12529415Sjmg * some differences among different products, mainly Crystal uses them 12629415Sjmg * differently from OPTi. 12729415Sjmg * 12829415Sjmg */ 12929415Sjmg 13029415Sjmg/* 13129415Sjmg * volume registers 13229415Sjmg */ 13329415Sjmg 13429415Sjmg#define I6_MUTE 0x80 13529415Sjmg 13629415Sjmg/* 13729415Sjmg * register I9 -- interface configuration. 13829415Sjmg */ 13929415Sjmg 14029415Sjmg#define I9_PEN 0x01 /* playback enable */ 14129415Sjmg#define I9_CEN 0x02 /* capture enable */ 14229415Sjmg 14329415Sjmg/* 14429415Sjmg * values used in bd_flags 14529415Sjmg */ 14629415Sjmg#define BD_F_MCE_BIT 0x0001 14729415Sjmg#define BD_F_IRQ_OK 0x0002 14829415Sjmg#define BD_F_TMR_RUN 0x0004 14950723Scg#define BD_F_MSS_OFFSET 0x0008 /* offset mss writes by -4 */ 15050723Scg#define BD_F_DUPLEX 0x0010 15174711Scg#define BD_F_924PNP 0x0020 /* OPTi924 is in PNP mode */ 15229415Sjmg 15329415Sjmg/* 15429415Sjmg * sound/ad1848_mixer.h 15550723Scg * 15629415Sjmg * Definitions for the mixer of AD1848 and compatible codecs. 15750723Scg * 15829415Sjmg * Copyright by Hannu Savolainen 1994 15950723Scg * 16029415Sjmg * Redistribution and use in source and binary forms, with or without 16129415Sjmg * modification, are permitted provided that the following conditions are 16229415Sjmg * met: 1. Redistributions of source code must retain the above copyright 16329415Sjmg * notice, this list of conditions and the following disclaimer. 2. 16429415Sjmg * Redistributions in binary form must reproduce the above copyright notice, 16529415Sjmg * this list of conditions and the following disclaimer in the documentation 16629415Sjmg * and/or other materials provided with the distribution. 16750723Scg * 16829415Sjmg * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND ANY 16929415Sjmg * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 17029415Sjmg * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 17129415Sjmg * DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR 17229415Sjmg * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 17329415Sjmg * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 17429415Sjmg * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER 17529415Sjmg * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 17629415Sjmg * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 17729415Sjmg * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 17829415Sjmg * SUCH DAMAGE. 17929415Sjmg */ 18029415Sjmg/* 18129415Sjmg * The AD1848 codec has generic input lines called Line, Aux1 and Aux2. 18229415Sjmg * Soundcard manufacturers have connected actual inputs (CD, synth, line, 18329415Sjmg * etc) to these inputs in different order. Therefore it's difficult 18429415Sjmg * to assign mixer channels to to these inputs correctly. The following 18529415Sjmg * contains two alternative mappings. The first one is for GUS MAX and 18629415Sjmg * the second is just a generic one (line1, line2 and line3). 18729415Sjmg * (Actually this is not a mapping but rather some kind of interleaving 18829415Sjmg * solution). 18929415Sjmg */ 19030869Sjmg 19130869Sjmg#define MSS_REC_DEVICES \ 19229415Sjmg (SOUND_MASK_LINE | SOUND_MASK_MIC | SOUND_MASK_CD|SOUND_MASK_IMIX) 19329415Sjmg 19429415Sjmg 19529415Sjmg/* 19630869Sjmg * Table of mixer registers. There is a default table for the 19774711Scg * AD1848/CS423x clones, one for the OPTI931 and one for the 19874711Scg * OPTi930. As more MSS clones come out, there ought to be 19974711Scg * more tables. 20029415Sjmg * 20130869Sjmg * Fields in the table are : polarity, register, offset, bits 20230869Sjmg * 20329415Sjmg * The channel numbering used by individual soundcards is not fixed. 20429415Sjmg * Some cards have assigned different meanings for the AUX1, AUX2 20529415Sjmg * and LINE inputs. Some have different features... 20629415Sjmg * 20730869Sjmg * Following there is a macro ...MIXER_DEVICES which is a bitmap 20830869Sjmg * of all non-zero fields in the table. 20930869Sjmg * MODE1_MIXER_DEVICES is the basic mixer of the 1848 in mode 1 21030869Sjmg * registers I0..I15) 21130869Sjmg * 21229415Sjmg */ 21329415Sjmg 21430869Sjmgmixer_ent mix_devices[32][2] = { 21530869SjmgMIX_NONE(SOUND_MIXER_VOLUME), 21630869SjmgMIX_NONE(SOUND_MIXER_BASS), 21730869SjmgMIX_NONE(SOUND_MIXER_TREBLE), 21874797Scg#ifdef PC98 /* PC98's synth is assigned to AUX#2 */ 21960711SnyanMIX_ENT(SOUND_MIXER_SYNTH, 4, 1, 0, 5, 5, 1, 0, 5), 22074797Scg#else /* AT386's synth is assigned to AUX#1 */ 22130869SjmgMIX_ENT(SOUND_MIXER_SYNTH, 2, 1, 0, 5, 3, 1, 0, 5), 22260711Snyan#endif 22329415SjmgMIX_ENT(SOUND_MIXER_PCM, 6, 1, 0, 6, 7, 1, 0, 6), 22429415SjmgMIX_ENT(SOUND_MIXER_SPEAKER, 26, 1, 0, 4, 0, 0, 0, 0), 22529415SjmgMIX_ENT(SOUND_MIXER_LINE, 18, 1, 0, 5, 19, 1, 0, 5), 22629415SjmgMIX_ENT(SOUND_MIXER_MIC, 0, 0, 5, 1, 1, 0, 5, 1), 22774797Scg#ifdef PC98 /* PC98's cd-audio is assigned to AUX#1 */ 22860711SnyanMIX_ENT(SOUND_MIXER_CD, 2, 1, 0, 5, 3, 1, 0, 5), 22974797Scg#else /* AT386's cd-audio is assigned to AUX#2 */ 23030869SjmgMIX_ENT(SOUND_MIXER_CD, 4, 1, 0, 5, 5, 1, 0, 5), 23160711Snyan#endif 23229415SjmgMIX_ENT(SOUND_MIXER_IMIX, 13, 1, 2, 6, 0, 0, 0, 0), 23330869SjmgMIX_NONE(SOUND_MIXER_ALTPCM), 23430869SjmgMIX_NONE(SOUND_MIXER_RECLEV), 23529415SjmgMIX_ENT(SOUND_MIXER_IGAIN, 0, 0, 0, 4, 1, 0, 0, 4), 23630869SjmgMIX_NONE(SOUND_MIXER_OGAIN), 23730869SjmgMIX_NONE(SOUND_MIXER_LINE1), 23830869SjmgMIX_NONE(SOUND_MIXER_LINE2), 23930869SjmgMIX_NONE(SOUND_MIXER_LINE3), 24029415Sjmg}; 24129415Sjmg 24230869Sjmg#define MODE2_MIXER_DEVICES \ 24330869Sjmg (SOUND_MASK_SYNTH | SOUND_MASK_PCM | SOUND_MASK_SPEAKER | \ 24430869Sjmg SOUND_MASK_LINE | SOUND_MASK_MIC | SOUND_MASK_CD | \ 24530869Sjmg SOUND_MASK_IMIX | SOUND_MASK_IGAIN ) 24630869Sjmg 24730869Sjmg#define MODE1_MIXER_DEVICES \ 24830869Sjmg (SOUND_MASK_SYNTH | SOUND_MASK_PCM | SOUND_MASK_MIC | \ 24930869Sjmg SOUND_MASK_CD | SOUND_MASK_IMIX | SOUND_MASK_IGAIN ) 25030869Sjmg 25130869Sjmg 25274711Scgmixer_ent opti930_devices[32][2] = { 25374711ScgMIX_ENT(SOUND_MIXER_VOLUME, 22, 1, 0, 4, 23, 1, 0, 4), 25474711ScgMIX_NONE(SOUND_MIXER_BASS), 25574711ScgMIX_NONE(SOUND_MIXER_TREBLE), 25674711ScgMIX_ENT(SOUND_MIXER_SYNTH, 4, 1, 0, 4, 5, 1, 0, 4), 25774711ScgMIX_ENT(SOUND_MIXER_PCM, 6, 1, 1, 5, 7, 1, 1, 5), 25874711ScgMIX_ENT(SOUND_MIXER_LINE, 18, 1, 1, 4, 19, 1, 1, 4), 25974711ScgMIX_NONE(SOUND_MIXER_SPEAKER), 26074711ScgMIX_ENT(SOUND_MIXER_MIC, 21, 1, 0, 4, 22, 1, 0, 4), 26174711ScgMIX_ENT(SOUND_MIXER_CD, 2, 1, 1, 4, 3, 1, 1, 4), 26274711ScgMIX_NONE(SOUND_MIXER_IMIX), 26374711ScgMIX_NONE(SOUND_MIXER_ALTPCM), 26474711ScgMIX_NONE(SOUND_MIXER_RECLEV), 26574711ScgMIX_NONE(SOUND_MIXER_IGAIN), 26674711ScgMIX_NONE(SOUND_MIXER_OGAIN), 26774711ScgMIX_NONE(SOUND_MIXER_LINE1), 26874711ScgMIX_NONE(SOUND_MIXER_LINE2), 26974711ScgMIX_NONE(SOUND_MIXER_LINE3), 27074711Scg}; 27174711Scg 27274711Scg#define OPTI930_MIXER_DEVICES \ 27374711Scg (SOUND_MASK_VOLUME | SOUND_MASK_SYNTH | SOUND_MASK_PCM | \ 27474711Scg SOUND_MASK_LINE | SOUND_MASK_MIC | SOUND_MASK_CD ) 27574711Scg 27630869Sjmg/* 27730869Sjmg * entries for the opti931... 27830869Sjmg */ 27930869Sjmg 28029415Sjmgmixer_ent opti931_devices[32][2] = { /* for the opti931 */ 28129415SjmgMIX_ENT(SOUND_MIXER_VOLUME, 22, 1, 1, 5, 23, 1, 1, 5), 28230869SjmgMIX_NONE(SOUND_MIXER_BASS), 28330869SjmgMIX_NONE(SOUND_MIXER_TREBLE), 28429415SjmgMIX_ENT(SOUND_MIXER_SYNTH, 4, 1, 1, 4, 5, 1, 1, 4), 28529415SjmgMIX_ENT(SOUND_MIXER_PCM, 6, 1, 0, 5, 7, 1, 0, 5), 28630869SjmgMIX_NONE(SOUND_MIXER_SPEAKER), 28729415SjmgMIX_ENT(SOUND_MIXER_LINE, 18, 1, 1, 4, 19, 1, 1, 4), 28829415SjmgMIX_ENT(SOUND_MIXER_MIC, 0, 0, 5, 1, 1, 0, 5, 1), 28929415SjmgMIX_ENT(SOUND_MIXER_CD, 2, 1, 1, 4, 3, 1, 1, 4), 29030869SjmgMIX_NONE(SOUND_MIXER_IMIX), 29130869SjmgMIX_NONE(SOUND_MIXER_ALTPCM), 29230869SjmgMIX_NONE(SOUND_MIXER_RECLEV), 29329415SjmgMIX_ENT(SOUND_MIXER_IGAIN, 0, 0, 0, 4, 1, 0, 0, 4), 29430869SjmgMIX_NONE(SOUND_MIXER_OGAIN), 29530869SjmgMIX_ENT(SOUND_MIXER_LINE1, 16, 1, 1, 4, 17, 1, 1, 4), 29630869SjmgMIX_NONE(SOUND_MIXER_LINE2), 29730869SjmgMIX_NONE(SOUND_MIXER_LINE3), 29829415Sjmg}; 29929415Sjmg 30030869Sjmg#define OPTI931_MIXER_DEVICES \ 30130869Sjmg (SOUND_MASK_VOLUME | SOUND_MASK_SYNTH | SOUND_MASK_PCM | \ 30230869Sjmg SOUND_MASK_LINE | SOUND_MASK_MIC | SOUND_MASK_CD | \ 30330869Sjmg SOUND_MASK_IGAIN | SOUND_MASK_LINE1 ) 30430869Sjmg 30550723Scg/* 30650723Scg * Register definitions for the Yamaha OPL3-SA[23x]. 30750723Scg */ 30850723Scg#define OPL3SAx_POWER 0x01 /* Power Management (R/W) */ 30950723Scg#define OPL3SAx_POWER_PDX 0x01 /* Set to 1 to halt oscillator */ 31050723Scg#define OPL3SAx_POWER_PDN 0x02 /* Set to 1 to power down */ 31150723Scg#define OPL3SAx_POWER_PSV 0x04 /* Set to 1 to power save */ 31250723Scg#define OPL3SAx_POWER_ADOWN 0x20 /* Analog power (?) */ 31350723Scg 31450723Scg#define OPL3SAx_SYSTEM 0x02 /* System control (R/W) */ 31550723Scg#define OPL3SAx_SYSTEM_VZE 0x01 /* I2S audio routing */ 31650723Scg#define OPL3SAx_SYSTEM_IDSEL 0x03 /* SB compat version select */ 31750723Scg#define OPL3SAx_SYSTEM_SBHE 0x80 /* 0 for AT bus, 1 for XT bus */ 31850723Scg 31950723Scg#define OPL3SAx_IRQCONF 0x03 /* Interrupt configuration (R/W */ 32050723Scg#define OPL3SAx_IRQCONF_WSSA 0x01 /* WSS interrupts through IRQA */ 32150723Scg#define OPL3SAx_IRQCONF_SBA 0x02 /* WSS interrupts through IRQA */ 32250723Scg#define OPL3SAx_IRQCONF_MPUA 0x04 /* WSS interrupts through IRQA */ 32350723Scg#define OPL3SAx_IRQCONF_OPL3A 0x08 /* WSS interrupts through IRQA */ 32450723Scg#define OPL3SAx_IRQCONF_WSSB 0x10 /* WSS interrupts through IRQB */ 32550723Scg#define OPL3SAx_IRQCONF_SBB 0x20 /* WSS interrupts through IRQB */ 32650723Scg#define OPL3SAx_IRQCONF_MPUB 0x40 /* WSS interrupts through IRQB */ 32750723Scg#define OPL3SAx_IRQCONF_OPL3B 0x80 /* WSS interrupts through IRQB */ 32850723Scg 32950723Scg#define OPL3SAx_IRQSTATUSA 0x04 /* Interrupt (IRQ-A) Status (RO) */ 33050723Scg#define OPL3SAx_IRQSTATUSB 0x05 /* Interrupt (IRQ-B) Status (RO) */ 33150723Scg#define OPL3SAx_IRQSTATUS_PI 0x01 /* Playback Flag of CODEC */ 33250723Scg#define OPL3SAx_IRQSTATUS_CI 0x02 /* Recording Flag of CODEC */ 33350723Scg#define OPL3SAx_IRQSTATUS_TI 0x04 /* Timer Flag of CODEC */ 33450723Scg#define OPL3SAx_IRQSTATUS_SB 0x08 /* SB compat Playback Interrupt Flag */ 33550723Scg#define OPL3SAx_IRQSTATUS_MPU 0x10 /* MPU401 Interrupt Flag */ 33650723Scg#define OPL3SAx_IRQSTATUS_OPL3 0x20 /* Internal FM Timer Flag */ 33750723Scg#define OPL3SAx_IRQSTATUS_MV 0x40 /* HW Volume Interrupt Flag */ 33850723Scg#define OPL3SAx_IRQSTATUS_PI 0x01 /* Playback Flag of CODEC */ 33950723Scg#define OPL3SAx_IRQSTATUS_CI 0x02 /* Recording Flag of CODEC */ 34050723Scg#define OPL3SAx_IRQSTATUS_TI 0x04 /* Timer Flag of CODEC */ 34150723Scg#define OPL3SAx_IRQSTATUS_SB 0x08 /* SB compat Playback Interrupt Flag */ 34250723Scg#define OPL3SAx_IRQSTATUS_MPU 0x10 /* MPU401 Interrupt Flag */ 34350723Scg#define OPL3SAx_IRQSTATUS_OPL3 0x20 /* Internal FM Timer Flag */ 34450723Scg#define OPL3SAx_IRQSTATUS_MV 0x40 /* HW Volume Interrupt Flag */ 34550723Scg 34650723Scg#define OPL3SAx_DMACONF 0x06 /* DMA configuration (R/W) */ 34750723Scg#define OPL3SAx_DMACONF_WSSPA 0x01 /* WSS Playback on DMA-A */ 34850723Scg#define OPL3SAx_DMACONF_WSSRA 0x02 /* WSS Recording on DMA-A */ 34950723Scg#define OPL3SAx_DMACONF_SBA 0x02 /* SB Playback on DMA-A */ 35050723Scg#define OPL3SAx_DMACONF_WSSPB 0x10 /* WSS Playback on DMA-A */ 35150723Scg#define OPL3SAx_DMACONF_WSSRB 0x20 /* WSS Recording on DMA-A */ 35250723Scg#define OPL3SAx_DMACONF_SBB 0x20 /* SB Playback on DMA-A */ 35350723Scg 35450723Scg#define OPL3SAx_VOLUMEL 0x07 /* Master Volume Left (R/W) */ 35550723Scg#define OPL3SAx_VOLUMEL_MVL 0x0f /* Attenuation level */ 35650723Scg#define OPL3SAx_VOLUMEL_MVLM 0x80 /* Mute */ 35750723Scg 35850723Scg#define OPL3SAx_VOLUMER 0x08 /* Master Volume Right (R/W) */ 35950723Scg#define OPL3SAx_VOLUMER_MVR 0x0f /* Attenuation level */ 36050723Scg#define OPL3SAx_VOLUMER_MVRM 0x80 /* Mute */ 36150723Scg 36250723Scg#define OPL3SAx_MIC 0x09 /* MIC Volume (R/W) */ 36350723Scg#define OPL3SAx_VOLUMER_MCV 0x1f /* Attenuation level */ 36450723Scg#define OPL3SAx_VOLUMER_MICM 0x80 /* Mute */ 36550723Scg 36650723Scg#define OPL3SAx_MISC 0x0a /* Miscellaneous */ 36750723Scg#define OPL3SAx_MISC_VER 0x07 /* Version */ 36850723Scg#define OPL3SAx_MISC_MODE 0x08 /* SB or WSS mode */ 36950723Scg#define OPL3SAx_MISC_MCSW 0x10 /* */ 37050723Scg#define OPL3SAx_MISC_VEN 0x80 /* Enable hardware volume control */ 37150723Scg 37250723Scg#define OPL3SAx_WSSDMA 0x0b /* WSS DMA Counter (RW) (4 regs) */ 37350723Scg 37450723Scg#define OPL3SAx_WSSIRQSCAN 0x0f /* WSS Interrupt Scan out/in (R/W) */ 37550723Scg#define OPL3SAx_WSSIRQSCAN_SPI 0x01 37650723Scg#define OPL3SAx_WSSIRQSCAN_SCI 0x02 37750723Scg#define OPL3SAx_WSSIRQSCAN_STI 0x04 37850723Scg 37950723Scg#define OPL3SAx_SBSTATE 0x10 /* SB compat Internal State (R/W) */ 38050723Scg#define OPL3SAx_SBSTATE_SBPDR 0x01 /* SB Power Down Request */ 38150723Scg#define OPL3SAx_SBSTATE_SE 0x02 /* Scan Enable */ 38250723Scg#define OPL3SAx_SBSTATE_SM 0x04 /* Scan Mode */ 38350723Scg#define OPL3SAx_SBSTATE_SS 0x08 /* Scan Select */ 38450723Scg#define OPL3SAx_SBSTATE_SBPDA 0x80 /* SB Power Down Acknowledge */ 38550723Scg 38650723Scg#define OPL3SAx_SBDATA 0x11 /* SB compat State Scan Data (R/W) */ 38750723Scg 38850723Scg#define OPL3SAx_DIGITALPOWER 0x12 /* Digital Partial Power Down (R/W) */ 38950723Scg#define OPL3SAx_DIGITALPOWER_PnP 0x01 39050723Scg#define OPL3SAx_DIGITALPOWER_SB 0x02 39150723Scg#define OPL3SAx_DIGITALPOWER_WSSP 0x04 39250723Scg#define OPL3SAx_DIGITALPOWER_WSSR 0x08 39350723Scg#define OPL3SAx_DIGITALPOWER_FM 0x10 39450723Scg#define OPL3SAx_DIGITALPOWER_MCLK0 0x20 39550723Scg#define OPL3SAx_DIGITALPOWER_MPU 0x40 39650723Scg#define OPL3SAx_DIGITALPOWER_JOY 0x80 39750723Scg 39850723Scg#define OPL3SAx_ANALOGPOWER 0x13 /* Analog Partial Power Down (R/W) */ 39950723Scg#define OPL3SAx_ANALOGPOWER_WIDE 0x01 40050723Scg#define OPL3SAx_ANALOGPOWER_SBDAC 0x02 40150723Scg#define OPL3SAx_ANALOGPOWER_DA 0x04 40250723Scg#define OPL3SAx_ANALOGPOWER_AD 0x08 40350723Scg#define OPL3SAx_ANALOGPOWER_FMDAC 0x10 40450723Scg 40550723Scg#define OPL3SAx_WIDE 0x14 /* Enhanced control(WIDE) (R/W) */ 40650723Scg#define OPL3SAx_WIDE_WIDEL 0x07 /* Wide level on Left Channel */ 40750723Scg#define OPL3SAx_WIDE_WIDER 0x70 /* Wide level on Right Channel */ 40850723Scg 40950723Scg#define OPL3SAx_BASS 0x15 /* Enhanced control(BASS) (R/W) */ 41050723Scg#define OPL3SAx_BASS_BASSL 0x07 /* Bass level on Left Channel */ 41150723Scg#define OPL3SAx_BASS_BASSR 0x70 /* Bass level on Right Channel */ 41250723Scg 41350723Scg#define OPL3SAx_TREBLE 0x16 /* Enhanced control(TREBLE) (R/W) */ 41450723Scg#define OPL3SAx_TREBLE_TREBLEL 0x07 /* Treble level on Left Channel */ 41550723Scg#define OPL3SAx_TREBLE_TREBLER 0x70 /* Treble level on Right Channel */ 41650723Scg 41750723Scg#define OPL3SAx_HWVOL 0x17 /* HW Volume IRQ Configuration (R/W) */ 41850723Scg#define OPL3SAx_HWVOL_IRQA 0x10 /* HW Volume IRQ on IRQ-A */ 41950723Scg#define OPL3SAx_HWVOL_IRQB 0x20 /* HW Volume IRQ on IRQ-B */ 42050723Scg 42150723Scg 422