mss.c revision 84112
112651Skvn/* 212651Skvn * Copyright (c) 2001 George Reid <greid@ukug.uk.freebsd.org> 312651Skvn * Copyright (c) 1999 Cameron Grant <gandalf@vilnya.demon.co.uk> 412651Skvn * Copyright Luigi Rizzo, 1997,1998 512651Skvn * Copyright by Hannu Savolainen 1994, 1995 612651Skvn * All rights reserved. 712651Skvn * 812651Skvn * Redistribution and use in source and binary forms, with or without 912651Skvn * modification, are permitted provided that the following conditions 1012651Skvn * are met: 1112651Skvn * 1. Redistributions of source code must retain the above copyright 1212651Skvn * notice, this list of conditions and the following disclaimer. 1312651Skvn * 2. Redistributions in binary form must reproduce the above copyright 1412651Skvn * notice, this list of conditions and the following disclaimer in the 1512651Skvn * documentation and/or other materials provided with the distribution. 1612651Skvn * 1712651Skvn * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 1812651Skvn * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 1912651Skvn * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 2012651Skvn * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 2112651Skvn * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 2212651Skvn * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 2312651Skvn * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 2412651Skvn * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 2512651Skvn * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 2612651Skvn * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 2712651Skvn * SUCH DAMAGE. 2812651Skvn */ 2912651Skvn 3012651Skvn#include <dev/sound/pcm/sound.h> 3112651Skvn 3212651SkvnSND_DECLARE_FILE("$FreeBSD: head/sys/dev/sound/isa/mss.c 84112 2001-09-29 08:01:42Z cg $"); 3312651Skvn 3412651Skvn/* board-specific include files */ 3512651Skvn#include <dev/sound/isa/mss.h> 3612651Skvn#include <dev/sound/chip.h> 3712651Skvn 3812651Skvn#include "mixer_if.h" 3912651Skvn 4012651Skvn#define MSS_DEFAULT_BUFSZ (4096) 4112651Skvn#define abs(x) (((x) < 0) ? -(x) : (x)) 4212651Skvn#define MSS_INDEXED_REGS 0x20 4312651Skvn#define OPL_INDEXED_REGS 0x19 4412651Skvn 4512651Skvnstruct mss_info; 4612651Skvn 4712651Skvnstruct mss_chinfo { 4812651Skvn struct mss_info *parent; 4912651Skvn struct pcm_channel *channel; 5012651Skvn struct snd_dbuf *buffer; 5112651Skvn int dir; 5212651Skvn u_int32_t fmt, blksz; 5312651Skvn}; 5412651Skvn 5512651Skvnstruct mss_info { 5612651Skvn struct resource *io_base; /* primary I/O address for the board */ 5712651Skvn int io_rid; 5812651Skvn struct resource *conf_base; /* and the opti931 also has a config space */ 5912651Skvn int conf_rid; 6012651Skvn struct resource *irq; 6112651Skvn int irq_rid; 6212651Skvn struct resource *drq1; /* play */ 6312651Skvn int drq1_rid; 6412651Skvn struct resource *drq2; /* rec */ 6512651Skvn int drq2_rid; 6612651Skvn void *ih; 6712651Skvn bus_dma_tag_t parent_dmat; 6812651Skvn void *lock; 6912651Skvn 7012651Skvn char mss_indexed_regs[MSS_INDEXED_REGS]; 7112651Skvn char opl_indexed_regs[OPL_INDEXED_REGS]; 7212651Skvn int bd_id; /* used to hold board-id info, eg. sb version, 7312651Skvn * mss codec type, etc. etc. 7412651Skvn */ 7512651Skvn int opti_offset; /* offset from config_base for opti931 */ 7612651Skvn u_long bd_flags; /* board-specific flags */ 7712651Skvn int optibase; /* base address for OPTi9xx config */ 7812651Skvn struct resource *indir; /* Indirect register index address */ 7912651Skvn int indir_rid; 8012651Skvn int password; /* password for opti9xx cards */ 8112651Skvn int passwdreg; /* password register */ 8212651Skvn unsigned int bufsize; 8312651Skvn struct mss_chinfo pch, rch; 8412651Skvn}; 8512651Skvn 8612651Skvnstatic int mss_probe(device_t dev); 8712651Skvnstatic int mss_attach(device_t dev); 8812651Skvn 8912651Skvnstatic driver_intr_t mss_intr; 9012651Skvn 9112651Skvn/* prototypes for local functions */ 9212651Skvnstatic int mss_detect(device_t dev, struct mss_info *mss); 9312651Skvnstatic int opti_detect(device_t dev, struct mss_info *mss); 9412651Skvnstatic char *ymf_test(device_t dev, struct mss_info *mss); 9512651Skvnstatic void ad_unmute(struct mss_info *mss); 9612651Skvn 9712651Skvn/* mixer set funcs */ 9812651Skvnstatic int mss_mixer_set(struct mss_info *mss, int dev, int left, int right); 9912651Skvnstatic int mss_set_recsrc(struct mss_info *mss, int mask); 10012651Skvn 10112651Skvn/* io funcs */ 10212651Skvnstatic int ad_wait_init(struct mss_info *mss, int x); 10312651Skvnstatic int ad_read(struct mss_info *mss, int reg); 10412651Skvnstatic void ad_write(struct mss_info *mss, int reg, u_char data); 10512651Skvnstatic void ad_write_cnt(struct mss_info *mss, int reg, u_short data); 10612651Skvnstatic void ad_enter_MCE(struct mss_info *mss); 10712651Skvnstatic void ad_leave_MCE(struct mss_info *mss); 10812651Skvn 10912651Skvn/* OPTi-specific functions */ 11012651Skvnstatic void opti_write(struct mss_info *mss, u_char reg, 11112651Skvn u_char data); 11212651Skvnstatic u_char opti_read(struct mss_info *mss, u_char reg); 11312651Skvnstatic int opti_init(device_t dev, struct mss_info *mss); 11412651Skvn 11512651Skvn/* io primitives */ 11612651Skvnstatic void conf_wr(struct mss_info *mss, u_char reg, u_char data); 11712651Skvnstatic u_char conf_rd(struct mss_info *mss, u_char reg); 11812651Skvn 11912651Skvnstatic int pnpmss_probe(device_t dev); 12012651Skvnstatic int pnpmss_attach(device_t dev); 12112651Skvn 12212651Skvnstatic driver_intr_t opti931_intr; 12312651Skvn 12412651Skvnstatic u_int32_t mss_fmt[] = { 12512651Skvn AFMT_U8, 12612651Skvn AFMT_STEREO | AFMT_U8, 12712651Skvn AFMT_S16_LE, 12812651Skvn AFMT_STEREO | AFMT_S16_LE, 12912651Skvn AFMT_MU_LAW, 13012651Skvn AFMT_STEREO | AFMT_MU_LAW, 13112651Skvn AFMT_A_LAW, 13212651Skvn AFMT_STEREO | AFMT_A_LAW, 13312651Skvn 0 13412651Skvn}; 13512651Skvnstatic struct pcmchan_caps mss_caps = {4000, 48000, mss_fmt, 0}; 13612651Skvn 13712651Skvnstatic u_int32_t guspnp_fmt[] = { 13812651Skvn AFMT_U8, 13912651Skvn AFMT_STEREO | AFMT_U8, 14012651Skvn AFMT_S16_LE, 14112651Skvn AFMT_STEREO | AFMT_S16_LE, 14212651Skvn AFMT_A_LAW, 14312651Skvn AFMT_STEREO | AFMT_A_LAW, 14412651Skvn 0 14512651Skvn}; 14612651Skvnstatic struct pcmchan_caps guspnp_caps = {4000, 48000, guspnp_fmt, 0}; 14712651Skvn 14812651Skvnstatic u_int32_t opti931_fmt[] = { 14912651Skvn AFMT_U8, 15012651Skvn AFMT_STEREO | AFMT_U8, 15112651Skvn AFMT_S16_LE, 15212651Skvn AFMT_STEREO | AFMT_S16_LE, 15312651Skvn 0 15412651Skvn}; 15512651Skvnstatic struct pcmchan_caps opti931_caps = {4000, 48000, opti931_fmt, 0}; 15612651Skvn 15712651Skvn#define MD_AD1848 0x91 15812651Skvn#define MD_AD1845 0x92 15912651Skvn#define MD_CS42XX 0xA1 16012651Skvn#define MD_OPTI930 0xB0 16112651Skvn#define MD_OPTI931 0xB1 16212651Skvn#define MD_OPTI925 0xB2 16312651Skvn#define MD_OPTI924 0xB3 16412651Skvn#define MD_GUSPNP 0xB8 16512651Skvn#define MD_GUSMAX 0xB9 16612651Skvn#define MD_YM0020 0xC1 16712651Skvn#define MD_VIVO 0xD1 16812651Skvn 16912651Skvn#define DV_F_TRUE_MSS 0x00010000 /* mss _with_ base regs */ 17012651Skvn 17112651Skvn#define FULL_DUPLEX(x) ((x)->bd_flags & BD_F_DUPLEX) 17212651Skvn 17312651Skvnstatic void 17412651Skvnmss_lock(struct mss_info *mss) 17512651Skvn{ 17612651Skvn snd_mtxlock(mss->lock); 17712651Skvn} 17812651Skvn 17912651Skvnstatic void 18012651Skvnmss_unlock(struct mss_info *mss) 18112651Skvn{ 18212651Skvn snd_mtxunlock(mss->lock); 18312651Skvn} 18412651Skvn 18512651Skvnstatic int 18612651Skvnport_rd(struct resource *port, int off) 18712651Skvn{ 18812651Skvn if (port) 18912651Skvn return bus_space_read_1(rman_get_bustag(port), 19012651Skvn rman_get_bushandle(port), 19112651Skvn off); 19212651Skvn else 19312651Skvn return -1; 19412651Skvn} 19512651Skvn 19612651Skvnstatic void 19712651Skvnport_wr(struct resource *port, int off, u_int8_t data) 19812651Skvn{ 19912651Skvn if (port) 20012651Skvn return bus_space_write_1(rman_get_bustag(port), 20112651Skvn rman_get_bushandle(port), 20212651Skvn off, data); 20312651Skvn} 20412651Skvn 20512651Skvnstatic int 20612651Skvnio_rd(struct mss_info *mss, int reg) 20712651Skvn{ 20812651Skvn if (mss->bd_flags & BD_F_MSS_OFFSET) reg -= 4; 20912651Skvn return port_rd(mss->io_base, reg); 21012651Skvn} 21112651Skvn 21212651Skvnstatic void 21312651Skvnio_wr(struct mss_info *mss, int reg, u_int8_t data) 21412651Skvn{ 21512651Skvn if (mss->bd_flags & BD_F_MSS_OFFSET) reg -= 4; 21612651Skvn return port_wr(mss->io_base, reg, data); 21712651Skvn} 21812651Skvn 21912651Skvnstatic void 22012651Skvnconf_wr(struct mss_info *mss, u_char reg, u_char value) 22112651Skvn{ 22212651Skvn port_wr(mss->conf_base, 0, reg); 22312651Skvn port_wr(mss->conf_base, 1, value); 22412651Skvn} 22512651Skvn 22612651Skvnstatic u_char 22712651Skvnconf_rd(struct mss_info *mss, u_char reg) 22812651Skvn{ 22912651Skvn port_wr(mss->conf_base, 0, reg); 23012651Skvn return port_rd(mss->conf_base, 1); 23112651Skvn} 23212651Skvn 23312651Skvnstatic void 23412651Skvnopti_wr(struct mss_info *mss, u_char reg, u_char value) 23512651Skvn{ 23612651Skvn port_wr(mss->conf_base, mss->opti_offset + 0, reg); 23712651Skvn port_wr(mss->conf_base, mss->opti_offset + 1, value); 23812651Skvn} 23912651Skvn 24012651Skvnstatic u_char 24112651Skvnopti_rd(struct mss_info *mss, u_char reg) 24212651Skvn{ 24312651Skvn port_wr(mss->conf_base, mss->opti_offset + 0, reg); 24412651Skvn return port_rd(mss->conf_base, mss->opti_offset + 1); 24512651Skvn} 24612651Skvn 24712651Skvnstatic void 24812651Skvngus_wr(struct mss_info *mss, u_char reg, u_char value) 24912651Skvn{ 25012651Skvn port_wr(mss->conf_base, 3, reg); 25112651Skvn port_wr(mss->conf_base, 5, value); 25212651Skvn} 25312651Skvn 25412651Skvnstatic u_char 25512651Skvngus_rd(struct mss_info *mss, u_char reg) 25612651Skvn{ 25712651Skvn port_wr(mss->conf_base, 3, reg); 25812651Skvn return port_rd(mss->conf_base, 5); 25912651Skvn} 26012651Skvn 26112651Skvnstatic void 26212651Skvnmss_release_resources(struct mss_info *mss, device_t dev) 26312651Skvn{ 26412651Skvn if (mss->irq) { 26512651Skvn if (mss->ih) 26612651Skvn bus_teardown_intr(dev, mss->irq, mss->ih); 26712651Skvn bus_release_resource(dev, SYS_RES_IRQ, mss->irq_rid, 26812651Skvn mss->irq); 26912651Skvn mss->irq = 0; 27012651Skvn } 27112651Skvn if (mss->drq2) { 27212651Skvn if (mss->drq2 != mss->drq1) { 27312651Skvn isa_dma_release(rman_get_start(mss->drq2)); 27412651Skvn bus_release_resource(dev, SYS_RES_DRQ, mss->drq2_rid, 27512651Skvn mss->drq2); 27612651Skvn } 27712651Skvn mss->drq2 = 0; 27812651Skvn } 27912651Skvn if (mss->drq1) { 28012651Skvn isa_dma_release(rman_get_start(mss->drq1)); 28112651Skvn bus_release_resource(dev, SYS_RES_DRQ, mss->drq1_rid, 28212651Skvn mss->drq1); 28312651Skvn mss->drq1 = 0; 28412651Skvn } 28512651Skvn if (mss->io_base) { 28612651Skvn bus_release_resource(dev, SYS_RES_IOPORT, mss->io_rid, 28712651Skvn mss->io_base); 28812651Skvn mss->io_base = 0; 28912651Skvn } 29012651Skvn if (mss->conf_base) { 29112651Skvn bus_release_resource(dev, SYS_RES_IOPORT, mss->conf_rid, 29212651Skvn mss->conf_base); 29312651Skvn mss->conf_base = 0; 29412651Skvn } 29512651Skvn if (mss->indir) { 29612651Skvn bus_release_resource(dev, SYS_RES_IOPORT, mss->indir_rid, 297 mss->indir); 298 mss->indir = 0; 299 } 300 if (mss->parent_dmat) { 301 bus_dma_tag_destroy(mss->parent_dmat); 302 mss->parent_dmat = 0; 303 } 304 if (mss->lock) snd_mtxfree(mss->lock); 305 306 free(mss, M_DEVBUF); 307} 308 309static int 310mss_alloc_resources(struct mss_info *mss, device_t dev) 311{ 312 int pdma, rdma, ok = 1; 313 if (!mss->io_base) 314 mss->io_base = bus_alloc_resource(dev, SYS_RES_IOPORT, &mss->io_rid, 315 0, ~0, 1, RF_ACTIVE); 316 if (!mss->irq) 317 mss->irq = bus_alloc_resource(dev, SYS_RES_IRQ, &mss->irq_rid, 318 0, ~0, 1, RF_ACTIVE); 319 if (!mss->drq1) 320 mss->drq1 = bus_alloc_resource(dev, SYS_RES_DRQ, &mss->drq1_rid, 321 0, ~0, 1, RF_ACTIVE); 322 if (mss->conf_rid >= 0 && !mss->conf_base) 323 mss->conf_base = bus_alloc_resource(dev, SYS_RES_IOPORT, &mss->conf_rid, 324 0, ~0, 1, RF_ACTIVE); 325 if (mss->drq2_rid >= 0 && !mss->drq2) 326 mss->drq2 = bus_alloc_resource(dev, SYS_RES_DRQ, &mss->drq2_rid, 327 0, ~0, 1, RF_ACTIVE); 328 329 if (!mss->io_base || !mss->drq1 || !mss->irq) ok = 0; 330 if (mss->conf_rid >= 0 && !mss->conf_base) ok = 0; 331 if (mss->drq2_rid >= 0 && !mss->drq2) ok = 0; 332 333 if (ok) { 334 pdma = rman_get_start(mss->drq1); 335 isa_dma_acquire(pdma); 336 isa_dmainit(pdma, mss->bufsize); 337 mss->bd_flags &= ~BD_F_DUPLEX; 338 if (mss->drq2) { 339 rdma = rman_get_start(mss->drq2); 340 isa_dma_acquire(rdma); 341 isa_dmainit(rdma, mss->bufsize); 342 mss->bd_flags |= BD_F_DUPLEX; 343 } else mss->drq2 = mss->drq1; 344 } 345 return ok; 346} 347 348/* 349 * The various mixers use a variety of bitmasks etc. The Voxware 350 * driver had a very nice technique to describe a mixer and interface 351 * to it. A table defines, for each channel, which register, bits, 352 * offset, polarity to use. This procedure creates the new value 353 * using the table and the old value. 354 */ 355 356static void 357change_bits(mixer_tab *t, u_char *regval, int dev, int chn, int newval) 358{ 359 u_char mask; 360 int shift; 361 362 DEB(printf("ch_bits dev %d ch %d val %d old 0x%02x " 363 "r %d p %d bit %d off %d\n", 364 dev, chn, newval, *regval, 365 (*t)[dev][chn].regno, (*t)[dev][chn].polarity, 366 (*t)[dev][chn].nbits, (*t)[dev][chn].bitoffs ) ); 367 368 if ( (*t)[dev][chn].polarity == 1) /* reverse */ 369 newval = 100 - newval ; 370 371 mask = (1 << (*t)[dev][chn].nbits) - 1; 372 newval = (int) ((newval * mask) + 50) / 100; /* Scale it */ 373 shift = (*t)[dev][chn].bitoffs /*- (*t)[dev][LEFT_CHN].nbits + 1*/; 374 375 *regval &= ~(mask << shift); /* Filter out the previous value */ 376 *regval |= (newval & mask) << shift; /* Set the new value */ 377} 378 379/* -------------------------------------------------------------------- */ 380/* only one source can be set... */ 381static int 382mss_set_recsrc(struct mss_info *mss, int mask) 383{ 384 u_char recdev; 385 386 switch (mask) { 387 case SOUND_MASK_LINE: 388 case SOUND_MASK_LINE3: 389 recdev = 0; 390 break; 391 392 case SOUND_MASK_CD: 393 case SOUND_MASK_LINE1: 394 recdev = 0x40; 395 break; 396 397 case SOUND_MASK_IMIX: 398 recdev = 0xc0; 399 break; 400 401 case SOUND_MASK_MIC: 402 default: 403 mask = SOUND_MASK_MIC; 404 recdev = 0x80; 405 } 406 ad_write(mss, 0, (ad_read(mss, 0) & 0x3f) | recdev); 407 ad_write(mss, 1, (ad_read(mss, 1) & 0x3f) | recdev); 408 return mask; 409} 410 411/* there are differences in the mixer depending on the actual sound card. */ 412static int 413mss_mixer_set(struct mss_info *mss, int dev, int left, int right) 414{ 415 int regoffs; 416 mixer_tab *mix_d; 417 u_char old, val; 418 419 switch (mss->bd_id) { 420 case MD_OPTI931: 421 mix_d = &opti931_devices; 422 break; 423 case MD_OPTI930: 424 mix_d = &opti930_devices; 425 break; 426 default: 427 mix_d = &mix_devices; 428 } 429 430 if ((*mix_d)[dev][LEFT_CHN].nbits == 0) { 431 DEB(printf("nbits = 0 for dev %d\n", dev)); 432 return -1; 433 } 434 435 if ((*mix_d)[dev][RIGHT_CHN].nbits == 0) right = left; /* mono */ 436 437 /* Set the left channel */ 438 439 regoffs = (*mix_d)[dev][LEFT_CHN].regno; 440 old = val = ad_read(mss, regoffs); 441 /* if volume is 0, mute chan. Otherwise, unmute. */ 442 if (regoffs != 0) val = (left == 0)? old | 0x80 : old & 0x7f; 443 change_bits(mix_d, &val, dev, LEFT_CHN, left); 444 ad_write(mss, regoffs, val); 445 446 DEB(printf("LEFT: dev %d reg %d old 0x%02x new 0x%02x\n", 447 dev, regoffs, old, val)); 448 449 if ((*mix_d)[dev][RIGHT_CHN].nbits != 0) { /* have stereo */ 450 /* Set the right channel */ 451 regoffs = (*mix_d)[dev][RIGHT_CHN].regno; 452 old = val = ad_read(mss, regoffs); 453 if (regoffs != 1) val = (right == 0)? old | 0x80 : old & 0x7f; 454 change_bits(mix_d, &val, dev, RIGHT_CHN, right); 455 ad_write(mss, regoffs, val); 456 457 DEB(printf("RIGHT: dev %d reg %d old 0x%02x new 0x%02x\n", 458 dev, regoffs, old, val)); 459 } 460 return 0; /* success */ 461} 462 463/* -------------------------------------------------------------------- */ 464 465static int 466mssmix_init(struct snd_mixer *m) 467{ 468 struct mss_info *mss = mix_getdevinfo(m); 469 470 mix_setdevs(m, MODE2_MIXER_DEVICES); 471 mix_setrecdevs(m, MSS_REC_DEVICES); 472 switch(mss->bd_id) { 473 case MD_OPTI930: 474 mix_setdevs(m, OPTI930_MIXER_DEVICES); 475 break; 476 477 case MD_OPTI931: 478 mix_setdevs(m, OPTI931_MIXER_DEVICES); 479 mss_lock(mss); 480 ad_write(mss, 20, 0x88); 481 ad_write(mss, 21, 0x88); 482 mss_unlock(mss); 483 break; 484 485 case MD_AD1848: 486 mix_setdevs(m, MODE1_MIXER_DEVICES); 487 break; 488 489 case MD_GUSPNP: 490 case MD_GUSMAX: 491 /* this is only necessary in mode 3 ... */ 492 mss_lock(mss); 493 ad_write(mss, 22, 0x88); 494 ad_write(mss, 23, 0x88); 495 mss_unlock(mss); 496 break; 497 } 498 return 0; 499} 500 501static int 502mssmix_set(struct snd_mixer *m, unsigned dev, unsigned left, unsigned right) 503{ 504 struct mss_info *mss = mix_getdevinfo(m); 505 506 mss_lock(mss); 507 mss_mixer_set(mss, dev, left, right); 508 mss_unlock(mss); 509 510 return left | (right << 8); 511} 512 513static int 514mssmix_setrecsrc(struct snd_mixer *m, u_int32_t src) 515{ 516 struct mss_info *mss = mix_getdevinfo(m); 517 518 mss_lock(mss); 519 src = mss_set_recsrc(mss, src); 520 mss_unlock(mss); 521 return src; 522} 523 524static kobj_method_t mssmix_mixer_methods[] = { 525 KOBJMETHOD(mixer_init, mssmix_init), 526 KOBJMETHOD(mixer_set, mssmix_set), 527 KOBJMETHOD(mixer_setrecsrc, mssmix_setrecsrc), 528 { 0, 0 } 529}; 530MIXER_DECLARE(mssmix_mixer); 531 532/* -------------------------------------------------------------------- */ 533 534static int 535ymmix_init(struct snd_mixer *m) 536{ 537 struct mss_info *mss = mix_getdevinfo(m); 538 539 mssmix_init(m); 540 mix_setdevs(m, mix_getdevs(m) | SOUND_MASK_VOLUME | SOUND_MASK_MIC 541 | SOUND_MASK_BASS | SOUND_MASK_TREBLE); 542 /* Set master volume */ 543 mss_lock(mss); 544 conf_wr(mss, OPL3SAx_VOLUMEL, 7); 545 conf_wr(mss, OPL3SAx_VOLUMER, 7); 546 mss_unlock(mss); 547 548 return 0; 549} 550 551static int 552ymmix_set(struct snd_mixer *m, unsigned dev, unsigned left, unsigned right) 553{ 554 struct mss_info *mss = mix_getdevinfo(m); 555 int t, l, r; 556 557 mss_lock(mss); 558 switch (dev) { 559 case SOUND_MIXER_VOLUME: 560 if (left) t = 15 - (left * 15) / 100; 561 else t = 0x80; /* mute */ 562 conf_wr(mss, OPL3SAx_VOLUMEL, t); 563 if (right) t = 15 - (right * 15) / 100; 564 else t = 0x80; /* mute */ 565 conf_wr(mss, OPL3SAx_VOLUMER, t); 566 break; 567 568 case SOUND_MIXER_MIC: 569 t = left; 570 if (left) t = 31 - (left * 31) / 100; 571 else t = 0x80; /* mute */ 572 conf_wr(mss, OPL3SAx_MIC, t); 573 break; 574 575 case SOUND_MIXER_BASS: 576 l = (left * 7) / 100; 577 r = (right * 7) / 100; 578 t = (r << 4) | l; 579 conf_wr(mss, OPL3SAx_BASS, t); 580 break; 581 582 case SOUND_MIXER_TREBLE: 583 l = (left * 7) / 100; 584 r = (right * 7) / 100; 585 t = (r << 4) | l; 586 conf_wr(mss, OPL3SAx_TREBLE, t); 587 break; 588 589 default: 590 mss_mixer_set(mss, dev, left, right); 591 } 592 mss_unlock(mss); 593 594 return left | (right << 8); 595} 596 597static int 598ymmix_setrecsrc(struct snd_mixer *m, u_int32_t src) 599{ 600 struct mss_info *mss = mix_getdevinfo(m); 601 mss_lock(mss); 602 src = mss_set_recsrc(mss, src); 603 mss_unlock(mss); 604 return src; 605} 606 607static kobj_method_t ymmix_mixer_methods[] = { 608 KOBJMETHOD(mixer_init, ymmix_init), 609 KOBJMETHOD(mixer_set, ymmix_set), 610 KOBJMETHOD(mixer_setrecsrc, ymmix_setrecsrc), 611 { 0, 0 } 612}; 613MIXER_DECLARE(ymmix_mixer); 614 615/* -------------------------------------------------------------------- */ 616/* 617 * XXX This might be better off in the gusc driver. 618 */ 619static void 620gusmax_setup(struct mss_info *mss, device_t dev, struct resource *alt) 621{ 622 static const unsigned char irq_bits[16] = { 623 0, 0, 0, 3, 0, 2, 0, 4, 0, 1, 0, 5, 6, 0, 0, 7 624 }; 625 static const unsigned char dma_bits[8] = { 626 0, 1, 0, 2, 0, 3, 4, 5 627 }; 628 device_t parent = device_get_parent(dev); 629 unsigned char irqctl, dmactl; 630 int s; 631 632 s = splhigh(); 633 634 port_wr(alt, 0x0f, 0x05); 635 port_wr(alt, 0x00, 0x0c); 636 port_wr(alt, 0x0b, 0x00); 637 638 port_wr(alt, 0x0f, 0x00); 639 640 irqctl = irq_bits[isa_get_irq(parent)]; 641 /* Share the IRQ with the MIDI driver. */ 642 irqctl |= 0x40; 643 dmactl = dma_bits[isa_get_drq(parent)]; 644 if (device_get_flags(parent) & DV_F_DUAL_DMA) 645 dmactl |= dma_bits[device_get_flags(parent) & DV_F_DRQ_MASK] 646 << 3; 647 648 /* 649 * Set the DMA and IRQ control latches. 650 */ 651 port_wr(alt, 0x00, 0x0c); 652 port_wr(alt, 0x0b, dmactl | 0x80); 653 port_wr(alt, 0x00, 0x4c); 654 port_wr(alt, 0x0b, irqctl); 655 656 port_wr(alt, 0x00, 0x0c); 657 port_wr(alt, 0x0b, dmactl); 658 port_wr(alt, 0x00, 0x4c); 659 port_wr(alt, 0x0b, irqctl); 660 661 port_wr(mss->conf_base, 2, 0); 662 port_wr(alt, 0x00, 0x0c); 663 port_wr(mss->conf_base, 2, 0); 664 665 splx(s); 666} 667 668static int 669mss_init(struct mss_info *mss, device_t dev) 670{ 671 u_char r6, r9; 672 struct resource *alt; 673 int rid, tmp; 674 675 mss->bd_flags |= BD_F_MCE_BIT; 676 switch(mss->bd_id) { 677 case MD_OPTI931: 678 /* 679 * The MED3931 v.1.0 allocates 3 bytes for the config 680 * space, whereas v.2.0 allocates 4 bytes. What I know 681 * for sure is that the upper two ports must be used, 682 * and they should end on a boundary of 4 bytes. So I 683 * need the following trick. 684 */ 685 mss->opti_offset = 686 (rman_get_start(mss->conf_base) & ~3) + 2 687 - rman_get_start(mss->conf_base); 688 BVDDB(printf("mss_init: opti_offset=%d\n", mss->opti_offset)); 689 opti_wr(mss, 4, 0xd6); /* fifo empty, OPL3, audio enable, SB3.2 */ 690 ad_write(mss, 10, 2); /* enable interrupts */ 691 opti_wr(mss, 6, 2); /* MCIR6: mss enable, sb disable */ 692 opti_wr(mss, 5, 0x28); /* MCIR5: codec in exp. mode,fifo */ 693 break; 694 695 case MD_GUSPNP: 696 case MD_GUSMAX: 697 gus_wr(mss, 0x4c /* _URSTI */, 0);/* Pull reset */ 698 DELAY(1000 * 30); 699 /* release reset and enable DAC */ 700 gus_wr(mss, 0x4c /* _URSTI */, 3); 701 DELAY(1000 * 30); 702 /* end of reset */ 703 704 rid = 0; 705 alt = bus_alloc_resource(dev, SYS_RES_IOPORT, &rid, 706 0, ~0, 1, RF_ACTIVE); 707 if (alt == NULL) { 708 printf("XXX couldn't init GUS PnP/MAX\n"); 709 break; 710 } 711 port_wr(alt, 0, 0xC); /* enable int and dma */ 712 if (mss->bd_id == MD_GUSMAX) 713 gusmax_setup(mss, dev, alt); 714 bus_release_resource(dev, SYS_RES_IOPORT, rid, alt); 715 716 /* 717 * unmute left & right line. Need to go in mode3, unmute, 718 * and back to mode 2 719 */ 720 tmp = ad_read(mss, 0x0c); 721 ad_write(mss, 0x0c, 0x6c); /* special value to enter mode 3 */ 722 ad_write(mss, 0x19, 0); /* unmute left */ 723 ad_write(mss, 0x1b, 0); /* unmute right */ 724 ad_write(mss, 0x0c, tmp); /* restore old mode */ 725 726 /* send codec interrupts on irq1 and only use that one */ 727 gus_wr(mss, 0x5a, 0x4f); 728 729 /* enable access to hidden regs */ 730 tmp = gus_rd(mss, 0x5b /* IVERI */); 731 gus_wr(mss, 0x5b, tmp | 1); 732 BVDDB(printf("GUS: silicon rev %c\n", 'A' + ((tmp & 0xf) >> 4))); 733 break; 734 735 case MD_YM0020: 736 conf_wr(mss, OPL3SAx_DMACONF, 0xa9); /* dma-b rec, dma-a play */ 737 r6 = conf_rd(mss, OPL3SAx_DMACONF); 738 r9 = conf_rd(mss, OPL3SAx_MISC); /* version */ 739 BVDDB(printf("Yamaha: ver 0x%x DMA config 0x%x\n", r6, r9);) 740 /* yamaha - set volume to max */ 741 conf_wr(mss, OPL3SAx_VOLUMEL, 0); 742 conf_wr(mss, OPL3SAx_VOLUMER, 0); 743 conf_wr(mss, OPL3SAx_DMACONF, FULL_DUPLEX(mss)? 0xa9 : 0x8b); 744 break; 745 } 746 if (FULL_DUPLEX(mss) && mss->bd_id != MD_OPTI931) 747 ad_write(mss, 12, ad_read(mss, 12) | 0x40); /* mode 2 */ 748 ad_enter_MCE(mss); 749 ad_write(mss, 9, FULL_DUPLEX(mss)? 0 : 4); 750 ad_leave_MCE(mss); 751 ad_write(mss, 10, 2); /* int enable */ 752 io_wr(mss, MSS_STATUS, 0); /* Clear interrupt status */ 753 /* the following seem required on the CS4232 */ 754 ad_unmute(mss); 755 return 0; 756} 757 758 759/* 760 * main irq handler for the CS423x. The OPTi931 code is 761 * a separate one. 762 * The correct way to operate for a device with multiple internal 763 * interrupt sources is to loop on the status register and ack 764 * interrupts until all interrupts are served and none are reported. At 765 * this point the IRQ line to the ISA IRQ controller should go low 766 * and be raised at the next interrupt. 767 * 768 * Since the ISA IRQ controller is sent EOI _before_ passing control 769 * to the isr, it might happen that we serve an interrupt early, in 770 * which case the status register at the next interrupt should just 771 * say that there are no more interrupts... 772 */ 773 774static void 775mss_intr(void *arg) 776{ 777 struct mss_info *mss = arg; 778 u_char c = 0, served = 0; 779 int i; 780 781 DEB(printf("mss_intr\n")); 782 mss_lock(mss); 783 ad_read(mss, 11); /* fake read of status bits */ 784 785 /* loop until there are interrupts, but no more than 10 times. */ 786 for (i = 10; i > 0 && io_rd(mss, MSS_STATUS) & 1; i--) { 787 /* get exact reason for full-duplex boards */ 788 c = FULL_DUPLEX(mss)? ad_read(mss, 24) : 0x30; 789 c &= ~served; 790 if (sndbuf_runsz(mss->pch.buffer) && (c & 0x10)) { 791 served |= 0x10; 792 chn_intr(mss->pch.channel); 793 } 794 if (sndbuf_runsz(mss->rch.buffer) && (c & 0x20)) { 795 served |= 0x20; 796 chn_intr(mss->rch.channel); 797 } 798 /* now ack the interrupt */ 799 if (FULL_DUPLEX(mss)) ad_write(mss, 24, ~c); /* ack selectively */ 800 else io_wr(mss, MSS_STATUS, 0); /* Clear interrupt status */ 801 } 802 if (i == 10) { 803 BVDDB(printf("mss_intr: irq, but not from mss\n")); 804 } else if (served == 0) { 805 BVDDB(printf("mss_intr: unexpected irq with reason %x\n", c)); 806 /* 807 * this should not happen... I have no idea what to do now. 808 * maybe should do a sanity check and restart dmas ? 809 */ 810 io_wr(mss, MSS_STATUS, 0); /* Clear interrupt status */ 811 } 812 mss_unlock(mss); 813} 814 815/* 816 * AD_WAIT_INIT waits if we are initializing the board and 817 * we cannot modify its settings 818 */ 819static int 820ad_wait_init(struct mss_info *mss, int x) 821{ 822 int arg = x, n = 0; /* to shut up the compiler... */ 823 for (; x > 0; x--) 824 if ((n = io_rd(mss, MSS_INDEX)) & MSS_IDXBUSY) DELAY(10000); 825 else return n; 826 printf("AD_WAIT_INIT FAILED %d 0x%02x\n", arg, n); 827 return n; 828} 829 830static int 831ad_read(struct mss_info *mss, int reg) 832{ 833 int x; 834 835 ad_wait_init(mss, 201000); 836 x = io_rd(mss, MSS_INDEX) & ~MSS_IDXMASK; 837 io_wr(mss, MSS_INDEX, (u_char)(reg & MSS_IDXMASK) | x); 838 x = io_rd(mss, MSS_IDATA); 839 /* printf("ad_read %d, %x\n", reg, x); */ 840 return x; 841} 842 843static void 844ad_write(struct mss_info *mss, int reg, u_char data) 845{ 846 int x; 847 848 /* printf("ad_write %d, %x\n", reg, data); */ 849 ad_wait_init(mss, 1002000); 850 x = io_rd(mss, MSS_INDEX) & ~MSS_IDXMASK; 851 io_wr(mss, MSS_INDEX, (u_char)(reg & MSS_IDXMASK) | x); 852 io_wr(mss, MSS_IDATA, data); 853} 854 855static void 856ad_write_cnt(struct mss_info *mss, int reg, u_short cnt) 857{ 858 ad_write(mss, reg+1, cnt & 0xff); 859 ad_write(mss, reg, cnt >> 8); /* upper base must be last */ 860} 861 862static void 863wait_for_calibration(struct mss_info *mss) 864{ 865 int t; 866 867 /* 868 * Wait until the auto calibration process has finished. 869 * 870 * 1) Wait until the chip becomes ready (reads don't return 0x80). 871 * 2) Wait until the ACI bit of I11 gets on 872 * 3) Wait until the ACI bit of I11 gets off 873 */ 874 875 t = ad_wait_init(mss, 1000000); 876 if (t & MSS_IDXBUSY) printf("mss: Auto calibration timed out(1).\n"); 877 878 /* 879 * The calibration mode for chips that support it is set so that 880 * we never see ACI go on. 881 */ 882 if (mss->bd_id == MD_GUSMAX || mss->bd_id == MD_GUSPNP) { 883 for (t = 100; t > 0 && (ad_read(mss, 11) & 0x20) == 0; t--); 884 } else { 885 /* 886 * XXX This should only be enabled for cards that *really* 887 * need it. Are there any? 888 */ 889 for (t = 100; t > 0 && (ad_read(mss, 11) & 0x20) == 0; t--) DELAY(100); 890 } 891 for (t = 100; t > 0 && ad_read(mss, 11) & 0x20; t--) DELAY(100); 892} 893 894static void 895ad_unmute(struct mss_info *mss) 896{ 897 ad_write(mss, 6, ad_read(mss, 6) & ~I6_MUTE); 898 ad_write(mss, 7, ad_read(mss, 7) & ~I6_MUTE); 899} 900 901static void 902ad_enter_MCE(struct mss_info *mss) 903{ 904 int prev; 905 906 mss->bd_flags |= BD_F_MCE_BIT; 907 ad_wait_init(mss, 203000); 908 prev = io_rd(mss, MSS_INDEX); 909 prev &= ~MSS_TRD; 910 io_wr(mss, MSS_INDEX, prev | MSS_MCE); 911} 912 913static void 914ad_leave_MCE(struct mss_info *mss) 915{ 916 u_char prev; 917 918 if ((mss->bd_flags & BD_F_MCE_BIT) == 0) { 919 DEB(printf("--- hey, leave_MCE: MCE bit was not set!\n")); 920 return; 921 } 922 923 ad_wait_init(mss, 1000000); 924 925 mss->bd_flags &= ~BD_F_MCE_BIT; 926 927 prev = io_rd(mss, MSS_INDEX); 928 prev &= ~MSS_TRD; 929 io_wr(mss, MSS_INDEX, prev & ~MSS_MCE); /* Clear the MCE bit */ 930 wait_for_calibration(mss); 931} 932 933static int 934mss_speed(struct mss_chinfo *ch, int speed) 935{ 936 struct mss_info *mss = ch->parent; 937 /* 938 * In the CS4231, the low 4 bits of I8 are used to hold the 939 * sample rate. Only a fixed number of values is allowed. This 940 * table lists them. The speed-setting routines scans the table 941 * looking for the closest match. This is the only supported method. 942 * 943 * In the CS4236, there is an alternate metod (which we do not 944 * support yet) which provides almost arbitrary frequency setting. 945 * In the AD1845, it looks like the sample rate can be 946 * almost arbitrary, and written directly to a register. 947 * In the OPTi931, there is a SB command which provides for 948 * almost arbitrary frequency setting. 949 * 950 */ 951 ad_enter_MCE(mss); 952 if (mss->bd_id == MD_AD1845) { /* Use alternate speed select regs */ 953 ad_write(mss, 22, (speed >> 8) & 0xff); /* Speed MSB */ 954 ad_write(mss, 23, speed & 0xff); /* Speed LSB */ 955 /* XXX must also do something in I27 for the ad1845 */ 956 } else { 957 int i, sel = 0; /* assume entry 0 does not contain -1 */ 958 static int speeds[] = 959 {8000, 5512, 16000, 11025, 27429, 18900, 32000, 22050, 960 -1, 37800, -1, 44100, 48000, 33075, 9600, 6615}; 961 962 for (i = 1; i < 16; i++) 963 if (speeds[i] > 0 && 964 abs(speed-speeds[i]) < abs(speed-speeds[sel])) sel = i; 965 speed = speeds[sel]; 966 ad_write(mss, 8, (ad_read(mss, 8) & 0xf0) | sel); 967 } 968 ad_leave_MCE(mss); 969 970 return speed; 971} 972 973/* 974 * mss_format checks that the format is supported (or defaults to AFMT_U8) 975 * and returns the bit setting for the 1848 register corresponding to 976 * the desired format. 977 * 978 * fixed lr970724 979 */ 980 981static int 982mss_format(struct mss_chinfo *ch, u_int32_t format) 983{ 984 struct mss_info *mss = ch->parent; 985 int i, arg = format & ~AFMT_STEREO; 986 987 /* 988 * The data format uses 3 bits (just 2 on the 1848). For each 989 * bit setting, the following array returns the corresponding format. 990 * The code scans the array looking for a suitable format. In 991 * case it is not found, default to AFMT_U8 (not such a good 992 * choice, but let's do it for compatibility...). 993 */ 994 995 static int fmts[] = 996 {AFMT_U8, AFMT_MU_LAW, AFMT_S16_LE, AFMT_A_LAW, 997 -1, AFMT_IMA_ADPCM, AFMT_U16_BE, -1}; 998 999 ch->fmt = format; 1000 for (i = 0; i < 8; i++) if (arg == fmts[i]) break; 1001 arg = i << 1; 1002 if (format & AFMT_STEREO) arg |= 1; 1003 arg <<= 4; 1004 ad_enter_MCE(mss); 1005 ad_write(mss, 8, (ad_read(mss, 8) & 0x0f) | arg); 1006 if (FULL_DUPLEX(mss)) ad_write(mss, 28, arg); /* capture mode */ 1007 ad_leave_MCE(mss); 1008 return format; 1009} 1010 1011static int 1012mss_trigger(struct mss_chinfo *ch, int go) 1013{ 1014 struct mss_info *mss = ch->parent; 1015 u_char m; 1016 int retry, wr, cnt, ss; 1017 1018 ss = 1; 1019 ss <<= (ch->fmt & AFMT_STEREO)? 1 : 0; 1020 ss <<= (ch->fmt & AFMT_16BIT)? 1 : 0; 1021 1022 wr = (ch->dir == PCMDIR_PLAY)? 1 : 0; 1023 m = ad_read(mss, 9); 1024 switch (go) { 1025 case PCMTRIG_START: 1026 cnt = (ch->blksz / ss) - 1; 1027 1028 DEB(if (m & 4) printf("OUCH! reg 9 0x%02x\n", m);); 1029 m |= wr? I9_PEN : I9_CEN; /* enable DMA */ 1030 ad_write_cnt(mss, (wr || !FULL_DUPLEX(mss))? 14 : 30, cnt); 1031 break; 1032 1033 case PCMTRIG_STOP: 1034 case PCMTRIG_ABORT: /* XXX check this... */ 1035 m &= ~(wr? I9_PEN : I9_CEN); /* Stop DMA */ 1036#if 0 1037 /* 1038 * try to disable DMA by clearing count registers. Not sure it 1039 * is needed, and it might cause false interrupts when the 1040 * DMA is re-enabled later. 1041 */ 1042 ad_write_cnt(mss, (wr || !FULL_DUPLEX(mss))? 14 : 30, 0); 1043#endif 1044 } 1045 /* on the OPTi931 the enable bit seems hard to set... */ 1046 for (retry = 10; retry > 0; retry--) { 1047 ad_write(mss, 9, m); 1048 if (ad_read(mss, 9) == m) break; 1049 } 1050 if (retry == 0) BVDDB(printf("stop dma, failed to set bit 0x%02x 0x%02x\n", \ 1051 m, ad_read(mss, 9))); 1052 return 0; 1053} 1054 1055 1056/* 1057 * the opti931 seems to miss interrupts when working in full 1058 * duplex, so we try some heuristics to catch them. 1059 */ 1060static void 1061opti931_intr(void *arg) 1062{ 1063 struct mss_info *mss = (struct mss_info *)arg; 1064 u_char masked = 0, i11, mc11, c = 0; 1065 u_char reason; /* b0 = playback, b1 = capture, b2 = timer */ 1066 int loops = 10; 1067 1068#if 0 1069 reason = io_rd(mss, MSS_STATUS); 1070 if (!(reason & 1)) {/* no int, maybe a shared line ? */ 1071 DEB(printf("intr: flag 0, mcir11 0x%02x\n", ad_read(mss, 11))); 1072 return; 1073 } 1074#endif 1075 mss_lock(mss); 1076 i11 = ad_read(mss, 11); /* XXX what's for ? */ 1077 again: 1078 1079 c = mc11 = FULL_DUPLEX(mss)? opti_rd(mss, 11) : 0xc; 1080 mc11 &= 0x0c; 1081 if (c & 0x10) { 1082 DEB(printf("Warning: CD interrupt\n");) 1083 mc11 |= 0x10; 1084 } 1085 if (c & 0x20) { 1086 DEB(printf("Warning: MPU interrupt\n");) 1087 mc11 |= 0x20; 1088 } 1089 if (mc11 & masked) BVDDB(printf("irq reset failed, mc11 0x%02x, 0x%02x\n",\ 1090 mc11, masked)); 1091 masked |= mc11; 1092 /* 1093 * the nice OPTi931 sets the IRQ line before setting the bits in 1094 * mc11. So, on some occasions I have to retry (max 10 times). 1095 */ 1096 if (mc11 == 0) { /* perhaps can return ... */ 1097 reason = io_rd(mss, MSS_STATUS); 1098 if (reason & 1) { 1099 DEB(printf("one more try...\n");) 1100 if (--loops) goto again; 1101 else DDB(printf("intr, but mc11 not set\n");) 1102 } 1103 if (loops == 0) BVDDB(printf("intr, nothing in mcir11 0x%02x\n", mc11)); 1104 mss_unlock(mss); 1105 return; 1106 } 1107 1108 if (sndbuf_runsz(mss->rch.buffer) && (mc11 & 8)) chn_intr(mss->rch.channel); 1109 if (sndbuf_runsz(mss->pch.buffer) && (mc11 & 4)) chn_intr(mss->pch.channel); 1110 opti_wr(mss, 11, ~mc11); /* ack */ 1111 if (--loops) goto again; 1112 mss_unlock(mss); 1113 DEB(printf("xxx too many loops\n");) 1114} 1115 1116/* -------------------------------------------------------------------- */ 1117/* channel interface */ 1118static void * 1119msschan_init(kobj_t obj, void *devinfo, struct snd_dbuf *b, struct pcm_channel *c, int dir) 1120{ 1121 struct mss_info *mss = devinfo; 1122 struct mss_chinfo *ch = (dir == PCMDIR_PLAY)? &mss->pch : &mss->rch; 1123 1124 ch->parent = mss; 1125 ch->channel = c; 1126 ch->buffer = b; 1127 ch->dir = dir; 1128 if (sndbuf_alloc(ch->buffer, mss->parent_dmat, mss->bufsize) == -1) return NULL; 1129 sndbuf_isadmasetup(ch->buffer, (dir == PCMDIR_PLAY)? mss->drq1 : mss->drq2); 1130 return ch; 1131} 1132 1133static int 1134msschan_setformat(kobj_t obj, void *data, u_int32_t format) 1135{ 1136 struct mss_chinfo *ch = data; 1137 struct mss_info *mss = ch->parent; 1138 1139 mss_lock(mss); 1140 mss_format(ch, format); 1141 mss_unlock(mss); 1142 return 0; 1143} 1144 1145static int 1146msschan_setspeed(kobj_t obj, void *data, u_int32_t speed) 1147{ 1148 struct mss_chinfo *ch = data; 1149 struct mss_info *mss = ch->parent; 1150 int r; 1151 1152 mss_lock(mss); 1153 r = mss_speed(ch, speed); 1154 mss_unlock(mss); 1155 1156 return r; 1157} 1158 1159static int 1160msschan_setblocksize(kobj_t obj, void *data, u_int32_t blocksize) 1161{ 1162 struct mss_chinfo *ch = data; 1163 1164 ch->blksz = blocksize; 1165 sndbuf_resize(ch->buffer, 2, ch->blksz); 1166 1167 return ch->blksz; 1168} 1169 1170static int 1171msschan_trigger(kobj_t obj, void *data, int go) 1172{ 1173 struct mss_chinfo *ch = data; 1174 struct mss_info *mss = ch->parent; 1175 1176 if (go == PCMTRIG_EMLDMAWR || go == PCMTRIG_EMLDMARD) 1177 return 0; 1178 1179 sndbuf_isadma(ch->buffer, go); 1180 mss_lock(mss); 1181 mss_trigger(ch, go); 1182 mss_unlock(mss); 1183 return 0; 1184} 1185 1186static int 1187msschan_getptr(kobj_t obj, void *data) 1188{ 1189 struct mss_chinfo *ch = data; 1190 return sndbuf_isadmaptr(ch->buffer); 1191} 1192 1193static struct pcmchan_caps * 1194msschan_getcaps(kobj_t obj, void *data) 1195{ 1196 struct mss_chinfo *ch = data; 1197 1198 switch(ch->parent->bd_id) { 1199 case MD_OPTI931: 1200 return &opti931_caps; 1201 break; 1202 1203 case MD_GUSPNP: 1204 case MD_GUSMAX: 1205 return &guspnp_caps; 1206 break; 1207 1208 default: 1209 return &mss_caps; 1210 break; 1211 } 1212} 1213 1214static kobj_method_t msschan_methods[] = { 1215 KOBJMETHOD(channel_init, msschan_init), 1216 KOBJMETHOD(channel_setformat, msschan_setformat), 1217 KOBJMETHOD(channel_setspeed, msschan_setspeed), 1218 KOBJMETHOD(channel_setblocksize, msschan_setblocksize), 1219 KOBJMETHOD(channel_trigger, msschan_trigger), 1220 KOBJMETHOD(channel_getptr, msschan_getptr), 1221 KOBJMETHOD(channel_getcaps, msschan_getcaps), 1222 { 0, 0 } 1223}; 1224CHANNEL_DECLARE(msschan); 1225 1226/* -------------------------------------------------------------------- */ 1227 1228/* 1229 * mss_probe() is the probe routine. Note, it is not necessary to 1230 * go through this for PnP devices, since they are already 1231 * indentified precisely using their PnP id. 1232 * 1233 * The base address supplied in the device refers to the old MSS 1234 * specs where the four 4 registers in io space contain configuration 1235 * information. Some boards (as an example, early MSS boards) 1236 * has such a block of registers, whereas others (generally CS42xx) 1237 * do not. In order to distinguish between the two and do not have 1238 * to supply two separate probe routines, the flags entry in isa_device 1239 * has a bit to mark this. 1240 * 1241 */ 1242 1243static int 1244mss_probe(device_t dev) 1245{ 1246 u_char tmp, tmpx; 1247 int flags, irq, drq, result = ENXIO, setres = 0; 1248 struct mss_info *mss; 1249 1250 if (isa_get_logicalid(dev)) return ENXIO; /* not yet */ 1251 1252 mss = (struct mss_info *)malloc(sizeof *mss, M_DEVBUF, M_NOWAIT | M_ZERO); 1253 if (!mss) return ENXIO; 1254 1255 mss->io_rid = 0; 1256 mss->conf_rid = -1; 1257 mss->irq_rid = 0; 1258 mss->drq1_rid = 0; 1259 mss->drq2_rid = -1; 1260 mss->io_base = bus_alloc_resource(dev, SYS_RES_IOPORT, &mss->io_rid, 1261 0, ~0, 8, RF_ACTIVE); 1262 if (!mss->io_base) { 1263 BVDDB(printf("mss_probe: no address given, try 0x%x\n", 0x530)); 1264 mss->io_rid = 0; 1265 /* XXX verify this */ 1266 setres = 1; 1267 bus_set_resource(dev, SYS_RES_IOPORT, mss->io_rid, 1268 0x530, 8); 1269 mss->io_base = bus_alloc_resource(dev, SYS_RES_IOPORT, &mss->io_rid, 1270 0, ~0, 8, RF_ACTIVE); 1271 } 1272 if (!mss->io_base) goto no; 1273 1274 /* got irq/dma regs? */ 1275 flags = device_get_flags(dev); 1276 irq = isa_get_irq(dev); 1277 drq = isa_get_drq(dev); 1278 1279 if (!(device_get_flags(dev) & DV_F_TRUE_MSS)) goto mss_probe_end; 1280 1281 /* 1282 * Check if the IO port returns valid signature. The original MS 1283 * Sound system returns 0x04 while some cards 1284 * (AudioTriX Pro for example) return 0x00 or 0x0f. 1285 */ 1286 1287 device_set_desc(dev, "MSS"); 1288 tmpx = tmp = io_rd(mss, 3); 1289 if (tmp == 0xff) { /* Bus float */ 1290 BVDDB(printf("I/O addr inactive (%x), try pseudo_mss\n", tmp)); 1291 device_set_flags(dev, flags & ~DV_F_TRUE_MSS); 1292 goto mss_probe_end; 1293 } 1294 tmp &= 0x3f; 1295 if (!(tmp == 0x04 || tmp == 0x0f || tmp == 0x00)) { 1296 BVDDB(printf("No MSS signature detected on port 0x%lx (0x%x)\n", 1297 rman_get_start(mss->io_base), tmpx)); 1298 goto no; 1299 } 1300#ifdef PC98 1301 if (irq > 12) { 1302#else 1303 if (irq > 11) { 1304#endif 1305 printf("MSS: Bad IRQ %d\n", irq); 1306 goto no; 1307 } 1308 if (!(drq == 0 || drq == 1 || drq == 3)) { 1309 printf("MSS: Bad DMA %d\n", drq); 1310 goto no; 1311 } 1312 if (tmpx & 0x80) { 1313 /* 8-bit board: only drq1/3 and irq7/9 */ 1314 if (drq == 0) { 1315 printf("MSS: Can't use DMA0 with a 8 bit card/slot\n"); 1316 goto no; 1317 } 1318 if (!(irq == 7 || irq == 9)) { 1319 printf("MSS: Can't use IRQ%d with a 8 bit card/slot\n", 1320 irq); 1321 goto no; 1322 } 1323 } 1324 mss_probe_end: 1325 result = mss_detect(dev, mss); 1326 no: 1327 mss_release_resources(mss, dev); 1328#if 0 1329 if (setres) ISA_DELETE_RESOURCE(device_get_parent(dev), dev, 1330 SYS_RES_IOPORT, mss->io_rid); /* XXX ? */ 1331#endif 1332 return result; 1333} 1334 1335static int 1336mss_detect(device_t dev, struct mss_info *mss) 1337{ 1338 int i; 1339 u_char tmp = 0, tmp1, tmp2; 1340 char *name, *yamaha; 1341 1342 if (mss->bd_id != 0) { 1343 device_printf(dev, "presel bd_id 0x%04x -- %s\n", mss->bd_id, 1344 device_get_desc(dev)); 1345 return 0; 1346 } 1347 1348 name = "AD1848"; 1349 mss->bd_id = MD_AD1848; /* AD1848 or CS4248 */ 1350 1351 if (opti_detect(dev, mss)) { 1352 switch (mss->bd_id) { 1353 case MD_OPTI924: 1354 name = "OPTi924"; 1355 break; 1356 case MD_OPTI930: 1357 name = "OPTi930"; 1358 break; 1359 } 1360 printf("Found OPTi device %s\n", name); 1361 if (opti_init(dev, mss) == 0) goto gotit; 1362 } 1363 1364 /* 1365 * Check that the I/O address is in use. 1366 * 1367 * bit 7 of the base I/O port is known to be 0 after the chip has 1368 * performed its power on initialization. Just assume this has 1369 * happened before the OS is starting. 1370 * 1371 * If the I/O address is unused, it typically returns 0xff. 1372 */ 1373 1374 for (i = 0; i < 10; i++) 1375 if ((tmp = io_rd(mss, MSS_INDEX)) & MSS_IDXBUSY) DELAY(10000); 1376 else break; 1377 1378 if (i >= 10) { /* Not a AD1848 */ 1379 BVDDB(printf("mss_detect, busy still set (0x%02x)\n", tmp)); 1380 goto no; 1381 } 1382 /* 1383 * Test if it's possible to change contents of the indirect 1384 * registers. Registers 0 and 1 are ADC volume registers. The bit 1385 * 0x10 is read only so try to avoid using it. 1386 */ 1387 1388 ad_write(mss, 0, 0xaa); 1389 ad_write(mss, 1, 0x45);/* 0x55 with bit 0x10 clear */ 1390 tmp1 = ad_read(mss, 0); 1391 tmp2 = ad_read(mss, 1); 1392 if (tmp1 != 0xaa || tmp2 != 0x45) { 1393 BVDDB(printf("mss_detect error - IREG (%x/%x)\n", tmp1, tmp2)); 1394 goto no; 1395 } 1396 1397 ad_write(mss, 0, 0x45); 1398 ad_write(mss, 1, 0xaa); 1399 tmp1 = ad_read(mss, 0); 1400 tmp2 = ad_read(mss, 1); 1401 if (tmp1 != 0x45 || tmp2 != 0xaa) { 1402 BVDDB(printf("mss_detect error - IREG2 (%x/%x)\n", tmp1, tmp2)); 1403 goto no; 1404 } 1405 1406 /* 1407 * The indirect register I12 has some read only bits. Lets try to 1408 * change them. 1409 */ 1410 1411 tmp = ad_read(mss, 12); 1412 ad_write(mss, 12, (~tmp) & 0x0f); 1413 tmp1 = ad_read(mss, 12); 1414 1415 if ((tmp & 0x0f) != (tmp1 & 0x0f)) { 1416 BVDDB(printf("mss_detect - I12 (0x%02x was 0x%02x)\n", tmp1, tmp)); 1417 goto no; 1418 } 1419 1420 /* 1421 * NOTE! Last 4 bits of the reg I12 tell the chip revision. 1422 * 0x01=RevB 1423 * 0x0A=RevC. also CS4231/CS4231A and OPTi931 1424 */ 1425 1426 BVDDB(printf("mss_detect - chip revision 0x%02x\n", tmp & 0x0f);) 1427 1428 /* 1429 * The original AD1848/CS4248 has just 16 indirect registers. This 1430 * means that I0 and I16 should return the same value (etc.). Ensure 1431 * that the Mode2 enable bit of I12 is 0. Otherwise this test fails 1432 * with new parts. 1433 */ 1434 1435 ad_write(mss, 12, 0); /* Mode2=disabled */ 1436#if 0 1437 for (i = 0; i < 16; i++) { 1438 if ((tmp1 = ad_read(mss, i)) != (tmp2 = ad_read(mss, i + 16))) { 1439 BVDDB(printf("mss_detect warning - I%d: 0x%02x/0x%02x\n", 1440 i, tmp1, tmp2)); 1441 /* 1442 * note - this seems to fail on the 4232 on I11. So we just break 1443 * rather than fail. (which makes this test pointless - cg) 1444 */ 1445 break; /* return 0; */ 1446 } 1447 } 1448#endif 1449 /* 1450 * Try to switch the chip to mode2 (CS4231) by setting the MODE2 bit 1451 * (0x40). The bit 0x80 is always 1 in CS4248 and CS4231. 1452 * 1453 * On the OPTi931, however, I12 is readonly and only contains the 1454 * chip revision ID (as in the CS4231A). The upper bits return 0. 1455 */ 1456 1457 ad_write(mss, 12, 0x40); /* Set mode2, clear 0x80 */ 1458 1459 tmp1 = ad_read(mss, 12); 1460 if (tmp1 & 0x80) name = "CS4248"; /* Our best knowledge just now */ 1461 if ((tmp1 & 0xf0) == 0x00) { 1462 BVDDB(printf("this should be an OPTi931\n");) 1463 } else if ((tmp1 & 0xc0) != 0xC0) goto gotit; 1464 /* 1465 * The 4231 has bit7=1 always, and bit6 we just set to 1. 1466 * We want to check that this is really a CS4231 1467 * Verify that setting I0 doesn't change I16. 1468 */ 1469 ad_write(mss, 16, 0); /* Set I16 to known value */ 1470 ad_write(mss, 0, 0x45); 1471 if ((tmp1 = ad_read(mss, 16)) == 0x45) goto gotit; 1472 1473 ad_write(mss, 0, 0xaa); 1474 if ((tmp1 = ad_read(mss, 16)) == 0xaa) { /* Rotten bits? */ 1475 BVDDB(printf("mss_detect error - step H(%x)\n", tmp1)); 1476 goto no; 1477 } 1478 /* Verify that some bits of I25 are read only. */ 1479 tmp1 = ad_read(mss, 25); /* Original bits */ 1480 ad_write(mss, 25, ~tmp1); /* Invert all bits */ 1481 if ((ad_read(mss, 25) & 0xe7) == (tmp1 & 0xe7)) { 1482 int id; 1483 1484 /* It's at least CS4231 */ 1485 name = "CS4231"; 1486 mss->bd_id = MD_CS42XX; 1487 1488 /* 1489 * It could be an AD1845 or CS4231A as well. 1490 * CS4231 and AD1845 report the same revision info in I25 1491 * while the CS4231A reports different. 1492 */ 1493 1494 id = ad_read(mss, 25) & 0xe7; 1495 /* 1496 * b7-b5 = version number; 1497 * 100 : all CS4231 1498 * 101 : CS4231A 1499 * 1500 * b2-b0 = chip id; 1501 */ 1502 switch (id) { 1503 1504 case 0xa0: 1505 name = "CS4231A"; 1506 mss->bd_id = MD_CS42XX; 1507 break; 1508 1509 case 0xa2: 1510 name = "CS4232"; 1511 mss->bd_id = MD_CS42XX; 1512 break; 1513 1514 case 0xb2: 1515 /* strange: the 4231 data sheet says b4-b3 are XX 1516 * so this should be the same as 0xa2 1517 */ 1518 name = "CS4232A"; 1519 mss->bd_id = MD_CS42XX; 1520 break; 1521 1522 case 0x80: 1523 /* 1524 * It must be a CS4231 or AD1845. The register I23 1525 * of CS4231 is undefined and it appears to be read 1526 * only. AD1845 uses I23 for setting sample rate. 1527 * Assume the chip is AD1845 if I23 is changeable. 1528 */ 1529 1530 tmp = ad_read(mss, 23); 1531 1532 ad_write(mss, 23, ~tmp); 1533 if (ad_read(mss, 23) != tmp) { /* AD1845 ? */ 1534 name = "AD1845"; 1535 mss->bd_id = MD_AD1845; 1536 } 1537 ad_write(mss, 23, tmp); /* Restore */ 1538 1539 yamaha = ymf_test(dev, mss); 1540 if (yamaha) { 1541 mss->bd_id = MD_YM0020; 1542 name = yamaha; 1543 } 1544 break; 1545 1546 case 0x83: /* CS4236 */ 1547 case 0x03: /* CS4236 on Intel PR440FX motherboard XXX */ 1548 name = "CS4236"; 1549 mss->bd_id = MD_CS42XX; 1550 break; 1551 1552 default: /* Assume CS4231 */ 1553 BVDDB(printf("unknown id 0x%02x, assuming CS4231\n", id);) 1554 mss->bd_id = MD_CS42XX; 1555 } 1556 } 1557 ad_write(mss, 25, tmp1); /* Restore bits */ 1558gotit: 1559 BVDDB(printf("mss_detect() - Detected %s\n", name)); 1560 device_set_desc(dev, name); 1561 device_set_flags(dev, 1562 ((device_get_flags(dev) & ~DV_F_DEV_MASK) | 1563 ((mss->bd_id << DV_F_DEV_SHIFT) & DV_F_DEV_MASK))); 1564 return 0; 1565no: 1566 return ENXIO; 1567} 1568 1569static int 1570opti_detect(device_t dev, struct mss_info *mss) 1571{ 1572 int c; 1573 static const struct opticard { 1574 int boardid; 1575 int passwdreg; 1576 int password; 1577 int base; 1578 int indir_reg; 1579 } cards[] = { 1580 { MD_OPTI930, 0, 0xe4, 0xf8f, 0xe0e }, /* 930 */ 1581 { MD_OPTI924, 3, 0xe5, 0xf8c, 0, }, /* 924 */ 1582 { 0 }, 1583 }; 1584 mss->conf_rid = 3; 1585 mss->indir_rid = 4; 1586 for (c = 0; cards[c].base; c++) { 1587 mss->optibase = cards[c].base; 1588 mss->password = cards[c].password; 1589 mss->passwdreg = cards[c].passwdreg; 1590 mss->bd_id = cards[c].boardid; 1591 1592 if (cards[c].indir_reg) 1593 mss->indir = bus_alloc_resource(dev, SYS_RES_IOPORT, 1594 &mss->indir_rid, cards[c].indir_reg, 1595 cards[c].indir_reg+1, 1, RF_ACTIVE); 1596 1597 mss->conf_base = bus_alloc_resource(dev, SYS_RES_IOPORT, 1598 &mss->conf_rid, mss->optibase, mss->optibase+9, 1599 9, RF_ACTIVE); 1600 1601 if (opti_read(mss, 1) != 0xff) { 1602 return 1; 1603 } else { 1604 if (mss->indir) 1605 bus_release_resource(dev, SYS_RES_IOPORT, mss->indir_rid, mss->indir); 1606 mss->indir = NULL; 1607 if (mss->conf_base) 1608 bus_release_resource(dev, SYS_RES_IOPORT, mss->conf_rid, mss->conf_base); 1609 mss->conf_base = NULL; 1610 } 1611 } 1612 return 0; 1613} 1614 1615static char * 1616ymf_test(device_t dev, struct mss_info *mss) 1617{ 1618 static int ports[] = {0x370, 0x310, 0x538}; 1619 int p, i, j, version; 1620 static char *chipset[] = { 1621 NULL, /* 0 */ 1622 "OPL3-SA2 (YMF711)", /* 1 */ 1623 "OPL3-SA3 (YMF715)", /* 2 */ 1624 "OPL3-SA3 (YMF715)", /* 3 */ 1625 "OPL3-SAx (YMF719)", /* 4 */ 1626 "OPL3-SAx (YMF719)", /* 5 */ 1627 "OPL3-SAx (YMF719)", /* 6 */ 1628 "OPL3-SAx (YMF719)", /* 7 */ 1629 }; 1630 1631 for (p = 0; p < 3; p++) { 1632 mss->conf_rid = 1; 1633 mss->conf_base = bus_alloc_resource(dev, 1634 SYS_RES_IOPORT, 1635 &mss->conf_rid, 1636 ports[p], ports[p] + 1, 2, 1637 RF_ACTIVE); 1638 if (!mss->conf_base) return 0; 1639 1640 /* Test the index port of the config registers */ 1641 i = port_rd(mss->conf_base, 0); 1642 port_wr(mss->conf_base, 0, OPL3SAx_DMACONF); 1643 j = (port_rd(mss->conf_base, 0) == OPL3SAx_DMACONF)? 1 : 0; 1644 port_wr(mss->conf_base, 0, i); 1645 if (!j) { 1646 bus_release_resource(dev, SYS_RES_IOPORT, 1647 mss->conf_rid, mss->conf_base); 1648#ifdef PC98 1649 /* PC98 need this. I don't know reason why. */ 1650 bus_delete_resource(dev, SYS_RES_IOPORT, mss->conf_rid); 1651#endif 1652 mss->conf_base = 0; 1653 continue; 1654 } 1655 version = conf_rd(mss, OPL3SAx_MISC) & 0x07; 1656 return chipset[version]; 1657 } 1658 return NULL; 1659} 1660 1661static int 1662mss_doattach(device_t dev, struct mss_info *mss) 1663{ 1664 int pdma, rdma, flags = device_get_flags(dev); 1665 char status[SND_STATUSLEN], status2[SND_STATUSLEN]; 1666 1667 mss->lock = snd_mtxcreate(device_get_nameunit(dev)); 1668 mss->bufsize = pcm_getbuffersize(dev, 4096, MSS_DEFAULT_BUFSZ, 65536); 1669 if (!mss_alloc_resources(mss, dev)) goto no; 1670 mss_init(mss, dev); 1671 pdma = rman_get_start(mss->drq1); 1672 rdma = rman_get_start(mss->drq2); 1673 if (flags & DV_F_TRUE_MSS) { 1674 /* has IRQ/DMA registers, set IRQ and DMA addr */ 1675#ifdef PC98 /* CS423[12] in PC98 can use IRQ3,5,10,12 */ 1676 static char interrupt_bits[13] = 1677 {-1, -1, -1, 0x08, -1, 0x10, -1, -1, -1, -1, 0x18, -1, 0x20}; 1678#else 1679 static char interrupt_bits[12] = 1680 {-1, -1, -1, -1, -1, 0x28, -1, 0x08, -1, 0x10, 0x18, 0x20}; 1681#endif 1682 static char pdma_bits[4] = {1, 2, -1, 3}; 1683 static char valid_rdma[4] = {1, 0, -1, 0}; 1684 char bits; 1685 1686 if (!mss->irq || (bits = interrupt_bits[rman_get_start(mss->irq)]) == -1) 1687 goto no; 1688#ifndef PC98 /* CS423[12] in PC98 don't support this. */ 1689 io_wr(mss, 0, bits | 0x40); /* config port */ 1690 if ((io_rd(mss, 3) & 0x40) == 0) device_printf(dev, "IRQ Conflict?\n"); 1691#endif 1692 /* Write IRQ+DMA setup */ 1693 if (pdma_bits[pdma] == -1) goto no; 1694 bits |= pdma_bits[pdma]; 1695 if (pdma != rdma) { 1696 if (rdma == valid_rdma[pdma]) bits |= 4; 1697 else { 1698 printf("invalid dual dma config %d:%d\n", pdma, rdma); 1699 goto no; 1700 } 1701 } 1702 io_wr(mss, 0, bits); 1703 printf("drq/irq conf %x\n", io_rd(mss, 0)); 1704 } 1705 mixer_init(dev, (mss->bd_id == MD_YM0020)? &ymmix_mixer_class : &mssmix_mixer_class, mss); 1706 switch (mss->bd_id) { 1707 case MD_OPTI931: 1708 snd_setup_intr(dev, mss->irq, INTR_MPSAFE, opti931_intr, mss, &mss->ih); 1709 break; 1710 default: 1711 snd_setup_intr(dev, mss->irq, INTR_MPSAFE, mss_intr, mss, &mss->ih); 1712 } 1713 if (pdma == rdma) 1714 pcm_setflags(dev, pcm_getflags(dev) | SD_F_SIMPLEX); 1715 if (bus_dma_tag_create(/*parent*/NULL, /*alignment*/2, /*boundary*/0, 1716 /*lowaddr*/BUS_SPACE_MAXADDR_24BIT, 1717 /*highaddr*/BUS_SPACE_MAXADDR, 1718 /*filter*/NULL, /*filterarg*/NULL, 1719 /*maxsize*/mss->bufsize, /*nsegments*/1, 1720 /*maxsegz*/0x3ffff, 1721 /*flags*/0, &mss->parent_dmat) != 0) { 1722 device_printf(dev, "unable to create dma tag\n"); 1723 goto no; 1724 } 1725 1726 if (pdma != rdma) 1727 snprintf(status2, SND_STATUSLEN, ":%d", rdma); 1728 else 1729 status2[0] = '\0'; 1730 1731 snprintf(status, SND_STATUSLEN, "at io 0x%lx irq %ld drq %d%s bufsz %u", 1732 rman_get_start(mss->io_base), rman_get_start(mss->irq), pdma, status2, mss->bufsize); 1733 1734 if (pcm_register(dev, mss, 1, 1)) goto no; 1735 pcm_addchan(dev, PCMDIR_REC, &msschan_class, mss); 1736 pcm_addchan(dev, PCMDIR_PLAY, &msschan_class, mss); 1737 pcm_setstatus(dev, status); 1738 1739 return 0; 1740no: 1741 mss_release_resources(mss, dev); 1742 return ENXIO; 1743} 1744 1745static int 1746mss_detach(device_t dev) 1747{ 1748 int r; 1749 struct mss_info *mss; 1750 1751 r = pcm_unregister(dev); 1752 if (r) 1753 return r; 1754 1755 mss = pcm_getdevinfo(dev); 1756 mss_release_resources(mss, dev); 1757 1758 return 0; 1759} 1760 1761static int 1762mss_attach(device_t dev) 1763{ 1764 struct mss_info *mss; 1765 int flags = device_get_flags(dev); 1766 1767 mss = (struct mss_info *)malloc(sizeof *mss, M_DEVBUF, M_NOWAIT | M_ZERO); 1768 if (!mss) return ENXIO; 1769 1770 mss->io_rid = 0; 1771 mss->conf_rid = -1; 1772 mss->irq_rid = 0; 1773 mss->drq1_rid = 0; 1774 mss->drq2_rid = -1; 1775 if (flags & DV_F_DUAL_DMA) { 1776 bus_set_resource(dev, SYS_RES_DRQ, 1, 1777 flags & DV_F_DRQ_MASK, 1); 1778 mss->drq2_rid = 1; 1779 } 1780 mss->bd_id = (device_get_flags(dev) & DV_F_DEV_MASK) >> DV_F_DEV_SHIFT; 1781 if (mss->bd_id == MD_YM0020) ymf_test(dev, mss); 1782 return mss_doattach(dev, mss); 1783} 1784 1785/* 1786 * mss_resume() is the code to allow a laptop to resume using the sound 1787 * card. 1788 * 1789 * This routine re-sets the state of the board to the state before going 1790 * to sleep. According to the yamaha docs this is the right thing to do, 1791 * but getting DMA restarted appears to be a bit of a trick, so the device 1792 * has to be closed and re-opened to be re-used, but there is no skipping 1793 * problem, and volume, bass/treble and most other things are restored 1794 * properly. 1795 * 1796 */ 1797 1798static int 1799mss_resume(device_t dev) 1800{ 1801 /* 1802 * Restore the state taken below. 1803 */ 1804 struct mss_info *mss; 1805 int i; 1806 1807 mss = pcm_getdevinfo(dev); 1808 1809 if (mss->bd_id == MD_YM0020) 1810 { 1811 /* This works on a Toshiba Libretto 100CT. */ 1812 for (i = 0; i < MSS_INDEXED_REGS; i++) 1813 ad_write(mss, i, mss->mss_indexed_regs[i]); 1814 for (i = 0; i < OPL_INDEXED_REGS; i++) 1815 conf_wr(mss, i, mss->opl_indexed_regs[i]); 1816 mss_intr(mss); 1817 } 1818 return 0; 1819 1820} 1821 1822/* 1823 * mss_suspend() is the code that gets called right before a laptop 1824 * suspends. 1825 * 1826 * This code saves the state of the sound card right before shutdown 1827 * so it can be restored above. 1828 * 1829 */ 1830 1831static int 1832mss_suspend(device_t dev) 1833{ 1834 int i; 1835 struct mss_info *mss; 1836 1837 mss = pcm_getdevinfo(dev); 1838 1839 if(mss->bd_id == MD_YM0020) 1840 { 1841 /* this stops playback. */ 1842 conf_wr(mss, 0x12, 0x0c); 1843 for(i = 0; i < MSS_INDEXED_REGS; i++) 1844 mss->mss_indexed_regs[i] = ad_read(mss, i); 1845 for(i = 0; i < OPL_INDEXED_REGS; i++) 1846 mss->opl_indexed_regs[i] = conf_rd(mss, i); 1847 mss->opl_indexed_regs[0x12] = 0x0; 1848 } 1849 return 0; 1850} 1851 1852static device_method_t mss_methods[] = { 1853 /* Device interface */ 1854 DEVMETHOD(device_probe, mss_probe), 1855 DEVMETHOD(device_attach, mss_attach), 1856 DEVMETHOD(device_detach, mss_detach), 1857 DEVMETHOD(device_suspend, mss_suspend), 1858 DEVMETHOD(device_resume, mss_resume), 1859 1860 { 0, 0 } 1861}; 1862 1863static driver_t mss_driver = { 1864 "pcm", 1865 mss_methods, 1866 PCM_SOFTC_SIZE, 1867}; 1868 1869DRIVER_MODULE(snd_mss, isa, mss_driver, pcm_devclass, 0, 0); 1870MODULE_DEPEND(snd_mss, snd_pcm, PCM_MINVER, PCM_PREFVER, PCM_MAXVER); 1871MODULE_VERSION(snd_mss, 1); 1872 1873static struct isa_pnp_id pnpmss_ids[] = { 1874 {0x0000630e, "CS423x"}, /* CSC0000 */ 1875 {0x0001630e, "CS423x-PCI"}, /* CSC0100 */ 1876 {0x01000000, "CMI8330"}, /* @@@0001 */ 1877 {0x2100a865, "Yamaha OPL-SAx"}, /* YMH0021 */ 1878 {0x1110d315, "ENSONIQ SoundscapeVIVO"}, /* ENS1011 */ 1879 {0x1093143e, "OPTi931"}, /* OPT9310 */ 1880 {0x5092143e, "OPTi925"}, /* OPT9250 XXX guess */ 1881 {0x0000143e, "OPTi924"}, /* OPT0924 */ 1882 {0x1022b839, "Neomagic 256AV (non-ac97)"}, /* NMX2210 */ 1883#if 0 1884 {0x0000561e, "GusPnP"}, /* GRV0000 */ 1885#endif 1886 {0}, 1887}; 1888 1889static int 1890pnpmss_probe(device_t dev) 1891{ 1892 u_int32_t lid, vid; 1893 1894 lid = isa_get_logicalid(dev); 1895 vid = isa_get_vendorid(dev); 1896 if (lid == 0x01000000 && vid != 0x0100a90d) /* CMI0001 */ 1897 return ENXIO; 1898 return ISA_PNP_PROBE(device_get_parent(dev), dev, pnpmss_ids); 1899} 1900 1901static int 1902pnpmss_attach(device_t dev) 1903{ 1904 struct mss_info *mss; 1905 1906 mss = (struct mss_info *)malloc(sizeof *mss, M_DEVBUF, M_NOWAIT | M_ZERO); 1907 if (!mss) 1908 return ENXIO; 1909 1910 mss->io_rid = 0; 1911 mss->conf_rid = -1; 1912 mss->irq_rid = 0; 1913 mss->drq1_rid = 0; 1914 mss->drq2_rid = 1; 1915 mss->bd_id = MD_CS42XX; 1916 1917 switch (isa_get_logicalid(dev)) { 1918 case 0x0000630e: /* CSC0000 */ 1919 case 0x0001630e: /* CSC0100 */ 1920 mss->bd_flags |= BD_F_MSS_OFFSET; 1921 break; 1922 1923 case 0x2100a865: /* YHM0021 */ 1924 mss->io_rid = 1; 1925 mss->conf_rid = 4; 1926 mss->bd_id = MD_YM0020; 1927 break; 1928 1929 case 0x1110d315: /* ENS1011 */ 1930 mss->io_rid = 1; 1931 mss->bd_id = MD_VIVO; 1932 break; 1933 1934 case 0x1093143e: /* OPT9310 */ 1935 mss->bd_flags |= BD_F_MSS_OFFSET; 1936 mss->conf_rid = 3; 1937 mss->bd_id = MD_OPTI931; 1938 break; 1939 1940 case 0x5092143e: /* OPT9250 XXX guess */ 1941 mss->io_rid = 1; 1942 mss->conf_rid = 3; 1943 mss->bd_id = MD_OPTI925; 1944 break; 1945 1946 case 0x0000143e: /* OPT0924 */ 1947 mss->password = 0xe5; 1948 mss->passwdreg = 3; 1949 mss->optibase = 0xf0c; 1950 mss->io_rid = 2; 1951 mss->conf_rid = 3; 1952 mss->bd_id = MD_OPTI924; 1953 mss->bd_flags |= BD_F_924PNP; 1954 if(opti_init(dev, mss) != 0) 1955 return ENXIO; 1956 break; 1957 1958 case 0x1022b839: /* NMX2210 */ 1959 mss->io_rid = 1; 1960 break; 1961 1962#if 0 1963 case 0x0000561e: /* GRV0000 */ 1964 mss->bd_flags |= BD_F_MSS_OFFSET; 1965 mss->io_rid = 2; 1966 mss->conf_rid = 1; 1967 mss->drq1_rid = 1; 1968 mss->drq2_rid = 0; 1969 mss->bd_id = MD_GUSPNP; 1970 break; 1971#endif 1972 case 0x01000000: /* @@@0001 */ 1973 mss->drq2_rid = -1; 1974 break; 1975 1976 /* Unknown MSS default. We could let the CSC0000 stuff match too */ 1977 default: 1978 mss->bd_flags |= BD_F_MSS_OFFSET; 1979 break; 1980 } 1981 return mss_doattach(dev, mss); 1982} 1983 1984static int 1985opti_init(device_t dev, struct mss_info *mss) 1986{ 1987 int flags = device_get_flags(dev); 1988 int basebits = 0; 1989 1990 if (!mss->conf_base) { 1991 bus_set_resource(dev, SYS_RES_IOPORT, mss->conf_rid, 1992 mss->optibase, 0x9); 1993 1994 mss->conf_base = bus_alloc_resource(dev, SYS_RES_IOPORT, 1995 &mss->conf_rid, mss->optibase, mss->optibase+0x9, 1996 0x9, RF_ACTIVE); 1997 } 1998 1999 if (!mss->conf_base) 2000 return ENXIO; 2001 2002 if (!mss->io_base) 2003 mss->io_base = bus_alloc_resource(dev, SYS_RES_IOPORT, 2004 &mss->io_rid, 0, ~0, 8, RF_ACTIVE); 2005 2006 if (!mss->io_base) /* No hint specified, use 0x530 */ 2007 mss->io_base = bus_alloc_resource(dev, SYS_RES_IOPORT, 2008 &mss->io_rid, 0x530, 0x537, 8, RF_ACTIVE); 2009 2010 if (!mss->io_base) 2011 return ENXIO; 2012 2013 switch (rman_get_start(mss->io_base)) { 2014 case 0x530: 2015 basebits = 0x0; 2016 break; 2017 case 0xe80: 2018 basebits = 0x10; 2019 break; 2020 case 0xf40: 2021 basebits = 0x20; 2022 break; 2023 case 0x604: 2024 basebits = 0x30; 2025 break; 2026 default: 2027 printf("opti_init: invalid MSS base address!\n"); 2028 return ENXIO; 2029 } 2030 2031 2032 switch (mss->bd_id) { 2033 case MD_OPTI924: 2034 opti_write(mss, 1, 0x80 | basebits); /* MSS mode */ 2035 opti_write(mss, 2, 0x00); /* Disable CD */ 2036 opti_write(mss, 3, 0xf0); /* Disable SB IRQ */ 2037 opti_write(mss, 4, 0xf0); 2038 opti_write(mss, 5, 0x00); 2039 opti_write(mss, 6, 0x02); /* MPU stuff */ 2040 break; 2041 2042 case MD_OPTI930: 2043 opti_write(mss, 1, 0x00 | basebits); 2044 opti_write(mss, 3, 0x00); /* Disable SB IRQ/DMA */ 2045 opti_write(mss, 4, 0x52); /* Empty FIFO */ 2046 opti_write(mss, 5, 0x3c); /* Mode 2 */ 2047 opti_write(mss, 6, 0x02); /* Enable MSS */ 2048 break; 2049 } 2050 2051 if (mss->bd_flags & BD_F_924PNP) { 2052 u_int32_t irq = isa_get_irq(dev); 2053 u_int32_t drq = isa_get_drq(dev); 2054 bus_set_resource(dev, SYS_RES_IRQ, 0, irq, 1); 2055 bus_set_resource(dev, SYS_RES_DRQ, mss->drq1_rid, drq, 1); 2056 if (flags & DV_F_DUAL_DMA) { 2057 bus_set_resource(dev, SYS_RES_DRQ, 1, 2058 flags & DV_F_DRQ_MASK, 1); 2059 mss->drq2_rid = 1; 2060 } 2061 } 2062 2063 /* OPTixxx has I/DRQ registers */ 2064 2065 device_set_flags(dev, device_get_flags(dev) | DV_F_TRUE_MSS); 2066 2067 return 0; 2068} 2069 2070static void 2071opti_write(struct mss_info *mss, u_char reg, u_char val) 2072{ 2073 port_wr(mss->conf_base, mss->passwdreg, mss->password); 2074 2075 switch(mss->bd_id) { 2076 case MD_OPTI924: 2077 if (reg > 7) { /* Indirect register */ 2078 port_wr(mss->conf_base, mss->passwdreg, reg); 2079 port_wr(mss->conf_base, mss->passwdreg, 2080 mss->password); 2081 port_wr(mss->conf_base, 9, val); 2082 return; 2083 } 2084 port_wr(mss->conf_base, reg, val); 2085 break; 2086 2087 case MD_OPTI930: 2088 port_wr(mss->indir, 0, reg); 2089 port_wr(mss->conf_base, mss->passwdreg, mss->password); 2090 port_wr(mss->indir, 1, val); 2091 break; 2092 } 2093} 2094 2095u_char 2096opti_read(struct mss_info *mss, u_char reg) 2097{ 2098 port_wr(mss->conf_base, mss->passwdreg, mss->password); 2099 2100 switch(mss->bd_id) { 2101 case MD_OPTI924: 2102 if (reg > 7) { /* Indirect register */ 2103 port_wr(mss->conf_base, mss->passwdreg, reg); 2104 port_wr(mss->conf_base, mss->passwdreg, mss->password); 2105 return(port_rd(mss->conf_base, 9)); 2106 } 2107 return(port_rd(mss->conf_base, reg)); 2108 break; 2109 2110 case MD_OPTI930: 2111 port_wr(mss->indir, 0, reg); 2112 port_wr(mss->conf_base, mss->passwdreg, mss->password); 2113 return port_rd(mss->indir, 1); 2114 break; 2115 } 2116 return -1; 2117} 2118 2119static device_method_t pnpmss_methods[] = { 2120 /* Device interface */ 2121 DEVMETHOD(device_probe, pnpmss_probe), 2122 DEVMETHOD(device_attach, pnpmss_attach), 2123 DEVMETHOD(device_detach, mss_detach), 2124 DEVMETHOD(device_suspend, mss_suspend), 2125 DEVMETHOD(device_resume, mss_resume), 2126 2127 { 0, 0 } 2128}; 2129 2130static driver_t pnpmss_driver = { 2131 "pcm", 2132 pnpmss_methods, 2133 PCM_SOFTC_SIZE, 2134}; 2135 2136DRIVER_MODULE(snd_pnpmss, isa, pnpmss_driver, pcm_devclass, 0, 0); 2137MODULE_DEPEND(snd_pnpmss, snd_pcm, PCM_MINVER, PCM_PREFVER, PCM_MAXVER); 2138MODULE_VERSION(snd_pnpmss, 1); 2139 2140static int 2141guspcm_probe(device_t dev) 2142{ 2143 struct sndcard_func *func; 2144 2145 func = device_get_ivars(dev); 2146 if (func == NULL || func->func != SCF_PCM) 2147 return ENXIO; 2148 2149 device_set_desc(dev, "GUS CS4231"); 2150 return 0; 2151} 2152 2153static int 2154guspcm_attach(device_t dev) 2155{ 2156 device_t parent = device_get_parent(dev); 2157 struct mss_info *mss; 2158 int base, flags; 2159 unsigned char ctl; 2160 2161 mss = (struct mss_info *)malloc(sizeof *mss, M_DEVBUF, M_NOWAIT | M_ZERO); 2162 if (mss == NULL) 2163 return ENOMEM; 2164 2165 mss->bd_flags = BD_F_MSS_OFFSET; 2166 mss->io_rid = 2; 2167 mss->conf_rid = 1; 2168 mss->irq_rid = 0; 2169 mss->drq1_rid = 1; 2170 mss->drq2_rid = -1; 2171 2172 if (isa_get_logicalid(parent) == 0) 2173 mss->bd_id = MD_GUSMAX; 2174 else { 2175 mss->bd_id = MD_GUSPNP; 2176 mss->drq2_rid = 0; 2177 goto skip_setup; 2178 } 2179 2180 flags = device_get_flags(parent); 2181 if (flags & DV_F_DUAL_DMA) 2182 mss->drq2_rid = 0; 2183 2184 mss->conf_base = bus_alloc_resource(dev, SYS_RES_IOPORT, &mss->conf_rid, 2185 0, ~0, 8, RF_ACTIVE); 2186 2187 if (mss->conf_base == NULL) { 2188 mss_release_resources(mss, dev); 2189 return ENXIO; 2190 } 2191 2192 base = isa_get_port(parent); 2193 2194 ctl = 0x40; /* CS4231 enable */ 2195 if (isa_get_drq(dev) > 3) 2196 ctl |= 0x10; /* 16-bit dma channel 1 */ 2197 if ((flags & DV_F_DUAL_DMA) != 0 && (flags & DV_F_DRQ_MASK) > 3) 2198 ctl |= 0x20; /* 16-bit dma channel 2 */ 2199 ctl |= (base >> 4) & 0x0f; /* 2X0 -> 3XC */ 2200 port_wr(mss->conf_base, 6, ctl); 2201 2202skip_setup: 2203 return mss_doattach(dev, mss); 2204} 2205 2206static device_method_t guspcm_methods[] = { 2207 DEVMETHOD(device_probe, guspcm_probe), 2208 DEVMETHOD(device_attach, guspcm_attach), 2209 DEVMETHOD(device_detach, mss_detach), 2210 2211 { 0, 0 } 2212}; 2213 2214static driver_t guspcm_driver = { 2215 "pcm", 2216 guspcm_methods, 2217 PCM_SOFTC_SIZE, 2218}; 2219 2220DRIVER_MODULE(snd_guspcm, gusc, guspcm_driver, pcm_devclass, 0, 0); 2221MODULE_DEPEND(snd_guspcm, snd_pcm, PCM_MINVER, PCM_PREFVER, PCM_MAXVER); 2222MODULE_VERSION(snd_guspcm, 1); 2223 2224 2225