mss.c revision 53184
1/* 2 * Copyright (c) 1999 Cameron Grant <gandalf@vilnya.demon.co.uk> 3 * Copyright Luigi Rizzo, 1997,1998 4 * Copyright by Hannu Savolainen 1994, 1995 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 19 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 20 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 21 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 22 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26 * SUCH DAMAGE. 27 * 28 * $FreeBSD: head/sys/dev/sound/isa/mss.c 53184 1999-11-15 17:02:32Z peter $ 29 */ 30 31#include <dev/pcm/sound.h> 32 33#if NPCM > 0 34 35/* board-specific include files */ 36#include <dev/pcm/isa/mss.h> 37 38struct mss_info; 39 40struct mss_chinfo { 41 struct mss_info *parent; 42 pcm_channel *channel; 43 snd_dbuf *buffer; 44 int dir; 45}; 46 47struct mss_info { 48 struct resource *io_base; /* primary I/O address for the board */ 49 int io_rid; 50 struct resource *conf_base; /* and the opti931 also has a config space */ 51 int conf_rid; 52 struct resource *irq; 53 int irq_rid; 54 struct resource *drq1; /* play */ 55 int drq1_rid; 56 struct resource *drq2; /* rec */ 57 int drq2_rid; 58 bus_dma_tag_t parent_dmat; 59 60 int pdma, rdma; 61 int bd_id; /* used to hold board-id info, eg. sb version, 62 * mss codec type, etc. etc. 63 */ 64 int opti_offset; /* offset from config_base for opti931 */ 65 u_long bd_flags; /* board-specific flags */ 66 struct mss_chinfo pch, rch; 67}; 68 69static int mss_probe(device_t dev); 70static int mss_attach(device_t dev); 71 72static driver_intr_t mss_intr; 73 74/* prototypes for local functions */ 75static int mss_detect(device_t dev, struct mss_info *mss); 76static char *ymf_test(device_t dev, struct mss_info *mss); 77static void ad_unmute(struct mss_info *mss); 78 79/* mixer set funcs */ 80static int mss_mixer_set(struct mss_info *mss, int dev, int left, int right); 81static int mss_set_recsrc(struct mss_info *mss, int mask); 82 83/* io funcs */ 84static int ad_wait_init(struct mss_info *mss, int x); 85static int ad_read(struct mss_info *mss, int reg); 86static void ad_write(struct mss_info *mss, int reg, u_char data); 87static void ad_write_cnt(struct mss_info *mss, int reg, u_short data); 88 89/* io primitives */ 90static void conf_wr(struct mss_info *mss, u_char reg, u_char data); 91static u_char conf_rd(struct mss_info *mss, u_char reg); 92 93#if NPNP > 0 94static int pnpmss_probe(device_t dev); 95static int pnpmss_attach(device_t dev); 96 97static driver_intr_t opti931_intr; 98#endif 99 100static int mssmix_init(snd_mixer *m); 101static int mssmix_set(snd_mixer *m, unsigned dev, unsigned left, unsigned right); 102static int mssmix_setrecsrc(snd_mixer *m, u_int32_t src); 103static snd_mixer mss_mixer = { 104 "MSS mixer", 105 mssmix_init, 106 mssmix_set, 107 mssmix_setrecsrc, 108}; 109 110static int ymmix_init(snd_mixer *m); 111static int ymmix_set(snd_mixer *m, unsigned dev, unsigned left, unsigned right); 112static int ymmix_setrecsrc(snd_mixer *m, u_int32_t src); 113static snd_mixer yamaha_mixer = { 114 "OPL3-SAx mixer", 115 ymmix_init, 116 ymmix_set, 117 ymmix_setrecsrc, 118}; 119 120static devclass_t pcm_devclass; 121 122/* channel interface */ 123static void *msschan_init(void *devinfo, snd_dbuf *b, pcm_channel *c, int dir); 124static int msschan_setdir(void *data, int dir); 125static int msschan_setformat(void *data, u_int32_t format); 126static int msschan_setspeed(void *data, u_int32_t speed); 127static int msschan_setblocksize(void *data, u_int32_t blocksize); 128static int msschan_trigger(void *data, int go); 129static int msschan_getptr(void *data); 130static pcmchan_caps *msschan_getcaps(void *data); 131 132static pcmchan_caps mss_caps = { 133 4000, 48000, 134 AFMT_STEREO | AFMT_U8 | AFMT_S16_LE | AFMT_MU_LAW | AFMT_A_LAW, 135 AFMT_STEREO | AFMT_S16_LE 136}; 137 138static pcmchan_caps guspnp_caps = { 139 4000, 48000, 140 AFMT_STEREO | AFMT_U8 | AFMT_S16_LE | AFMT_A_LAW, 141 AFMT_STEREO | AFMT_S16_LE 142}; 143 144static pcmchan_caps opti931_caps = { 145 4000, 48000, 146 AFMT_STEREO | AFMT_U8 | AFMT_S16_LE, 147 AFMT_STEREO | AFMT_S16_LE 148}; 149 150static pcm_channel mss_chantemplate = { 151 msschan_init, 152 msschan_setdir, 153 msschan_setformat, 154 msschan_setspeed, 155 msschan_setblocksize, 156 msschan_trigger, 157 msschan_getptr, 158 msschan_getcaps, 159}; 160 161#define MD_AD1848 0x91 162#define MD_AD1845 0x92 163#define MD_CS4248 0xA1 164#define MD_CS4231 0xA2 165#define MD_CS4231A 0xA3 166#define MD_CS4232 0xA4 167#define MD_CS4232A 0xA5 168#define MD_CS4236 0xA6 169#define MD_CS4237 0xA7 170#define MD_OPTI931 0xB1 171#define MD_OPTI925 0xB2 172#define MD_GUSPNP 0xB8 173#define MD_YM0020 0xC1 174#define MD_VIVO 0xD1 175 176#define DV_F_TRUE_MSS 0x00010000 /* mss _with_ base regs */ 177 178#define FULL_DUPLEX(x) ((x)->bd_flags & BD_F_DUPLEX) 179 180static int 181port_rd(struct resource *port, int off) 182{ 183 if (port) 184 return bus_space_read_1(rman_get_bustag(port), 185 rman_get_bushandle(port), 186 off); 187 else 188 return -1; 189} 190 191static void 192port_wr(struct resource *port, int off, u_int8_t data) 193{ 194 if (port) 195 return bus_space_write_1(rman_get_bustag(port), 196 rman_get_bushandle(port), 197 off, data); 198} 199 200static int 201io_rd(struct mss_info *mss, int reg) 202{ 203 if (mss->bd_flags & BD_F_MSS_OFFSET) reg -= 4; 204 return port_rd(mss->io_base, reg); 205} 206 207static void 208io_wr(struct mss_info *mss, int reg, u_int8_t data) 209{ 210 if (mss->bd_flags & BD_F_MSS_OFFSET) reg -= 4; 211 return port_wr(mss->io_base, reg, data); 212} 213 214static void 215conf_wr(struct mss_info *mss, u_char reg, u_char value) 216{ 217 port_wr(mss->conf_base, 0, reg); 218 port_wr(mss->conf_base, 1, value); 219} 220 221static u_char 222conf_rd(struct mss_info *mss, u_char reg) 223{ 224 port_wr(mss->conf_base, 0, reg); 225 return port_rd(mss->conf_base, 1); 226} 227 228static void 229opti_wr(struct mss_info *mss, u_char reg, u_char value) 230{ 231 port_wr(mss->conf_base, mss->opti_offset + 0, reg); 232 port_wr(mss->conf_base, mss->opti_offset + 1, value); 233} 234 235static u_char 236opti_rd(struct mss_info *mss, u_char reg) 237{ 238 port_wr(mss->conf_base, mss->opti_offset + 0, reg); 239 return port_rd(mss->conf_base, mss->opti_offset + 1); 240} 241 242#if NPNP > 0 243static void 244gus_wr(struct mss_info *mss, u_char reg, u_char value) 245{ 246 port_wr(mss->conf_base, 3, reg); 247 port_wr(mss->conf_base, 5, value); 248} 249 250static u_char 251gus_rd(struct mss_info *mss, u_char reg) 252{ 253 port_wr(mss->conf_base, 3, reg); 254 return port_rd(mss->conf_base, 5); 255} 256#endif 257 258static void 259mss_release_resources(struct mss_info *mss, device_t dev) 260{ 261 if (mss->irq) { 262 bus_release_resource(dev, SYS_RES_IRQ, mss->irq_rid, 263 mss->irq); 264 mss->irq = 0; 265 } 266 if (mss->drq1) { 267 bus_release_resource(dev, SYS_RES_DRQ, mss->drq1_rid, 268 mss->drq1); 269 mss->drq1 = 0; 270 mss->pdma = -1; 271 } 272 if (mss->drq2) { 273 bus_release_resource(dev, SYS_RES_DRQ, mss->drq2_rid, 274 mss->drq2); 275 mss->drq2 = 0; 276 mss->rdma = -1; 277 } 278 if (mss->io_base) { 279 bus_release_resource(dev, SYS_RES_IOPORT, mss->io_rid, 280 mss->io_base); 281 mss->io_base = 0; 282 } 283 if (mss->conf_base) { 284 bus_release_resource(dev, SYS_RES_IOPORT, mss->conf_rid, 285 mss->conf_base); 286 mss->conf_base = 0; 287 } 288 free(mss, M_DEVBUF); 289} 290 291static int 292mss_alloc_resources(struct mss_info *mss, device_t dev) 293{ 294 int ok = 1; 295 if (!mss->io_base) 296 mss->io_base = bus_alloc_resource(dev, SYS_RES_IOPORT, &mss->io_rid, 297 0, ~0, 1, RF_ACTIVE); 298 if (!mss->irq) 299 mss->irq = bus_alloc_resource(dev, SYS_RES_IRQ, &mss->irq_rid, 300 0, ~0, 1, RF_ACTIVE); 301 if (!mss->drq1) 302 mss->drq1 = bus_alloc_resource(dev, SYS_RES_DRQ, &mss->drq1_rid, 303 0, ~0, 1, RF_ACTIVE); 304 if (mss->conf_rid >= 0 && !mss->conf_base) 305 mss->conf_base = bus_alloc_resource(dev, SYS_RES_IOPORT, &mss->conf_rid, 306 0, ~0, 1, RF_ACTIVE); 307 if (mss->drq2_rid >= 0 && !mss->drq2) 308 mss->drq2 = bus_alloc_resource(dev, SYS_RES_DRQ, &mss->drq2_rid, 309 0, ~0, 1, RF_ACTIVE); 310 311 if (!mss->io_base || !mss->drq1 || !mss->irq) ok = 0; 312 if (mss->conf_rid >= 0 && !mss->conf_base) ok = 0; 313 if (mss->drq2_rid >= 0 && !mss->drq2) ok = 0; 314 315 if (ok) { 316 mss->pdma = rman_get_start(mss->drq1); 317 isa_dma_acquire(mss->pdma); 318 isa_dmainit(mss->pdma, DSP_BUFFSIZE); 319 mss->bd_flags &= ~BD_F_DUPLEX; 320 if (mss->drq2) { 321 mss->rdma = rman_get_start(mss->drq2); 322 isa_dma_acquire(mss->rdma); 323 isa_dmainit(mss->rdma, DSP_BUFFSIZE); 324 mss->bd_flags |= BD_F_DUPLEX; 325 } else mss->rdma = mss->pdma; 326 } 327 return ok; 328} 329 330static int 331mss_init(struct mss_info *mss, device_t dev) 332{ 333 u_char r6, r9; 334 struct resource *alt; 335 int rid, tmp; 336 337 mss->bd_flags |= BD_F_MCE_BIT; 338 switch(mss->bd_id) { 339#if NPNP > 0 340 case MD_OPTI931: 341 /* 342 * The MED3931 v.1.0 allocates 3 bytes for the config 343 * space, whereas v.2.0 allocates 4 bytes. What I know 344 * for sure is that the upper two ports must be used, 345 * and they should end on a boundary of 4 bytes. So I 346 * need the following trick. 347 */ 348 mss->opti_offset = 349 (rman_get_start(mss->conf_base) & ~3) + 2 350 - rman_get_start(mss->conf_base); 351 printf("mss_init: opti_offset=%d\n", mss->opti_offset); 352 opti_wr(mss, 4, 0xd6); /* fifo empty, OPL3, audio enable, SB3.2 */ 353 ad_write(mss, 10, 2); /* enable interrupts */ 354 opti_wr(mss, 6, 2); /* MCIR6: mss enable, sb disable */ 355 opti_wr(mss, 5, 0x28); /* MCIR5: codec in exp. mode,fifo */ 356 break; 357 358 case MD_GUSPNP: 359 gus_wr(mss, 0x4c /* _URSTI */, 0);/* Pull reset */ 360 DELAY(1000 * 30); 361 /* release reset and enable DAC */ 362 gus_wr(mss, 0x4c /* _URSTI */, 3); 363 DELAY(1000 * 30); 364 /* end of reset */ 365 366 rid = 0; 367 alt = bus_alloc_resource(dev, SYS_RES_IOPORT, &rid, 368 0, ~0, 1, RF_ACTIVE); 369 port_wr(alt, 0, 0xC); /* enable int and dma */ 370 bus_release_resource(dev, SYS_RES_IOPORT, rid, alt); 371 372 /* 373 * unmute left & right line. Need to go in mode3, unmute, 374 * and back to mode 2 375 */ 376 tmp = ad_read(mss, 0x0c); 377 ad_write(mss, 0x0c, 0x6c); /* special value to enter mode 3 */ 378 ad_write(mss, 0x19, 0); /* unmute left */ 379 ad_write(mss, 0x1b, 0); /* unmute right */ 380 ad_write(mss, 0x0c, tmp); /* restore old mode */ 381 382 /* send codec interrupts on irq1 and only use that one */ 383 gus_wr(mss, 0x5a, 0x4f); 384 385 /* enable access to hidden regs */ 386 tmp = gus_rd(mss, 0x5b /* IVERI */); 387 gus_wr(mss, 0x5b, tmp | 1); 388 BVDDB(printf("GUS: silicon rev %c\n", 'A' + ((tmp & 0xf) >> 4))); 389 break; 390#endif 391 case MD_YM0020: 392 conf_wr(mss, OPL3SAx_DMACONF, 0xa9); /* dma-b rec, dma-a play */ 393 r6 = conf_rd(mss, OPL3SAx_DMACONF); 394 r9 = conf_rd(mss, OPL3SAx_MISC); /* version */ 395 BVDDB(printf("Yamaha: ver 0x%x DMA config 0x%x\n", r6, r9);) 396 /* yamaha - set volume to max */ 397 conf_wr(mss, OPL3SAx_VOLUMEL, 0); 398 conf_wr(mss, OPL3SAx_VOLUMER, 0); 399 conf_wr(mss, OPL3SAx_DMACONF, FULL_DUPLEX(mss)? 0xa9 : 0x8b); 400 break; 401 } 402 if (FULL_DUPLEX(mss) && mss->bd_id != MD_OPTI931) 403 ad_write(mss, 12, ad_read(mss, 12) | 0x40); /* mode 2 */ 404 ad_write(mss, 9, FULL_DUPLEX(mss)? 0 : 4); 405 ad_write(mss, 10, 2); /* int enable */ 406 io_wr(mss, MSS_STATUS, 0); /* Clear interrupt status */ 407 /* the following seem required on the CS4232 */ 408 ad_unmute(mss); 409 return 0; 410} 411 412/* 413 * mss_probe() is the probe routine. Note, it is not necessary to 414 * go through this for PnP devices, since they are already 415 * indentified precisely using their PnP id. 416 * 417 * The base address supplied in the device refers to the old MSS 418 * specs where the four 4 registers in io space contain configuration 419 * information. Some boards (as an example, early MSS boards) 420 * has such a block of registers, whereas others (generally CS42xx) 421 * do not. In order to distinguish between the two and do not have 422 * to supply two separate probe routines, the flags entry in isa_device 423 * has a bit to mark this. 424 * 425 */ 426 427static int 428mss_probe(device_t dev) 429{ 430 u_char tmp, tmpx; 431 int flags, irq, drq, result = ENXIO, setres = 0; 432 struct mss_info *mss; 433 434 if (isa_get_vendorid(dev)) return ENXIO; /* not yet */ 435 436 mss = (struct mss_info *)malloc(sizeof *mss, M_DEVBUF, M_NOWAIT); 437 if (!mss) return ENXIO; 438 bzero(mss, sizeof *mss); 439 440 mss->io_rid = 0; 441 mss->conf_rid = -1; 442 mss->irq_rid = 0; 443 mss->drq1_rid = 0; 444 mss->drq2_rid = -1; 445 mss->io_base = bus_alloc_resource(dev, SYS_RES_IOPORT, &mss->io_rid, 446 0, ~0, 8, RF_ACTIVE); 447 if (!mss->io_base) { 448 BVDDB(printf("mss_probe: no address given, try 0x%x\n", 0x530)); 449 mss->io_rid = 0; 450 /* XXX verify this */ 451 setres = 1; 452 bus_set_resource(dev, SYS_RES_IOPORT, mss->io_rid, 453 0x530, 8); 454 mss->io_base = bus_alloc_resource(dev, SYS_RES_IOPORT, &mss->io_rid, 455 0, ~0, 8, RF_ACTIVE); 456 } 457 if (!mss->io_base) goto no; 458 459 /* got irq/dma regs? */ 460 flags = device_get_flags(dev); 461 irq = isa_get_irq(dev); 462 drq = isa_get_drq(dev); 463 464 if (!(device_get_flags(dev) & DV_F_TRUE_MSS)) goto mss_probe_end; 465 466 /* 467 * Check if the IO port returns valid signature. The original MS 468 * Sound system returns 0x04 while some cards 469 * (AudioTriX Pro for example) return 0x00 or 0x0f. 470 */ 471 472 device_set_desc(dev, "MSS"); 473 tmpx = tmp = io_rd(mss, 3); 474 if (tmp == 0xff) { /* Bus float */ 475 BVDDB(printf("I/O addr inactive (%x), try pseudo_mss\n", tmp)); 476 device_set_flags(dev, flags & ~DV_F_TRUE_MSS); 477 goto mss_probe_end; 478 } 479 tmp &= 0x3f; 480 if (!(tmp == 0x04 || tmp == 0x0f || tmp == 0x00)) { 481 BVDDB(printf("No MSS signature detected on port 0x%lx (0x%x)\n", 482 rman_get_start(mss->io_base), tmpx)); 483 goto no; 484 } 485 if (irq > 11) { 486 printf("MSS: Bad IRQ %d\n", irq); 487 goto no; 488 } 489 if (!(drq == 0 || drq == 1 || drq == 3)) { 490 printf("MSS: Bad DMA %d\n", drq); 491 goto no; 492 } 493 if (tmpx & 0x80) { 494 /* 8-bit board: only drq1/3 and irq7/9 */ 495 if (drq == 0) { 496 printf("MSS: Can't use DMA0 with a 8 bit card/slot\n"); 497 goto no; 498 } 499 if (!(irq == 7 || irq == 9)) { 500 printf("MSS: Can't use IRQ%d with a 8 bit card/slot\n", 501 irq); 502 goto no; 503 } 504 } 505 mss_probe_end: 506 result = mss_detect(dev, mss); 507 no: 508 mss_release_resources(mss, dev); 509#if 0 510 if (setres) ISA_DELETE_RESOURCE(device_get_parent(dev), dev, 511 SYS_RES_IOPORT, mss->io_rid); /* XXX ? */ 512#endif 513 return result; 514} 515 516static int 517mss_detect(device_t dev, struct mss_info *mss) 518{ 519 int i; 520 u_char tmp, tmp1, tmp2; 521 char *name, *yamaha; 522 523 if (mss->bd_id != 0) { 524 device_printf(dev, "presel bd_id 0x%04x -- %s\n", mss->bd_id, 525 device_get_desc(dev)); 526 return 0; 527 } 528 529 name = "AD1848"; 530 mss->bd_id = MD_AD1848; /* AD1848 or CS4248 */ 531 532 /* 533 * Check that the I/O address is in use. 534 * 535 * bit 7 of the base I/O port is known to be 0 after the chip has 536 * performed its power on initialization. Just assume this has 537 * happened before the OS is starting. 538 * 539 * If the I/O address is unused, it typically returns 0xff. 540 */ 541 542 for (i = 0; i < 10; i++) 543 if ((tmp = io_rd(mss, MSS_INDEX)) & MSS_IDXBUSY) DELAY(10000); 544 else break; 545 546 if (i >= 10) { /* Not a AD1848 */ 547 BVDDB(printf("mss_detect, busy still set (0x%02x)\n", tmp)); 548 goto no; 549 } 550 /* 551 * Test if it's possible to change contents of the indirect 552 * registers. Registers 0 and 1 are ADC volume registers. The bit 553 * 0x10 is read only so try to avoid using it. 554 */ 555 556 ad_write(mss, 0, 0xaa); 557 ad_write(mss, 1, 0x45);/* 0x55 with bit 0x10 clear */ 558 tmp1 = ad_read(mss, 0); 559 tmp2 = ad_read(mss, 1); 560 if (tmp1 != 0xaa || tmp2 != 0x45) { 561 BVDDB(printf("mss_detect error - IREG (%x/%x)\n", tmp1, tmp2)); 562 goto no; 563 } 564 565 ad_write(mss, 0, 0x45); 566 ad_write(mss, 1, 0xaa); 567 tmp1 = ad_read(mss, 0); 568 tmp2 = ad_read(mss, 1); 569 if (tmp1 != 0x45 || tmp2 != 0xaa) { 570 BVDDB(printf("mss_detect error - IREG2 (%x/%x)\n", tmp1, tmp2)); 571 goto no; 572 } 573 574 /* 575 * The indirect register I12 has some read only bits. Lets try to 576 * change them. 577 */ 578 579 tmp = ad_read(mss, 12); 580 ad_write(mss, 12, (~tmp) & 0x0f); 581 tmp1 = ad_read(mss, 12); 582 583 if ((tmp & 0x0f) != (tmp1 & 0x0f)) { 584 BVDDB(printf("mss_detect - I12 (0x%02x was 0x%02x)\n", tmp1, tmp)); 585 goto no; 586 } 587 588 /* 589 * NOTE! Last 4 bits of the reg I12 tell the chip revision. 590 * 0x01=RevB 591 * 0x0A=RevC. also CS4231/CS4231A and OPTi931 592 */ 593 594 BVDDB(printf("mss_detect - chip revision 0x%02x\n", tmp & 0x0f);) 595 596 /* 597 * The original AD1848/CS4248 has just 16 indirect registers. This 598 * means that I0 and I16 should return the same value (etc.). Ensure 599 * that the Mode2 enable bit of I12 is 0. Otherwise this test fails 600 * with new parts. 601 */ 602 603 ad_write(mss, 12, 0); /* Mode2=disabled */ 604#if 0 605 for (i = 0; i < 16; i++) { 606 if ((tmp1 = ad_read(mss, i)) != (tmp2 = ad_read(mss, i + 16))) { 607 BVDDB(printf("mss_detect warning - I%d: 0x%02x/0x%02x\n", 608 i, tmp1, tmp2)); 609 /* 610 * note - this seems to fail on the 4232 on I11. So we just break 611 * rather than fail. (which makes this test pointless - cg) 612 */ 613 break; /* return 0; */ 614 } 615 } 616#endif 617 /* 618 * Try to switch the chip to mode2 (CS4231) by setting the MODE2 bit 619 * (0x40). The bit 0x80 is always 1 in CS4248 and CS4231. 620 * 621 * On the OPTi931, however, I12 is readonly and only contains the 622 * chip revision ID (as in the CS4231A). The upper bits return 0. 623 */ 624 625 ad_write(mss, 12, 0x40); /* Set mode2, clear 0x80 */ 626 627 tmp1 = ad_read(mss, 12); 628 if (tmp1 & 0x80) name = "CS4248"; /* Our best knowledge just now */ 629 if ((tmp1 & 0xf0) == 0x00) { 630 BVDDB(printf("this should be an OPTi931\n");) 631 } else if ((tmp1 & 0xc0) != 0xC0) goto gotit; 632 /* 633 * The 4231 has bit7=1 always, and bit6 we just set to 1. 634 * We want to check that this is really a CS4231 635 * Verify that setting I0 doesn't change I16. 636 */ 637 ad_write(mss, 16, 0); /* Set I16 to known value */ 638 ad_write(mss, 0, 0x45); 639 if ((tmp1 = ad_read(mss, 16)) == 0x45) goto gotit; 640 641 ad_write(mss, 0, 0xaa); 642 if ((tmp1 = ad_read(mss, 16)) == 0xaa) { /* Rotten bits? */ 643 BVDDB(printf("mss_detect error - step H(%x)\n", tmp1)); 644 goto no; 645 } 646 /* Verify that some bits of I25 are read only. */ 647 tmp1 = ad_read(mss, 25); /* Original bits */ 648 ad_write(mss, 25, ~tmp1); /* Invert all bits */ 649 if ((ad_read(mss, 25) & 0xe7) == (tmp1 & 0xe7)) { 650 int id; 651 652 /* It's at least CS4231 */ 653 name = "CS4231"; 654 mss->bd_id = MD_CS4231; 655 656 /* 657 * It could be an AD1845 or CS4231A as well. 658 * CS4231 and AD1845 report the same revision info in I25 659 * while the CS4231A reports different. 660 */ 661 662 id = ad_read(mss, 25) & 0xe7; 663 /* 664 * b7-b5 = version number; 665 * 100 : all CS4231 666 * 101 : CS4231A 667 * 668 * b2-b0 = chip id; 669 */ 670 switch (id) { 671 672 case 0xa0: 673 name = "CS4231A"; 674 mss->bd_id = MD_CS4231A; 675 break; 676 677 case 0xa2: 678 name = "CS4232"; 679 mss->bd_id = MD_CS4232; 680 break; 681 682 case 0xb2: 683 /* strange: the 4231 data sheet says b4-b3 are XX 684 * so this should be the same as 0xa2 685 */ 686 name = "CS4232A"; 687 mss->bd_id = MD_CS4232A; 688 break; 689 690 case 0x80: 691 /* 692 * It must be a CS4231 or AD1845. The register I23 693 * of CS4231 is undefined and it appears to be read 694 * only. AD1845 uses I23 for setting sample rate. 695 * Assume the chip is AD1845 if I23 is changeable. 696 */ 697 698 tmp = ad_read(mss, 23); 699 700 ad_write(mss, 23, ~tmp); 701 if (ad_read(mss, 23) != tmp) { /* AD1845 ? */ 702 name = "AD1845"; 703 mss->bd_id = MD_AD1845; 704 } 705 ad_write(mss, 23, tmp); /* Restore */ 706 707 yamaha = ymf_test(dev, mss); 708 if (yamaha) { 709 mss->bd_id = MD_YM0020; 710 name = yamaha; 711 } 712 break; 713 714 case 0x83: /* CS4236 */ 715 case 0x03: /* CS4236 on Intel PR440FX motherboard XXX */ 716 name = "CS4236"; 717 mss->bd_id = MD_CS4236; 718 break; 719 720 default: /* Assume CS4231 */ 721 BVDDB(printf("unknown id 0x%02x, assuming CS4231\n", id);) 722 mss->bd_id = MD_CS4231; 723 } 724 } 725 ad_write(mss, 25, tmp1); /* Restore bits */ 726gotit: 727 BVDDB(printf("mss_detect() - Detected %s\n", name)); 728 device_set_desc(dev, name); 729 device_set_flags(dev, 730 ((device_get_flags(dev) & ~DV_F_DEV_MASK) | 731 ((mss->bd_id << DV_F_DEV_SHIFT) & DV_F_DEV_MASK))); 732 return 0; 733no: 734 return ENXIO; 735} 736 737static char * 738ymf_test(device_t dev, struct mss_info *mss) 739{ 740 static int ports[] = {0x370, 0x310, 0x538}; 741 int p, i, j, version; 742 static char *chipset[] = { 743 NULL, /* 0 */ 744 "OPL3-SA2 (YMF711)", /* 1 */ 745 "OPL3-SA3 (YMF715)", /* 2 */ 746 "OPL3-SA3 (YMF715)", /* 3 */ 747 "OPL3-SAx (YMF719)", /* 4 */ 748 "OPL3-SAx (YMF719)", /* 5 */ 749 "OPL3-SAx (YMF719)", /* 6 */ 750 "OPL3-SAx (YMF719)", /* 7 */ 751 }; 752 753 for (p = 0; p < 3; p++) { 754 mss->conf_rid = 1; 755 mss->conf_base = bus_alloc_resource(dev, 756 SYS_RES_IOPORT, 757 &mss->conf_rid, 758 ports[p], ports[p] + 1, 2, 759 RF_ACTIVE); 760 if (!mss->conf_base) return 0; 761 762 /* Test the index port of the config registers */ 763 i = port_rd(mss->conf_base, 0); 764 port_wr(mss->conf_base, 0, OPL3SAx_DMACONF); 765 j = (port_rd(mss->conf_base, 0) == OPL3SAx_DMACONF)? 1 : 0; 766 port_wr(mss->conf_base, 0, i); 767 if (!j) { 768 bus_release_resource(dev, SYS_RES_IOPORT, 769 mss->conf_rid, mss->conf_base); 770 mss->conf_base = 0; 771 continue; 772 } 773 version = conf_rd(mss, OPL3SAx_MISC) & 0x07; 774 return chipset[version]; 775 } 776 return NULL; 777} 778 779static int 780mss_doattach(device_t dev, struct mss_info *mss) 781{ 782 snddev_info *d = device_get_softc(dev); 783 void *ih; 784 int flags = device_get_flags(dev); 785 char status[SND_STATUSLEN]; 786 787 if (!mss_alloc_resources(mss, dev)) goto no; 788 mss_init(mss, dev); 789 if (flags & DV_F_TRUE_MSS) { 790 /* has IRQ/DMA registers, set IRQ and DMA addr */ 791 static char interrupt_bits[12] = 792 {-1, -1, -1, -1, -1, 0x28, -1, 0x08, -1, 0x10, 0x18, 0x20}; 793 static char pdma_bits[4] = {1, 2, -1, 3}; 794 static char valid_rdma[4] = {1, 0, -1, 0}; 795 char bits; 796 797 if (!mss->irq || (bits = interrupt_bits[rman_get_start(mss->irq)]) == -1) 798 goto no; 799 io_wr(mss, 0, bits | 0x40); /* config port */ 800 if ((io_rd(mss, 3) & 0x40) == 0) device_printf(dev, "IRQ Conflict?\n"); 801 /* Write IRQ+DMA setup */ 802 if (pdma_bits[mss->pdma] == -1) goto no; 803 bits |= pdma_bits[mss->pdma]; 804 if (mss->pdma != mss->rdma) { 805 if (mss->rdma == valid_rdma[mss->pdma]) bits |= 4; 806 else { 807 printf("invalid dual dma config %d:%d\n", 808 mss->pdma, mss->rdma); 809 goto no; 810 } 811 } 812 io_wr(mss, 0, bits); 813 printf("drq/irq conf %x\n", io_rd(mss, 0)); 814 } 815 mixer_init(d, (mss->bd_id == MD_YM0020)? &yamaha_mixer : &mss_mixer, mss); 816 switch (mss->bd_id) { 817 #if NPNP > 0 818 case MD_OPTI931: 819 bus_setup_intr(dev, mss->irq, INTR_TYPE_TTY, opti931_intr, mss, &ih); 820 break; 821 #endif 822 default: 823 bus_setup_intr(dev, mss->irq, INTR_TYPE_TTY, mss_intr, mss, &ih); 824 } 825 if (mss->pdma == mss->rdma) 826 pcm_setflags(dev, pcm_getflags(dev) | SD_F_SIMPLEX); 827 if (bus_dma_tag_create(/*parent*/NULL, /*alignment*/2, /*boundary*/0, 828 /*lowaddr*/BUS_SPACE_MAXADDR_24BIT, 829 /*highaddr*/BUS_SPACE_MAXADDR, 830 /*filter*/NULL, /*filterarg*/NULL, 831 /*maxsize*/DSP_BUFFSIZE, /*nsegments*/1, 832 /*maxsegz*/0x3ffff, 833 /*flags*/0, &mss->parent_dmat) != 0) { 834 device_printf(dev, "unable to create dma tag\n"); 835 goto no; 836 } 837 snprintf(status, SND_STATUSLEN, "at io 0x%lx irq %ld drq %d", 838 rman_get_start(mss->io_base), rman_get_start(mss->irq), mss->pdma); 839 if (mss->pdma != mss->rdma) snprintf(status + strlen(status), 840 SND_STATUSLEN - strlen(status), ":%d", mss->rdma); 841 842 if (pcm_register(dev, mss, 1, 1)) goto no; 843 pcm_addchan(dev, PCMDIR_REC, &mss_chantemplate, mss); 844 pcm_addchan(dev, PCMDIR_PLAY, &mss_chantemplate, mss); 845 pcm_setstatus(dev, status); 846 847 return 0; 848no: 849 mss_release_resources(mss, dev); 850 return ENXIO; 851} 852 853static int 854mss_attach(device_t dev) 855{ 856 struct mss_info *mss; 857 int flags = device_get_flags(dev); 858 859 mss = (struct mss_info *)malloc(sizeof *mss, M_DEVBUF, M_NOWAIT); 860 if (!mss) return ENXIO; 861 bzero(mss, sizeof *mss); 862 863 mss->io_rid = 0; 864 mss->conf_rid = -1; 865 mss->irq_rid = 0; 866 mss->drq1_rid = 0; 867 mss->drq2_rid = -1; 868 if (flags & DV_F_DUAL_DMA) { 869 bus_set_resource(dev, SYS_RES_DRQ, 1, 870 flags & DV_F_DRQ_MASK, 1); 871 mss->drq2_rid = 1; 872 } 873 mss->bd_id = (device_get_flags(dev) & DV_F_DEV_MASK) >> DV_F_DEV_SHIFT; 874 if (mss->bd_id == MD_YM0020) ymf_test(dev, mss); 875 return mss_doattach(dev, mss); 876} 877 878static device_method_t mss_methods[] = { 879 /* Device interface */ 880 DEVMETHOD(device_probe, mss_probe), 881 DEVMETHOD(device_attach, mss_attach), 882 883 { 0, 0 } 884}; 885 886static driver_t mss_driver = { 887 "pcm", 888 mss_methods, 889 sizeof(snddev_info), 890}; 891 892DRIVER_MODULE(mss, isa, mss_driver, pcm_devclass, 0, 0); 893 894/* 895 * main irq handler for the CS423x. The OPTi931 code is 896 * a separate one. 897 * The correct way to operate for a device with multiple internal 898 * interrupt sources is to loop on the status register and ack 899 * interrupts until all interrupts are served and none are reported. At 900 * this point the IRQ line to the ISA IRQ controller should go low 901 * and be raised at the next interrupt. 902 * 903 * Since the ISA IRQ controller is sent EOI _before_ passing control 904 * to the isr, it might happen that we serve an interrupt early, in 905 * which case the status register at the next interrupt should just 906 * say that there are no more interrupts... 907 */ 908 909static void 910mss_intr(void *arg) 911{ 912 struct mss_info *mss = arg; 913 u_char c = 0, served = 0; 914 int i; 915 916 DEB(printf("mss_intr\n")); 917 ad_read(mss, 11); /* fake read of status bits */ 918 919 /* loop until there are interrupts, but no more than 10 times. */ 920 for (i = 10; i > 0 && io_rd(mss, MSS_STATUS) & 1; i--) { 921 /* get exact reason for full-duplex boards */ 922 c = FULL_DUPLEX(mss)? ad_read(mss, 24) : 0x30; 923 c &= ~served; 924 if (mss->pch.buffer->dl && (c & 0x10)) { 925 served |= 0x10; 926 chn_intr(mss->pch.channel); 927 } 928 if (mss->rch.buffer->dl && (c & 0x20)) { 929 served |= 0x20; 930 chn_intr(mss->rch.channel); 931 } 932 /* now ack the interrupt */ 933 if (FULL_DUPLEX(mss)) ad_write(mss, 24, ~c); /* ack selectively */ 934 else io_wr(mss, MSS_STATUS, 0); /* Clear interrupt status */ 935 } 936 if (i == 10) printf("mss_intr: irq, but not from mss\n"); 937 else if (served == 0) { 938 printf("mss_intr: unexpected irq with reason %x\n", c); 939 /* 940 * this should not happen... I have no idea what to do now. 941 * maybe should do a sanity check and restart dmas ? 942 */ 943 io_wr(mss, MSS_STATUS, 0); /* Clear interrupt status */ 944 } 945} 946 947/* 948 * AD_WAIT_INIT waits if we are initializing the board and 949 * we cannot modify its settings 950 */ 951static int 952ad_wait_init(struct mss_info *mss, int x) 953{ 954 int arg = x, n = 0; /* to shut up the compiler... */ 955 for (; x > 0; x--) 956 if ((n = io_rd(mss, MSS_INDEX)) & MSS_IDXBUSY) DELAY(10); 957 else return n; 958 printf("AD_WAIT_INIT FAILED %d 0x%02x\n", arg, n); 959 return n; 960} 961 962static int 963ad_read(struct mss_info *mss, int reg) 964{ 965 u_long flags; 966 int x; 967 968 flags = spltty(); 969 ad_wait_init(mss, 201); 970 x = io_rd(mss, MSS_INDEX) & ~MSS_IDXMASK; 971 io_wr(mss, MSS_INDEX, (u_char)(reg & MSS_IDXMASK) | x); 972 x = io_rd(mss, MSS_IDATA); 973 splx(flags); 974 /* printf("ad_read %d, %x\n", reg, x); */ 975 return x; 976} 977 978static void 979ad_write(struct mss_info *mss, int reg, u_char data) 980{ 981 u_long flags; 982 983 int x; 984 /* printf("ad_write %d, %x\n", reg, data); */ 985 flags = spltty(); 986 ad_wait_init(mss, 1002); 987 x = io_rd(mss, MSS_INDEX) & ~MSS_IDXMASK; 988 io_wr(mss, MSS_INDEX, (u_char)(reg & MSS_IDXMASK) | x); 989 io_wr(mss, MSS_IDATA, data); 990 splx(flags); 991} 992 993static void 994ad_write_cnt(struct mss_info *mss, int reg, u_short cnt) 995{ 996 ad_write(mss, reg+1, cnt & 0xff); 997 ad_write(mss, reg, cnt >> 8); /* upper base must be last */ 998} 999 1000static void 1001wait_for_calibration(struct mss_info *mss) 1002{ 1003 int n, t; 1004 1005 /* 1006 * Wait until the auto calibration process has finished. 1007 * 1008 * 1) Wait until the chip becomes ready (reads don't return 0x80). 1009 * 2) Wait until the ACI bit of I11 gets on 1010 * 3) Wait until the ACI bit of I11 gets off 1011 */ 1012 1013 n = ad_wait_init(mss, 1000); 1014 if (n & MSS_IDXBUSY) printf("mss: Auto calibration timed out(1).\n"); 1015 1016 for (t = 100; t > 0 && (ad_read(mss, 11) & 0x20) == 0; t--) DELAY(100); 1017 for (t = 100; t > 0 && ad_read(mss, 11) & 0x20; t--) DELAY(100); 1018} 1019 1020static void 1021ad_unmute(struct mss_info *mss) 1022{ 1023 ad_write(mss, 6, ad_read(mss, 6) & ~I6_MUTE); 1024 ad_write(mss, 7, ad_read(mss, 7) & ~I6_MUTE); 1025} 1026 1027static void 1028ad_enter_MCE(struct mss_info *mss) 1029{ 1030 int prev; 1031 1032 mss->bd_flags |= BD_F_MCE_BIT; 1033 ad_wait_init(mss, 203); 1034 prev = io_rd(mss, MSS_INDEX); 1035 prev &= ~MSS_TRD; 1036 io_wr(mss, MSS_INDEX, prev | MSS_MCE); 1037} 1038 1039static void 1040ad_leave_MCE(struct mss_info *mss) 1041{ 1042 u_long flags; 1043 u_char prev; 1044 1045 if ((mss->bd_flags & BD_F_MCE_BIT) == 0) { 1046 printf("--- hey, leave_MCE: MCE bit was not set!\n"); 1047 return; 1048 } 1049 1050 ad_wait_init(mss, 1000); 1051 1052 flags = spltty(); 1053 mss->bd_flags &= ~BD_F_MCE_BIT; 1054 1055 prev = io_rd(mss, MSS_INDEX); 1056 prev &= ~MSS_TRD; 1057 io_wr(mss, MSS_INDEX, prev & ~MSS_MCE); /* Clear the MCE bit */ 1058 wait_for_calibration(mss); 1059 splx(flags); 1060} 1061 1062/* 1063 * only one source can be set... 1064 */ 1065static int 1066mss_set_recsrc(struct mss_info *mss, int mask) 1067{ 1068 u_char recdev; 1069 1070 switch (mask) { 1071 case SOUND_MASK_LINE: 1072 case SOUND_MASK_LINE3: 1073 recdev = 0; 1074 break; 1075 1076 case SOUND_MASK_CD: 1077 case SOUND_MASK_LINE1: 1078 recdev = 0x40; 1079 break; 1080 1081 case SOUND_MASK_IMIX: 1082 recdev = 0xc0; 1083 break; 1084 1085 case SOUND_MASK_MIC: 1086 default: 1087 mask = SOUND_MASK_MIC; 1088 recdev = 0x80; 1089 } 1090 ad_write(mss, 0, (ad_read(mss, 0) & 0x3f) | recdev); 1091 ad_write(mss, 1, (ad_read(mss, 1) & 0x3f) | recdev); 1092 return mask; 1093} 1094 1095/* there are differences in the mixer depending on the actual sound card. */ 1096static int 1097mss_mixer_set(struct mss_info *mss, int dev, int left, int right) 1098{ 1099 int regoffs; 1100 mixer_tab *mix_d = (mss->bd_id == MD_OPTI931)? &opti931_devices : &mix_devices; 1101 u_char old, val; 1102 1103 if ((*mix_d)[dev][LEFT_CHN].nbits == 0) { 1104 DEB(printf("nbits = 0 for dev %d\n", dev)); 1105 return -1; 1106 } 1107 1108 if ((*mix_d)[dev][RIGHT_CHN].nbits == 0) right = left; /* mono */ 1109 1110 /* Set the left channel */ 1111 1112 regoffs = (*mix_d)[dev][LEFT_CHN].regno; 1113 old = val = ad_read(mss, regoffs); 1114 /* if volume is 0, mute chan. Otherwise, unmute. */ 1115 if (regoffs != 0) val = (left == 0)? old | 0x80 : old & 0x7f; 1116 change_bits(mix_d, &val, dev, LEFT_CHN, left); 1117 ad_write(mss, regoffs, val); 1118 1119 DEB(printf("LEFT: dev %d reg %d old 0x%02x new 0x%02x\n", 1120 dev, regoffs, old, val)); 1121 1122 if ((*mix_d)[dev][RIGHT_CHN].nbits != 0) { /* have stereo */ 1123 /* Set the right channel */ 1124 regoffs = (*mix_d)[dev][RIGHT_CHN].regno; 1125 old = val = ad_read(mss, regoffs); 1126 if (regoffs != 1) val = (right == 0)? old | 0x80 : old & 0x7f; 1127 change_bits(mix_d, &val, dev, RIGHT_CHN, right); 1128 ad_write(mss, regoffs, val); 1129 1130 DEB(printf("RIGHT: dev %d reg %d old 0x%02x new 0x%02x\n", 1131 dev, regoffs, old, val)); 1132 } 1133 return 0; /* success */ 1134} 1135 1136static int 1137mss_speed(struct mss_chinfo *ch, int speed) 1138{ 1139 struct mss_info *mss = ch->parent; 1140 /* 1141 * In the CS4231, the low 4 bits of I8 are used to hold the 1142 * sample rate. Only a fixed number of values is allowed. This 1143 * table lists them. The speed-setting routines scans the table 1144 * looking for the closest match. This is the only supported method. 1145 * 1146 * In the CS4236, there is an alternate metod (which we do not 1147 * support yet) which provides almost arbitrary frequency setting. 1148 * In the AD1845, it looks like the sample rate can be 1149 * almost arbitrary, and written directly to a register. 1150 * In the OPTi931, there is a SB command which provides for 1151 * almost arbitrary frequency setting. 1152 * 1153 */ 1154 ad_enter_MCE(mss); 1155 if (mss->bd_id == MD_AD1845) { /* Use alternate speed select regs */ 1156 ad_write(mss, 22, (speed >> 8) & 0xff); /* Speed MSB */ 1157 ad_write(mss, 23, speed & 0xff); /* Speed LSB */ 1158 /* XXX must also do something in I27 for the ad1845 */ 1159 } else { 1160 int i, sel = 0; /* assume entry 0 does not contain -1 */ 1161 static int speeds[] = 1162 {8000, 5512, 16000, 11025, 27429, 18900, 32000, 22050, 1163 -1, 37800, -1, 44100, 48000, 33075, 9600, 6615}; 1164 1165 for (i = 1; i < 16; i++) 1166 if (speeds[i] > 0 && 1167 abs(speed-speeds[i]) < abs(speed-speeds[sel])) sel = i; 1168 speed = speeds[sel]; 1169 ad_write(mss, 8, (ad_read(mss, 8) & 0xf0) | sel); 1170 } 1171 ad_leave_MCE(mss); 1172 1173 return speed; 1174} 1175 1176/* 1177 * mss_format checks that the format is supported (or defaults to AFMT_U8) 1178 * and returns the bit setting for the 1848 register corresponding to 1179 * the desired format. 1180 * 1181 * fixed lr970724 1182 */ 1183 1184static int 1185mss_format(struct mss_chinfo *ch, u_int32_t format) 1186{ 1187 struct mss_info *mss = ch->parent; 1188 int i, arg = format & ~AFMT_STEREO; 1189 1190 /* 1191 * The data format uses 3 bits (just 2 on the 1848). For each 1192 * bit setting, the following array returns the corresponding format. 1193 * The code scans the array looking for a suitable format. In 1194 * case it is not found, default to AFMT_U8 (not such a good 1195 * choice, but let's do it for compatibility...). 1196 */ 1197 1198 static int fmts[] = 1199 {AFMT_U8, AFMT_MU_LAW, AFMT_S16_LE, AFMT_A_LAW, 1200 -1, AFMT_IMA_ADPCM, AFMT_U16_BE, -1}; 1201 1202 for (i = 0; i < 8; i++) if (arg == fmts[i]) break; 1203 arg = i << 1; 1204 if (format & AFMT_STEREO) arg |= 1; 1205 arg <<= 4; 1206 ad_enter_MCE(mss); 1207 ad_write(mss, 8, (ad_read(mss, 8) & 0x0f) | arg); 1208 if (FULL_DUPLEX(mss)) ad_write(mss, 28, arg); /* capture mode */ 1209 ad_leave_MCE(mss); 1210 return format; 1211} 1212 1213static int 1214mss_trigger(struct mss_chinfo *ch, int go) 1215{ 1216 struct mss_info *mss = ch->parent; 1217 u_char m; 1218 int retry, wr, cnt; 1219 1220 wr = (ch->dir == PCMDIR_PLAY)? 1 : 0; 1221 m = ad_read(mss, 9); 1222 switch (go) { 1223 case PCMTRIG_START: 1224 cnt = (ch->buffer->dl / ch->buffer->sample_size) - 1; 1225 1226 DEB(if (m & 4) printf("OUCH! reg 9 0x%02x\n", m);); 1227 m |= wr? I9_PEN : I9_CEN; /* enable DMA */ 1228 ad_write_cnt(mss, (wr || !FULL_DUPLEX(mss))? 14 : 30, cnt); 1229 break; 1230 1231 case PCMTRIG_STOP: 1232 case PCMTRIG_ABORT: /* XXX check this... */ 1233 m &= ~(wr? I9_PEN : I9_CEN); /* Stop DMA */ 1234#if 0 1235 /* 1236 * try to disable DMA by clearing count registers. Not sure it 1237 * is needed, and it might cause false interrupts when the 1238 * DMA is re-enabled later. 1239 */ 1240 ad_write_cnt(mss, (wr || !FULL_DUPLEX(mss))? 14 : 30, 0); 1241#endif 1242 } 1243 /* on the OPTi931 the enable bit seems hard to set... */ 1244 for (retry = 10; retry > 0; retry--) { 1245 ad_write(mss, 9, m); 1246 if (ad_read(mss, 9) == m) break; 1247 } 1248 if (retry == 0) printf("start dma, failed to set bit 0x%02x 0x%02x\n", 1249 m, ad_read(mss, 9)); 1250 return 0; 1251} 1252 1253#if NPNP > 0 1254static int 1255pnpmss_probe(device_t dev) 1256{ 1257 char *s = NULL; 1258 u_int32_t logical_id = isa_get_logicalid(dev); 1259 u_int32_t vend_id = isa_get_vendorid(dev); 1260 u_int32_t id = vend_id & 0xff00ffff; 1261 1262 switch (logical_id) { 1263 case 0x0000630e: /* CSC0000 */ 1264 if (id == 0x3700630e) s = "CS4237"; 1265 else if (id == 0x2500630e) s = "CS4235"; 1266 else if (id == 0x3600630e) s = "CS4236"; 1267 else if (id == 0x3500630e) s = "CS4236B"; 1268 else if (id == 0x3200630e) s = "CS4232"; 1269 else s = "Unknown CS"; 1270 break; 1271 1272 case 0x2100a865: /* YMH0021 */ 1273 if (id == 0x2000a865) s = "Yamaha SA2"; 1274 else if (id == 0x3000a865) s = "Yamaha SA3"; 1275 else if (id == 0x0000a865) s = "Yamaha YMF719 OPL-SA3"; 1276 else s = "Yamaha OPL-SAx"; 1277 break; 1278 1279 case 0x1110d315: /* ENS1011 */ 1280 s = "ENSONIQ SoundscapeVIVO"; 1281 break; 1282 1283 case 0x1093143e: /* OPT9310 */ 1284 s = "OPTi931"; 1285 break; 1286 1287 case 0x5092143e: /* OPT9250 XXX guessing */ 1288 s = "OPTi925"; 1289 break; 1290 1291 case 0x0000561e: 1292 s = "GusPnP"; 1293 break; 1294 1295 case 0x01000000: 1296 if (vend_id == 0x0100a90d) s = "CMI8330"; 1297 break; 1298 } 1299 1300 if (s) { 1301 device_set_desc(dev, s); 1302 return 0; 1303 } 1304 return ENXIO; 1305} 1306 1307static int 1308pnpmss_attach(device_t dev) 1309{ 1310 struct mss_info *mss; 1311 u_int32_t vend_id = isa_get_vendorid(dev); 1312 1313 mss = (struct mss_info *)malloc(sizeof *mss, M_DEVBUF, M_NOWAIT); 1314 if (!mss) return ENXIO; 1315 bzero(mss, sizeof *mss); 1316 1317 mss->io_rid = 0; 1318 mss->conf_rid = -1; 1319 mss->irq_rid = 0; 1320 mss->drq1_rid = 0; 1321 mss->drq2_rid = 1; 1322 1323 switch (vend_id & 0xff00ffff) { 1324 case 0x2000a865: /* Yamaha SA2 */ 1325 case 0x3000a865: /* Yamaha SA3 */ 1326 case 0x0000a865: /* Yamaha YMF719 SA3 */ 1327 case 0x2100a865: /* pnpbios sets vendor=logical */ 1328 mss->io_rid = 1; 1329 mss->conf_rid = 4; 1330 mss->bd_id = MD_YM0020; 1331 break; 1332 1333 case 0x8100d315: /* ENSONIQ SoundscapeVIVO */ 1334 mss->io_rid = 1; 1335 mss->bd_id = MD_VIVO; 1336 break; 1337 1338 case 0x3700630e: /* CS4237 */ 1339 case 0x2500630e: /* AOpen AW37, CS4235 */ 1340 mss->bd_flags |= BD_F_MSS_OFFSET; 1341 mss->bd_id = MD_CS4237; 1342 break; 1343 1344 case 0x3500630e: /* CS4236B */ 1345 case 0x3600630e: /* CS4236 */ 1346 mss->bd_flags |= BD_F_MSS_OFFSET; 1347 mss->bd_id = MD_CS4236; 1348 break; 1349 1350 case 0x3100143e: /* opti931 */ 1351 mss->bd_flags |= BD_F_MSS_OFFSET; 1352 mss->conf_rid = 3; 1353 mss->bd_id = MD_OPTI931; 1354 break; 1355 1356 case 0x2500143e: /* opti925 */ 1357 mss->io_rid = 1; 1358 mss->conf_rid = 3; 1359 mss->bd_id = MD_OPTI925; 1360 break; 1361 1362 case 0x0100561e: /* guspnp */ 1363 mss->bd_flags |= BD_F_MSS_OFFSET; 1364 mss->io_rid = 2; 1365 mss->conf_rid = 1; 1366 mss->drq1_rid = 1; 1367 mss->drq2_rid = 0; 1368 mss->bd_id = MD_GUSPNP; 1369 break; 1370 1371 default: 1372 mss->bd_flags |= BD_F_MSS_OFFSET; 1373 mss->bd_id = MD_CS4232; 1374 break; 1375 } 1376 return mss_doattach(dev, mss); 1377} 1378 1379static device_method_t pnpmss_methods[] = { 1380 /* Device interface */ 1381 DEVMETHOD(device_probe, pnpmss_probe), 1382 DEVMETHOD(device_attach, pnpmss_attach), 1383 1384 { 0, 0 } 1385}; 1386 1387static driver_t pnpmss_driver = { 1388 "pcm", 1389 pnpmss_methods, 1390 sizeof(snddev_info), 1391}; 1392 1393DRIVER_MODULE(pnpmss, isa, pnpmss_driver, pcm_devclass, 0, 0); 1394 1395/* 1396 * the opti931 seems to miss interrupts when working in full 1397 * duplex, so we try some heuristics to catch them. 1398 */ 1399static void 1400opti931_intr(void *arg) 1401{ 1402 struct mss_info *mss = (struct mss_info *)arg; 1403 u_char masked = 0, i11, mc11, c = 0; 1404 u_char reason; /* b0 = playback, b1 = capture, b2 = timer */ 1405 int loops = 10; 1406 1407#if 0 1408 reason = io_rd(mss, MSS_STATUS); 1409 if (!(reason & 1)) {/* no int, maybe a shared line ? */ 1410 printf("intr: flag 0, mcir11 0x%02x\n", ad_read(mss, 11)); 1411 return; 1412 } 1413#endif 1414 i11 = ad_read(mss, 11); /* XXX what's for ? */ 1415 again: 1416 1417 c = mc11 = FULL_DUPLEX(mss)? opti_rd(mss, 11) : 0xc; 1418 mc11 &= 0x0c; 1419 if (c & 0x10) { 1420 DEB(printf("Warning: CD interrupt\n");) 1421 mc11 |= 0x10; 1422 } 1423 if (c & 0x20) { 1424 DEB(printf("Warning: MPU interrupt\n");) 1425 mc11 |= 0x20; 1426 } 1427 if (mc11 & masked) printf("irq reset failed, mc11 0x%02x, 0x%02x\n", 1428 mc11, masked); 1429 masked |= mc11; 1430 /* 1431 * the nice OPTi931 sets the IRQ line before setting the bits in 1432 * mc11. So, on some occasions I have to retry (max 10 times). 1433 */ 1434 if (mc11 == 0) { /* perhaps can return ... */ 1435 reason = io_rd(mss, MSS_STATUS); 1436 if (reason & 1) { 1437 DEB(printf("one more try...\n");) 1438 if (--loops) goto again; 1439 else DDB(printf("intr, but mc11 not set\n");) 1440 } 1441 if (loops == 0) printf("intr, nothing in mcir11 0x%02x\n", mc11); 1442 return; 1443 } 1444 1445 if (mss->rch.buffer->dl && (mc11 & 8)) chn_intr(mss->rch.channel); 1446 if (mss->pch.buffer->dl && (mc11 & 4)) chn_intr(mss->pch.channel); 1447 opti_wr(mss, 11, ~mc11); /* ack */ 1448 if (--loops) goto again; 1449 DEB(printf("xxx too many loops\n");) 1450} 1451 1452#endif /* NPNP > 0 */ 1453 1454static int 1455mssmix_init(snd_mixer *m) 1456{ 1457 struct mss_info *mss = mix_getdevinfo(m); 1458 1459 mix_setdevs(m, MODE2_MIXER_DEVICES); 1460 mix_setrecdevs(m, MSS_REC_DEVICES); 1461 switch(mss->bd_id) { 1462 case MD_OPTI931: 1463 mix_setdevs(m, OPTI931_MIXER_DEVICES); 1464 ad_write(mss, 20, 0x88); 1465 ad_write(mss, 21, 0x88); 1466 break; 1467 1468 case MD_AD1848: 1469 mix_setdevs(m, MODE1_MIXER_DEVICES); 1470 break; 1471 1472 case MD_GUSPNP: 1473 /* this is only necessary in mode 3 ... */ 1474 ad_write(mss, 22, 0x88); 1475 ad_write(mss, 23, 0x88); 1476 break; 1477 } 1478 return 0; 1479} 1480 1481static int 1482mssmix_set(snd_mixer *m, unsigned dev, unsigned left, unsigned right) 1483{ 1484 struct mss_info *mss = mix_getdevinfo(m); 1485 1486 mss_mixer_set(mss, dev, left, right); 1487 1488 return left | (right << 8); 1489} 1490 1491static int 1492mssmix_setrecsrc(snd_mixer *m, u_int32_t src) 1493{ 1494 struct mss_info *mss = mix_getdevinfo(m); 1495 1496 src = mss_set_recsrc(mss, src); 1497 return src; 1498} 1499 1500static int 1501ymmix_init(snd_mixer *m) 1502{ 1503 struct mss_info *mss = mix_getdevinfo(m); 1504 1505 mssmix_init(m); 1506 mix_setdevs(m, mix_getdevs(m) | SOUND_MASK_VOLUME | SOUND_MASK_MIC); 1507 /* Set master volume */ 1508 conf_wr(mss, OPL3SAx_VOLUMEL, 7); 1509 conf_wr(mss, OPL3SAx_VOLUMER, 7); 1510 1511 return 0; 1512} 1513 1514static int 1515ymmix_set(snd_mixer *m, unsigned dev, unsigned left, unsigned right) 1516{ 1517 struct mss_info *mss = mix_getdevinfo(m); 1518 int t; 1519 1520 switch (dev) { 1521 case SOUND_MIXER_VOLUME: 1522 if (left) t = 15 - (left * 15) / 100; 1523 else t = 0x80; /* mute */ 1524 conf_wr(mss, OPL3SAx_VOLUMEL, t); 1525 if (right) t = 15 - (right * 15) / 100; 1526 else t = 0x80; /* mute */ 1527 conf_wr(mss, OPL3SAx_VOLUMER, t); 1528 break; 1529 1530 case SOUND_MIXER_MIC: 1531 t = left; 1532 if (left) t = 31 - (left * 31) / 100; 1533 else t = 0x80; /* mute */ 1534 conf_wr(mss, OPL3SAx_MIC, t); 1535 break; 1536 1537 case SOUND_MIXER_BASS: 1538 case SOUND_MIXER_TREBLE: 1539 /* Later maybe */ 1540 1541 default: 1542 mss_mixer_set(mss, dev, left, right); 1543 } 1544 1545 return left | (right << 8); 1546} 1547 1548static int 1549ymmix_setrecsrc(snd_mixer *m, u_int32_t src) 1550{ 1551 struct mss_info *mss = mix_getdevinfo(m); 1552 src = mss_set_recsrc(mss, src); 1553 return src; 1554} 1555 1556/* channel interface */ 1557static void * 1558msschan_init(void *devinfo, snd_dbuf *b, pcm_channel *c, int dir) 1559{ 1560 struct mss_info *mss = devinfo; 1561 struct mss_chinfo *ch = (dir == PCMDIR_PLAY)? &mss->pch : &mss->rch; 1562 1563 ch->parent = mss; 1564 ch->channel = c; 1565 ch->buffer = b; 1566 ch->buffer->bufsize = DSP_BUFFSIZE; 1567 if (chn_allocbuf(ch->buffer, mss->parent_dmat) == -1) return NULL; 1568 return ch; 1569} 1570 1571static int 1572msschan_setdir(void *data, int dir) 1573{ 1574 struct mss_chinfo *ch = data; 1575 1576 ch->buffer->chan = (dir == PCMDIR_PLAY)? ch->parent->pdma : ch->parent->rdma; 1577 ch->dir = dir; 1578 return 0; 1579} 1580 1581static int 1582msschan_setformat(void *data, u_int32_t format) 1583{ 1584 struct mss_chinfo *ch = data; 1585 1586 mss_format(ch, format); 1587 return 0; 1588} 1589 1590static int 1591msschan_setspeed(void *data, u_int32_t speed) 1592{ 1593 struct mss_chinfo *ch = data; 1594 1595 return mss_speed(ch, speed); 1596} 1597 1598static int 1599msschan_setblocksize(void *data, u_int32_t blocksize) 1600{ 1601 return blocksize; 1602} 1603 1604static int 1605msschan_trigger(void *data, int go) 1606{ 1607 struct mss_chinfo *ch = data; 1608 1609 buf_isadma(ch->buffer, go); 1610 mss_trigger(ch, go); 1611 return 0; 1612} 1613 1614static int 1615msschan_getptr(void *data) 1616{ 1617 struct mss_chinfo *ch = data; 1618 return buf_isadmaptr(ch->buffer); 1619} 1620 1621static pcmchan_caps * 1622msschan_getcaps(void *data) 1623{ 1624 struct mss_chinfo *ch = data; 1625 1626 switch(ch->parent->bd_id) { 1627 case MD_OPTI931: 1628 return &opti931_caps; 1629 break; 1630 1631 case MD_GUSPNP: 1632 return &guspnp_caps; 1633 break; 1634 1635 default: 1636 return &mss_caps; 1637 break; 1638 } 1639} 1640 1641#endif /* NPCM > 0 */ 1642