mss.c revision 139749
1/*- 2 * Copyright (c) 2001 George Reid <greid@ukug.uk.freebsd.org> 3 * Copyright (c) 1999 Cameron Grant <cg@freebsd.org> 4 * Copyright Luigi Rizzo, 1997,1998 5 * Copyright by Hannu Savolainen 1994, 1995 6 * All rights reserved. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 18 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 19 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 20 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 21 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 22 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 23 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 24 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 25 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 26 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 27 * SUCH DAMAGE. 28 */ 29 30#include <dev/sound/pcm/sound.h> 31 32SND_DECLARE_FILE("$FreeBSD: head/sys/dev/sound/isa/mss.c 139749 2005-01-06 01:43:34Z imp $"); 33 34/* board-specific include files */ 35#include <dev/sound/isa/mss.h> 36#include <dev/sound/isa/sb.h> 37#include <dev/sound/chip.h> 38 39#include <isa/isavar.h> 40 41#include "mixer_if.h" 42 43#define MSS_DEFAULT_BUFSZ (4096) 44#define MSS_INDEXED_REGS 0x20 45#define OPL_INDEXED_REGS 0x19 46 47struct mss_info; 48 49struct mss_chinfo { 50 struct mss_info *parent; 51 struct pcm_channel *channel; 52 struct snd_dbuf *buffer; 53 int dir; 54 u_int32_t fmt, blksz; 55}; 56 57struct mss_info { 58 struct resource *io_base; /* primary I/O address for the board */ 59 int io_rid; 60 struct resource *conf_base; /* and the opti931 also has a config space */ 61 int conf_rid; 62 struct resource *irq; 63 int irq_rid; 64 struct resource *drq1; /* play */ 65 int drq1_rid; 66 struct resource *drq2; /* rec */ 67 int drq2_rid; 68 void *ih; 69 bus_dma_tag_t parent_dmat; 70 struct mtx *lock; 71 72 char mss_indexed_regs[MSS_INDEXED_REGS]; 73 char opl_indexed_regs[OPL_INDEXED_REGS]; 74 int bd_id; /* used to hold board-id info, eg. sb version, 75 * mss codec type, etc. etc. 76 */ 77 int opti_offset; /* offset from config_base for opti931 */ 78 u_long bd_flags; /* board-specific flags */ 79 int optibase; /* base address for OPTi9xx config */ 80 struct resource *indir; /* Indirect register index address */ 81 int indir_rid; 82 int password; /* password for opti9xx cards */ 83 int passwdreg; /* password register */ 84 unsigned int bufsize; 85 struct mss_chinfo pch, rch; 86}; 87 88static int mss_probe(device_t dev); 89static int mss_attach(device_t dev); 90 91static driver_intr_t mss_intr; 92 93/* prototypes for local functions */ 94static int mss_detect(device_t dev, struct mss_info *mss); 95static int opti_detect(device_t dev, struct mss_info *mss); 96static char *ymf_test(device_t dev, struct mss_info *mss); 97static void ad_unmute(struct mss_info *mss); 98 99/* mixer set funcs */ 100static int mss_mixer_set(struct mss_info *mss, int dev, int left, int right); 101static int mss_set_recsrc(struct mss_info *mss, int mask); 102 103/* io funcs */ 104static int ad_wait_init(struct mss_info *mss, int x); 105static int ad_read(struct mss_info *mss, int reg); 106static void ad_write(struct mss_info *mss, int reg, u_char data); 107static void ad_write_cnt(struct mss_info *mss, int reg, u_short data); 108static void ad_enter_MCE(struct mss_info *mss); 109static void ad_leave_MCE(struct mss_info *mss); 110 111/* OPTi-specific functions */ 112static void opti_write(struct mss_info *mss, u_char reg, 113 u_char data); 114static u_char opti_read(struct mss_info *mss, u_char reg); 115static int opti_init(device_t dev, struct mss_info *mss); 116 117/* io primitives */ 118static void conf_wr(struct mss_info *mss, u_char reg, u_char data); 119static u_char conf_rd(struct mss_info *mss, u_char reg); 120 121static int pnpmss_probe(device_t dev); 122static int pnpmss_attach(device_t dev); 123 124static driver_intr_t opti931_intr; 125 126static u_int32_t mss_fmt[] = { 127 AFMT_U8, 128 AFMT_STEREO | AFMT_U8, 129 AFMT_S16_LE, 130 AFMT_STEREO | AFMT_S16_LE, 131 AFMT_MU_LAW, 132 AFMT_STEREO | AFMT_MU_LAW, 133 AFMT_A_LAW, 134 AFMT_STEREO | AFMT_A_LAW, 135 0 136}; 137static struct pcmchan_caps mss_caps = {4000, 48000, mss_fmt, 0}; 138 139static u_int32_t guspnp_fmt[] = { 140 AFMT_U8, 141 AFMT_STEREO | AFMT_U8, 142 AFMT_S16_LE, 143 AFMT_STEREO | AFMT_S16_LE, 144 AFMT_A_LAW, 145 AFMT_STEREO | AFMT_A_LAW, 146 0 147}; 148static struct pcmchan_caps guspnp_caps = {4000, 48000, guspnp_fmt, 0}; 149 150static u_int32_t opti931_fmt[] = { 151 AFMT_U8, 152 AFMT_STEREO | AFMT_U8, 153 AFMT_S16_LE, 154 AFMT_STEREO | AFMT_S16_LE, 155 0 156}; 157static struct pcmchan_caps opti931_caps = {4000, 48000, opti931_fmt, 0}; 158 159#define MD_AD1848 0x91 160#define MD_AD1845 0x92 161#define MD_CS42XX 0xA1 162#define MD_CS423X 0xA2 163#define MD_OPTI930 0xB0 164#define MD_OPTI931 0xB1 165#define MD_OPTI925 0xB2 166#define MD_OPTI924 0xB3 167#define MD_GUSPNP 0xB8 168#define MD_GUSMAX 0xB9 169#define MD_YM0020 0xC1 170#define MD_VIVO 0xD1 171 172#define DV_F_TRUE_MSS 0x00010000 /* mss _with_ base regs */ 173 174#define FULL_DUPLEX(x) ((x)->bd_flags & BD_F_DUPLEX) 175 176static void 177mss_lock(struct mss_info *mss) 178{ 179 snd_mtxlock(mss->lock); 180} 181 182static void 183mss_unlock(struct mss_info *mss) 184{ 185 snd_mtxunlock(mss->lock); 186} 187 188static int 189port_rd(struct resource *port, int off) 190{ 191 if (port) 192 return bus_space_read_1(rman_get_bustag(port), 193 rman_get_bushandle(port), 194 off); 195 else 196 return -1; 197} 198 199static void 200port_wr(struct resource *port, int off, u_int8_t data) 201{ 202 if (port) 203 bus_space_write_1(rman_get_bustag(port), 204 rman_get_bushandle(port), 205 off, data); 206} 207 208static int 209io_rd(struct mss_info *mss, int reg) 210{ 211 if (mss->bd_flags & BD_F_MSS_OFFSET) reg -= 4; 212 return port_rd(mss->io_base, reg); 213} 214 215static void 216io_wr(struct mss_info *mss, int reg, u_int8_t data) 217{ 218 if (mss->bd_flags & BD_F_MSS_OFFSET) reg -= 4; 219 port_wr(mss->io_base, reg, data); 220} 221 222static void 223conf_wr(struct mss_info *mss, u_char reg, u_char value) 224{ 225 port_wr(mss->conf_base, 0, reg); 226 port_wr(mss->conf_base, 1, value); 227} 228 229static u_char 230conf_rd(struct mss_info *mss, u_char reg) 231{ 232 port_wr(mss->conf_base, 0, reg); 233 return port_rd(mss->conf_base, 1); 234} 235 236static void 237opti_wr(struct mss_info *mss, u_char reg, u_char value) 238{ 239 port_wr(mss->conf_base, mss->opti_offset + 0, reg); 240 port_wr(mss->conf_base, mss->opti_offset + 1, value); 241} 242 243static u_char 244opti_rd(struct mss_info *mss, u_char reg) 245{ 246 port_wr(mss->conf_base, mss->opti_offset + 0, reg); 247 return port_rd(mss->conf_base, mss->opti_offset + 1); 248} 249 250static void 251gus_wr(struct mss_info *mss, u_char reg, u_char value) 252{ 253 port_wr(mss->conf_base, 3, reg); 254 port_wr(mss->conf_base, 5, value); 255} 256 257static u_char 258gus_rd(struct mss_info *mss, u_char reg) 259{ 260 port_wr(mss->conf_base, 3, reg); 261 return port_rd(mss->conf_base, 5); 262} 263 264static void 265mss_release_resources(struct mss_info *mss, device_t dev) 266{ 267 if (mss->irq) { 268 if (mss->ih) 269 bus_teardown_intr(dev, mss->irq, mss->ih); 270 bus_release_resource(dev, SYS_RES_IRQ, mss->irq_rid, 271 mss->irq); 272 mss->irq = 0; 273 } 274 if (mss->drq2) { 275 if (mss->drq2 != mss->drq1) { 276 isa_dma_release(rman_get_start(mss->drq2)); 277 bus_release_resource(dev, SYS_RES_DRQ, mss->drq2_rid, 278 mss->drq2); 279 } 280 mss->drq2 = 0; 281 } 282 if (mss->drq1) { 283 isa_dma_release(rman_get_start(mss->drq1)); 284 bus_release_resource(dev, SYS_RES_DRQ, mss->drq1_rid, 285 mss->drq1); 286 mss->drq1 = 0; 287 } 288 if (mss->io_base) { 289 bus_release_resource(dev, SYS_RES_IOPORT, mss->io_rid, 290 mss->io_base); 291 mss->io_base = 0; 292 } 293 if (mss->conf_base) { 294 bus_release_resource(dev, SYS_RES_IOPORT, mss->conf_rid, 295 mss->conf_base); 296 mss->conf_base = 0; 297 } 298 if (mss->indir) { 299 bus_release_resource(dev, SYS_RES_IOPORT, mss->indir_rid, 300 mss->indir); 301 mss->indir = 0; 302 } 303 if (mss->parent_dmat) { 304 bus_dma_tag_destroy(mss->parent_dmat); 305 mss->parent_dmat = 0; 306 } 307 if (mss->lock) snd_mtxfree(mss->lock); 308 309 free(mss, M_DEVBUF); 310} 311 312static int 313mss_alloc_resources(struct mss_info *mss, device_t dev) 314{ 315 int pdma, rdma, ok = 1; 316 if (!mss->io_base) 317 mss->io_base = bus_alloc_resource_any(dev, SYS_RES_IOPORT, 318 &mss->io_rid, RF_ACTIVE); 319 if (!mss->irq) 320 mss->irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, 321 &mss->irq_rid, RF_ACTIVE); 322 if (!mss->drq1) 323 mss->drq1 = bus_alloc_resource_any(dev, SYS_RES_DRQ, 324 &mss->drq1_rid, 325 RF_ACTIVE); 326 if (mss->conf_rid >= 0 && !mss->conf_base) 327 mss->conf_base = bus_alloc_resource_any(dev, SYS_RES_IOPORT, 328 &mss->conf_rid, 329 RF_ACTIVE); 330 if (mss->drq2_rid >= 0 && !mss->drq2) 331 mss->drq2 = bus_alloc_resource_any(dev, SYS_RES_DRQ, 332 &mss->drq2_rid, 333 RF_ACTIVE); 334 335 if (!mss->io_base || !mss->drq1 || !mss->irq) ok = 0; 336 if (mss->conf_rid >= 0 && !mss->conf_base) ok = 0; 337 if (mss->drq2_rid >= 0 && !mss->drq2) ok = 0; 338 339 if (ok) { 340 pdma = rman_get_start(mss->drq1); 341 isa_dma_acquire(pdma); 342 isa_dmainit(pdma, mss->bufsize); 343 mss->bd_flags &= ~BD_F_DUPLEX; 344 if (mss->drq2) { 345 rdma = rman_get_start(mss->drq2); 346 isa_dma_acquire(rdma); 347 isa_dmainit(rdma, mss->bufsize); 348 mss->bd_flags |= BD_F_DUPLEX; 349 } else mss->drq2 = mss->drq1; 350 } 351 return ok; 352} 353 354/* 355 * The various mixers use a variety of bitmasks etc. The Voxware 356 * driver had a very nice technique to describe a mixer and interface 357 * to it. A table defines, for each channel, which register, bits, 358 * offset, polarity to use. This procedure creates the new value 359 * using the table and the old value. 360 */ 361 362static void 363change_bits(mixer_tab *t, u_char *regval, int dev, int chn, int newval) 364{ 365 u_char mask; 366 int shift; 367 368 DEB(printf("ch_bits dev %d ch %d val %d old 0x%02x " 369 "r %d p %d bit %d off %d\n", 370 dev, chn, newval, *regval, 371 (*t)[dev][chn].regno, (*t)[dev][chn].polarity, 372 (*t)[dev][chn].nbits, (*t)[dev][chn].bitoffs ) ); 373 374 if ( (*t)[dev][chn].polarity == 1) /* reverse */ 375 newval = 100 - newval ; 376 377 mask = (1 << (*t)[dev][chn].nbits) - 1; 378 newval = (int) ((newval * mask) + 50) / 100; /* Scale it */ 379 shift = (*t)[dev][chn].bitoffs /*- (*t)[dev][LEFT_CHN].nbits + 1*/; 380 381 *regval &= ~(mask << shift); /* Filter out the previous value */ 382 *regval |= (newval & mask) << shift; /* Set the new value */ 383} 384 385/* -------------------------------------------------------------------- */ 386/* only one source can be set... */ 387static int 388mss_set_recsrc(struct mss_info *mss, int mask) 389{ 390 u_char recdev; 391 392 switch (mask) { 393 case SOUND_MASK_LINE: 394 case SOUND_MASK_LINE3: 395 recdev = 0; 396 break; 397 398 case SOUND_MASK_CD: 399 case SOUND_MASK_LINE1: 400 recdev = 0x40; 401 break; 402 403 case SOUND_MASK_IMIX: 404 recdev = 0xc0; 405 break; 406 407 case SOUND_MASK_MIC: 408 default: 409 mask = SOUND_MASK_MIC; 410 recdev = 0x80; 411 } 412 ad_write(mss, 0, (ad_read(mss, 0) & 0x3f) | recdev); 413 ad_write(mss, 1, (ad_read(mss, 1) & 0x3f) | recdev); 414 return mask; 415} 416 417/* there are differences in the mixer depending on the actual sound card. */ 418static int 419mss_mixer_set(struct mss_info *mss, int dev, int left, int right) 420{ 421 int regoffs; 422 mixer_tab *mix_d; 423 u_char old, val; 424 425 switch (mss->bd_id) { 426 case MD_OPTI931: 427 mix_d = &opti931_devices; 428 break; 429 case MD_OPTI930: 430 mix_d = &opti930_devices; 431 break; 432 default: 433 mix_d = &mix_devices; 434 } 435 436 if ((*mix_d)[dev][LEFT_CHN].nbits == 0) { 437 DEB(printf("nbits = 0 for dev %d\n", dev)); 438 return -1; 439 } 440 441 if ((*mix_d)[dev][RIGHT_CHN].nbits == 0) right = left; /* mono */ 442 443 /* Set the left channel */ 444 445 regoffs = (*mix_d)[dev][LEFT_CHN].regno; 446 old = val = ad_read(mss, regoffs); 447 /* if volume is 0, mute chan. Otherwise, unmute. */ 448 if (regoffs != 0) val = (left == 0)? old | 0x80 : old & 0x7f; 449 change_bits(mix_d, &val, dev, LEFT_CHN, left); 450 ad_write(mss, regoffs, val); 451 452 DEB(printf("LEFT: dev %d reg %d old 0x%02x new 0x%02x\n", 453 dev, regoffs, old, val)); 454 455 if ((*mix_d)[dev][RIGHT_CHN].nbits != 0) { /* have stereo */ 456 /* Set the right channel */ 457 regoffs = (*mix_d)[dev][RIGHT_CHN].regno; 458 old = val = ad_read(mss, regoffs); 459 if (regoffs != 1) val = (right == 0)? old | 0x80 : old & 0x7f; 460 change_bits(mix_d, &val, dev, RIGHT_CHN, right); 461 ad_write(mss, regoffs, val); 462 463 DEB(printf("RIGHT: dev %d reg %d old 0x%02x new 0x%02x\n", 464 dev, regoffs, old, val)); 465 } 466 return 0; /* success */ 467} 468 469/* -------------------------------------------------------------------- */ 470 471static int 472mssmix_init(struct snd_mixer *m) 473{ 474 struct mss_info *mss = mix_getdevinfo(m); 475 476 mix_setdevs(m, MODE2_MIXER_DEVICES); 477 mix_setrecdevs(m, MSS_REC_DEVICES); 478 switch(mss->bd_id) { 479 case MD_OPTI930: 480 mix_setdevs(m, OPTI930_MIXER_DEVICES); 481 break; 482 483 case MD_OPTI931: 484 mix_setdevs(m, OPTI931_MIXER_DEVICES); 485 mss_lock(mss); 486 ad_write(mss, 20, 0x88); 487 ad_write(mss, 21, 0x88); 488 mss_unlock(mss); 489 break; 490 491 case MD_AD1848: 492 mix_setdevs(m, MODE1_MIXER_DEVICES); 493 break; 494 495 case MD_GUSPNP: 496 case MD_GUSMAX: 497 /* this is only necessary in mode 3 ... */ 498 mss_lock(mss); 499 ad_write(mss, 22, 0x88); 500 ad_write(mss, 23, 0x88); 501 mss_unlock(mss); 502 break; 503 } 504 return 0; 505} 506 507static int 508mssmix_set(struct snd_mixer *m, unsigned dev, unsigned left, unsigned right) 509{ 510 struct mss_info *mss = mix_getdevinfo(m); 511 512 mss_lock(mss); 513 mss_mixer_set(mss, dev, left, right); 514 mss_unlock(mss); 515 516 return left | (right << 8); 517} 518 519static int 520mssmix_setrecsrc(struct snd_mixer *m, u_int32_t src) 521{ 522 struct mss_info *mss = mix_getdevinfo(m); 523 524 mss_lock(mss); 525 src = mss_set_recsrc(mss, src); 526 mss_unlock(mss); 527 return src; 528} 529 530static kobj_method_t mssmix_mixer_methods[] = { 531 KOBJMETHOD(mixer_init, mssmix_init), 532 KOBJMETHOD(mixer_set, mssmix_set), 533 KOBJMETHOD(mixer_setrecsrc, mssmix_setrecsrc), 534 { 0, 0 } 535}; 536MIXER_DECLARE(mssmix_mixer); 537 538/* -------------------------------------------------------------------- */ 539 540static int 541ymmix_init(struct snd_mixer *m) 542{ 543 struct mss_info *mss = mix_getdevinfo(m); 544 545 mssmix_init(m); 546 mix_setdevs(m, mix_getdevs(m) | SOUND_MASK_VOLUME | SOUND_MASK_MIC 547 | SOUND_MASK_BASS | SOUND_MASK_TREBLE); 548 /* Set master volume */ 549 mss_lock(mss); 550 conf_wr(mss, OPL3SAx_VOLUMEL, 7); 551 conf_wr(mss, OPL3SAx_VOLUMER, 7); 552 mss_unlock(mss); 553 554 return 0; 555} 556 557static int 558ymmix_set(struct snd_mixer *m, unsigned dev, unsigned left, unsigned right) 559{ 560 struct mss_info *mss = mix_getdevinfo(m); 561 int t, l, r; 562 563 mss_lock(mss); 564 switch (dev) { 565 case SOUND_MIXER_VOLUME: 566 if (left) t = 15 - (left * 15) / 100; 567 else t = 0x80; /* mute */ 568 conf_wr(mss, OPL3SAx_VOLUMEL, t); 569 if (right) t = 15 - (right * 15) / 100; 570 else t = 0x80; /* mute */ 571 conf_wr(mss, OPL3SAx_VOLUMER, t); 572 break; 573 574 case SOUND_MIXER_MIC: 575 t = left; 576 if (left) t = 31 - (left * 31) / 100; 577 else t = 0x80; /* mute */ 578 conf_wr(mss, OPL3SAx_MIC, t); 579 break; 580 581 case SOUND_MIXER_BASS: 582 l = (left * 7) / 100; 583 r = (right * 7) / 100; 584 t = (r << 4) | l; 585 conf_wr(mss, OPL3SAx_BASS, t); 586 break; 587 588 case SOUND_MIXER_TREBLE: 589 l = (left * 7) / 100; 590 r = (right * 7) / 100; 591 t = (r << 4) | l; 592 conf_wr(mss, OPL3SAx_TREBLE, t); 593 break; 594 595 default: 596 mss_mixer_set(mss, dev, left, right); 597 } 598 mss_unlock(mss); 599 600 return left | (right << 8); 601} 602 603static int 604ymmix_setrecsrc(struct snd_mixer *m, u_int32_t src) 605{ 606 struct mss_info *mss = mix_getdevinfo(m); 607 mss_lock(mss); 608 src = mss_set_recsrc(mss, src); 609 mss_unlock(mss); 610 return src; 611} 612 613static kobj_method_t ymmix_mixer_methods[] = { 614 KOBJMETHOD(mixer_init, ymmix_init), 615 KOBJMETHOD(mixer_set, ymmix_set), 616 KOBJMETHOD(mixer_setrecsrc, ymmix_setrecsrc), 617 { 0, 0 } 618}; 619MIXER_DECLARE(ymmix_mixer); 620 621/* -------------------------------------------------------------------- */ 622/* 623 * XXX This might be better off in the gusc driver. 624 */ 625static void 626gusmax_setup(struct mss_info *mss, device_t dev, struct resource *alt) 627{ 628 static const unsigned char irq_bits[16] = { 629 0, 0, 0, 3, 0, 2, 0, 4, 0, 1, 0, 5, 6, 0, 0, 7 630 }; 631 static const unsigned char dma_bits[8] = { 632 0, 1, 0, 2, 0, 3, 4, 5 633 }; 634 device_t parent = device_get_parent(dev); 635 unsigned char irqctl, dmactl; 636 int s; 637 638 s = splhigh(); 639 640 port_wr(alt, 0x0f, 0x05); 641 port_wr(alt, 0x00, 0x0c); 642 port_wr(alt, 0x0b, 0x00); 643 644 port_wr(alt, 0x0f, 0x00); 645 646 irqctl = irq_bits[isa_get_irq(parent)]; 647 /* Share the IRQ with the MIDI driver. */ 648 irqctl |= 0x40; 649 dmactl = dma_bits[isa_get_drq(parent)]; 650 if (device_get_flags(parent) & DV_F_DUAL_DMA) 651 dmactl |= dma_bits[device_get_flags(parent) & DV_F_DRQ_MASK] 652 << 3; 653 654 /* 655 * Set the DMA and IRQ control latches. 656 */ 657 port_wr(alt, 0x00, 0x0c); 658 port_wr(alt, 0x0b, dmactl | 0x80); 659 port_wr(alt, 0x00, 0x4c); 660 port_wr(alt, 0x0b, irqctl); 661 662 port_wr(alt, 0x00, 0x0c); 663 port_wr(alt, 0x0b, dmactl); 664 port_wr(alt, 0x00, 0x4c); 665 port_wr(alt, 0x0b, irqctl); 666 667 port_wr(mss->conf_base, 2, 0); 668 port_wr(alt, 0x00, 0x0c); 669 port_wr(mss->conf_base, 2, 0); 670 671 splx(s); 672} 673 674static int 675mss_init(struct mss_info *mss, device_t dev) 676{ 677 u_char r6, r9; 678 struct resource *alt; 679 int rid, tmp; 680 681 mss->bd_flags |= BD_F_MCE_BIT; 682 switch(mss->bd_id) { 683 case MD_OPTI931: 684 /* 685 * The MED3931 v.1.0 allocates 3 bytes for the config 686 * space, whereas v.2.0 allocates 4 bytes. What I know 687 * for sure is that the upper two ports must be used, 688 * and they should end on a boundary of 4 bytes. So I 689 * need the following trick. 690 */ 691 mss->opti_offset = 692 (rman_get_start(mss->conf_base) & ~3) + 2 693 - rman_get_start(mss->conf_base); 694 BVDDB(printf("mss_init: opti_offset=%d\n", mss->opti_offset)); 695 opti_wr(mss, 4, 0xd6); /* fifo empty, OPL3, audio enable, SB3.2 */ 696 ad_write(mss, 10, 2); /* enable interrupts */ 697 opti_wr(mss, 6, 2); /* MCIR6: mss enable, sb disable */ 698 opti_wr(mss, 5, 0x28); /* MCIR5: codec in exp. mode,fifo */ 699 break; 700 701 case MD_GUSPNP: 702 case MD_GUSMAX: 703 gus_wr(mss, 0x4c /* _URSTI */, 0);/* Pull reset */ 704 DELAY(1000 * 30); 705 /* release reset and enable DAC */ 706 gus_wr(mss, 0x4c /* _URSTI */, 3); 707 DELAY(1000 * 30); 708 /* end of reset */ 709 710 rid = 0; 711 alt = bus_alloc_resource_any(dev, SYS_RES_IOPORT, &rid, 712 RF_ACTIVE); 713 if (alt == NULL) { 714 printf("XXX couldn't init GUS PnP/MAX\n"); 715 break; 716 } 717 port_wr(alt, 0, 0xC); /* enable int and dma */ 718 if (mss->bd_id == MD_GUSMAX) 719 gusmax_setup(mss, dev, alt); 720 bus_release_resource(dev, SYS_RES_IOPORT, rid, alt); 721 722 /* 723 * unmute left & right line. Need to go in mode3, unmute, 724 * and back to mode 2 725 */ 726 tmp = ad_read(mss, 0x0c); 727 ad_write(mss, 0x0c, 0x6c); /* special value to enter mode 3 */ 728 ad_write(mss, 0x19, 0); /* unmute left */ 729 ad_write(mss, 0x1b, 0); /* unmute right */ 730 ad_write(mss, 0x0c, tmp); /* restore old mode */ 731 732 /* send codec interrupts on irq1 and only use that one */ 733 gus_wr(mss, 0x5a, 0x4f); 734 735 /* enable access to hidden regs */ 736 tmp = gus_rd(mss, 0x5b /* IVERI */); 737 gus_wr(mss, 0x5b, tmp | 1); 738 BVDDB(printf("GUS: silicon rev %c\n", 'A' + ((tmp & 0xf) >> 4))); 739 break; 740 741 case MD_YM0020: 742 conf_wr(mss, OPL3SAx_DMACONF, 0xa9); /* dma-b rec, dma-a play */ 743 r6 = conf_rd(mss, OPL3SAx_DMACONF); 744 r9 = conf_rd(mss, OPL3SAx_MISC); /* version */ 745 BVDDB(printf("Yamaha: ver 0x%x DMA config 0x%x\n", r6, r9);) 746 /* yamaha - set volume to max */ 747 conf_wr(mss, OPL3SAx_VOLUMEL, 0); 748 conf_wr(mss, OPL3SAx_VOLUMER, 0); 749 conf_wr(mss, OPL3SAx_DMACONF, FULL_DUPLEX(mss)? 0xa9 : 0x8b); 750 break; 751 } 752 if (FULL_DUPLEX(mss) && mss->bd_id != MD_OPTI931) 753 ad_write(mss, 12, ad_read(mss, 12) | 0x40); /* mode 2 */ 754 ad_enter_MCE(mss); 755 ad_write(mss, 9, FULL_DUPLEX(mss)? 0 : 4); 756 ad_leave_MCE(mss); 757 ad_write(mss, 10, 2); /* int enable */ 758 io_wr(mss, MSS_STATUS, 0); /* Clear interrupt status */ 759 /* the following seem required on the CS4232 */ 760 ad_unmute(mss); 761 return 0; 762} 763 764 765/* 766 * main irq handler for the CS423x. The OPTi931 code is 767 * a separate one. 768 * The correct way to operate for a device with multiple internal 769 * interrupt sources is to loop on the status register and ack 770 * interrupts until all interrupts are served and none are reported. At 771 * this point the IRQ line to the ISA IRQ controller should go low 772 * and be raised at the next interrupt. 773 * 774 * Since the ISA IRQ controller is sent EOI _before_ passing control 775 * to the isr, it might happen that we serve an interrupt early, in 776 * which case the status register at the next interrupt should just 777 * say that there are no more interrupts... 778 */ 779 780static void 781mss_intr(void *arg) 782{ 783 struct mss_info *mss = arg; 784 u_char c = 0, served = 0; 785 int i; 786 787 DEB(printf("mss_intr\n")); 788 mss_lock(mss); 789 ad_read(mss, 11); /* fake read of status bits */ 790 791 /* loop until there are interrupts, but no more than 10 times. */ 792 for (i = 10; i > 0 && io_rd(mss, MSS_STATUS) & 1; i--) { 793 /* get exact reason for full-duplex boards */ 794 c = FULL_DUPLEX(mss)? ad_read(mss, 24) : 0x30; 795 c &= ~served; 796 if (sndbuf_runsz(mss->pch.buffer) && (c & 0x10)) { 797 served |= 0x10; 798 chn_intr(mss->pch.channel); 799 } 800 if (sndbuf_runsz(mss->rch.buffer) && (c & 0x20)) { 801 served |= 0x20; 802 chn_intr(mss->rch.channel); 803 } 804 /* now ack the interrupt */ 805 if (FULL_DUPLEX(mss)) ad_write(mss, 24, ~c); /* ack selectively */ 806 else io_wr(mss, MSS_STATUS, 0); /* Clear interrupt status */ 807 } 808 if (i == 10) { 809 BVDDB(printf("mss_intr: irq, but not from mss\n")); 810 } else if (served == 0) { 811 BVDDB(printf("mss_intr: unexpected irq with reason %x\n", c)); 812 /* 813 * this should not happen... I have no idea what to do now. 814 * maybe should do a sanity check and restart dmas ? 815 */ 816 io_wr(mss, MSS_STATUS, 0); /* Clear interrupt status */ 817 } 818 mss_unlock(mss); 819} 820 821/* 822 * AD_WAIT_INIT waits if we are initializing the board and 823 * we cannot modify its settings 824 */ 825static int 826ad_wait_init(struct mss_info *mss, int x) 827{ 828 int arg = x, n = 0; /* to shut up the compiler... */ 829 for (; x > 0; x--) 830 if ((n = io_rd(mss, MSS_INDEX)) & MSS_IDXBUSY) DELAY(10); 831 else return n; 832 printf("AD_WAIT_INIT FAILED %d 0x%02x\n", arg, n); 833 return n; 834} 835 836static int 837ad_read(struct mss_info *mss, int reg) 838{ 839 int x; 840 841 ad_wait_init(mss, 201000); 842 x = io_rd(mss, MSS_INDEX) & ~MSS_IDXMASK; 843 io_wr(mss, MSS_INDEX, (u_char)(reg & MSS_IDXMASK) | x); 844 x = io_rd(mss, MSS_IDATA); 845 /* printf("ad_read %d, %x\n", reg, x); */ 846 return x; 847} 848 849static void 850ad_write(struct mss_info *mss, int reg, u_char data) 851{ 852 int x; 853 854 /* printf("ad_write %d, %x\n", reg, data); */ 855 ad_wait_init(mss, 1002000); 856 x = io_rd(mss, MSS_INDEX) & ~MSS_IDXMASK; 857 io_wr(mss, MSS_INDEX, (u_char)(reg & MSS_IDXMASK) | x); 858 io_wr(mss, MSS_IDATA, data); 859} 860 861static void 862ad_write_cnt(struct mss_info *mss, int reg, u_short cnt) 863{ 864 ad_write(mss, reg+1, cnt & 0xff); 865 ad_write(mss, reg, cnt >> 8); /* upper base must be last */ 866} 867 868static void 869wait_for_calibration(struct mss_info *mss) 870{ 871 int t; 872 873 /* 874 * Wait until the auto calibration process has finished. 875 * 876 * 1) Wait until the chip becomes ready (reads don't return 0x80). 877 * 2) Wait until the ACI bit of I11 gets on 878 * 3) Wait until the ACI bit of I11 gets off 879 */ 880 881 t = ad_wait_init(mss, 1000000); 882 if (t & MSS_IDXBUSY) printf("mss: Auto calibration timed out(1).\n"); 883 884 /* 885 * The calibration mode for chips that support it is set so that 886 * we never see ACI go on. 887 */ 888 if (mss->bd_id == MD_GUSMAX || mss->bd_id == MD_GUSPNP) { 889 for (t = 100; t > 0 && (ad_read(mss, 11) & 0x20) == 0; t--); 890 } else { 891 /* 892 * XXX This should only be enabled for cards that *really* 893 * need it. Are there any? 894 */ 895 for (t = 100; t > 0 && (ad_read(mss, 11) & 0x20) == 0; t--) DELAY(100); 896 } 897 for (t = 100; t > 0 && ad_read(mss, 11) & 0x20; t--) DELAY(100); 898} 899 900static void 901ad_unmute(struct mss_info *mss) 902{ 903 ad_write(mss, 6, ad_read(mss, 6) & ~I6_MUTE); 904 ad_write(mss, 7, ad_read(mss, 7) & ~I6_MUTE); 905} 906 907static void 908ad_enter_MCE(struct mss_info *mss) 909{ 910 int prev; 911 912 mss->bd_flags |= BD_F_MCE_BIT; 913 ad_wait_init(mss, 203000); 914 prev = io_rd(mss, MSS_INDEX); 915 prev &= ~MSS_TRD; 916 io_wr(mss, MSS_INDEX, prev | MSS_MCE); 917} 918 919static void 920ad_leave_MCE(struct mss_info *mss) 921{ 922 u_char prev; 923 924 if ((mss->bd_flags & BD_F_MCE_BIT) == 0) { 925 DEB(printf("--- hey, leave_MCE: MCE bit was not set!\n")); 926 return; 927 } 928 929 ad_wait_init(mss, 1000000); 930 931 mss->bd_flags &= ~BD_F_MCE_BIT; 932 933 prev = io_rd(mss, MSS_INDEX); 934 prev &= ~MSS_TRD; 935 io_wr(mss, MSS_INDEX, prev & ~MSS_MCE); /* Clear the MCE bit */ 936 wait_for_calibration(mss); 937} 938 939static int 940mss_speed(struct mss_chinfo *ch, int speed) 941{ 942 struct mss_info *mss = ch->parent; 943 /* 944 * In the CS4231, the low 4 bits of I8 are used to hold the 945 * sample rate. Only a fixed number of values is allowed. This 946 * table lists them. The speed-setting routines scans the table 947 * looking for the closest match. This is the only supported method. 948 * 949 * In the CS4236, there is an alternate metod (which we do not 950 * support yet) which provides almost arbitrary frequency setting. 951 * In the AD1845, it looks like the sample rate can be 952 * almost arbitrary, and written directly to a register. 953 * In the OPTi931, there is a SB command which provides for 954 * almost arbitrary frequency setting. 955 * 956 */ 957 ad_enter_MCE(mss); 958 if (mss->bd_id == MD_AD1845) { /* Use alternate speed select regs */ 959 ad_write(mss, 22, (speed >> 8) & 0xff); /* Speed MSB */ 960 ad_write(mss, 23, speed & 0xff); /* Speed LSB */ 961 /* XXX must also do something in I27 for the ad1845 */ 962 } else { 963 int i, sel = 0; /* assume entry 0 does not contain -1 */ 964 static int speeds[] = 965 {8000, 5512, 16000, 11025, 27429, 18900, 32000, 22050, 966 -1, 37800, -1, 44100, 48000, 33075, 9600, 6615}; 967 968 for (i = 1; i < 16; i++) 969 if (speeds[i] > 0 && 970 abs(speed-speeds[i]) < abs(speed-speeds[sel])) sel = i; 971 speed = speeds[sel]; 972 ad_write(mss, 8, (ad_read(mss, 8) & 0xf0) | sel); 973 } 974 ad_leave_MCE(mss); 975 976 return speed; 977} 978 979/* 980 * mss_format checks that the format is supported (or defaults to AFMT_U8) 981 * and returns the bit setting for the 1848 register corresponding to 982 * the desired format. 983 * 984 * fixed lr970724 985 */ 986 987static int 988mss_format(struct mss_chinfo *ch, u_int32_t format) 989{ 990 struct mss_info *mss = ch->parent; 991 int i, arg = format & ~AFMT_STEREO; 992 993 /* 994 * The data format uses 3 bits (just 2 on the 1848). For each 995 * bit setting, the following array returns the corresponding format. 996 * The code scans the array looking for a suitable format. In 997 * case it is not found, default to AFMT_U8 (not such a good 998 * choice, but let's do it for compatibility...). 999 */ 1000 1001 static int fmts[] = 1002 {AFMT_U8, AFMT_MU_LAW, AFMT_S16_LE, AFMT_A_LAW, 1003 -1, AFMT_IMA_ADPCM, AFMT_U16_BE, -1}; 1004 1005 ch->fmt = format; 1006 for (i = 0; i < 8; i++) if (arg == fmts[i]) break; 1007 arg = i << 1; 1008 if (format & AFMT_STEREO) arg |= 1; 1009 arg <<= 4; 1010 ad_enter_MCE(mss); 1011 ad_write(mss, 8, (ad_read(mss, 8) & 0x0f) | arg); 1012 if (FULL_DUPLEX(mss)) ad_write(mss, 28, arg); /* capture mode */ 1013 ad_leave_MCE(mss); 1014 return format; 1015} 1016 1017static int 1018mss_trigger(struct mss_chinfo *ch, int go) 1019{ 1020 struct mss_info *mss = ch->parent; 1021 u_char m; 1022 int retry, wr, cnt, ss; 1023 1024 ss = 1; 1025 ss <<= (ch->fmt & AFMT_STEREO)? 1 : 0; 1026 ss <<= (ch->fmt & AFMT_16BIT)? 1 : 0; 1027 1028 wr = (ch->dir == PCMDIR_PLAY)? 1 : 0; 1029 m = ad_read(mss, 9); 1030 switch (go) { 1031 case PCMTRIG_START: 1032 cnt = (ch->blksz / ss) - 1; 1033 1034 DEB(if (m & 4) printf("OUCH! reg 9 0x%02x\n", m);); 1035 m |= wr? I9_PEN : I9_CEN; /* enable DMA */ 1036 ad_write_cnt(mss, (wr || !FULL_DUPLEX(mss))? 14 : 30, cnt); 1037 break; 1038 1039 case PCMTRIG_STOP: 1040 case PCMTRIG_ABORT: /* XXX check this... */ 1041 m &= ~(wr? I9_PEN : I9_CEN); /* Stop DMA */ 1042#if 0 1043 /* 1044 * try to disable DMA by clearing count registers. Not sure it 1045 * is needed, and it might cause false interrupts when the 1046 * DMA is re-enabled later. 1047 */ 1048 ad_write_cnt(mss, (wr || !FULL_DUPLEX(mss))? 14 : 30, 0); 1049#endif 1050 } 1051 /* on the OPTi931 the enable bit seems hard to set... */ 1052 for (retry = 10; retry > 0; retry--) { 1053 ad_write(mss, 9, m); 1054 if (ad_read(mss, 9) == m) break; 1055 } 1056 if (retry == 0) BVDDB(printf("stop dma, failed to set bit 0x%02x 0x%02x\n", \ 1057 m, ad_read(mss, 9))); 1058 return 0; 1059} 1060 1061 1062/* 1063 * the opti931 seems to miss interrupts when working in full 1064 * duplex, so we try some heuristics to catch them. 1065 */ 1066static void 1067opti931_intr(void *arg) 1068{ 1069 struct mss_info *mss = (struct mss_info *)arg; 1070 u_char masked = 0, i11, mc11, c = 0; 1071 u_char reason; /* b0 = playback, b1 = capture, b2 = timer */ 1072 int loops = 10; 1073 1074#if 0 1075 reason = io_rd(mss, MSS_STATUS); 1076 if (!(reason & 1)) {/* no int, maybe a shared line ? */ 1077 DEB(printf("intr: flag 0, mcir11 0x%02x\n", ad_read(mss, 11))); 1078 return; 1079 } 1080#endif 1081 mss_lock(mss); 1082 i11 = ad_read(mss, 11); /* XXX what's for ? */ 1083 again: 1084 1085 c = mc11 = FULL_DUPLEX(mss)? opti_rd(mss, 11) : 0xc; 1086 mc11 &= 0x0c; 1087 if (c & 0x10) { 1088 DEB(printf("Warning: CD interrupt\n");) 1089 mc11 |= 0x10; 1090 } 1091 if (c & 0x20) { 1092 DEB(printf("Warning: MPU interrupt\n");) 1093 mc11 |= 0x20; 1094 } 1095 if (mc11 & masked) BVDDB(printf("irq reset failed, mc11 0x%02x, 0x%02x\n",\ 1096 mc11, masked)); 1097 masked |= mc11; 1098 /* 1099 * the nice OPTi931 sets the IRQ line before setting the bits in 1100 * mc11. So, on some occasions I have to retry (max 10 times). 1101 */ 1102 if (mc11 == 0) { /* perhaps can return ... */ 1103 reason = io_rd(mss, MSS_STATUS); 1104 if (reason & 1) { 1105 DEB(printf("one more try...\n");) 1106 if (--loops) goto again; 1107 else BVDDB(printf("intr, but mc11 not set\n");) 1108 } 1109 if (loops == 0) BVDDB(printf("intr, nothing in mcir11 0x%02x\n", mc11)); 1110 mss_unlock(mss); 1111 return; 1112 } 1113 1114 if (sndbuf_runsz(mss->rch.buffer) && (mc11 & 8)) chn_intr(mss->rch.channel); 1115 if (sndbuf_runsz(mss->pch.buffer) && (mc11 & 4)) chn_intr(mss->pch.channel); 1116 opti_wr(mss, 11, ~mc11); /* ack */ 1117 if (--loops) goto again; 1118 mss_unlock(mss); 1119 DEB(printf("xxx too many loops\n");) 1120} 1121 1122/* -------------------------------------------------------------------- */ 1123/* channel interface */ 1124static void * 1125msschan_init(kobj_t obj, void *devinfo, struct snd_dbuf *b, struct pcm_channel *c, int dir) 1126{ 1127 struct mss_info *mss = devinfo; 1128 struct mss_chinfo *ch = (dir == PCMDIR_PLAY)? &mss->pch : &mss->rch; 1129 1130 ch->parent = mss; 1131 ch->channel = c; 1132 ch->buffer = b; 1133 ch->dir = dir; 1134 if (sndbuf_alloc(ch->buffer, mss->parent_dmat, mss->bufsize) != 0) 1135 return NULL; 1136 sndbuf_dmasetup(ch->buffer, (dir == PCMDIR_PLAY)? mss->drq1 : mss->drq2); 1137 return ch; 1138} 1139 1140static int 1141msschan_setformat(kobj_t obj, void *data, u_int32_t format) 1142{ 1143 struct mss_chinfo *ch = data; 1144 struct mss_info *mss = ch->parent; 1145 1146 mss_lock(mss); 1147 mss_format(ch, format); 1148 mss_unlock(mss); 1149 return 0; 1150} 1151 1152static int 1153msschan_setspeed(kobj_t obj, void *data, u_int32_t speed) 1154{ 1155 struct mss_chinfo *ch = data; 1156 struct mss_info *mss = ch->parent; 1157 int r; 1158 1159 mss_lock(mss); 1160 r = mss_speed(ch, speed); 1161 mss_unlock(mss); 1162 1163 return r; 1164} 1165 1166static int 1167msschan_setblocksize(kobj_t obj, void *data, u_int32_t blocksize) 1168{ 1169 struct mss_chinfo *ch = data; 1170 1171 ch->blksz = blocksize; 1172 sndbuf_resize(ch->buffer, 2, ch->blksz); 1173 1174 return ch->blksz; 1175} 1176 1177static int 1178msschan_trigger(kobj_t obj, void *data, int go) 1179{ 1180 struct mss_chinfo *ch = data; 1181 struct mss_info *mss = ch->parent; 1182 1183 if (go == PCMTRIG_EMLDMAWR || go == PCMTRIG_EMLDMARD) 1184 return 0; 1185 1186 sndbuf_dma(ch->buffer, go); 1187 mss_lock(mss); 1188 mss_trigger(ch, go); 1189 mss_unlock(mss); 1190 return 0; 1191} 1192 1193static int 1194msschan_getptr(kobj_t obj, void *data) 1195{ 1196 struct mss_chinfo *ch = data; 1197 return sndbuf_dmaptr(ch->buffer); 1198} 1199 1200static struct pcmchan_caps * 1201msschan_getcaps(kobj_t obj, void *data) 1202{ 1203 struct mss_chinfo *ch = data; 1204 1205 switch(ch->parent->bd_id) { 1206 case MD_OPTI931: 1207 return &opti931_caps; 1208 break; 1209 1210 case MD_GUSPNP: 1211 case MD_GUSMAX: 1212 return &guspnp_caps; 1213 break; 1214 1215 default: 1216 return &mss_caps; 1217 break; 1218 } 1219} 1220 1221static kobj_method_t msschan_methods[] = { 1222 KOBJMETHOD(channel_init, msschan_init), 1223 KOBJMETHOD(channel_setformat, msschan_setformat), 1224 KOBJMETHOD(channel_setspeed, msschan_setspeed), 1225 KOBJMETHOD(channel_setblocksize, msschan_setblocksize), 1226 KOBJMETHOD(channel_trigger, msschan_trigger), 1227 KOBJMETHOD(channel_getptr, msschan_getptr), 1228 KOBJMETHOD(channel_getcaps, msschan_getcaps), 1229 { 0, 0 } 1230}; 1231CHANNEL_DECLARE(msschan); 1232 1233/* -------------------------------------------------------------------- */ 1234 1235/* 1236 * mss_probe() is the probe routine. Note, it is not necessary to 1237 * go through this for PnP devices, since they are already 1238 * indentified precisely using their PnP id. 1239 * 1240 * The base address supplied in the device refers to the old MSS 1241 * specs where the four 4 registers in io space contain configuration 1242 * information. Some boards (as an example, early MSS boards) 1243 * has such a block of registers, whereas others (generally CS42xx) 1244 * do not. In order to distinguish between the two and do not have 1245 * to supply two separate probe routines, the flags entry in isa_device 1246 * has a bit to mark this. 1247 * 1248 */ 1249 1250static int 1251mss_probe(device_t dev) 1252{ 1253 u_char tmp, tmpx; 1254 int flags, irq, drq, result = ENXIO, setres = 0; 1255 struct mss_info *mss; 1256 1257 if (isa_get_logicalid(dev)) return ENXIO; /* not yet */ 1258 1259 mss = (struct mss_info *)malloc(sizeof *mss, M_DEVBUF, M_NOWAIT | M_ZERO); 1260 if (!mss) return ENXIO; 1261 1262 mss->io_rid = 0; 1263 mss->conf_rid = -1; 1264 mss->irq_rid = 0; 1265 mss->drq1_rid = 0; 1266 mss->drq2_rid = -1; 1267 mss->io_base = bus_alloc_resource(dev, SYS_RES_IOPORT, &mss->io_rid, 1268 0, ~0, 8, RF_ACTIVE); 1269 if (!mss->io_base) { 1270 BVDDB(printf("mss_probe: no address given, try 0x%x\n", 0x530)); 1271 mss->io_rid = 0; 1272 /* XXX verify this */ 1273 setres = 1; 1274 bus_set_resource(dev, SYS_RES_IOPORT, mss->io_rid, 1275 0x530, 8); 1276 mss->io_base = bus_alloc_resource(dev, SYS_RES_IOPORT, &mss->io_rid, 1277 0, ~0, 8, RF_ACTIVE); 1278 } 1279 if (!mss->io_base) goto no; 1280 1281 /* got irq/dma regs? */ 1282 flags = device_get_flags(dev); 1283 irq = isa_get_irq(dev); 1284 drq = isa_get_drq(dev); 1285 1286 if (!(device_get_flags(dev) & DV_F_TRUE_MSS)) goto mss_probe_end; 1287 1288 /* 1289 * Check if the IO port returns valid signature. The original MS 1290 * Sound system returns 0x04 while some cards 1291 * (AudioTriX Pro for example) return 0x00 or 0x0f. 1292 */ 1293 1294 device_set_desc(dev, "MSS"); 1295 tmpx = tmp = io_rd(mss, 3); 1296 if (tmp == 0xff) { /* Bus float */ 1297 BVDDB(printf("I/O addr inactive (%x), try pseudo_mss\n", tmp)); 1298 device_set_flags(dev, flags & ~DV_F_TRUE_MSS); 1299 goto mss_probe_end; 1300 } 1301 tmp &= 0x3f; 1302 if (!(tmp == 0x04 || tmp == 0x0f || tmp == 0x00)) { 1303 BVDDB(printf("No MSS signature detected on port 0x%lx (0x%x)\n", 1304 rman_get_start(mss->io_base), tmpx)); 1305 goto no; 1306 } 1307#ifdef PC98 1308 if (irq > 12) { 1309#else 1310 if (irq > 11) { 1311#endif 1312 printf("MSS: Bad IRQ %d\n", irq); 1313 goto no; 1314 } 1315 if (!(drq == 0 || drq == 1 || drq == 3)) { 1316 printf("MSS: Bad DMA %d\n", drq); 1317 goto no; 1318 } 1319 if (tmpx & 0x80) { 1320 /* 8-bit board: only drq1/3 and irq7/9 */ 1321 if (drq == 0) { 1322 printf("MSS: Can't use DMA0 with a 8 bit card/slot\n"); 1323 goto no; 1324 } 1325 if (!(irq == 7 || irq == 9)) { 1326 printf("MSS: Can't use IRQ%d with a 8 bit card/slot\n", 1327 irq); 1328 goto no; 1329 } 1330 } 1331 mss_probe_end: 1332 result = mss_detect(dev, mss); 1333 no: 1334 mss_release_resources(mss, dev); 1335#if 0 1336 if (setres) ISA_DELETE_RESOURCE(device_get_parent(dev), dev, 1337 SYS_RES_IOPORT, mss->io_rid); /* XXX ? */ 1338#endif 1339 return result; 1340} 1341 1342static int 1343mss_detect(device_t dev, struct mss_info *mss) 1344{ 1345 int i; 1346 u_char tmp = 0, tmp1, tmp2; 1347 char *name, *yamaha; 1348 1349 if (mss->bd_id != 0) { 1350 device_printf(dev, "presel bd_id 0x%04x -- %s\n", mss->bd_id, 1351 device_get_desc(dev)); 1352 return 0; 1353 } 1354 1355 name = "AD1848"; 1356 mss->bd_id = MD_AD1848; /* AD1848 or CS4248 */ 1357 1358 if (opti_detect(dev, mss)) { 1359 switch (mss->bd_id) { 1360 case MD_OPTI924: 1361 name = "OPTi924"; 1362 break; 1363 case MD_OPTI930: 1364 name = "OPTi930"; 1365 break; 1366 } 1367 printf("Found OPTi device %s\n", name); 1368 if (opti_init(dev, mss) == 0) goto gotit; 1369 } 1370 1371 /* 1372 * Check that the I/O address is in use. 1373 * 1374 * bit 7 of the base I/O port is known to be 0 after the chip has 1375 * performed its power on initialization. Just assume this has 1376 * happened before the OS is starting. 1377 * 1378 * If the I/O address is unused, it typically returns 0xff. 1379 */ 1380 1381 for (i = 0; i < 10; i++) 1382 if ((tmp = io_rd(mss, MSS_INDEX)) & MSS_IDXBUSY) DELAY(10000); 1383 else break; 1384 1385 if (i >= 10) { /* Not an AD1848 */ 1386 BVDDB(printf("mss_detect, busy still set (0x%02x)\n", tmp)); 1387 goto no; 1388 } 1389 /* 1390 * Test if it's possible to change contents of the indirect 1391 * registers. Registers 0 and 1 are ADC volume registers. The bit 1392 * 0x10 is read only so try to avoid using it. 1393 */ 1394 1395 ad_write(mss, 0, 0xaa); 1396 ad_write(mss, 1, 0x45);/* 0x55 with bit 0x10 clear */ 1397 tmp1 = ad_read(mss, 0); 1398 tmp2 = ad_read(mss, 1); 1399 if (tmp1 != 0xaa || tmp2 != 0x45) { 1400 BVDDB(printf("mss_detect error - IREG (%x/%x)\n", tmp1, tmp2)); 1401 goto no; 1402 } 1403 1404 ad_write(mss, 0, 0x45); 1405 ad_write(mss, 1, 0xaa); 1406 tmp1 = ad_read(mss, 0); 1407 tmp2 = ad_read(mss, 1); 1408 if (tmp1 != 0x45 || tmp2 != 0xaa) { 1409 BVDDB(printf("mss_detect error - IREG2 (%x/%x)\n", tmp1, tmp2)); 1410 goto no; 1411 } 1412 1413 /* 1414 * The indirect register I12 has some read only bits. Lets try to 1415 * change them. 1416 */ 1417 1418 tmp = ad_read(mss, 12); 1419 ad_write(mss, 12, (~tmp) & 0x0f); 1420 tmp1 = ad_read(mss, 12); 1421 1422 if ((tmp & 0x0f) != (tmp1 & 0x0f)) { 1423 BVDDB(printf("mss_detect - I12 (0x%02x was 0x%02x)\n", tmp1, tmp)); 1424 goto no; 1425 } 1426 1427 /* 1428 * NOTE! Last 4 bits of the reg I12 tell the chip revision. 1429 * 0x01=RevB 1430 * 0x0A=RevC. also CS4231/CS4231A and OPTi931 1431 */ 1432 1433 BVDDB(printf("mss_detect - chip revision 0x%02x\n", tmp & 0x0f);) 1434 1435 /* 1436 * The original AD1848/CS4248 has just 16 indirect registers. This 1437 * means that I0 and I16 should return the same value (etc.). Ensure 1438 * that the Mode2 enable bit of I12 is 0. Otherwise this test fails 1439 * with new parts. 1440 */ 1441 1442 ad_write(mss, 12, 0); /* Mode2=disabled */ 1443#if 0 1444 for (i = 0; i < 16; i++) { 1445 if ((tmp1 = ad_read(mss, i)) != (tmp2 = ad_read(mss, i + 16))) { 1446 BVDDB(printf("mss_detect warning - I%d: 0x%02x/0x%02x\n", 1447 i, tmp1, tmp2)); 1448 /* 1449 * note - this seems to fail on the 4232 on I11. So we just break 1450 * rather than fail. (which makes this test pointless - cg) 1451 */ 1452 break; /* return 0; */ 1453 } 1454 } 1455#endif 1456 /* 1457 * Try to switch the chip to mode2 (CS4231) by setting the MODE2 bit 1458 * (0x40). The bit 0x80 is always 1 in CS4248 and CS4231. 1459 * 1460 * On the OPTi931, however, I12 is readonly and only contains the 1461 * chip revision ID (as in the CS4231A). The upper bits return 0. 1462 */ 1463 1464 ad_write(mss, 12, 0x40); /* Set mode2, clear 0x80 */ 1465 1466 tmp1 = ad_read(mss, 12); 1467 if (tmp1 & 0x80) name = "CS4248"; /* Our best knowledge just now */ 1468 if ((tmp1 & 0xf0) == 0x00) { 1469 BVDDB(printf("this should be an OPTi931\n");) 1470 } else if ((tmp1 & 0xc0) != 0xC0) goto gotit; 1471 /* 1472 * The 4231 has bit7=1 always, and bit6 we just set to 1. 1473 * We want to check that this is really a CS4231 1474 * Verify that setting I0 doesn't change I16. 1475 */ 1476 ad_write(mss, 16, 0); /* Set I16 to known value */ 1477 ad_write(mss, 0, 0x45); 1478 if ((tmp1 = ad_read(mss, 16)) == 0x45) goto gotit; 1479 1480 ad_write(mss, 0, 0xaa); 1481 if ((tmp1 = ad_read(mss, 16)) == 0xaa) { /* Rotten bits? */ 1482 BVDDB(printf("mss_detect error - step H(%x)\n", tmp1)); 1483 goto no; 1484 } 1485 /* Verify that some bits of I25 are read only. */ 1486 tmp1 = ad_read(mss, 25); /* Original bits */ 1487 ad_write(mss, 25, ~tmp1); /* Invert all bits */ 1488 if ((ad_read(mss, 25) & 0xe7) == (tmp1 & 0xe7)) { 1489 int id; 1490 1491 /* It's at least CS4231 */ 1492 name = "CS4231"; 1493 mss->bd_id = MD_CS42XX; 1494 1495 /* 1496 * It could be an AD1845 or CS4231A as well. 1497 * CS4231 and AD1845 report the same revision info in I25 1498 * while the CS4231A reports different. 1499 */ 1500 1501 id = ad_read(mss, 25) & 0xe7; 1502 /* 1503 * b7-b5 = version number; 1504 * 100 : all CS4231 1505 * 101 : CS4231A 1506 * 1507 * b2-b0 = chip id; 1508 */ 1509 switch (id) { 1510 1511 case 0xa0: 1512 name = "CS4231A"; 1513 mss->bd_id = MD_CS42XX; 1514 break; 1515 1516 case 0xa2: 1517 name = "CS4232"; 1518 mss->bd_id = MD_CS42XX; 1519 break; 1520 1521 case 0xb2: 1522 /* strange: the 4231 data sheet says b4-b3 are XX 1523 * so this should be the same as 0xa2 1524 */ 1525 name = "CS4232A"; 1526 mss->bd_id = MD_CS42XX; 1527 break; 1528 1529 case 0x80: 1530 /* 1531 * It must be a CS4231 or AD1845. The register I23 1532 * of CS4231 is undefined and it appears to be read 1533 * only. AD1845 uses I23 for setting sample rate. 1534 * Assume the chip is AD1845 if I23 is changeable. 1535 */ 1536 1537 tmp = ad_read(mss, 23); 1538 1539 ad_write(mss, 23, ~tmp); 1540 if (ad_read(mss, 23) != tmp) { /* AD1845 ? */ 1541 name = "AD1845"; 1542 mss->bd_id = MD_AD1845; 1543 } 1544 ad_write(mss, 23, tmp); /* Restore */ 1545 1546 yamaha = ymf_test(dev, mss); 1547 if (yamaha) { 1548 mss->bd_id = MD_YM0020; 1549 name = yamaha; 1550 } 1551 break; 1552 1553 case 0x83: /* CS4236 */ 1554 case 0x03: /* CS4236 on Intel PR440FX motherboard XXX */ 1555 name = "CS4236"; 1556 mss->bd_id = MD_CS42XX; 1557 break; 1558 1559 default: /* Assume CS4231 */ 1560 BVDDB(printf("unknown id 0x%02x, assuming CS4231\n", id);) 1561 mss->bd_id = MD_CS42XX; 1562 } 1563 } 1564 ad_write(mss, 25, tmp1); /* Restore bits */ 1565gotit: 1566 BVDDB(printf("mss_detect() - Detected %s\n", name)); 1567 device_set_desc(dev, name); 1568 device_set_flags(dev, 1569 ((device_get_flags(dev) & ~DV_F_DEV_MASK) | 1570 ((mss->bd_id << DV_F_DEV_SHIFT) & DV_F_DEV_MASK))); 1571 return 0; 1572no: 1573 return ENXIO; 1574} 1575 1576static int 1577opti_detect(device_t dev, struct mss_info *mss) 1578{ 1579 int c; 1580 static const struct opticard { 1581 int boardid; 1582 int passwdreg; 1583 int password; 1584 int base; 1585 int indir_reg; 1586 } cards[] = { 1587 { MD_OPTI930, 0, 0xe4, 0xf8f, 0xe0e }, /* 930 */ 1588 { MD_OPTI924, 3, 0xe5, 0xf8c, 0, }, /* 924 */ 1589 { 0 }, 1590 }; 1591 mss->conf_rid = 3; 1592 mss->indir_rid = 4; 1593 for (c = 0; cards[c].base; c++) { 1594 mss->optibase = cards[c].base; 1595 mss->password = cards[c].password; 1596 mss->passwdreg = cards[c].passwdreg; 1597 mss->bd_id = cards[c].boardid; 1598 1599 if (cards[c].indir_reg) 1600 mss->indir = bus_alloc_resource(dev, SYS_RES_IOPORT, 1601 &mss->indir_rid, cards[c].indir_reg, 1602 cards[c].indir_reg+1, 1, RF_ACTIVE); 1603 1604 mss->conf_base = bus_alloc_resource(dev, SYS_RES_IOPORT, 1605 &mss->conf_rid, mss->optibase, mss->optibase+9, 1606 9, RF_ACTIVE); 1607 1608 if (opti_read(mss, 1) != 0xff) { 1609 return 1; 1610 } else { 1611 if (mss->indir) 1612 bus_release_resource(dev, SYS_RES_IOPORT, mss->indir_rid, mss->indir); 1613 mss->indir = NULL; 1614 if (mss->conf_base) 1615 bus_release_resource(dev, SYS_RES_IOPORT, mss->conf_rid, mss->conf_base); 1616 mss->conf_base = NULL; 1617 } 1618 } 1619 return 0; 1620} 1621 1622static char * 1623ymf_test(device_t dev, struct mss_info *mss) 1624{ 1625 static int ports[] = {0x370, 0x310, 0x538}; 1626 int p, i, j, version; 1627 static char *chipset[] = { 1628 NULL, /* 0 */ 1629 "OPL3-SA2 (YMF711)", /* 1 */ 1630 "OPL3-SA3 (YMF715)", /* 2 */ 1631 "OPL3-SA3 (YMF715)", /* 3 */ 1632 "OPL3-SAx (YMF719)", /* 4 */ 1633 "OPL3-SAx (YMF719)", /* 5 */ 1634 "OPL3-SAx (YMF719)", /* 6 */ 1635 "OPL3-SAx (YMF719)", /* 7 */ 1636 }; 1637 1638 for (p = 0; p < 3; p++) { 1639 mss->conf_rid = 1; 1640 mss->conf_base = bus_alloc_resource(dev, 1641 SYS_RES_IOPORT, 1642 &mss->conf_rid, 1643 ports[p], ports[p] + 1, 2, 1644 RF_ACTIVE); 1645 if (!mss->conf_base) return 0; 1646 1647 /* Test the index port of the config registers */ 1648 i = port_rd(mss->conf_base, 0); 1649 port_wr(mss->conf_base, 0, OPL3SAx_DMACONF); 1650 j = (port_rd(mss->conf_base, 0) == OPL3SAx_DMACONF)? 1 : 0; 1651 port_wr(mss->conf_base, 0, i); 1652 if (!j) { 1653 bus_release_resource(dev, SYS_RES_IOPORT, 1654 mss->conf_rid, mss->conf_base); 1655#ifdef PC98 1656 /* PC98 need this. I don't know reason why. */ 1657 bus_delete_resource(dev, SYS_RES_IOPORT, mss->conf_rid); 1658#endif 1659 mss->conf_base = 0; 1660 continue; 1661 } 1662 version = conf_rd(mss, OPL3SAx_MISC) & 0x07; 1663 return chipset[version]; 1664 } 1665 return NULL; 1666} 1667 1668static int 1669mss_doattach(device_t dev, struct mss_info *mss) 1670{ 1671 int pdma, rdma, flags = device_get_flags(dev); 1672 char status[SND_STATUSLEN], status2[SND_STATUSLEN]; 1673 1674 mss->lock = snd_mtxcreate(device_get_nameunit(dev), "sound softc"); 1675 mss->bufsize = pcm_getbuffersize(dev, 4096, MSS_DEFAULT_BUFSZ, 65536); 1676 if (!mss_alloc_resources(mss, dev)) goto no; 1677 mss_init(mss, dev); 1678 pdma = rman_get_start(mss->drq1); 1679 rdma = rman_get_start(mss->drq2); 1680 if (flags & DV_F_TRUE_MSS) { 1681 /* has IRQ/DMA registers, set IRQ and DMA addr */ 1682#ifdef PC98 /* CS423[12] in PC98 can use IRQ3,5,10,12 */ 1683 static char interrupt_bits[13] = 1684 {-1, -1, -1, 0x08, -1, 0x10, -1, -1, -1, -1, 0x18, -1, 0x20}; 1685#else 1686 static char interrupt_bits[12] = 1687 {-1, -1, -1, -1, -1, 0x28, -1, 0x08, -1, 0x10, 0x18, 0x20}; 1688#endif 1689 static char pdma_bits[4] = {1, 2, -1, 3}; 1690 static char valid_rdma[4] = {1, 0, -1, 0}; 1691 char bits; 1692 1693 if (!mss->irq || (bits = interrupt_bits[rman_get_start(mss->irq)]) == -1) 1694 goto no; 1695#ifndef PC98 /* CS423[12] in PC98 don't support this. */ 1696 io_wr(mss, 0, bits | 0x40); /* config port */ 1697 if ((io_rd(mss, 3) & 0x40) == 0) device_printf(dev, "IRQ Conflict?\n"); 1698#endif 1699 /* Write IRQ+DMA setup */ 1700 if (pdma_bits[pdma] == -1) goto no; 1701 bits |= pdma_bits[pdma]; 1702 if (pdma != rdma) { 1703 if (rdma == valid_rdma[pdma]) bits |= 4; 1704 else { 1705 printf("invalid dual dma config %d:%d\n", pdma, rdma); 1706 goto no; 1707 } 1708 } 1709 io_wr(mss, 0, bits); 1710 printf("drq/irq conf %x\n", io_rd(mss, 0)); 1711 } 1712 mixer_init(dev, (mss->bd_id == MD_YM0020)? &ymmix_mixer_class : &mssmix_mixer_class, mss); 1713 switch (mss->bd_id) { 1714 case MD_OPTI931: 1715 snd_setup_intr(dev, mss->irq, 0, opti931_intr, mss, &mss->ih); 1716 break; 1717 default: 1718 snd_setup_intr(dev, mss->irq, 0, mss_intr, mss, &mss->ih); 1719 } 1720 if (pdma == rdma) 1721 pcm_setflags(dev, pcm_getflags(dev) | SD_F_SIMPLEX); 1722 if (bus_dma_tag_create(/*parent*/NULL, /*alignment*/2, /*boundary*/0, 1723 /*lowaddr*/BUS_SPACE_MAXADDR_24BIT, 1724 /*highaddr*/BUS_SPACE_MAXADDR, 1725 /*filter*/NULL, /*filterarg*/NULL, 1726 /*maxsize*/mss->bufsize, /*nsegments*/1, 1727 /*maxsegz*/0x3ffff, /*flags*/0, 1728 /*lockfunc*/busdma_lock_mutex, /*lockarg*/&Giant, 1729 &mss->parent_dmat) != 0) { 1730 device_printf(dev, "unable to create dma tag\n"); 1731 goto no; 1732 } 1733 1734 if (pdma != rdma) 1735 snprintf(status2, SND_STATUSLEN, ":%d", rdma); 1736 else 1737 status2[0] = '\0'; 1738 1739 snprintf(status, SND_STATUSLEN, "at io 0x%lx irq %ld drq %d%s bufsz %u", 1740 rman_get_start(mss->io_base), rman_get_start(mss->irq), pdma, status2, mss->bufsize); 1741 1742 if (pcm_register(dev, mss, 1, 1)) goto no; 1743 pcm_addchan(dev, PCMDIR_REC, &msschan_class, mss); 1744 pcm_addchan(dev, PCMDIR_PLAY, &msschan_class, mss); 1745 pcm_setstatus(dev, status); 1746 1747 return 0; 1748no: 1749 mss_release_resources(mss, dev); 1750 return ENXIO; 1751} 1752 1753static int 1754mss_detach(device_t dev) 1755{ 1756 int r; 1757 struct mss_info *mss; 1758 1759 r = pcm_unregister(dev); 1760 if (r) 1761 return r; 1762 1763 mss = pcm_getdevinfo(dev); 1764 mss_release_resources(mss, dev); 1765 1766 return 0; 1767} 1768 1769static int 1770mss_attach(device_t dev) 1771{ 1772 struct mss_info *mss; 1773 int flags = device_get_flags(dev); 1774 1775 mss = (struct mss_info *)malloc(sizeof *mss, M_DEVBUF, M_NOWAIT | M_ZERO); 1776 if (!mss) return ENXIO; 1777 1778 mss->io_rid = 0; 1779 mss->conf_rid = -1; 1780 mss->irq_rid = 0; 1781 mss->drq1_rid = 0; 1782 mss->drq2_rid = -1; 1783 if (flags & DV_F_DUAL_DMA) { 1784 bus_set_resource(dev, SYS_RES_DRQ, 1, 1785 flags & DV_F_DRQ_MASK, 1); 1786 mss->drq2_rid = 1; 1787 } 1788 mss->bd_id = (device_get_flags(dev) & DV_F_DEV_MASK) >> DV_F_DEV_SHIFT; 1789 if (mss->bd_id == MD_YM0020) ymf_test(dev, mss); 1790 return mss_doattach(dev, mss); 1791} 1792 1793/* 1794 * mss_resume() is the code to allow a laptop to resume using the sound 1795 * card. 1796 * 1797 * This routine re-sets the state of the board to the state before going 1798 * to sleep. According to the yamaha docs this is the right thing to do, 1799 * but getting DMA restarted appears to be a bit of a trick, so the device 1800 * has to be closed and re-opened to be re-used, but there is no skipping 1801 * problem, and volume, bass/treble and most other things are restored 1802 * properly. 1803 * 1804 */ 1805 1806static int 1807mss_resume(device_t dev) 1808{ 1809 /* 1810 * Restore the state taken below. 1811 */ 1812 struct mss_info *mss; 1813 int i; 1814 1815 mss = pcm_getdevinfo(dev); 1816 1817 if(mss->bd_id == MD_YM0020 || mss->bd_id == MD_CS423X) { 1818 /* This works on a Toshiba Libretto 100CT. */ 1819 for (i = 0; i < MSS_INDEXED_REGS; i++) 1820 ad_write(mss, i, mss->mss_indexed_regs[i]); 1821 for (i = 0; i < OPL_INDEXED_REGS; i++) 1822 conf_wr(mss, i, mss->opl_indexed_regs[i]); 1823 mss_intr(mss); 1824 } 1825 1826 if (mss->bd_id == MD_CS423X) { 1827 /* Needed on IBM Thinkpad 600E */ 1828 chn_setformat(mss->pch.channel, mss->pch.channel->format); 1829 chn_setspeed(mss->pch.channel, mss->pch.channel->speed); 1830 } 1831 1832 return 0; 1833 1834} 1835 1836/* 1837 * mss_suspend() is the code that gets called right before a laptop 1838 * suspends. 1839 * 1840 * This code saves the state of the sound card right before shutdown 1841 * so it can be restored above. 1842 * 1843 */ 1844 1845static int 1846mss_suspend(device_t dev) 1847{ 1848 int i; 1849 struct mss_info *mss; 1850 1851 mss = pcm_getdevinfo(dev); 1852 1853 if(mss->bd_id == MD_YM0020 || mss->bd_id == MD_CS423X) 1854 { 1855 /* this stops playback. */ 1856 conf_wr(mss, 0x12, 0x0c); 1857 for(i = 0; i < MSS_INDEXED_REGS; i++) 1858 mss->mss_indexed_regs[i] = ad_read(mss, i); 1859 for(i = 0; i < OPL_INDEXED_REGS; i++) 1860 mss->opl_indexed_regs[i] = conf_rd(mss, i); 1861 mss->opl_indexed_regs[0x12] = 0x0; 1862 } 1863 return 0; 1864} 1865 1866static device_method_t mss_methods[] = { 1867 /* Device interface */ 1868 DEVMETHOD(device_probe, mss_probe), 1869 DEVMETHOD(device_attach, mss_attach), 1870 DEVMETHOD(device_detach, mss_detach), 1871 DEVMETHOD(device_suspend, mss_suspend), 1872 DEVMETHOD(device_resume, mss_resume), 1873 1874 { 0, 0 } 1875}; 1876 1877static driver_t mss_driver = { 1878 "pcm", 1879 mss_methods, 1880 PCM_SOFTC_SIZE, 1881}; 1882 1883DRIVER_MODULE(snd_mss, isa, mss_driver, pcm_devclass, 0, 0); 1884DRIVER_MODULE(snd_mss, acpi, mss_driver, pcm_devclass, 0, 0); 1885MODULE_DEPEND(snd_mss, sound, SOUND_MINVER, SOUND_PREFVER, SOUND_MAXVER); 1886MODULE_VERSION(snd_mss, 1); 1887 1888static int 1889azt2320_mss_mode(struct mss_info *mss, device_t dev) 1890{ 1891 struct resource *sbport; 1892 int i, ret, rid; 1893 1894 rid = 0; 1895 ret = -1; 1896 sbport = bus_alloc_resource_any(dev, SYS_RES_IOPORT, &rid, RF_ACTIVE); 1897 if (sbport) { 1898 for (i = 0; i < 1000; i++) { 1899 if ((port_rd(sbport, SBDSP_STATUS) & 0x80)) 1900 DELAY((i > 100) ? 1000 : 10); 1901 else { 1902 port_wr(sbport, SBDSP_CMD, 0x09); 1903 break; 1904 } 1905 } 1906 for (i = 0; i < 1000; i++) { 1907 if ((port_rd(sbport, SBDSP_STATUS) & 0x80)) 1908 DELAY((i > 100) ? 1000 : 10); 1909 else { 1910 port_wr(sbport, SBDSP_CMD, 0x00); 1911 ret = 0; 1912 break; 1913 } 1914 } 1915 DELAY(1000); 1916 bus_release_resource(dev, SYS_RES_IOPORT, rid, sbport); 1917 } 1918 return ret; 1919} 1920 1921static struct isa_pnp_id pnpmss_ids[] = { 1922 {0x0000630e, "CS423x"}, /* CSC0000 */ 1923 {0x0001630e, "CS423x-PCI"}, /* CSC0100 */ 1924 {0x01000000, "CMI8330"}, /* @@@0001 */ 1925 {0x2100a865, "Yamaha OPL-SAx"}, /* YMH0021 */ 1926 {0x1110d315, "ENSONIQ SoundscapeVIVO"}, /* ENS1011 */ 1927 {0x1093143e, "OPTi931"}, /* OPT9310 */ 1928 {0x5092143e, "OPTi925"}, /* OPT9250 XXX guess */ 1929 {0x0000143e, "OPTi924"}, /* OPT0924 */ 1930 {0x1022b839, "Neomagic 256AV (non-ac97)"}, /* NMX2210 */ 1931 {0x01005407, "Aztech 2320"}, /* AZT0001 */ 1932#if 0 1933 {0x0000561e, "GusPnP"}, /* GRV0000 */ 1934#endif 1935 {0}, 1936}; 1937 1938static int 1939pnpmss_probe(device_t dev) 1940{ 1941 u_int32_t lid, vid; 1942 1943 lid = isa_get_logicalid(dev); 1944 vid = isa_get_vendorid(dev); 1945 if (lid == 0x01000000 && vid != 0x0100a90d) /* CMI0001 */ 1946 return ENXIO; 1947 return ISA_PNP_PROBE(device_get_parent(dev), dev, pnpmss_ids); 1948} 1949 1950static int 1951pnpmss_attach(device_t dev) 1952{ 1953 struct mss_info *mss; 1954 1955 mss = (struct mss_info *)malloc(sizeof *mss, M_DEVBUF, M_NOWAIT | M_ZERO); 1956 if (!mss) 1957 return ENXIO; 1958 1959 mss->io_rid = 0; 1960 mss->conf_rid = -1; 1961 mss->irq_rid = 0; 1962 mss->drq1_rid = 0; 1963 mss->drq2_rid = 1; 1964 mss->bd_id = MD_CS42XX; 1965 1966 switch (isa_get_logicalid(dev)) { 1967 case 0x0000630e: /* CSC0000 */ 1968 case 0x0001630e: /* CSC0100 */ 1969 mss->bd_flags |= BD_F_MSS_OFFSET; 1970 mss->bd_id = MD_CS423X; 1971 break; 1972 1973 case 0x2100a865: /* YHM0021 */ 1974 mss->io_rid = 1; 1975 mss->conf_rid = 4; 1976 mss->bd_id = MD_YM0020; 1977 break; 1978 1979 case 0x1110d315: /* ENS1011 */ 1980 mss->io_rid = 1; 1981 mss->bd_id = MD_VIVO; 1982 break; 1983 1984 case 0x1093143e: /* OPT9310 */ 1985 mss->bd_flags |= BD_F_MSS_OFFSET; 1986 mss->conf_rid = 3; 1987 mss->bd_id = MD_OPTI931; 1988 break; 1989 1990 case 0x5092143e: /* OPT9250 XXX guess */ 1991 mss->io_rid = 1; 1992 mss->conf_rid = 3; 1993 mss->bd_id = MD_OPTI925; 1994 break; 1995 1996 case 0x0000143e: /* OPT0924 */ 1997 mss->password = 0xe5; 1998 mss->passwdreg = 3; 1999 mss->optibase = 0xf0c; 2000 mss->io_rid = 2; 2001 mss->conf_rid = 3; 2002 mss->bd_id = MD_OPTI924; 2003 mss->bd_flags |= BD_F_924PNP; 2004 if(opti_init(dev, mss) != 0) 2005 return ENXIO; 2006 break; 2007 2008 case 0x1022b839: /* NMX2210 */ 2009 mss->io_rid = 1; 2010 break; 2011 2012 case 0x01005407: /* AZT0001 */ 2013 /* put into MSS mode first (snatched from NetBSD) */ 2014 if (azt2320_mss_mode(mss, dev) == -1) 2015 return ENXIO; 2016 2017 mss->bd_flags |= BD_F_MSS_OFFSET; 2018 mss->io_rid = 2; 2019 break; 2020 2021#if 0 2022 case 0x0000561e: /* GRV0000 */ 2023 mss->bd_flags |= BD_F_MSS_OFFSET; 2024 mss->io_rid = 2; 2025 mss->conf_rid = 1; 2026 mss->drq1_rid = 1; 2027 mss->drq2_rid = 0; 2028 mss->bd_id = MD_GUSPNP; 2029 break; 2030#endif 2031 case 0x01000000: /* @@@0001 */ 2032 mss->drq2_rid = -1; 2033 break; 2034 2035 /* Unknown MSS default. We could let the CSC0000 stuff match too */ 2036 default: 2037 mss->bd_flags |= BD_F_MSS_OFFSET; 2038 break; 2039 } 2040 return mss_doattach(dev, mss); 2041} 2042 2043static int 2044opti_init(device_t dev, struct mss_info *mss) 2045{ 2046 int flags = device_get_flags(dev); 2047 int basebits = 0; 2048 2049 if (!mss->conf_base) { 2050 bus_set_resource(dev, SYS_RES_IOPORT, mss->conf_rid, 2051 mss->optibase, 0x9); 2052 2053 mss->conf_base = bus_alloc_resource(dev, SYS_RES_IOPORT, 2054 &mss->conf_rid, mss->optibase, mss->optibase+0x9, 2055 0x9, RF_ACTIVE); 2056 } 2057 2058 if (!mss->conf_base) 2059 return ENXIO; 2060 2061 if (!mss->io_base) 2062 mss->io_base = bus_alloc_resource(dev, SYS_RES_IOPORT, 2063 &mss->io_rid, 0, ~0, 8, RF_ACTIVE); 2064 2065 if (!mss->io_base) /* No hint specified, use 0x530 */ 2066 mss->io_base = bus_alloc_resource(dev, SYS_RES_IOPORT, 2067 &mss->io_rid, 0x530, 0x537, 8, RF_ACTIVE); 2068 2069 if (!mss->io_base) 2070 return ENXIO; 2071 2072 switch (rman_get_start(mss->io_base)) { 2073 case 0x530: 2074 basebits = 0x0; 2075 break; 2076 case 0xe80: 2077 basebits = 0x10; 2078 break; 2079 case 0xf40: 2080 basebits = 0x20; 2081 break; 2082 case 0x604: 2083 basebits = 0x30; 2084 break; 2085 default: 2086 printf("opti_init: invalid MSS base address!\n"); 2087 return ENXIO; 2088 } 2089 2090 2091 switch (mss->bd_id) { 2092 case MD_OPTI924: 2093 opti_write(mss, 1, 0x80 | basebits); /* MSS mode */ 2094 opti_write(mss, 2, 0x00); /* Disable CD */ 2095 opti_write(mss, 3, 0xf0); /* Disable SB IRQ */ 2096 opti_write(mss, 4, 0xf0); 2097 opti_write(mss, 5, 0x00); 2098 opti_write(mss, 6, 0x02); /* MPU stuff */ 2099 break; 2100 2101 case MD_OPTI930: 2102 opti_write(mss, 1, 0x00 | basebits); 2103 opti_write(mss, 3, 0x00); /* Disable SB IRQ/DMA */ 2104 opti_write(mss, 4, 0x52); /* Empty FIFO */ 2105 opti_write(mss, 5, 0x3c); /* Mode 2 */ 2106 opti_write(mss, 6, 0x02); /* Enable MSS */ 2107 break; 2108 } 2109 2110 if (mss->bd_flags & BD_F_924PNP) { 2111 u_int32_t irq = isa_get_irq(dev); 2112 u_int32_t drq = isa_get_drq(dev); 2113 bus_set_resource(dev, SYS_RES_IRQ, 0, irq, 1); 2114 bus_set_resource(dev, SYS_RES_DRQ, mss->drq1_rid, drq, 1); 2115 if (flags & DV_F_DUAL_DMA) { 2116 bus_set_resource(dev, SYS_RES_DRQ, 1, 2117 flags & DV_F_DRQ_MASK, 1); 2118 mss->drq2_rid = 1; 2119 } 2120 } 2121 2122 /* OPTixxx has I/DRQ registers */ 2123 2124 device_set_flags(dev, device_get_flags(dev) | DV_F_TRUE_MSS); 2125 2126 return 0; 2127} 2128 2129static void 2130opti_write(struct mss_info *mss, u_char reg, u_char val) 2131{ 2132 port_wr(mss->conf_base, mss->passwdreg, mss->password); 2133 2134 switch(mss->bd_id) { 2135 case MD_OPTI924: 2136 if (reg > 7) { /* Indirect register */ 2137 port_wr(mss->conf_base, mss->passwdreg, reg); 2138 port_wr(mss->conf_base, mss->passwdreg, 2139 mss->password); 2140 port_wr(mss->conf_base, 9, val); 2141 return; 2142 } 2143 port_wr(mss->conf_base, reg, val); 2144 break; 2145 2146 case MD_OPTI930: 2147 port_wr(mss->indir, 0, reg); 2148 port_wr(mss->conf_base, mss->passwdreg, mss->password); 2149 port_wr(mss->indir, 1, val); 2150 break; 2151 } 2152} 2153 2154u_char 2155opti_read(struct mss_info *mss, u_char reg) 2156{ 2157 port_wr(mss->conf_base, mss->passwdreg, mss->password); 2158 2159 switch(mss->bd_id) { 2160 case MD_OPTI924: 2161 if (reg > 7) { /* Indirect register */ 2162 port_wr(mss->conf_base, mss->passwdreg, reg); 2163 port_wr(mss->conf_base, mss->passwdreg, mss->password); 2164 return(port_rd(mss->conf_base, 9)); 2165 } 2166 return(port_rd(mss->conf_base, reg)); 2167 break; 2168 2169 case MD_OPTI930: 2170 port_wr(mss->indir, 0, reg); 2171 port_wr(mss->conf_base, mss->passwdreg, mss->password); 2172 return port_rd(mss->indir, 1); 2173 break; 2174 } 2175 return -1; 2176} 2177 2178static device_method_t pnpmss_methods[] = { 2179 /* Device interface */ 2180 DEVMETHOD(device_probe, pnpmss_probe), 2181 DEVMETHOD(device_attach, pnpmss_attach), 2182 DEVMETHOD(device_detach, mss_detach), 2183 DEVMETHOD(device_suspend, mss_suspend), 2184 DEVMETHOD(device_resume, mss_resume), 2185 2186 { 0, 0 } 2187}; 2188 2189static driver_t pnpmss_driver = { 2190 "pcm", 2191 pnpmss_methods, 2192 PCM_SOFTC_SIZE, 2193}; 2194 2195DRIVER_MODULE(snd_pnpmss, isa, pnpmss_driver, pcm_devclass, 0, 0); 2196DRIVER_MODULE(snd_pnpmss, acpi, pnpmss_driver, pcm_devclass, 0, 0); 2197MODULE_DEPEND(snd_pnpmss, sound, SOUND_MINVER, SOUND_PREFVER, SOUND_MAXVER); 2198MODULE_VERSION(snd_pnpmss, 1); 2199 2200static int 2201guspcm_probe(device_t dev) 2202{ 2203 struct sndcard_func *func; 2204 2205 func = device_get_ivars(dev); 2206 if (func == NULL || func->func != SCF_PCM) 2207 return ENXIO; 2208 2209 device_set_desc(dev, "GUS CS4231"); 2210 return 0; 2211} 2212 2213static int 2214guspcm_attach(device_t dev) 2215{ 2216 device_t parent = device_get_parent(dev); 2217 struct mss_info *mss; 2218 int base, flags; 2219 unsigned char ctl; 2220 2221 mss = (struct mss_info *)malloc(sizeof *mss, M_DEVBUF, M_NOWAIT | M_ZERO); 2222 if (mss == NULL) 2223 return ENOMEM; 2224 2225 mss->bd_flags = BD_F_MSS_OFFSET; 2226 mss->io_rid = 2; 2227 mss->conf_rid = 1; 2228 mss->irq_rid = 0; 2229 mss->drq1_rid = 1; 2230 mss->drq2_rid = -1; 2231 2232 if (isa_get_logicalid(parent) == 0) 2233 mss->bd_id = MD_GUSMAX; 2234 else { 2235 mss->bd_id = MD_GUSPNP; 2236 mss->drq2_rid = 0; 2237 goto skip_setup; 2238 } 2239 2240 flags = device_get_flags(parent); 2241 if (flags & DV_F_DUAL_DMA) 2242 mss->drq2_rid = 0; 2243 2244 mss->conf_base = bus_alloc_resource(dev, SYS_RES_IOPORT, &mss->conf_rid, 2245 0, ~0, 8, RF_ACTIVE); 2246 2247 if (mss->conf_base == NULL) { 2248 mss_release_resources(mss, dev); 2249 return ENXIO; 2250 } 2251 2252 base = isa_get_port(parent); 2253 2254 ctl = 0x40; /* CS4231 enable */ 2255 if (isa_get_drq(dev) > 3) 2256 ctl |= 0x10; /* 16-bit dma channel 1 */ 2257 if ((flags & DV_F_DUAL_DMA) != 0 && (flags & DV_F_DRQ_MASK) > 3) 2258 ctl |= 0x20; /* 16-bit dma channel 2 */ 2259 ctl |= (base >> 4) & 0x0f; /* 2X0 -> 3XC */ 2260 port_wr(mss->conf_base, 6, ctl); 2261 2262skip_setup: 2263 return mss_doattach(dev, mss); 2264} 2265 2266static device_method_t guspcm_methods[] = { 2267 DEVMETHOD(device_probe, guspcm_probe), 2268 DEVMETHOD(device_attach, guspcm_attach), 2269 DEVMETHOD(device_detach, mss_detach), 2270 2271 { 0, 0 } 2272}; 2273 2274static driver_t guspcm_driver = { 2275 "pcm", 2276 guspcm_methods, 2277 PCM_SOFTC_SIZE, 2278}; 2279 2280DRIVER_MODULE(snd_guspcm, gusc, guspcm_driver, pcm_devclass, 0, 0); 2281MODULE_DEPEND(snd_guspcm, sound, SOUND_MINVER, SOUND_PREFVER, SOUND_MAXVER); 2282MODULE_VERSION(snd_guspcm, 1); 2283 2284 2285