if_sn.c revision 122625
1/* 2 * Copyright (c) 1996 Gardner Buchanan <gbuchanan@shl.com> 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 3. All advertising materials mentioning features or use of this software 14 * must display the following acknowledgement: 15 * This product includes software developed by Gardner Buchanan. 16 * 4. The name of Gardner Buchanan may not be used to endorse or promote 17 * products derived from this software without specific prior written 18 * permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 21 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 22 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 23 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 24 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 25 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 26 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 27 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 28 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 29 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 30 * 31 */ 32 33#include <sys/cdefs.h> 34__FBSDID("$FreeBSD: head/sys/dev/sn/if_sn.c 122625 2003-11-13 20:55:53Z obrien $"); 35 36/* 37 * This is a driver for SMC's 9000 series of Ethernet adapters. 38 * 39 * This FreeBSD driver is derived from the smc9194 Linux driver by 40 * Erik Stahlman and is Copyright (C) 1996 by Erik Stahlman. 41 * This driver also shamelessly borrows from the FreeBSD ep driver 42 * which is Copyright (C) 1994 Herb Peyerl <hpeyerl@novatel.ca> 43 * All rights reserved. 44 * 45 * It is set up for my SMC91C92 equipped Ampro LittleBoard embedded 46 * PC. It is adapted from Erik Stahlman's Linux driver which worked 47 * with his EFA Info*Express SVC VLB adaptor. According to SMC's databook, 48 * it will work for the entire SMC 9xxx series. (Ha Ha) 49 * 50 * "Features" of the SMC chip: 51 * 4608 byte packet memory. (for the 91C92. Others have more) 52 * EEPROM for configuration 53 * AUI/TP selection 54 * 55 * Authors: 56 * Erik Stahlman erik@vt.edu 57 * Herb Peyerl hpeyerl@novatel.ca 58 * Andres Vega Garcia avega@sophia.inria.fr 59 * Serge Babkin babkin@hq.icb.chel.su 60 * Gardner Buchanan gbuchanan@shl.com 61 * 62 * Sources: 63 * o SMC databook 64 * o "smc9194.c:v0.10(FIXED) 02/15/96 by Erik Stahlman (erik@vt.edu)" 65 * o "if_ep.c,v 1.19 1995/01/24 20:53:45 davidg Exp" 66 * 67 * Known Bugs: 68 * o Setting of the hardware address isn't supported. 69 * o Hardware padding isn't used. 70 */ 71 72/* 73 * Modifications for Megahertz X-Jack Ethernet Card (XJ-10BT) 74 * 75 * Copyright (c) 1996 by Tatsumi Hosokawa <hosokawa@jp.FreeBSD.org> 76 * BSD-nomads, Tokyo, Japan. 77 */ 78/* 79 * Multicast support by Kei TANAKA <kei@pal.xerox.com> 80 * Special thanks to itojun@itojun.org 81 */ 82 83#include <sys/param.h> 84#include <sys/systm.h> 85#include <sys/errno.h> 86#include <sys/sockio.h> 87#include <sys/mbuf.h> 88#include <sys/socket.h> 89#include <sys/syslog.h> 90 91#include <sys/module.h> 92#include <sys/bus.h> 93 94#include <machine/bus.h> 95#include <machine/resource.h> 96#include <sys/rman.h> 97 98#include <net/ethernet.h> 99#include <net/if.h> 100#include <net/if_arp.h> 101#include <net/if_dl.h> 102#include <net/if_types.h> 103#include <net/if_mib.h> 104 105#ifdef INET 106#include <netinet/in.h> 107#include <netinet/in_systm.h> 108#include <netinet/in_var.h> 109#include <netinet/ip.h> 110#endif 111 112#include <net/bpf.h> 113#include <net/bpfdesc.h> 114 115 116#include <dev/sn/if_snreg.h> 117#include <dev/sn/if_snvar.h> 118 119/* Exported variables */ 120devclass_t sn_devclass; 121 122static int snioctl(struct ifnet * ifp, u_long, caddr_t); 123 124static void snresume(struct ifnet *); 125 126static void sninit_locked(void *); 127static void snstart_locked(struct ifnet *); 128 129static void sninit(void *); 130static void snread(struct ifnet *); 131static void snstart(struct ifnet *); 132static void snstop(struct sn_softc *); 133static void snwatchdog(struct ifnet *); 134 135static void sn_setmcast(struct sn_softc *); 136static int sn_getmcf(struct arpcom *ac, u_char *mcf); 137static u_int32_t sn_mchash(caddr_t); 138 139/* I (GB) have been unlucky getting the hardware padding 140 * to work properly. 141 */ 142#define SW_PAD 143 144static const char *chip_ids[15] = { 145 NULL, NULL, NULL, 146 /* 3 */ "SMC91C90/91C92", 147 /* 4 */ "SMC91C94", 148 /* 5 */ "SMC91C95", 149 NULL, 150 /* 7 */ "SMC91C100", 151 /* 8 */ "SMC91C100FD", 152 NULL, NULL, NULL, 153 NULL, NULL, NULL 154}; 155 156int 157sn_attach(device_t dev) 158{ 159 struct sn_softc *sc = device_get_softc(dev); 160 struct ifnet *ifp = &sc->arpcom.ac_if; 161 uint16_t i, w; 162 uint8_t *p; 163 struct ifaddr *ifa; 164 struct sockaddr_dl *sdl; 165 int rev; 166 uint16_t address; 167 int j; 168 int err; 169 170 sc->dev = dev; 171 sn_activate(dev); 172 SN_LOCK_INIT(sc); 173 snstop(sc); 174 sc->pages_wanted = -1; 175 176 SMC_SELECT_BANK(sc, 3); 177 rev = (CSR_READ_2(sc, REVISION_REG_W) >> 4) & 0xf; 178 if (chip_ids[rev]) 179 device_printf(dev, " %s ", chip_ids[rev]); 180 else 181 device_printf(dev, " unsupported chip"); 182 183 SMC_SELECT_BANK(sc, 1); 184 i = CSR_READ_2(sc, CONFIG_REG_W); 185 printf(i & CR_AUI_SELECT ? "AUI" : "UTP"); 186 187 if (sc->pccard_enaddr) 188 for (j = 0; j < 3; j++) { 189 w = (uint16_t)sc->arpcom.ac_enaddr[j * 2] | 190 (((uint16_t)sc->arpcom.ac_enaddr[j * 2 + 1]) << 8); 191 CSR_WRITE_2(sc, IAR_ADDR0_REG_W + j * 2, w); 192 } 193 194 /* 195 * Read the station address from the chip. The MAC address is bank 1, 196 * regs 4 - 9 197 */ 198 SMC_SELECT_BANK(sc, 1); 199 p = (uint8_t *) &sc->arpcom.ac_enaddr; 200 for (i = 0; i < 6; i += 2) { 201 address = CSR_READ_2(sc, IAR_ADDR0_REG_W + i); 202 p[i + 1] = address >> 8; 203 p[i] = address & 0xFF; 204 } 205 printf(" MAC address %6D\n", sc->arpcom.ac_enaddr, ":"); 206 ifp->if_softc = sc; 207 if_initname(ifp, device_get_name(dev), device_get_unit(dev)); 208 ifp->if_mtu = ETHERMTU; 209 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 210 ifp->if_output = ether_output; 211 ifp->if_start = snstart; 212 ifp->if_ioctl = snioctl; 213 ifp->if_watchdog = snwatchdog; 214 ifp->if_init = sninit; 215 ifp->if_snd.ifq_maxlen = IFQ_MAXLEN; 216 ifp->if_timer = 0; 217 218 ether_ifattach(ifp, sc->arpcom.ac_enaddr); 219 220 /* 221 * Fill the hardware address into ifa_addr if we find an AF_LINK 222 * entry. We need to do this so bpf's can get the hardware addr of 223 * this card. netstat likes this too! 224 */ 225 ifa = TAILQ_FIRST(&ifp->if_addrhead); 226 while ((ifa != 0) && (ifa->ifa_addr != 0) && 227 (ifa->ifa_addr->sa_family != AF_LINK)) 228 ifa = TAILQ_NEXT(ifa, ifa_link); 229 230 if ((ifa != 0) && (ifa->ifa_addr != 0)) { 231 sdl = (struct sockaddr_dl *) ifa->ifa_addr; 232 sdl->sdl_type = IFT_ETHER; 233 sdl->sdl_alen = ETHER_ADDR_LEN; 234 sdl->sdl_slen = 0; 235 bcopy(sc->arpcom.ac_enaddr, LLADDR(sdl), ETHER_ADDR_LEN); 236 } 237 238 /* 239 * Activate the interrupt so we can get card interrupts. This 240 * needs to be done last so that we don't have/hold the lock 241 * during startup to avoid LORs in the network layer. 242 */ 243 if ((err = bus_setup_intr(dev, sc->irq_res, 244 INTR_TYPE_NET | INTR_MPSAFE, sn_intr, sc, &sc->intrhand)) != 0) { 245 sn_detach(dev); 246 return err; 247 } 248 return 0; 249} 250 251 252int 253sn_detach(device_t dev) 254{ 255 struct sn_softc *sc = device_get_softc(dev); 256 257 snstop(sc); 258 sc->arpcom.ac_if.if_flags &= ~IFF_RUNNING; 259 ether_ifdetach(&sc->arpcom.ac_if); 260 sn_deactivate(dev); 261 SN_LOCK_DESTORY(sc); 262 return 0; 263} 264 265static void 266sninit(void *xsc) 267{ 268 struct sn_softc *sc = xsc; 269 SN_LOCK(sc); 270 sninit_locked(sc); 271 SN_UNLOCK(sc); 272} 273 274/* 275 * Reset and initialize the chip 276 */ 277static void 278sninit_locked(void *xsc) 279{ 280 struct sn_softc *sc = xsc; 281 struct ifnet *ifp = &sc->arpcom.ac_if; 282 int flags; 283 int mask; 284 285 SN_ASSERT_LOCKED(sc); 286 287 /* 288 * This resets the registers mostly to defaults, but doesn't affect 289 * EEPROM. After the reset cycle, we pause briefly for the chip to 290 * be happy. 291 */ 292 SMC_SELECT_BANK(sc, 0); 293 CSR_WRITE_2(sc, RECV_CONTROL_REG_W, RCR_SOFTRESET); 294 SMC_DELAY(sc); 295 CSR_WRITE_2(sc, RECV_CONTROL_REG_W, 0x0000); 296 SMC_DELAY(sc); 297 SMC_DELAY(sc); 298 299 CSR_WRITE_2(sc, TXMIT_CONTROL_REG_W, 0x0000); 300 301 /* 302 * Set the control register to automatically release succesfully 303 * transmitted packets (making the best use out of our limited 304 * memory) and to enable the EPH interrupt on certain TX errors. 305 */ 306 SMC_SELECT_BANK(sc, 1); 307 CSR_WRITE_2(sc, CONTROL_REG_W, (CTR_AUTO_RELEASE | CTR_TE_ENABLE | 308 CTR_CR_ENABLE | CTR_LE_ENABLE)); 309 310 /* Set squelch level to 240mV (default 480mV) */ 311 flags = CSR_READ_2(sc, CONFIG_REG_W); 312 flags |= CR_SET_SQLCH; 313 CSR_WRITE_2(sc, CONFIG_REG_W, flags); 314 315 /* 316 * Reset the MMU and wait for it to be un-busy. 317 */ 318 SMC_SELECT_BANK(sc, 2); 319 CSR_WRITE_2(sc, MMU_CMD_REG_W, MMUCR_RESET); 320 while (CSR_READ_2(sc, MMU_CMD_REG_W) & MMUCR_BUSY) /* NOTHING */ 321 ; 322 323 /* 324 * Disable all interrupts 325 */ 326 CSR_WRITE_1(sc, INTR_MASK_REG_B, 0x00); 327 328 sn_setmcast(sc); 329 330 /* 331 * Set the transmitter control. We want it enabled. 332 */ 333 flags = TCR_ENABLE; 334 335#ifndef SW_PAD 336 /* 337 * I (GB) have been unlucky getting this to work. 338 */ 339 flags |= TCR_PAD_ENABLE; 340#endif /* SW_PAD */ 341 342 CSR_WRITE_2(sc, TXMIT_CONTROL_REG_W, flags); 343 344 345 /* 346 * Now, enable interrupts 347 */ 348 SMC_SELECT_BANK(sc, 2); 349 350 mask = IM_EPH_INT | 351 IM_RX_OVRN_INT | 352 IM_RCV_INT | 353 IM_TX_INT; 354 355 CSR_WRITE_1(sc, INTR_MASK_REG_B, mask); 356 sc->intr_mask = mask; 357 sc->pages_wanted = -1; 358 359 360 /* 361 * Mark the interface running but not active. 362 */ 363 ifp->if_flags |= IFF_RUNNING; 364 ifp->if_flags &= ~IFF_OACTIVE; 365 366 /* 367 * Attempt to push out any waiting packets. 368 */ 369 snstart_locked(ifp); 370} 371 372static void 373snstart(struct ifnet *ifp) 374{ 375 struct sn_softc *sc = ifp->if_softc; 376 SN_LOCK(sc); 377 snstart_locked(ifp); 378 SN_UNLOCK(sc); 379} 380 381 382static void 383snstart_locked(struct ifnet *ifp) 384{ 385 struct sn_softc *sc = ifp->if_softc; 386 u_int len; 387 struct mbuf *m; 388 struct mbuf *top; 389 int pad; 390 int mask; 391 uint16_t length; 392 uint16_t numPages; 393 uint8_t packet_no; 394 int time_out; 395 int junk = 0; 396 397 SN_ASSERT_LOCKED(sc); 398 399 if (sc->arpcom.ac_if.if_flags & IFF_OACTIVE) 400 return; 401 if (sc->pages_wanted != -1) { 402 if_printf(ifp, "snstart() while memory allocation pending\n"); 403 return; 404 } 405startagain: 406 407 /* 408 * Sneak a peek at the next packet 409 */ 410 m = sc->arpcom.ac_if.if_snd.ifq_head; 411 if (m == 0) 412 return; 413 /* 414 * Compute the frame length and set pad to give an overall even 415 * number of bytes. Below we assume that the packet length is even. 416 */ 417 for (len = 0, top = m; m; m = m->m_next) 418 len += m->m_len; 419 420 pad = (len & 1); 421 422 /* 423 * We drop packets that are too large. Perhaps we should truncate 424 * them instead? 425 */ 426 if (len + pad > ETHER_MAX_LEN - ETHER_CRC_LEN) { 427 if_printf(ifp, "large packet discarded (A)\n"); 428 ++sc->arpcom.ac_if.if_oerrors; 429 IF_DEQUEUE(&sc->arpcom.ac_if.if_snd, m); 430 m_freem(m); 431 goto readcheck; 432 } 433#ifdef SW_PAD 434 435 /* 436 * If HW padding is not turned on, then pad to ETHER_MIN_LEN. 437 */ 438 if (len < ETHER_MIN_LEN - ETHER_CRC_LEN) 439 pad = ETHER_MIN_LEN - ETHER_CRC_LEN - len; 440 441#endif /* SW_PAD */ 442 443 length = pad + len; 444 445 /* 446 * The MMU wants the number of pages to be the number of 256 byte 447 * 'pages', minus 1 (A packet can't ever have 0 pages. We also 448 * include space for the status word, byte count and control bytes in 449 * the allocation request. 450 */ 451 numPages = (length + 6) >> 8; 452 453 454 /* 455 * Now, try to allocate the memory 456 */ 457 SMC_SELECT_BANK(sc, 2); 458 CSR_WRITE_2(sc, MMU_CMD_REG_W, MMUCR_ALLOC | numPages); 459 460 /* 461 * Wait a short amount of time to see if the allocation request 462 * completes. Otherwise, I enable the interrupt and wait for 463 * completion asyncronously. 464 */ 465 466 time_out = MEMORY_WAIT_TIME; 467 do { 468 if (CSR_READ_1(sc, INTR_STAT_REG_B) & IM_ALLOC_INT) 469 break; 470 } while (--time_out); 471 472 if (!time_out || junk > 10) { 473 474 /* 475 * No memory now. Oh well, wait until the chip finds memory 476 * later. Remember how many pages we were asking for and 477 * enable the allocation completion interrupt. Also set a 478 * watchdog in case we miss the interrupt. We mark the 479 * interface active since there is no point in attempting an 480 * snstart() until after the memory is available. 481 */ 482 mask = CSR_READ_1(sc, INTR_MASK_REG_B) | IM_ALLOC_INT; 483 CSR_WRITE_1(sc, INTR_MASK_REG_B, mask); 484 sc->intr_mask = mask; 485 486 sc->arpcom.ac_if.if_timer = 1; 487 sc->arpcom.ac_if.if_flags |= IFF_OACTIVE; 488 sc->pages_wanted = numPages; 489 return; 490 } 491 /* 492 * The memory allocation completed. Check the results. 493 */ 494 packet_no = CSR_READ_1(sc, ALLOC_RESULT_REG_B); 495 if (packet_no & ARR_FAILED) { 496 if (junk++ > 10) 497 if_printf(ifp, "Memory allocation failed\n"); 498 goto startagain; 499 } 500 /* 501 * We have a packet number, so tell the card to use it. 502 */ 503 CSR_WRITE_1(sc, PACKET_NUM_REG_B, packet_no); 504 505 /* 506 * Point to the beginning of the packet 507 */ 508 CSR_WRITE_2(sc, POINTER_REG_W, PTR_AUTOINC | 0x0000); 509 510 /* 511 * Send the packet length (+6 for status, length and control byte) 512 * and the status word (set to zeros) 513 */ 514 CSR_WRITE_2(sc, DATA_REG_W, 0); 515 CSR_WRITE_1(sc, DATA_REG_B, (length + 6) & 0xFF); 516 CSR_WRITE_1(sc, DATA_REG_B, (length + 6) >> 8); 517 518 /* 519 * Get the packet from the kernel. This will include the Ethernet 520 * frame header, MAC Addresses etc. 521 */ 522 IF_DEQUEUE(&sc->arpcom.ac_if.if_snd, m); 523 524 /* 525 * Push out the data to the card. 526 */ 527 for (top = m; m != 0; m = m->m_next) { 528 529 /* 530 * Push out words. 531 */ 532 CSR_WRITE_MULTI_2(sc, DATA_REG_W, mtod(m, uint16_t *), 533 m->m_len / 2); 534 535 /* 536 * Push out remaining byte. 537 */ 538 if (m->m_len & 1) 539 CSR_WRITE_1(sc, DATA_REG_B, 540 *(mtod(m, caddr_t) + m->m_len - 1)); 541 } 542 543 /* 544 * Push out padding. 545 */ 546 while (pad > 1) { 547 CSR_WRITE_2(sc, DATA_REG_W, 0); 548 pad -= 2; 549 } 550 if (pad) 551 CSR_WRITE_1(sc, DATA_REG_B, 0); 552 553 /* 554 * Push out control byte and unused packet byte The control byte is 0 555 * meaning the packet is even lengthed and no special CRC handling is 556 * desired. 557 */ 558 CSR_WRITE_2(sc, DATA_REG_W, 0); 559 560 /* 561 * Enable the interrupts and let the chipset deal with it Also set a 562 * watchdog in case we miss the interrupt. 563 */ 564 mask = CSR_READ_1(sc, INTR_MASK_REG_B) | (IM_TX_INT | IM_TX_EMPTY_INT); 565 CSR_WRITE_1(sc, INTR_MASK_REG_B, mask); 566 sc->intr_mask = mask; 567 568 CSR_WRITE_2(sc, MMU_CMD_REG_W, MMUCR_ENQUEUE); 569 570 sc->arpcom.ac_if.if_flags |= IFF_OACTIVE; 571 sc->arpcom.ac_if.if_timer = 1; 572 573 BPF_MTAP(ifp, top); 574 575 sc->arpcom.ac_if.if_opackets++; 576 m_freem(top); 577 578 579readcheck: 580 581 /* 582 * Is another packet coming in? We don't want to overflow the tiny 583 * RX FIFO. If nothing has arrived then attempt to queue another 584 * transmit packet. 585 */ 586 if (CSR_READ_2(sc, FIFO_PORTS_REG_W) & FIFO_REMPTY) 587 goto startagain; 588 return; 589} 590 591 592 593/* Resume a packet transmit operation after a memory allocation 594 * has completed. 595 * 596 * This is basically a hacked up copy of snstart() which handles 597 * a completed memory allocation the same way snstart() does. 598 * It then passes control to snstart to handle any other queued 599 * packets. 600 */ 601static void 602snresume(struct ifnet *ifp) 603{ 604 struct sn_softc *sc = ifp->if_softc; 605 u_int len; 606 struct mbuf *m; 607 struct mbuf *top; 608 int pad; 609 int mask; 610 uint16_t length; 611 uint16_t numPages; 612 uint16_t pages_wanted; 613 uint8_t packet_no; 614 615 if (sc->pages_wanted < 0) 616 return; 617 618 pages_wanted = sc->pages_wanted; 619 sc->pages_wanted = -1; 620 621 /* 622 * Sneak a peek at the next packet 623 */ 624 m = sc->arpcom.ac_if.if_snd.ifq_head; 625 if (m == 0) { 626 if_printf(ifp, "snresume() with nothing to send\n"); 627 return; 628 } 629 /* 630 * Compute the frame length and set pad to give an overall even 631 * number of bytes. Below we assume that the packet length is even. 632 */ 633 for (len = 0, top = m; m; m = m->m_next) 634 len += m->m_len; 635 636 pad = (len & 1); 637 638 /* 639 * We drop packets that are too large. Perhaps we should truncate 640 * them instead? 641 */ 642 if (len + pad > ETHER_MAX_LEN - ETHER_CRC_LEN) { 643 if_printf(ifp, "large packet discarded (B)\n"); 644 ++sc->arpcom.ac_if.if_oerrors; 645 IF_DEQUEUE(&sc->arpcom.ac_if.if_snd, m); 646 m_freem(m); 647 return; 648 } 649#ifdef SW_PAD 650 651 /* 652 * If HW padding is not turned on, then pad to ETHER_MIN_LEN. 653 */ 654 if (len < ETHER_MIN_LEN - ETHER_CRC_LEN) 655 pad = ETHER_MIN_LEN - ETHER_CRC_LEN - len; 656 657#endif /* SW_PAD */ 658 659 length = pad + len; 660 661 662 /* 663 * The MMU wants the number of pages to be the number of 256 byte 664 * 'pages', minus 1 (A packet can't ever have 0 pages. We also 665 * include space for the status word, byte count and control bytes in 666 * the allocation request. 667 */ 668 numPages = (length + 6) >> 8; 669 670 671 SMC_SELECT_BANK(sc, 2); 672 673 /* 674 * The memory allocation completed. Check the results. If it failed, 675 * we simply set a watchdog timer and hope for the best. 676 */ 677 packet_no = CSR_READ_1(sc, ALLOC_RESULT_REG_B); 678 if (packet_no & ARR_FAILED) { 679 if_printf(ifp, "Memory allocation failed. Weird.\n"); 680 sc->arpcom.ac_if.if_timer = 1; 681 goto try_start; 682 } 683 /* 684 * We have a packet number, so tell the card to use it. 685 */ 686 CSR_WRITE_1(sc, PACKET_NUM_REG_B, packet_no); 687 688 /* 689 * Now, numPages should match the pages_wanted recorded when the 690 * memory allocation was initiated. 691 */ 692 if (pages_wanted != numPages) { 693 if_printf(ifp, "memory allocation wrong size. Weird.\n"); 694 /* 695 * If the allocation was the wrong size we simply release the 696 * memory once it is granted. Wait for the MMU to be un-busy. 697 */ 698 while (CSR_READ_2(sc, MMU_CMD_REG_W) & MMUCR_BUSY) /* NOTHING */ 699 ; 700 CSR_WRITE_2(sc, MMU_CMD_REG_W, MMUCR_FREEPKT); 701 702 return; 703 } 704 /* 705 * Point to the beginning of the packet 706 */ 707 CSR_WRITE_2(sc, POINTER_REG_W, PTR_AUTOINC | 0x0000); 708 709 /* 710 * Send the packet length (+6 for status, length and control byte) 711 * and the status word (set to zeros) 712 */ 713 CSR_WRITE_2(sc, DATA_REG_W, 0); 714 CSR_WRITE_1(sc, DATA_REG_B, (length + 6) & 0xFF); 715 CSR_WRITE_1(sc, DATA_REG_B, (length + 6) >> 8); 716 717 /* 718 * Get the packet from the kernel. This will include the Ethernet 719 * frame header, MAC Addresses etc. 720 */ 721 IF_DEQUEUE(&sc->arpcom.ac_if.if_snd, m); 722 723 /* 724 * Push out the data to the card. 725 */ 726 for (top = m; m != 0; m = m->m_next) { 727 728 /* 729 * Push out words. 730 */ 731 CSR_WRITE_MULTI_2(sc, DATA_REG_W, mtod(m, uint16_t *), 732 m->m_len / 2); 733 /* 734 * Push out remaining byte. 735 */ 736 if (m->m_len & 1) 737 CSR_WRITE_1(sc, DATA_REG_B, 738 *(mtod(m, caddr_t) + m->m_len - 1)); 739 } 740 741 /* 742 * Push out padding. 743 */ 744 while (pad > 1) { 745 CSR_WRITE_2(sc, DATA_REG_W, 0); 746 pad -= 2; 747 } 748 if (pad) 749 CSR_WRITE_1(sc, DATA_REG_B, 0); 750 751 /* 752 * Push out control byte and unused packet byte The control byte is 0 753 * meaning the packet is even lengthed and no special CRC handling is 754 * desired. 755 */ 756 CSR_WRITE_2(sc, DATA_REG_W, 0); 757 758 /* 759 * Enable the interrupts and let the chipset deal with it Also set a 760 * watchdog in case we miss the interrupt. 761 */ 762 mask = CSR_READ_1(sc, INTR_MASK_REG_B) | (IM_TX_INT | IM_TX_EMPTY_INT); 763 CSR_WRITE_1(sc, INTR_MASK_REG_B, mask); 764 sc->intr_mask = mask; 765 CSR_WRITE_2(sc, MMU_CMD_REG_W, MMUCR_ENQUEUE); 766 767 BPF_MTAP(ifp, top); 768 769 sc->arpcom.ac_if.if_opackets++; 770 m_freem(top); 771 772try_start: 773 774 /* 775 * Now pass control to snstart() to queue any additional packets 776 */ 777 sc->arpcom.ac_if.if_flags &= ~IFF_OACTIVE; 778 snstart(ifp); 779 780 /* 781 * We've sent something, so we're active. Set a watchdog in case the 782 * TX_EMPTY interrupt is lost. 783 */ 784 sc->arpcom.ac_if.if_flags |= IFF_OACTIVE; 785 sc->arpcom.ac_if.if_timer = 1; 786 787 return; 788} 789 790 791void 792sn_intr(void *arg) 793{ 794 int status, interrupts; 795 struct sn_softc *sc = (struct sn_softc *) arg; 796 struct ifnet *ifp = &sc->arpcom.ac_if; 797 798 /* 799 * Chip state registers 800 */ 801 uint8_t mask; 802 uint8_t packet_no; 803 uint16_t tx_status; 804 uint16_t card_stats; 805 806 SN_LOCK(sc); 807 808 /* 809 * Clear the watchdog. 810 */ 811 ifp->if_timer = 0; 812 813 SMC_SELECT_BANK(sc, 2); 814 815 /* 816 * Obtain the current interrupt mask and clear the hardware mask 817 * while servicing interrupts. 818 */ 819 mask = CSR_READ_1(sc, INTR_MASK_REG_B); 820 CSR_WRITE_1(sc, INTR_MASK_REG_B, 0x00); 821 822 /* 823 * Get the set of interrupts which occurred and eliminate any which 824 * are masked. 825 */ 826 interrupts = CSR_READ_1(sc, INTR_STAT_REG_B); 827 status = interrupts & mask; 828 829 /* 830 * Now, process each of the interrupt types. 831 */ 832 833 /* 834 * Receive Overrun. 835 */ 836 if (status & IM_RX_OVRN_INT) { 837 /* 838 * Acknowlege Interrupt 839 */ 840 SMC_SELECT_BANK(sc, 2); 841 CSR_WRITE_1(sc, INTR_ACK_REG_B, IM_RX_OVRN_INT); 842 843 ++sc->arpcom.ac_if.if_ierrors; 844 } 845 /* 846 * Got a packet. 847 */ 848 if (status & IM_RCV_INT) { 849 int packet_number; 850 851 SMC_SELECT_BANK(sc, 2); 852 packet_number = CSR_READ_2(sc, FIFO_PORTS_REG_W); 853 854 if (packet_number & FIFO_REMPTY) { 855 /* 856 * we got called , but nothing was on the FIFO 857 */ 858 printf("sn: Receive interrupt with nothing on FIFO\n"); 859 goto out; 860 } 861 snread(ifp); 862 } 863 /* 864 * An on-card memory allocation came through. 865 */ 866 if (status & IM_ALLOC_INT) { 867 /* 868 * Disable this interrupt. 869 */ 870 mask &= ~IM_ALLOC_INT; 871 sc->arpcom.ac_if.if_flags &= ~IFF_OACTIVE; 872 snresume(&sc->arpcom.ac_if); 873 } 874 /* 875 * TX Completion. Handle a transmit error message. This will only be 876 * called when there is an error, because of the AUTO_RELEASE mode. 877 */ 878 if (status & IM_TX_INT) { 879 /* 880 * Acknowlege Interrupt 881 */ 882 SMC_SELECT_BANK(sc, 2); 883 CSR_WRITE_1(sc, INTR_ACK_REG_B, IM_TX_INT); 884 885 packet_no = CSR_READ_2(sc, FIFO_PORTS_REG_W); 886 packet_no &= FIFO_TX_MASK; 887 888 /* 889 * select this as the packet to read from 890 */ 891 CSR_WRITE_1(sc, PACKET_NUM_REG_B, packet_no); 892 893 /* 894 * Position the pointer to the first word from this packet 895 */ 896 CSR_WRITE_2(sc, POINTER_REG_W, PTR_AUTOINC | PTR_READ | 0x0000); 897 898 /* 899 * Fetch the TX status word. The value found here will be a 900 * copy of the EPH_STATUS_REG_W at the time the transmit 901 * failed. 902 */ 903 tx_status = CSR_READ_2(sc, DATA_REG_W); 904 905 if (tx_status & EPHSR_TX_SUC) { 906 device_printf(sc->dev, 907 "Successful packet caused interrupt\n"); 908 } else { 909 ++sc->arpcom.ac_if.if_oerrors; 910 } 911 912 if (tx_status & EPHSR_LATCOL) 913 ++sc->arpcom.ac_if.if_collisions; 914 915 /* 916 * Some of these errors will have disabled transmit. 917 * Re-enable transmit now. 918 */ 919 SMC_SELECT_BANK(sc, 0); 920 921#ifdef SW_PAD 922 CSR_WRITE_2(sc, TXMIT_CONTROL_REG_W, TCR_ENABLE); 923#else 924 CSR_WRITE_2(sc, TXMIT_CONTROL_REG_W, TCR_ENABLE | TCR_PAD_ENABLE); 925#endif /* SW_PAD */ 926 927 /* 928 * kill the failed packet. Wait for the MMU to be un-busy. 929 */ 930 SMC_SELECT_BANK(sc, 2); 931 while (CSR_READ_2(sc, MMU_CMD_REG_W) & MMUCR_BUSY) /* NOTHING */ 932 ; 933 CSR_WRITE_2(sc, MMU_CMD_REG_W, MMUCR_FREEPKT); 934 935 /* 936 * Attempt to queue more transmits. 937 */ 938 sc->arpcom.ac_if.if_flags &= ~IFF_OACTIVE; 939 snstart_locked(&sc->arpcom.ac_if); 940 } 941 /* 942 * Transmit underrun. We use this opportunity to update transmit 943 * statistics from the card. 944 */ 945 if (status & IM_TX_EMPTY_INT) { 946 947 /* 948 * Acknowlege Interrupt 949 */ 950 SMC_SELECT_BANK(sc, 2); 951 CSR_WRITE_1(sc, INTR_ACK_REG_B, IM_TX_EMPTY_INT); 952 953 /* 954 * Disable this interrupt. 955 */ 956 mask &= ~IM_TX_EMPTY_INT; 957 958 SMC_SELECT_BANK(sc, 0); 959 card_stats = CSR_READ_2(sc, COUNTER_REG_W); 960 961 /* 962 * Single collisions 963 */ 964 sc->arpcom.ac_if.if_collisions += card_stats & ECR_COLN_MASK; 965 966 /* 967 * Multiple collisions 968 */ 969 sc->arpcom.ac_if.if_collisions += (card_stats & ECR_MCOLN_MASK) >> 4; 970 971 SMC_SELECT_BANK(sc, 2); 972 973 /* 974 * Attempt to enqueue some more stuff. 975 */ 976 sc->arpcom.ac_if.if_flags &= ~IFF_OACTIVE; 977 snstart_locked(&sc->arpcom.ac_if); 978 } 979 /* 980 * Some other error. Try to fix it by resetting the adapter. 981 */ 982 if (status & IM_EPH_INT) { 983 snstop(sc); 984 sninit_locked(sc); 985 } 986 987out: 988 /* 989 * Handled all interrupt sources. 990 */ 991 992 SMC_SELECT_BANK(sc, 2); 993 994 /* 995 * Reestablish interrupts from mask which have not been deselected 996 * during this interrupt. Note that the hardware mask, which was set 997 * to 0x00 at the start of this service routine, may have been 998 * updated by one or more of the interrupt handers and we must let 999 * those new interrupts stay enabled here. 1000 */ 1001 mask |= CSR_READ_1(sc, INTR_MASK_REG_B); 1002 CSR_WRITE_1(sc, INTR_MASK_REG_B, mask); 1003 sc->intr_mask = mask; 1004 SN_UNLOCK(sc); 1005} 1006 1007static void 1008snread(struct ifnet *ifp) 1009{ 1010 struct sn_softc *sc = ifp->if_softc; 1011 struct ether_header *eh; 1012 struct mbuf *m; 1013 short status; 1014 int packet_number; 1015 uint16_t packet_length; 1016 uint8_t *data; 1017 1018 SMC_SELECT_BANK(sc, 2); 1019#if 0 1020 packet_number = CSR_READ_2(sc, FIFO_PORTS_REG_W); 1021 1022 if (packet_number & FIFO_REMPTY) { 1023 1024 /* 1025 * we got called , but nothing was on the FIFO 1026 */ 1027 printf("sn: Receive interrupt with nothing on FIFO\n"); 1028 return; 1029 } 1030#endif 1031read_another: 1032 1033 /* 1034 * Start reading from the start of the packet. Since PTR_RCV is set, 1035 * packet number is found in FIFO_PORTS_REG_W, FIFO_RX_MASK. 1036 */ 1037 CSR_WRITE_2(sc, POINTER_REG_W, PTR_READ | PTR_RCV | PTR_AUTOINC | 0x0000); 1038 1039 /* 1040 * First two words are status and packet_length 1041 */ 1042 status = CSR_READ_2(sc, DATA_REG_W); 1043 packet_length = CSR_READ_2(sc, DATA_REG_W) & RLEN_MASK; 1044 1045 /* 1046 * The packet length contains 3 extra words: status, length, and a 1047 * extra word with the control byte. 1048 */ 1049 packet_length -= 6; 1050 1051 /* 1052 * Account for receive errors and discard. 1053 */ 1054 if (status & RS_ERRORS) { 1055 ++sc->arpcom.ac_if.if_ierrors; 1056 goto out; 1057 } 1058 /* 1059 * A packet is received. 1060 */ 1061 1062 /* 1063 * Adjust for odd-length packet. 1064 */ 1065 if (status & RS_ODDFRAME) 1066 packet_length++; 1067 1068 /* 1069 * Allocate a header mbuf from the kernel. 1070 */ 1071 MGETHDR(m, M_DONTWAIT, MT_DATA); 1072 if (m == NULL) 1073 goto out; 1074 1075 m->m_pkthdr.rcvif = &sc->arpcom.ac_if; 1076 m->m_pkthdr.len = m->m_len = packet_length; 1077 1078 /* 1079 * Attach an mbuf cluster 1080 */ 1081 MCLGET(m, M_DONTWAIT); 1082 1083 /* 1084 * Insist on getting a cluster 1085 */ 1086 if ((m->m_flags & M_EXT) == 0) { 1087 m_freem(m); 1088 ++sc->arpcom.ac_if.if_ierrors; 1089 printf("sn: snread() kernel memory allocation problem\n"); 1090 goto out; 1091 } 1092 eh = mtod(m, struct ether_header *); 1093 1094 /* 1095 * Get packet, including link layer address, from interface. 1096 */ 1097 data = (uint8_t *) eh; 1098 CSR_READ_MULTI_2(sc, DATA_REG_W, (uint16_t *) data, packet_length >> 1); 1099 if (packet_length & 1) { 1100 data += packet_length & ~1; 1101 *data = CSR_READ_1(sc, DATA_REG_B); 1102 } 1103 ++sc->arpcom.ac_if.if_ipackets; 1104 1105 /* 1106 * Remove link layer addresses and whatnot. 1107 */ 1108 m->m_pkthdr.len = m->m_len = packet_length; 1109 1110 /* 1111 * Drop locks before calling if_input() since it may re-enter 1112 * snstart() in the netisr case. This would result in a 1113 * lock reversal. Better performance might be obtained by 1114 * chaining all packets received, dropping the lock, and then 1115 * calling if_input() on each one. 1116 */ 1117 SN_UNLOCK(sc); 1118 (*ifp->if_input)(ifp, m); 1119 SN_LOCK(sc); 1120 1121out: 1122 1123 /* 1124 * Error or good, tell the card to get rid of this packet Wait for 1125 * the MMU to be un-busy. 1126 */ 1127 SMC_SELECT_BANK(sc, 2); 1128 while (CSR_READ_2(sc, MMU_CMD_REG_W) & MMUCR_BUSY) /* NOTHING */ 1129 ; 1130 CSR_WRITE_2(sc, MMU_CMD_REG_W, MMUCR_RELEASE); 1131 1132 /* 1133 * Check whether another packet is ready 1134 */ 1135 packet_number = CSR_READ_2(sc, FIFO_PORTS_REG_W); 1136 if (packet_number & FIFO_REMPTY) { 1137 return; 1138 } 1139 goto read_another; 1140} 1141 1142 1143/* 1144 * Handle IOCTLS. This function is completely stolen from if_ep.c 1145 * As with its progenitor, it does not handle hardware address 1146 * changes. 1147 */ 1148static int 1149snioctl(struct ifnet *ifp, u_long cmd, caddr_t data) 1150{ 1151 struct sn_softc *sc = ifp->if_softc; 1152 int error = 0; 1153 1154 switch (cmd) { 1155 case SIOCSIFFLAGS: 1156 SN_LOCK(sc); 1157 if ((ifp->if_flags & IFF_UP) == 0 && ifp->if_flags & IFF_RUNNING) { 1158 ifp->if_flags &= ~IFF_RUNNING; 1159 snstop(sc); 1160 } else { 1161 /* reinitialize card on any parameter change */ 1162 sninit_locked(sc); 1163 } 1164 SN_UNLOCK(sc); 1165 break; 1166 1167#ifdef notdef 1168 case SIOCGHWADDR: 1169 bcopy((caddr_t) sc->sc_addr, (caddr_t) & ifr->ifr_data, 1170 sizeof(sc->sc_addr)); 1171 break; 1172#endif 1173 1174 case SIOCADDMULTI: 1175 /* update multicast filter list. */ 1176 SN_LOCK(sc); 1177 sn_setmcast(sc); 1178 error = 0; 1179 SN_UNLOCK(sc); 1180 break; 1181 case SIOCDELMULTI: 1182 /* update multicast filter list. */ 1183 SN_LOCK(sc); 1184 sn_setmcast(sc); 1185 error = 0; 1186 SN_UNLOCK(sc); 1187 break; 1188 default: 1189 error = EINVAL; 1190 error = ether_ioctl(ifp, cmd, data); 1191 break; 1192 } 1193 return (error); 1194} 1195 1196static void 1197snwatchdog(struct ifnet *ifp) 1198{ 1199 sn_intr(ifp->if_softc); 1200} 1201 1202 1203/* 1. zero the interrupt mask 1204 * 2. clear the enable receive flag 1205 * 3. clear the enable xmit flags 1206 */ 1207static void 1208snstop(struct sn_softc *sc) 1209{ 1210 1211 struct ifnet *ifp = &sc->arpcom.ac_if; 1212 1213 /* 1214 * Clear interrupt mask; disable all interrupts. 1215 */ 1216 SMC_SELECT_BANK(sc, 2); 1217 CSR_WRITE_1(sc, INTR_MASK_REG_B, 0x00); 1218 1219 /* 1220 * Disable transmitter and Receiver 1221 */ 1222 SMC_SELECT_BANK(sc, 0); 1223 CSR_WRITE_2(sc, RECV_CONTROL_REG_W, 0x0000); 1224 CSR_WRITE_2(sc, TXMIT_CONTROL_REG_W, 0x0000); 1225 1226 /* 1227 * Cancel watchdog. 1228 */ 1229 ifp->if_timer = 0; 1230} 1231 1232 1233int 1234sn_activate(device_t dev) 1235{ 1236 struct sn_softc *sc = device_get_softc(dev); 1237 1238 sc->port_rid = 0; 1239 sc->port_res = bus_alloc_resource(dev, SYS_RES_IOPORT, &sc->port_rid, 1240 0, ~0, SMC_IO_EXTENT, RF_ACTIVE); 1241 if (!sc->port_res) { 1242 if (bootverbose) 1243 device_printf(dev, "Cannot allocate ioport\n"); 1244 return ENOMEM; 1245 } 1246 1247 sc->irq_rid = 0; 1248 sc->irq_res = bus_alloc_resource(dev, SYS_RES_IRQ, &sc->irq_rid, 1249 0, ~0, 1, RF_ACTIVE); 1250 if (!sc->irq_res) { 1251 if (bootverbose) 1252 device_printf(dev, "Cannot allocate irq\n"); 1253 sn_deactivate(dev); 1254 return ENOMEM; 1255 } 1256 sc->bst = rman_get_bustag(sc->port_res); 1257 sc->bsh = rman_get_bushandle(sc->port_res); 1258 return (0); 1259} 1260 1261void 1262sn_deactivate(device_t dev) 1263{ 1264 struct sn_softc *sc = device_get_softc(dev); 1265 1266 if (sc->intrhand) 1267 bus_teardown_intr(dev, sc->irq_res, sc->intrhand); 1268 sc->intrhand = 0; 1269 if (sc->port_res) 1270 bus_release_resource(dev, SYS_RES_IOPORT, sc->port_rid, 1271 sc->port_res); 1272 sc->port_res = 0; 1273 if (sc->irq_res) 1274 bus_release_resource(dev, SYS_RES_IRQ, sc->irq_rid, 1275 sc->irq_res); 1276 sc->irq_res = 0; 1277 return; 1278} 1279 1280/* 1281 * Function: sn_probe( device_t dev, int pccard ) 1282 * 1283 * Purpose: 1284 * Tests to see if a given ioaddr points to an SMC9xxx chip. 1285 * Tries to cause as little damage as possible if it's not a SMC chip. 1286 * Returns a 0 on success 1287 * 1288 * Algorithm: 1289 * (1) see if the high byte of BANK_SELECT is 0x33 1290 * (2) compare the ioaddr with the base register's address 1291 * (3) see if I recognize the chip ID in the appropriate register 1292 * 1293 * 1294 */ 1295int 1296sn_probe(device_t dev, int pccard) 1297{ 1298 struct sn_softc *sc = device_get_softc(dev); 1299 uint16_t bank; 1300 uint16_t revision_register; 1301 uint16_t base_address_register; 1302 int err; 1303 1304 if ((err = sn_activate(dev)) != 0) 1305 return err; 1306 1307 /* 1308 * First, see if the high byte is 0x33 1309 */ 1310 bank = CSR_READ_2(sc, BANK_SELECT_REG_W); 1311 if ((bank & BSR_DETECT_MASK) != BSR_DETECT_VALUE) { 1312#ifdef SN_DEBUG 1313 device_printf(dev, "test1 failed\n"); 1314#endif 1315 goto error; 1316 } 1317 /* 1318 * The above MIGHT indicate a device, but I need to write to further 1319 * test this. Go to bank 0, then test that the register still 1320 * reports the high byte is 0x33. 1321 */ 1322 CSR_WRITE_2(sc, BANK_SELECT_REG_W, 0x0000); 1323 bank = CSR_READ_2(sc, BANK_SELECT_REG_W); 1324 if ((bank & BSR_DETECT_MASK) != BSR_DETECT_VALUE) { 1325#ifdef SN_DEBUG 1326 device_printf(dev, "test2 failed\n"); 1327#endif 1328 goto error; 1329 } 1330 /* 1331 * well, we've already written once, so hopefully another time won't 1332 * hurt. This time, I need to switch the bank register to bank 1, so 1333 * I can access the base address register. The contents of the 1334 * BASE_ADDR_REG_W register, after some jiggery pokery, is expected 1335 * to match the I/O port address where the adapter is being probed. 1336 */ 1337 CSR_WRITE_2(sc, BANK_SELECT_REG_W, 0x0001); 1338 base_address_register = (CSR_READ_2(sc, BASE_ADDR_REG_W) >> 3) & 0x3e0; 1339 1340 /* 1341 * This test is nonsence on PC-card architecture, so if 1342 * pccard == 1, skip this test. (hosokawa) 1343 */ 1344 if (!pccard && rman_get_start(sc->port_res) != base_address_register) { 1345 1346 /* 1347 * Well, the base address register didn't match. Must not 1348 * have been a SMC chip after all. 1349 */ 1350#ifdef SN_DEBUG 1351 device_printf(dev, "test3 failed ioaddr = 0x%x, " 1352 "base_address_register = 0x%x\n", 1353 rman_get_start(sc->port_res), base_address_register); 1354#endif 1355 goto error; 1356 } 1357 1358 /* 1359 * Check if the revision register is something that I recognize. 1360 * These might need to be added to later, as future revisions could 1361 * be added. 1362 */ 1363 CSR_WRITE_2(sc, BANK_SELECT_REG_W, 0x3); 1364 revision_register = CSR_READ_2(sc, REVISION_REG_W); 1365 if (!chip_ids[(revision_register >> 4) & 0xF]) { 1366 1367 /* 1368 * I don't regonize this chip, so... 1369 */ 1370#ifdef SN_DEBUG 1371 device_printf(dev, "test4 failed\n"); 1372#endif 1373 goto error; 1374 } 1375 1376 /* 1377 * at this point I'll assume that the chip is an SMC9xxx. It might be 1378 * prudent to check a listing of MAC addresses against the hardware 1379 * address, or do some other tests. 1380 */ 1381 sn_deactivate(dev); 1382 return 0; 1383 error: 1384 sn_deactivate(dev); 1385 return ENXIO; 1386} 1387 1388#define MCFSZ 8 1389 1390static void 1391sn_setmcast(struct sn_softc *sc) 1392{ 1393 struct ifnet *ifp = (struct ifnet *)sc; 1394 int flags; 1395 uint8_t mcf[MCFSZ]; 1396 1397 SN_ASSERT_LOCKED(sc); 1398 1399 /* 1400 * Set the receiver filter. We want receive enabled and auto strip 1401 * of CRC from received packet. If we are promiscuous then set that 1402 * bit too. 1403 */ 1404 flags = RCR_ENABLE | RCR_STRIP_CRC; 1405 1406 if (ifp->if_flags & IFF_PROMISC) { 1407 flags |= RCR_PROMISC | RCR_ALMUL; 1408 } else if (ifp->if_flags & IFF_ALLMULTI) { 1409 flags |= RCR_ALMUL; 1410 } else { 1411 if (sn_getmcf(&sc->arpcom, mcf)) { 1412 /* set filter */ 1413 SMC_SELECT_BANK(sc, 3); 1414 CSR_WRITE_2(sc, MULTICAST1_REG_W, 1415 ((uint16_t)mcf[1] << 8) | mcf[0]); 1416 CSR_WRITE_2(sc, MULTICAST2_REG_W, 1417 ((uint16_t)mcf[3] << 8) | mcf[2]); 1418 CSR_WRITE_2(sc, MULTICAST3_REG_W, 1419 ((uint16_t)mcf[5] << 8) | mcf[4]); 1420 CSR_WRITE_2(sc, MULTICAST4_REG_W, 1421 ((uint16_t)mcf[7] << 8) | mcf[6]); 1422 } else { 1423 flags |= RCR_ALMUL; 1424 } 1425 } 1426 SMC_SELECT_BANK(sc, 0); 1427 CSR_WRITE_2(sc, RECV_CONTROL_REG_W, flags); 1428} 1429 1430static int 1431sn_getmcf(struct arpcom *ac, uint8_t *mcf) 1432{ 1433 int i; 1434 uint32_t index, index2; 1435 uint8_t *af = mcf; 1436 struct ifmultiaddr *ifma; 1437 1438 bzero(mcf, MCFSZ); 1439 1440 TAILQ_FOREACH(ifma, &ac->ac_if.if_multiaddrs, ifma_link) { 1441 if (ifma->ifma_addr->sa_family != AF_LINK) 1442 return 0; 1443 index = sn_mchash( 1444 LLADDR((struct sockaddr_dl *)ifma->ifma_addr)) & 0x3f; 1445 index2 = 0; 1446 for (i = 0; i < 6; i++) { 1447 index2 <<= 1; 1448 index2 |= (index & 0x01); 1449 index >>= 1; 1450 } 1451 af[index2 >> 3] |= 1 << (index2 & 7); 1452 } 1453 return 1; /* use multicast filter */ 1454} 1455 1456static u_int32_t 1457sn_mchash(caddr_t addr) 1458{ 1459 const uint32_t poly = 0xedb88320; 1460 u_int32_t crc; 1461 int idx, bit; 1462 u_int8_t data; 1463 1464 /* Compute CRC for the address value. */ 1465 crc = 0xFFFFFFFF; /* initial value */ 1466 1467 for (idx = 0; idx < ETHER_ADDR_LEN; idx++) { 1468 for (data = *addr++, bit = 0; bit < 8; bit++, data >>= 1) { 1469 crc = (crc >> 1)^(((crc ^ data) & 0x01) ? poly : 0); 1470 } 1471 } 1472 return crc; 1473} 1474