sio.c revision 85426
1/*- 2 * Copyright (c) 1991 The Regents of the University of California. 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 3. All advertising materials mentioning features or use of this software 14 * must display the following acknowledgement: 15 * This product includes software developed by the University of 16 * California, Berkeley and its contributors. 17 * 4. Neither the name of the University nor the names of its contributors 18 * may be used to endorse or promote products derived from this software 19 * without specific prior written permission. 20 * 21 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 22 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 23 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 24 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 25 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 26 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 27 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 28 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 29 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 30 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 31 * SUCH DAMAGE. 32 * 33 * $FreeBSD: head/sys/dev/sio/sio.c 85426 2001-10-24 18:30:05Z jlemon $ 34 * from: @(#)com.c 7.5 (Berkeley) 5/16/91 35 * from: i386/isa sio.c,v 1.234 36 */ 37 38#include "opt_comconsole.h" 39#include "opt_compat.h" 40#include "opt_ddb.h" 41#include "opt_sio.h" 42 43/* 44 * Serial driver, based on 386BSD-0.1 com driver. 45 * Mostly rewritten to use pseudo-DMA. 46 * Works for National Semiconductor NS8250-NS16550AF UARTs. 47 * COM driver, based on HP dca driver. 48 * 49 * Changes for PC-Card integration: 50 * - Added PC-Card driver table and handlers 51 */ 52#include <sys/param.h> 53#include <sys/systm.h> 54#include <sys/bus.h> 55#include <sys/conf.h> 56#include <sys/dkstat.h> 57#include <sys/fcntl.h> 58#include <sys/interrupt.h> 59#include <sys/kernel.h> 60#include <sys/lock.h> 61#include <sys/malloc.h> 62#include <sys/module.h> 63#include <sys/mutex.h> 64#include <sys/proc.h> 65#include <sys/reboot.h> 66#include <sys/sysctl.h> 67#include <sys/syslog.h> 68#include <sys/tty.h> 69#include <machine/bus_pio.h> 70#include <machine/bus.h> 71#include <sys/rman.h> 72#include <sys/timetc.h> 73#include <sys/timepps.h> 74 75#include <machine/clock.h> 76#include <machine/resource.h> 77 78#include <dev/sio/sioreg.h> 79#include <dev/sio/siovar.h> 80 81#include <isa/isavar.h> 82 83#ifdef COM_ESP 84#include <dev/ic/esp.h> 85#endif 86#include <dev/ic/ns16550.h> 87 88#define LOTS_OF_EVENTS 64 /* helps separate urgent events from input */ 89 90#define CALLOUT_MASK 0x80 91#define CONTROL_MASK 0x60 92#define CONTROL_INIT_STATE 0x20 93#define CONTROL_LOCK_STATE 0x40 94#define DEV_TO_UNIT(dev) (MINOR_TO_UNIT(minor(dev))) 95#define MINOR_MAGIC_MASK (CALLOUT_MASK | CONTROL_MASK) 96#define MINOR_TO_UNIT(mynor) ((mynor) & ~MINOR_MAGIC_MASK) 97 98#ifdef COM_MULTIPORT 99/* checks in flags for multiport and which is multiport "master chip" 100 * for a given card 101 */ 102#define COM_ISMULTIPORT(flags) ((flags) & 0x01) 103#define COM_MPMASTER(flags) (((flags) >> 8) & 0x0ff) 104#define COM_NOTAST4(flags) ((flags) & 0x04) 105#endif /* COM_MULTIPORT */ 106 107#define COM_CONSOLE(flags) ((flags) & 0x10) 108#define COM_FORCECONSOLE(flags) ((flags) & 0x20) 109#define COM_LLCONSOLE(flags) ((flags) & 0x40) 110#define COM_DEBUGGER(flags) ((flags) & 0x80) 111#define COM_LOSESOUTINTS(flags) ((flags) & 0x08) 112#define COM_NOFIFO(flags) ((flags) & 0x02) 113#define COM_ST16650A(flags) ((flags) & 0x20000) 114#define COM_C_IIR_TXRDYBUG (0x80000) 115#define COM_IIR_TXRDYBUG(flags) ((flags) & COM_C_IIR_TXRDYBUG) 116#define COM_FIFOSIZE(flags) (((flags) & 0xff000000) >> 24) 117 118#define com_scr 7 /* scratch register for 16450-16550 (R/W) */ 119 120#define sio_getreg(com, off) \ 121 (bus_space_read_1((com)->bst, (com)->bsh, (off))) 122#define sio_setreg(com, off, value) \ 123 (bus_space_write_1((com)->bst, (com)->bsh, (off), (value))) 124 125/* 126 * com state bits. 127 * (CS_BUSY | CS_TTGO) and (CS_BUSY | CS_TTGO | CS_ODEVREADY) must be higher 128 * than the other bits so that they can be tested as a group without masking 129 * off the low bits. 130 * 131 * The following com and tty flags correspond closely: 132 * CS_BUSY = TS_BUSY (maintained by comstart(), siopoll() and 133 * comstop()) 134 * CS_TTGO = ~TS_TTSTOP (maintained by comparam() and comstart()) 135 * CS_CTS_OFLOW = CCTS_OFLOW (maintained by comparam()) 136 * CS_RTS_IFLOW = CRTS_IFLOW (maintained by comparam()) 137 * TS_FLUSH is not used. 138 * XXX I think TIOCSETA doesn't clear TS_TTSTOP when it clears IXON. 139 * XXX CS_*FLOW should be CF_*FLOW in com->flags (control flags not state). 140 */ 141#define CS_BUSY 0x80 /* output in progress */ 142#define CS_TTGO 0x40 /* output not stopped by XOFF */ 143#define CS_ODEVREADY 0x20 /* external device h/w ready (CTS) */ 144#define CS_CHECKMSR 1 /* check of MSR scheduled */ 145#define CS_CTS_OFLOW 2 /* use CTS output flow control */ 146#define CS_DTR_OFF 0x10 /* DTR held off */ 147#define CS_ODONE 4 /* output completed */ 148#define CS_RTS_IFLOW 8 /* use RTS input flow control */ 149#define CSE_BUSYCHECK 1 /* siobusycheck() scheduled */ 150 151static char const * const error_desc[] = { 152#define CE_OVERRUN 0 153 "silo overflow", 154#define CE_INTERRUPT_BUF_OVERFLOW 1 155 "interrupt-level buffer overflow", 156#define CE_TTY_BUF_OVERFLOW 2 157 "tty-level buffer overflow", 158}; 159 160#define CE_RECORD(com, errnum) (++(com)->delta_error_counts[errnum]) 161 162#ifdef COM_ESP 163static int espattach __P((struct com_s *com, Port_t esp_port)); 164#endif 165 166static timeout_t siobusycheck; 167static timeout_t siodtrwakeup; 168static void comhardclose __P((struct com_s *com)); 169static void sioinput __P((struct com_s *com)); 170static void siointr1 __P((struct com_s *com)); 171static void siointr __P((void *arg)); 172static int commctl __P((struct com_s *com, int bits, int how)); 173static int comparam __P((struct tty *tp, struct termios *t)); 174static void siopoll __P((void *)); 175static void siosettimeout __P((void)); 176static int siosetwater __P((struct com_s *com, speed_t speed)); 177static void comstart __P((struct tty *tp)); 178static void comstop __P((struct tty *tp, int rw)); 179static timeout_t comwakeup; 180static void disc_optim __P((struct tty *tp, struct termios *t, 181 struct com_s *com)); 182 183char sio_driver_name[] = "sio"; 184static struct mtx sio_lock; 185static int sio_inited; 186 187/* table and macro for fast conversion from a unit number to its com struct */ 188devclass_t sio_devclass; 189#define com_addr(unit) ((struct com_s *) \ 190 devclass_get_softc(sio_devclass, unit)) 191 192static d_open_t sioopen; 193static d_close_t sioclose; 194static d_read_t sioread; 195static d_write_t siowrite; 196static d_ioctl_t sioioctl; 197 198#define CDEV_MAJOR 28 199static struct cdevsw sio_cdevsw = { 200 /* open */ sioopen, 201 /* close */ sioclose, 202 /* read */ sioread, 203 /* write */ siowrite, 204 /* ioctl */ sioioctl, 205 /* poll */ ttypoll, 206 /* mmap */ nommap, 207 /* strategy */ nostrategy, 208 /* name */ sio_driver_name, 209 /* maj */ CDEV_MAJOR, 210 /* dump */ nodump, 211 /* psize */ nopsize, 212 /* flags */ D_TTY | D_KQFILTER, 213 /* kqfilter */ ttykqfilter, 214}; 215 216int comconsole = -1; 217static volatile speed_t comdefaultrate = CONSPEED; 218#ifdef __alpha__ 219static volatile speed_t gdbdefaultrate = CONSPEED; 220#endif 221static u_int com_events; /* input chars + weighted output completions */ 222static Port_t siocniobase; 223#ifndef __alpha__ 224static int siocnunit; 225#endif 226static Port_t siogdbiobase; 227static int siogdbunit = -1; 228static void *sio_slow_ih; 229static void *sio_fast_ih; 230static int sio_timeout; 231static int sio_timeouts_until_log; 232static struct callout_handle sio_timeout_handle 233 = CALLOUT_HANDLE_INITIALIZER(&sio_timeout_handle); 234static int sio_numunits; 235 236static struct speedtab comspeedtab[] = { 237 { 0, 0 }, 238 { 50, COMBRD(50) }, 239 { 75, COMBRD(75) }, 240 { 110, COMBRD(110) }, 241 { 134, COMBRD(134) }, 242 { 150, COMBRD(150) }, 243 { 200, COMBRD(200) }, 244 { 300, COMBRD(300) }, 245 { 600, COMBRD(600) }, 246 { 1200, COMBRD(1200) }, 247 { 1800, COMBRD(1800) }, 248 { 2400, COMBRD(2400) }, 249 { 4800, COMBRD(4800) }, 250 { 9600, COMBRD(9600) }, 251 { 19200, COMBRD(19200) }, 252 { 28800, COMBRD(28800) }, 253 { 38400, COMBRD(38400) }, 254 { 57600, COMBRD(57600) }, 255 { 115200, COMBRD(115200) }, 256 { -1, -1 } 257}; 258 259#ifdef COM_ESP 260/* XXX configure this properly. */ 261static Port_t likely_com_ports[] = { 0x3f8, 0x2f8, 0x3e8, 0x2e8, }; 262static Port_t likely_esp_ports[] = { 0x140, 0x180, 0x280, 0 }; 263#endif 264 265/* 266 * handle sysctl read/write requests for console speed 267 * 268 * In addition to setting comdefaultrate for I/O through /dev/console, 269 * also set the initial and lock values for the /dev/ttyXX device 270 * if there is one associated with the console. Finally, if the /dev/tty 271 * device has already been open, change the speed on the open running port 272 * itself. 273 */ 274 275static int 276sysctl_machdep_comdefaultrate(SYSCTL_HANDLER_ARGS) 277{ 278 int error, s; 279 speed_t newspeed; 280 struct com_s *com; 281 struct tty *tp; 282 283 newspeed = comdefaultrate; 284 285 error = sysctl_handle_opaque(oidp, &newspeed, sizeof newspeed, req); 286 if (error || !req->newptr) 287 return (error); 288 289 comdefaultrate = newspeed; 290 291 if (comconsole < 0) /* serial console not selected? */ 292 return (0); 293 294 com = com_addr(comconsole); 295 if (com == NULL) 296 return (ENXIO); 297 298 /* 299 * set the initial and lock rates for /dev/ttydXX and /dev/cuaXX 300 * (note, the lock rates really are boolean -- if non-zero, disallow 301 * speed changes) 302 */ 303 com->it_in.c_ispeed = com->it_in.c_ospeed = 304 com->lt_in.c_ispeed = com->lt_in.c_ospeed = 305 com->it_out.c_ispeed = com->it_out.c_ospeed = 306 com->lt_out.c_ispeed = com->lt_out.c_ospeed = comdefaultrate; 307 308 /* 309 * if we're open, change the running rate too 310 */ 311 tp = com->tp; 312 if (tp && (tp->t_state & TS_ISOPEN)) { 313 tp->t_termios.c_ispeed = 314 tp->t_termios.c_ospeed = comdefaultrate; 315 s = spltty(); 316 error = comparam(tp, &tp->t_termios); 317 splx(s); 318 } 319 return error; 320} 321 322SYSCTL_PROC(_machdep, OID_AUTO, conspeed, CTLTYPE_INT | CTLFLAG_RW, 323 0, 0, sysctl_machdep_comdefaultrate, "I", ""); 324 325int 326siodetach(dev) 327 device_t dev; 328{ 329 struct com_s *com; 330 int i; 331 332 com = (struct com_s *) device_get_softc(dev); 333 if (com == NULL) { 334 device_printf(dev, "NULL com in siounload\n"); 335 return (0); 336 } 337 com->gone = 1; 338 for (i = 0 ; i < 6; i++) 339 destroy_dev(com->devs[i]); 340 if (com->irqres) { 341 bus_teardown_intr(dev, com->irqres, com->cookie); 342 bus_release_resource(dev, SYS_RES_IRQ, 0, com->irqres); 343 } 344 if (com->ioportres) 345 bus_release_resource(dev, SYS_RES_IOPORT, 0, com->ioportres); 346 if (com->tp && (com->tp->t_state & TS_ISOPEN)) { 347 device_printf(dev, "still open, forcing close\n"); 348 (*linesw[com->tp->t_line].l_close)(com->tp, 0); 349 com->tp->t_gen++; 350 ttyclose(com->tp); 351 ttwakeup(com->tp); 352 ttwwakeup(com->tp); 353 } else { 354 if (com->ibuf != NULL) 355 free(com->ibuf, M_DEVBUF); 356 } 357 return (0); 358} 359 360int 361sioprobe(dev, xrid, noprobe) 362 device_t dev; 363 int xrid; 364 int noprobe; 365{ 366#if 0 367 static bool_t already_init; 368 device_t xdev; 369#endif 370 struct com_s *com; 371 bool_t failures[10]; 372 int fn; 373 device_t idev; 374 Port_t iobase; 375 intrmask_t irqmap[4]; 376 intrmask_t irqs; 377 u_char mcr_image; 378 int result; 379 u_long xirq; 380 u_int flags = device_get_flags(dev); 381 int rid; 382 struct resource *port; 383 384 rid = xrid; 385 port = bus_alloc_resource(dev, SYS_RES_IOPORT, &rid, 386 0, ~0, IO_COMSIZE, RF_ACTIVE); 387 if (!port) 388 return (ENXIO); 389 390 com = device_get_softc(dev); 391 com->bst = rman_get_bustag(port); 392 com->bsh = rman_get_bushandle(port); 393 394 while (sio_inited != 2) 395 if (atomic_cmpset_int(&sio_inited, 0, 1)) { 396 mtx_init(&sio_lock, sio_driver_name, (comconsole != -1) ? 397 MTX_SPIN | MTX_QUIET : MTX_SPIN); 398 atomic_store_rel_int(&sio_inited, 2); 399 } 400 401#if 0 402 /* 403 * XXX this is broken - when we are first called, there are no 404 * previously configured IO ports. We could hard code 405 * 0x3f8, 0x2f8, 0x3e8, 0x2e8 etc but that's probably worse. 406 * This code has been doing nothing since the conversion since 407 * "count" is zero the first time around. 408 */ 409 if (!already_init) { 410 /* 411 * Turn off MCR_IENABLE for all likely serial ports. An unused 412 * port with its MCR_IENABLE gate open will inhibit interrupts 413 * from any used port that shares the interrupt vector. 414 * XXX the gate enable is elsewhere for some multiports. 415 */ 416 device_t *devs; 417 int count, i, xioport; 418 419 devclass_get_devices(sio_devclass, &devs, &count); 420 for (i = 0; i < count; i++) { 421 xdev = devs[i]; 422 if (device_is_enabled(xdev) && 423 bus_get_resource(xdev, SYS_RES_IOPORT, 0, &xioport, 424 NULL) == 0) 425 outb(xioport + com_mcr, 0); 426 } 427 free(devs, M_TEMP); 428 already_init = TRUE; 429 } 430#endif 431 432 if (COM_LLCONSOLE(flags)) { 433 printf("sio%d: reserved for low-level i/o\n", 434 device_get_unit(dev)); 435 bus_release_resource(dev, SYS_RES_IOPORT, rid, port); 436 return (ENXIO); 437 } 438 439 /* 440 * If the device is on a multiport card and has an AST/4 441 * compatible interrupt control register, initialize this 442 * register and prepare to leave MCR_IENABLE clear in the mcr. 443 * Otherwise, prepare to set MCR_IENABLE in the mcr. 444 * Point idev to the device struct giving the correct id_irq. 445 * This is the struct for the master device if there is one. 446 */ 447 idev = dev; 448 mcr_image = MCR_IENABLE; 449#ifdef COM_MULTIPORT 450 if (COM_ISMULTIPORT(flags)) { 451 Port_t xiobase; 452 u_long io; 453 454 idev = devclass_get_device(sio_devclass, COM_MPMASTER(flags)); 455 if (idev == NULL) { 456 printf("sio%d: master device %d not configured\n", 457 device_get_unit(dev), COM_MPMASTER(flags)); 458 idev = dev; 459 } 460 if (!COM_NOTAST4(flags)) { 461 if (bus_get_resource(idev, SYS_RES_IOPORT, 0, &io, 462 NULL) == 0) { 463 xiobase = io; 464 if (bus_get_resource(idev, SYS_RES_IRQ, 0, 465 NULL, NULL) == 0) 466 outb(xiobase + com_scr, 0x80); 467 else 468 outb(xiobase + com_scr, 0); 469 } 470 mcr_image = 0; 471 } 472 } 473#endif /* COM_MULTIPORT */ 474 if (bus_get_resource(idev, SYS_RES_IRQ, 0, NULL, NULL) != 0) 475 mcr_image = 0; 476 477 bzero(failures, sizeof failures); 478 iobase = rman_get_start(port); 479 480 /* 481 * We don't want to get actual interrupts, just masked ones. 482 * Interrupts from this line should already be masked in the ICU, 483 * but mask them in the processor as well in case there are some 484 * (misconfigured) shared interrupts. 485 */ 486 mtx_lock_spin(&sio_lock); 487/* EXTRA DELAY? */ 488 489 /* 490 * Initialize the speed and the word size and wait long enough to 491 * drain the maximum of 16 bytes of junk in device output queues. 492 * The speed is undefined after a master reset and must be set 493 * before relying on anything related to output. There may be 494 * junk after a (very fast) soft reboot and (apparently) after 495 * master reset. 496 * XXX what about the UART bug avoided by waiting in comparam()? 497 * We don't want to to wait long enough to drain at 2 bps. 498 */ 499 if (iobase == siocniobase) 500 DELAY((16 + 1) * 1000000 / (comdefaultrate / 10)); 501 else { 502 sio_setreg(com, com_cfcr, CFCR_DLAB | CFCR_8BITS); 503 sio_setreg(com, com_dlbl, COMBRD(SIO_TEST_SPEED) & 0xff); 504 sio_setreg(com, com_dlbh, (u_int) COMBRD(SIO_TEST_SPEED) >> 8); 505 sio_setreg(com, com_cfcr, CFCR_8BITS); 506 DELAY((16 + 1) * 1000000 / (SIO_TEST_SPEED / 10)); 507 } 508 509 /* 510 * Enable the interrupt gate and disable device interupts. This 511 * should leave the device driving the interrupt line low and 512 * guarantee an edge trigger if an interrupt can be generated. 513 */ 514/* EXTRA DELAY? */ 515 sio_setreg(com, com_mcr, mcr_image); 516 sio_setreg(com, com_ier, 0); 517 DELAY(1000); /* XXX */ 518 irqmap[0] = isa_irq_pending(); 519 520 /* 521 * Attempt to set loopback mode so that we can send a null byte 522 * without annoying any external device. 523 */ 524/* EXTRA DELAY? */ 525 sio_setreg(com, com_mcr, mcr_image | MCR_LOOPBACK); 526 527 /* 528 * Attempt to generate an output interrupt. On 8250's, setting 529 * IER_ETXRDY generates an interrupt independent of the current 530 * setting and independent of whether the THR is empty. On 16450's, 531 * setting IER_ETXRDY generates an interrupt independent of the 532 * current setting. On 16550A's, setting IER_ETXRDY only 533 * generates an interrupt when IER_ETXRDY is not already set. 534 */ 535 sio_setreg(com, com_ier, IER_ETXRDY); 536 537 /* 538 * On some 16x50 incompatibles, setting IER_ETXRDY doesn't generate 539 * an interrupt. They'd better generate one for actually doing 540 * output. Loopback may be broken on the same incompatibles but 541 * it's unlikely to do more than allow the null byte out. 542 */ 543 sio_setreg(com, com_data, 0); 544 DELAY((1 + 2) * 1000000 / (SIO_TEST_SPEED / 10)); 545 546 /* 547 * Turn off loopback mode so that the interrupt gate works again 548 * (MCR_IENABLE was hidden). This should leave the device driving 549 * an interrupt line high. It doesn't matter if the interrupt 550 * line oscillates while we are not looking at it, since interrupts 551 * are disabled. 552 */ 553/* EXTRA DELAY? */ 554 sio_setreg(com, com_mcr, mcr_image); 555 556 /* 557 * Some pcmcia cards have the "TXRDY bug", so we check everyone 558 * for IIR_TXRDY implementation ( Palido 321s, DC-1S... ) 559 */ 560 if (noprobe) { 561 /* Reading IIR register twice */ 562 for (fn = 0; fn < 2; fn ++) { 563 DELAY(10000); 564 failures[6] = sio_getreg(com, com_iir); 565 } 566 /* Check IIR_TXRDY clear ? */ 567 result = 0; 568 if (failures[6] & IIR_TXRDY) { 569 /* Nop, Double check with clearing IER */ 570 sio_setreg(com, com_ier, 0); 571 if (sio_getreg(com, com_iir) & IIR_NOPEND) { 572 /* Ok. we're familia this gang */ 573 SET_FLAG(dev, COM_C_IIR_TXRDYBUG); 574 } else { 575 /* Unknown, Just omit this chip.. XXX */ 576 result = ENXIO; 577 sio_setreg(com, com_mcr, 0); 578 } 579 } else { 580 /* OK. this is well-known guys */ 581 CLR_FLAG(dev, COM_C_IIR_TXRDYBUG); 582 } 583 sio_setreg(com, com_ier, 0); 584 sio_setreg(com, com_cfcr, CFCR_8BITS); 585 mtx_unlock_spin(&sio_lock); 586 bus_release_resource(dev, SYS_RES_IOPORT, rid, port); 587 return (iobase == siocniobase ? 0 : result); 588 } 589 590 /* 591 * Check that 592 * o the CFCR, IER and MCR in UART hold the values written to them 593 * (the values happen to be all distinct - this is good for 594 * avoiding false positive tests from bus echoes). 595 * o an output interrupt is generated and its vector is correct. 596 * o the interrupt goes away when the IIR in the UART is read. 597 */ 598/* EXTRA DELAY? */ 599 failures[0] = sio_getreg(com, com_cfcr) - CFCR_8BITS; 600 failures[1] = sio_getreg(com, com_ier) - IER_ETXRDY; 601 failures[2] = sio_getreg(com, com_mcr) - mcr_image; 602 DELAY(10000); /* Some internal modems need this time */ 603 irqmap[1] = isa_irq_pending(); 604 failures[4] = (sio_getreg(com, com_iir) & IIR_IMASK) - IIR_TXRDY; 605 DELAY(1000); /* XXX */ 606 irqmap[2] = isa_irq_pending(); 607 failures[6] = (sio_getreg(com, com_iir) & IIR_IMASK) - IIR_NOPEND; 608 609 /* 610 * Turn off all device interrupts and check that they go off properly. 611 * Leave MCR_IENABLE alone. For ports without a master port, it gates 612 * the OUT2 output of the UART to 613 * the ICU input. Closing the gate would give a floating ICU input 614 * (unless there is another device driving it) and spurious interrupts. 615 * (On the system that this was first tested on, the input floats high 616 * and gives a (masked) interrupt as soon as the gate is closed.) 617 */ 618 sio_setreg(com, com_ier, 0); 619 sio_setreg(com, com_cfcr, CFCR_8BITS); /* dummy to avoid bus echo */ 620 failures[7] = sio_getreg(com, com_ier); 621 DELAY(1000); /* XXX */ 622 irqmap[3] = isa_irq_pending(); 623 failures[9] = (sio_getreg(com, com_iir) & IIR_IMASK) - IIR_NOPEND; 624 625 mtx_unlock_spin(&sio_lock); 626 627 irqs = irqmap[1] & ~irqmap[0]; 628 if (bus_get_resource(idev, SYS_RES_IRQ, 0, &xirq, NULL) == 0 && 629 ((1 << xirq) & irqs) == 0) 630 printf( 631 "sio%d: configured irq %ld not in bitmap of probed irqs %#x\n", 632 device_get_unit(dev), xirq, irqs); 633 if (bootverbose) 634 printf("sio%d: irq maps: %#x %#x %#x %#x\n", 635 device_get_unit(dev), 636 irqmap[0], irqmap[1], irqmap[2], irqmap[3]); 637 638 result = 0; 639 for (fn = 0; fn < sizeof failures; ++fn) 640 if (failures[fn]) { 641 sio_setreg(com, com_mcr, 0); 642 result = ENXIO; 643 if (bootverbose) { 644 printf("sio%d: probe failed test(s):", 645 device_get_unit(dev)); 646 for (fn = 0; fn < sizeof failures; ++fn) 647 if (failures[fn]) 648 printf(" %d", fn); 649 printf("\n"); 650 } 651 break; 652 } 653 bus_release_resource(dev, SYS_RES_IOPORT, rid, port); 654 return (iobase == siocniobase ? 0 : result); 655} 656 657#ifdef COM_ESP 658static int 659espattach(com, esp_port) 660 struct com_s *com; 661 Port_t esp_port; 662{ 663 u_char dips; 664 u_char val; 665 666 /* 667 * Check the ESP-specific I/O port to see if we're an ESP 668 * card. If not, return failure immediately. 669 */ 670 if ((inb(esp_port) & 0xf3) == 0) { 671 printf(" port 0x%x is not an ESP board?\n", esp_port); 672 return (0); 673 } 674 675 /* 676 * We've got something that claims to be a Hayes ESP card. 677 * Let's hope so. 678 */ 679 680 /* Get the dip-switch configuration */ 681 outb(esp_port + ESP_CMD1, ESP_GETDIPS); 682 dips = inb(esp_port + ESP_STATUS1); 683 684 /* 685 * Bits 0,1 of dips say which COM port we are. 686 */ 687 if (rman_get_start(com->ioportres) == likely_com_ports[dips & 0x03]) 688 printf(" : ESP"); 689 else { 690 printf(" esp_port has com %d\n", dips & 0x03); 691 return (0); 692 } 693 694 /* 695 * Check for ESP version 2.0 or later: bits 4,5,6 = 010. 696 */ 697 outb(esp_port + ESP_CMD1, ESP_GETTEST); 698 val = inb(esp_port + ESP_STATUS1); /* clear reg 1 */ 699 val = inb(esp_port + ESP_STATUS2); 700 if ((val & 0x70) < 0x20) { 701 printf("-old (%o)", val & 0x70); 702 return (0); 703 } 704 705 /* 706 * Check for ability to emulate 16550: bit 7 == 1 707 */ 708 if ((dips & 0x80) == 0) { 709 printf(" slave"); 710 return (0); 711 } 712 713 /* 714 * Okay, we seem to be a Hayes ESP card. Whee. 715 */ 716 com->esp = TRUE; 717 com->esp_port = esp_port; 718 return (1); 719} 720#endif /* COM_ESP */ 721 722int 723sioattach(dev, xrid) 724 device_t dev; 725 int xrid; 726{ 727 struct com_s *com; 728#ifdef COM_ESP 729 Port_t *espp; 730#endif 731 Port_t iobase; 732 int unit; 733 u_int flags; 734 int rid; 735 struct resource *port; 736 int ret; 737 738 rid = xrid; 739 port = bus_alloc_resource(dev, SYS_RES_IOPORT, &rid, 740 0, ~0, IO_COMSIZE, RF_ACTIVE); 741 if (!port) 742 return (ENXIO); 743 744 iobase = rman_get_start(port); 745 unit = device_get_unit(dev); 746 com = device_get_softc(dev); 747 flags = device_get_flags(dev); 748 749 if (unit >= sio_numunits) 750 sio_numunits = unit + 1; 751 /* 752 * sioprobe() has initialized the device registers as follows: 753 * o cfcr = CFCR_8BITS. 754 * It is most important that CFCR_DLAB is off, so that the 755 * data port is not hidden when we enable interrupts. 756 * o ier = 0. 757 * Interrupts are only enabled when the line is open. 758 * o mcr = MCR_IENABLE, or 0 if the port has AST/4 compatible 759 * interrupt control register or the config specifies no irq. 760 * Keeping MCR_DTR and MCR_RTS off might stop the external 761 * device from sending before we are ready. 762 */ 763 bzero(com, sizeof *com); 764 com->unit = unit; 765 com->ioportres = port; 766 com->bst = rman_get_bustag(port); 767 com->bsh = rman_get_bushandle(port); 768 com->cfcr_image = CFCR_8BITS; 769 com->dtr_wait = 3 * hz; 770 com->loses_outints = COM_LOSESOUTINTS(flags) != 0; 771 com->no_irq = bus_get_resource(dev, SYS_RES_IRQ, 0, NULL, NULL) != 0; 772 com->tx_fifo_size = 1; 773 com->obufs[0].l_head = com->obuf1; 774 com->obufs[1].l_head = com->obuf2; 775 776 com->data_port = iobase + com_data; 777 com->int_id_port = iobase + com_iir; 778 com->modem_ctl_port = iobase + com_mcr; 779 com->mcr_image = inb(com->modem_ctl_port); 780 com->line_status_port = iobase + com_lsr; 781 com->modem_status_port = iobase + com_msr; 782 com->intr_ctl_port = iobase + com_ier; 783 784 /* 785 * We don't use all the flags from <sys/ttydefaults.h> since they 786 * are only relevant for logins. It's important to have echo off 787 * initially so that the line doesn't start blathering before the 788 * echo flag can be turned off. 789 */ 790 com->it_in.c_iflag = 0; 791 com->it_in.c_oflag = 0; 792 com->it_in.c_cflag = TTYDEF_CFLAG; 793 com->it_in.c_lflag = 0; 794 if (unit == comconsole) { 795 com->it_in.c_iflag = TTYDEF_IFLAG; 796 com->it_in.c_oflag = TTYDEF_OFLAG; 797 com->it_in.c_cflag = TTYDEF_CFLAG | CLOCAL; 798 com->it_in.c_lflag = TTYDEF_LFLAG; 799 com->lt_out.c_cflag = com->lt_in.c_cflag = CLOCAL; 800 com->lt_out.c_ispeed = com->lt_out.c_ospeed = 801 com->lt_in.c_ispeed = com->lt_in.c_ospeed = 802 com->it_in.c_ispeed = com->it_in.c_ospeed = comdefaultrate; 803 } else 804 com->it_in.c_ispeed = com->it_in.c_ospeed = TTYDEF_SPEED; 805 if (siosetwater(com, com->it_in.c_ispeed) != 0) { 806 mtx_unlock_spin(&sio_lock); 807 /* 808 * Leave i/o resources allocated if this is a `cn'-level 809 * console, so that other devices can't snarf them. 810 */ 811 if (iobase != siocniobase) 812 bus_release_resource(dev, SYS_RES_IOPORT, rid, port); 813 return (ENOMEM); 814 } 815 mtx_unlock_spin(&sio_lock); 816 termioschars(&com->it_in); 817 com->it_out = com->it_in; 818 819 /* attempt to determine UART type */ 820 printf("sio%d: type", unit); 821 822 823#ifdef COM_MULTIPORT 824 if (!COM_ISMULTIPORT(flags) && !COM_IIR_TXRDYBUG(flags)) 825#else 826 if (!COM_IIR_TXRDYBUG(flags)) 827#endif 828 { 829 u_char scr; 830 u_char scr1; 831 u_char scr2; 832 833 scr = sio_getreg(com, com_scr); 834 sio_setreg(com, com_scr, 0xa5); 835 scr1 = sio_getreg(com, com_scr); 836 sio_setreg(com, com_scr, 0x5a); 837 scr2 = sio_getreg(com, com_scr); 838 sio_setreg(com, com_scr, scr); 839 if (scr1 != 0xa5 || scr2 != 0x5a) { 840 printf(" 8250"); 841 goto determined_type; 842 } 843 } 844 sio_setreg(com, com_fifo, FIFO_ENABLE | FIFO_RX_HIGH); 845 DELAY(100); 846 com->st16650a = 0; 847 switch (inb(com->int_id_port) & IIR_FIFO_MASK) { 848 case FIFO_RX_LOW: 849 printf(" 16450"); 850 break; 851 case FIFO_RX_MEDL: 852 printf(" 16450?"); 853 break; 854 case FIFO_RX_MEDH: 855 printf(" 16550?"); 856 break; 857 case FIFO_RX_HIGH: 858 if (COM_NOFIFO(flags)) { 859 printf(" 16550A fifo disabled"); 860 } else { 861 com->hasfifo = TRUE; 862 if (COM_ST16650A(flags)) { 863 com->st16650a = 1; 864 com->tx_fifo_size = 32; 865 printf(" ST16650A"); 866 } else { 867 com->tx_fifo_size = COM_FIFOSIZE(flags); 868 printf(" 16550A"); 869 } 870 } 871#ifdef COM_ESP 872 for (espp = likely_esp_ports; *espp != 0; espp++) 873 if (espattach(com, *espp)) { 874 com->tx_fifo_size = 1024; 875 break; 876 } 877#endif 878 if (!com->st16650a) { 879 if (!com->tx_fifo_size) 880 com->tx_fifo_size = 16; 881 else 882 printf(" lookalike with %d bytes FIFO", 883 com->tx_fifo_size); 884 } 885 886 break; 887 } 888 889#ifdef COM_ESP 890 if (com->esp) { 891 /* 892 * Set 16550 compatibility mode. 893 * We don't use the ESP_MODE_SCALE bit to increase the 894 * fifo trigger levels because we can't handle large 895 * bursts of input. 896 * XXX flow control should be set in comparam(), not here. 897 */ 898 outb(com->esp_port + ESP_CMD1, ESP_SETMODE); 899 outb(com->esp_port + ESP_CMD2, ESP_MODE_RTS | ESP_MODE_FIFO); 900 901 /* Set RTS/CTS flow control. */ 902 outb(com->esp_port + ESP_CMD1, ESP_SETFLOWTYPE); 903 outb(com->esp_port + ESP_CMD2, ESP_FLOW_RTS); 904 outb(com->esp_port + ESP_CMD2, ESP_FLOW_CTS); 905 906 /* Set flow-control levels. */ 907 outb(com->esp_port + ESP_CMD1, ESP_SETRXFLOW); 908 outb(com->esp_port + ESP_CMD2, HIBYTE(768)); 909 outb(com->esp_port + ESP_CMD2, LOBYTE(768)); 910 outb(com->esp_port + ESP_CMD2, HIBYTE(512)); 911 outb(com->esp_port + ESP_CMD2, LOBYTE(512)); 912 } 913#endif /* COM_ESP */ 914 sio_setreg(com, com_fifo, 0); 915determined_type: ; 916 917#ifdef COM_MULTIPORT 918 if (COM_ISMULTIPORT(flags)) { 919 device_t masterdev; 920 921 com->multiport = TRUE; 922 printf(" (multiport"); 923 if (unit == COM_MPMASTER(flags)) 924 printf(" master"); 925 printf(")"); 926 masterdev = devclass_get_device(sio_devclass, 927 COM_MPMASTER(flags)); 928 com->no_irq = (masterdev == NULL || bus_get_resource(masterdev, 929 SYS_RES_IRQ, 0, NULL, NULL) != 0); 930 } 931#endif /* COM_MULTIPORT */ 932 if (unit == comconsole) 933 printf(", console"); 934 if (COM_IIR_TXRDYBUG(flags)) 935 printf(" with a bogus IIR_TXRDY register"); 936 printf("\n"); 937 938 if (sio_fast_ih == NULL) { 939 swi_add(&tty_ithd, "tty:sio", siopoll, NULL, SWI_TTY, 0, 940 &sio_fast_ih); 941 swi_add(&clk_ithd, "tty:sio", siopoll, NULL, SWI_TTY, 0, 942 &sio_slow_ih); 943 } 944 com->devs[0] = make_dev(&sio_cdevsw, unit, 945 UID_ROOT, GID_WHEEL, 0600, "ttyd%r", unit); 946 com->devs[1] = make_dev(&sio_cdevsw, unit | CONTROL_INIT_STATE, 947 UID_ROOT, GID_WHEEL, 0600, "ttyid%r", unit); 948 com->devs[2] = make_dev(&sio_cdevsw, unit | CONTROL_LOCK_STATE, 949 UID_ROOT, GID_WHEEL, 0600, "ttyld%r", unit); 950 com->devs[3] = make_dev(&sio_cdevsw, unit | CALLOUT_MASK, 951 UID_UUCP, GID_DIALER, 0660, "cuaa%r", unit); 952 com->devs[4] = make_dev(&sio_cdevsw, 953 unit | CALLOUT_MASK | CONTROL_INIT_STATE, 954 UID_UUCP, GID_DIALER, 0660, "cuaia%r", unit); 955 com->devs[5] = make_dev(&sio_cdevsw, 956 unit | CALLOUT_MASK | CONTROL_LOCK_STATE, 957 UID_UUCP, GID_DIALER, 0660, "cuala%r", unit); 958 com->flags = flags; 959 com->pps.ppscap = PPS_CAPTUREASSERT | PPS_CAPTURECLEAR; 960 pps_init(&com->pps); 961 962 rid = 0; 963 com->irqres = bus_alloc_resource(dev, SYS_RES_IRQ, &rid, 0ul, ~0ul, 1, 964 RF_ACTIVE); 965 if (com->irqres) { 966 ret = BUS_SETUP_INTR(device_get_parent(dev), dev, com->irqres, 967 INTR_TYPE_TTY | INTR_FAST, 968 siointr, com, &com->cookie); 969 if (ret) { 970 ret = BUS_SETUP_INTR(device_get_parent(dev), dev, 971 com->irqres, INTR_TYPE_TTY, 972 siointr, com, &com->cookie); 973 if (ret == 0) 974 device_printf(dev, "unable to activate interrupt in fast mode - using normal mode\n"); 975 } 976 if (ret) 977 device_printf(dev, "could not activate interrupt\n"); 978#if defined(DDB) && (defined(BREAK_TO_DEBUGGER) || \ 979 defined(ALT_BREAK_TO_DEBUGGER)) 980 /* 981 * Enable interrupts for early break-to-debugger support 982 * on the console. 983 */ 984 if (ret == 0 && unit == comconsole) 985 outb(siocniobase + com_ier, IER_ERXRDY | IER_ERLS | 986 IER_EMSC); 987#endif 988 } 989 990 return (0); 991} 992 993static int 994sioopen(dev, flag, mode, td) 995 dev_t dev; 996 int flag; 997 int mode; 998 struct thread *td; 999{ 1000 struct com_s *com; 1001 int error; 1002 int mynor; 1003 int s; 1004 struct tty *tp; 1005 int unit; 1006 1007 mynor = minor(dev); 1008 unit = MINOR_TO_UNIT(mynor); 1009 com = com_addr(unit); 1010 if (com == NULL) 1011 return (ENXIO); 1012 if (com->gone) 1013 return (ENXIO); 1014 if (mynor & CONTROL_MASK) 1015 return (0); 1016 tp = dev->si_tty = com->tp = ttymalloc(com->tp); 1017 s = spltty(); 1018 /* 1019 * We jump to this label after all non-interrupted sleeps to pick 1020 * up any changes of the device state. 1021 */ 1022open_top: 1023 while (com->state & CS_DTR_OFF) { 1024 error = tsleep(&com->dtr_wait, TTIPRI | PCATCH, "siodtr", 0); 1025 if (com_addr(unit) == NULL) 1026 return (ENXIO); 1027 if (error != 0 || com->gone) 1028 goto out; 1029 } 1030 if (tp->t_state & TS_ISOPEN) { 1031 /* 1032 * The device is open, so everything has been initialized. 1033 * Handle conflicts. 1034 */ 1035 if (mynor & CALLOUT_MASK) { 1036 if (!com->active_out) { 1037 error = EBUSY; 1038 goto out; 1039 } 1040 } else { 1041 if (com->active_out) { 1042 if (flag & O_NONBLOCK) { 1043 error = EBUSY; 1044 goto out; 1045 } 1046 error = tsleep(&com->active_out, 1047 TTIPRI | PCATCH, "siobi", 0); 1048 if (com_addr(unit) == NULL) 1049 return (ENXIO); 1050 if (error != 0 || com->gone) 1051 goto out; 1052 goto open_top; 1053 } 1054 } 1055 if (tp->t_state & TS_XCLUDE && 1056 suser_td(td)) { 1057 error = EBUSY; 1058 goto out; 1059 } 1060 } else { 1061 /* 1062 * The device isn't open, so there are no conflicts. 1063 * Initialize it. Initialization is done twice in many 1064 * cases: to preempt sleeping callin opens if we are 1065 * callout, and to complete a callin open after DCD rises. 1066 */ 1067 tp->t_oproc = comstart; 1068 tp->t_param = comparam; 1069 tp->t_stop = comstop; 1070 tp->t_dev = dev; 1071 tp->t_termios = mynor & CALLOUT_MASK 1072 ? com->it_out : com->it_in; 1073 (void)commctl(com, TIOCM_DTR | TIOCM_RTS, DMSET); 1074 com->poll = com->no_irq; 1075 com->poll_output = com->loses_outints; 1076 ++com->wopeners; 1077 error = comparam(tp, &tp->t_termios); 1078 --com->wopeners; 1079 if (error != 0) 1080 goto out; 1081 /* 1082 * XXX we should goto open_top if comparam() slept. 1083 */ 1084 if (com->hasfifo) { 1085 /* 1086 * (Re)enable and drain fifos. 1087 * 1088 * Certain SMC chips cause problems if the fifos 1089 * are enabled while input is ready. Turn off the 1090 * fifo if necessary to clear the input. We test 1091 * the input ready bit after enabling the fifos 1092 * since we've already enabled them in comparam() 1093 * and to handle races between enabling and fresh 1094 * input. 1095 */ 1096 while (TRUE) { 1097 sio_setreg(com, com_fifo, 1098 FIFO_RCV_RST | FIFO_XMT_RST 1099 | com->fifo_image); 1100 /* 1101 * XXX the delays are for superstitious 1102 * historical reasons. It must be less than 1103 * the character time at the maximum 1104 * supported speed (87 usec at 115200 bps 1105 * 8N1). Otherwise we might loop endlessly 1106 * if data is streaming in. We used to use 1107 * delays of 100. That usually worked 1108 * because DELAY(100) used to usually delay 1109 * for about 85 usec instead of 100. 1110 */ 1111 DELAY(50); 1112 if (!(inb(com->line_status_port) & LSR_RXRDY)) 1113 break; 1114 sio_setreg(com, com_fifo, 0); 1115 DELAY(50); 1116 (void) inb(com->data_port); 1117 } 1118 } 1119 1120 mtx_lock_spin(&sio_lock); 1121 (void) inb(com->line_status_port); 1122 (void) inb(com->data_port); 1123 com->prev_modem_status = com->last_modem_status 1124 = inb(com->modem_status_port); 1125 if (COM_IIR_TXRDYBUG(com->flags)) { 1126 outb(com->intr_ctl_port, IER_ERXRDY | IER_ERLS 1127 | IER_EMSC); 1128 } else { 1129 outb(com->intr_ctl_port, IER_ERXRDY | IER_ETXRDY 1130 | IER_ERLS | IER_EMSC); 1131 } 1132 mtx_unlock_spin(&sio_lock); 1133 /* 1134 * Handle initial DCD. Callout devices get a fake initial 1135 * DCD (trapdoor DCD). If we are callout, then any sleeping 1136 * callin opens get woken up and resume sleeping on "siobi" 1137 * instead of "siodcd". 1138 */ 1139 /* 1140 * XXX `mynor & CALLOUT_MASK' should be 1141 * `tp->t_cflag & (SOFT_CARRIER | TRAPDOOR_CARRIER) where 1142 * TRAPDOOR_CARRIER is the default initial state for callout 1143 * devices and SOFT_CARRIER is like CLOCAL except it hides 1144 * the true carrier. 1145 */ 1146 if (com->prev_modem_status & MSR_DCD || mynor & CALLOUT_MASK) 1147 (*linesw[tp->t_line].l_modem)(tp, 1); 1148 } 1149 /* 1150 * Wait for DCD if necessary. 1151 */ 1152 if (!(tp->t_state & TS_CARR_ON) && !(mynor & CALLOUT_MASK) 1153 && !(tp->t_cflag & CLOCAL) && !(flag & O_NONBLOCK)) { 1154 ++com->wopeners; 1155 error = tsleep(TSA_CARR_ON(tp), TTIPRI | PCATCH, "siodcd", 0); 1156 if (com_addr(unit) == NULL) 1157 return (ENXIO); 1158 --com->wopeners; 1159 if (error != 0 || com->gone) 1160 goto out; 1161 goto open_top; 1162 } 1163 error = (*linesw[tp->t_line].l_open)(dev, tp); 1164 disc_optim(tp, &tp->t_termios, com); 1165 if (tp->t_state & TS_ISOPEN && mynor & CALLOUT_MASK) 1166 com->active_out = TRUE; 1167 siosettimeout(); 1168out: 1169 splx(s); 1170 if (!(tp->t_state & TS_ISOPEN) && com->wopeners == 0) 1171 comhardclose(com); 1172 return (error); 1173} 1174 1175static int 1176sioclose(dev, flag, mode, td) 1177 dev_t dev; 1178 int flag; 1179 int mode; 1180 struct thread *td; 1181{ 1182 struct com_s *com; 1183 int mynor; 1184 int s; 1185 struct tty *tp; 1186 1187 mynor = minor(dev); 1188 if (mynor & CONTROL_MASK) 1189 return (0); 1190 com = com_addr(MINOR_TO_UNIT(mynor)); 1191 if (com == NULL) 1192 return (ENODEV); 1193 tp = com->tp; 1194 s = spltty(); 1195 (*linesw[tp->t_line].l_close)(tp, flag); 1196 disc_optim(tp, &tp->t_termios, com); 1197 comstop(tp, FREAD | FWRITE); 1198 comhardclose(com); 1199 ttyclose(tp); 1200 siosettimeout(); 1201 splx(s); 1202 if (com->gone) { 1203 printf("sio%d: gone\n", com->unit); 1204 s = spltty(); 1205 if (com->ibuf != NULL) 1206 free(com->ibuf, M_DEVBUF); 1207 bzero(tp, sizeof *tp); 1208 splx(s); 1209 } 1210 return (0); 1211} 1212 1213static void 1214comhardclose(com) 1215 struct com_s *com; 1216{ 1217 int s; 1218 struct tty *tp; 1219 int unit; 1220 1221 unit = com->unit; 1222 s = spltty(); 1223 com->poll = FALSE; 1224 com->poll_output = FALSE; 1225 com->do_timestamp = FALSE; 1226 com->do_dcd_timestamp = FALSE; 1227 com->pps.ppsparam.mode = 0; 1228 sio_setreg(com, com_cfcr, com->cfcr_image &= ~CFCR_SBREAK); 1229 tp = com->tp; 1230 1231#if defined(DDB) && (defined(BREAK_TO_DEBUGGER) || \ 1232 defined(ALT_BREAK_TO_DEBUGGER)) 1233 /* 1234 * Leave interrupts enabled and don't clear DTR if this is the 1235 * console. This allows us to detect break-to-debugger events 1236 * while the console device is closed. 1237 */ 1238 if (com->unit != comconsole) 1239#endif 1240 { 1241 sio_setreg(com, com_ier, 0); 1242 if (tp->t_cflag & HUPCL 1243 /* 1244 * XXX we will miss any carrier drop between here and the 1245 * next open. Perhaps we should watch DCD even when the 1246 * port is closed; it is not sufficient to check it at 1247 * the next open because it might go up and down while 1248 * we're not watching. 1249 */ 1250 || (!com->active_out 1251 && !(com->prev_modem_status & MSR_DCD) 1252 && !(com->it_in.c_cflag & CLOCAL)) 1253 || !(tp->t_state & TS_ISOPEN)) { 1254 (void)commctl(com, TIOCM_DTR, DMBIC); 1255 if (com->dtr_wait != 0 && !(com->state & CS_DTR_OFF)) { 1256 timeout(siodtrwakeup, com, com->dtr_wait); 1257 com->state |= CS_DTR_OFF; 1258 } 1259 } 1260 } 1261 if (com->hasfifo) { 1262 /* 1263 * Disable fifos so that they are off after controlled 1264 * reboots. Some BIOSes fail to detect 16550s when the 1265 * fifos are enabled. 1266 */ 1267 sio_setreg(com, com_fifo, 0); 1268 } 1269 com->active_out = FALSE; 1270 wakeup(&com->active_out); 1271 wakeup(TSA_CARR_ON(tp)); /* restart any wopeners */ 1272 splx(s); 1273} 1274 1275static int 1276sioread(dev, uio, flag) 1277 dev_t dev; 1278 struct uio *uio; 1279 int flag; 1280{ 1281 int mynor; 1282 struct com_s *com; 1283 1284 mynor = minor(dev); 1285 if (mynor & CONTROL_MASK) 1286 return (ENODEV); 1287 com = com_addr(MINOR_TO_UNIT(mynor)); 1288 if (com == NULL || com->gone) 1289 return (ENODEV); 1290 return ((*linesw[com->tp->t_line].l_read)(com->tp, uio, flag)); 1291} 1292 1293static int 1294siowrite(dev, uio, flag) 1295 dev_t dev; 1296 struct uio *uio; 1297 int flag; 1298{ 1299 int mynor; 1300 struct com_s *com; 1301 int unit; 1302 1303 mynor = minor(dev); 1304 if (mynor & CONTROL_MASK) 1305 return (ENODEV); 1306 1307 unit = MINOR_TO_UNIT(mynor); 1308 com = com_addr(unit); 1309 if (com == NULL || com->gone) 1310 return (ENODEV); 1311 /* 1312 * (XXX) We disallow virtual consoles if the physical console is 1313 * a serial port. This is in case there is a display attached that 1314 * is not the console. In that situation we don't need/want the X 1315 * server taking over the console. 1316 */ 1317 if (constty != NULL && unit == comconsole) 1318 constty = NULL; 1319 return ((*linesw[com->tp->t_line].l_write)(com->tp, uio, flag)); 1320} 1321 1322static void 1323siobusycheck(chan) 1324 void *chan; 1325{ 1326 struct com_s *com; 1327 int s; 1328 1329 com = (struct com_s *)chan; 1330 1331 /* 1332 * Clear TS_BUSY if low-level output is complete. 1333 * spl locking is sufficient because siointr1() does not set CS_BUSY. 1334 * If siointr1() clears CS_BUSY after we look at it, then we'll get 1335 * called again. Reading the line status port outside of siointr1() 1336 * is safe because CS_BUSY is clear so there are no output interrupts 1337 * to lose. 1338 */ 1339 s = spltty(); 1340 if (com->state & CS_BUSY) 1341 com->extra_state &= ~CSE_BUSYCHECK; /* False alarm. */ 1342 else if ((inb(com->line_status_port) & (LSR_TSRE | LSR_TXRDY)) 1343 == (LSR_TSRE | LSR_TXRDY)) { 1344 com->tp->t_state &= ~TS_BUSY; 1345 ttwwakeup(com->tp); 1346 com->extra_state &= ~CSE_BUSYCHECK; 1347 } else 1348 timeout(siobusycheck, com, hz / 100); 1349 splx(s); 1350} 1351 1352static void 1353siodtrwakeup(chan) 1354 void *chan; 1355{ 1356 struct com_s *com; 1357 1358 com = (struct com_s *)chan; 1359 com->state &= ~CS_DTR_OFF; 1360 wakeup(&com->dtr_wait); 1361} 1362 1363/* 1364 * Call this function with the sio_lock mutex held. It will return with the 1365 * lock still held. 1366 */ 1367static void 1368sioinput(com) 1369 struct com_s *com; 1370{ 1371 u_char *buf; 1372 int incc; 1373 u_char line_status; 1374 int recv_data; 1375 struct tty *tp; 1376 1377 buf = com->ibuf; 1378 tp = com->tp; 1379 if (!(tp->t_state & TS_ISOPEN) || !(tp->t_cflag & CREAD)) { 1380 com_events -= (com->iptr - com->ibuf); 1381 com->iptr = com->ibuf; 1382 return; 1383 } 1384 if (tp->t_state & TS_CAN_BYPASS_L_RINT) { 1385 /* 1386 * Avoid the grotesquely inefficient lineswitch routine 1387 * (ttyinput) in "raw" mode. It usually takes about 450 1388 * instructions (that's without canonical processing or echo!). 1389 * slinput is reasonably fast (usually 40 instructions plus 1390 * call overhead). 1391 */ 1392 do { 1393 /* 1394 * This may look odd, but it is using save-and-enable 1395 * semantics instead of the save-and-disable semantics 1396 * that are used everywhere else. 1397 */ 1398 mtx_unlock_spin(&sio_lock); 1399 incc = com->iptr - buf; 1400 if (tp->t_rawq.c_cc + incc > tp->t_ihiwat 1401 && (com->state & CS_RTS_IFLOW 1402 || tp->t_iflag & IXOFF) 1403 && !(tp->t_state & TS_TBLOCK)) 1404 ttyblock(tp); 1405 com->delta_error_counts[CE_TTY_BUF_OVERFLOW] 1406 += b_to_q((char *)buf, incc, &tp->t_rawq); 1407 buf += incc; 1408 tk_nin += incc; 1409 tk_rawcc += incc; 1410 tp->t_rawcc += incc; 1411 ttwakeup(tp); 1412 if (tp->t_state & TS_TTSTOP 1413 && (tp->t_iflag & IXANY 1414 || tp->t_cc[VSTART] == tp->t_cc[VSTOP])) { 1415 tp->t_state &= ~TS_TTSTOP; 1416 tp->t_lflag &= ~FLUSHO; 1417 comstart(tp); 1418 } 1419 mtx_lock_spin(&sio_lock); 1420 } while (buf < com->iptr); 1421 } else { 1422 do { 1423 /* 1424 * This may look odd, but it is using save-and-enable 1425 * semantics instead of the save-and-disable semantics 1426 * that are used everywhere else. 1427 */ 1428 mtx_unlock_spin(&sio_lock); 1429 line_status = buf[com->ierroff]; 1430 recv_data = *buf++; 1431 if (line_status 1432 & (LSR_BI | LSR_FE | LSR_OE | LSR_PE)) { 1433 if (line_status & LSR_BI) 1434 recv_data |= TTY_BI; 1435 if (line_status & LSR_FE) 1436 recv_data |= TTY_FE; 1437 if (line_status & LSR_OE) 1438 recv_data |= TTY_OE; 1439 if (line_status & LSR_PE) 1440 recv_data |= TTY_PE; 1441 } 1442 (*linesw[tp->t_line].l_rint)(recv_data, tp); 1443 mtx_lock_spin(&sio_lock); 1444 } while (buf < com->iptr); 1445 } 1446 com_events -= (com->iptr - com->ibuf); 1447 com->iptr = com->ibuf; 1448 1449 /* 1450 * There is now room for another low-level buffer full of input, 1451 * so enable RTS if it is now disabled and there is room in the 1452 * high-level buffer. 1453 */ 1454 if ((com->state & CS_RTS_IFLOW) && !(com->mcr_image & MCR_RTS) && 1455 !(tp->t_state & TS_TBLOCK)) 1456 outb(com->modem_ctl_port, com->mcr_image |= MCR_RTS); 1457} 1458 1459void 1460siointr(arg) 1461 void *arg; 1462{ 1463 struct com_s *com; 1464 1465#ifndef COM_MULTIPORT 1466 com = (struct com_s *)arg; 1467 1468 mtx_lock_spin(&sio_lock); 1469 siointr1(com); 1470 mtx_unlock_spin(&sio_lock); 1471#else /* COM_MULTIPORT */ 1472 bool_t possibly_more_intrs; 1473 int unit; 1474 1475 /* 1476 * Loop until there is no activity on any port. This is necessary 1477 * to get an interrupt edge more than to avoid another interrupt. 1478 * If the IRQ signal is just an OR of the IRQ signals from several 1479 * devices, then the edge from one may be lost because another is 1480 * on. 1481 */ 1482 mtx_lock_spin(&sio_lock); 1483 do { 1484 possibly_more_intrs = FALSE; 1485 for (unit = 0; unit < sio_numunits; ++unit) { 1486 com = com_addr(unit); 1487 /* 1488 * XXX COM_LOCK(); 1489 * would it work here, or be counter-productive? 1490 */ 1491 if (com != NULL 1492 && !com->gone 1493 && (inb(com->int_id_port) & IIR_IMASK) 1494 != IIR_NOPEND) { 1495 siointr1(com); 1496 possibly_more_intrs = TRUE; 1497 } 1498 /* XXX COM_UNLOCK(); */ 1499 } 1500 } while (possibly_more_intrs); 1501 mtx_unlock_spin(&sio_lock); 1502#endif /* COM_MULTIPORT */ 1503} 1504 1505static void 1506siointr1(com) 1507 struct com_s *com; 1508{ 1509 u_char line_status; 1510 u_char modem_status; 1511 u_char *ioptr; 1512 u_char recv_data; 1513 u_char int_ctl; 1514 u_char int_ctl_new; 1515 struct timecounter *tc; 1516 u_int count; 1517 1518 int_ctl = inb(com->intr_ctl_port); 1519 int_ctl_new = int_ctl; 1520 1521 while (!com->gone) { 1522 if (com->pps.ppsparam.mode & PPS_CAPTUREBOTH) { 1523 modem_status = inb(com->modem_status_port); 1524 if ((modem_status ^ com->last_modem_status) & MSR_DCD) { 1525 tc = timecounter; 1526 count = tc->tc_get_timecount(tc); 1527 pps_event(&com->pps, tc, count, 1528 (modem_status & MSR_DCD) ? 1529 PPS_CAPTUREASSERT : PPS_CAPTURECLEAR); 1530 } 1531 } 1532 line_status = inb(com->line_status_port); 1533 1534 /* input event? (check first to help avoid overruns) */ 1535 while (line_status & LSR_RCV_MASK) { 1536 /* break/unnattached error bits or real input? */ 1537 if (!(line_status & LSR_RXRDY)) 1538 recv_data = 0; 1539 else 1540 recv_data = inb(com->data_port); 1541#if defined(DDB) && defined(ALT_BREAK_TO_DEBUGGER) 1542 /* 1543 * Solaris implements a new BREAK which is initiated 1544 * by a character sequence CR ~ ^b which is similar 1545 * to a familiar pattern used on Sun servers by the 1546 * Remote Console. 1547 */ 1548#define KEY_CRTLB 2 /* ^B */ 1549#define KEY_CR 13 /* CR '\r' */ 1550#define KEY_TILDE 126 /* ~ */ 1551 1552 if (com->unit == comconsole) { 1553 static int brk_state1 = 0, brk_state2 = 0; 1554 if (recv_data == KEY_CR) { 1555 brk_state1 = recv_data; 1556 brk_state2 = 0; 1557 } else if (brk_state1 == KEY_CR 1558 && (recv_data == KEY_TILDE 1559 || recv_data == KEY_CRTLB)) { 1560 if (recv_data == KEY_TILDE) 1561 brk_state2 = recv_data; 1562 else if (brk_state2 == KEY_TILDE 1563 && recv_data == KEY_CRTLB) { 1564 breakpoint(); 1565 brk_state1 = 0; 1566 brk_state2 = 0; 1567 goto cont; 1568 } else 1569 brk_state2 = 0; 1570 } else 1571 brk_state1 = 0; 1572 } 1573#endif 1574 if (line_status & (LSR_BI | LSR_FE | LSR_PE)) { 1575 /* 1576 * Don't store BI if IGNBRK or FE/PE if IGNPAR. 1577 * Otherwise, push the work to a higher level 1578 * (to handle PARMRK) if we're bypassing. 1579 * Otherwise, convert BI/FE and PE+INPCK to 0. 1580 * 1581 * This makes bypassing work right in the 1582 * usual "raw" case (IGNBRK set, and IGNPAR 1583 * and INPCK clear). 1584 * 1585 * Note: BI together with FE/PE means just BI. 1586 */ 1587 if (line_status & LSR_BI) { 1588#if defined(DDB) && defined(BREAK_TO_DEBUGGER) 1589 if (com->unit == comconsole) { 1590 breakpoint(); 1591 goto cont; 1592 } 1593#endif 1594 if (com->tp == NULL 1595 || com->tp->t_iflag & IGNBRK) 1596 goto cont; 1597 } else { 1598 if (com->tp == NULL 1599 || com->tp->t_iflag & IGNPAR) 1600 goto cont; 1601 } 1602 if (com->tp->t_state & TS_CAN_BYPASS_L_RINT 1603 && (line_status & (LSR_BI | LSR_FE) 1604 || com->tp->t_iflag & INPCK)) 1605 recv_data = 0; 1606 } 1607 ++com->bytes_in; 1608 if (com->hotchar != 0 && recv_data == com->hotchar) 1609 swi_sched(sio_fast_ih, SWI_NOSWITCH); 1610 ioptr = com->iptr; 1611 if (ioptr >= com->ibufend) 1612 CE_RECORD(com, CE_INTERRUPT_BUF_OVERFLOW); 1613 else { 1614 if (com->do_timestamp) 1615 microtime(&com->timestamp); 1616 ++com_events; 1617 swi_sched(sio_slow_ih, SWI_DELAY); 1618#if 0 /* for testing input latency vs efficiency */ 1619if (com->iptr - com->ibuf == 8) 1620 swi_sched(sio_fast_ih, SWI_NOSWITCH); 1621#endif 1622 ioptr[0] = recv_data; 1623 ioptr[com->ierroff] = line_status; 1624 com->iptr = ++ioptr; 1625 if (ioptr == com->ihighwater 1626 && com->state & CS_RTS_IFLOW) 1627 outb(com->modem_ctl_port, 1628 com->mcr_image &= ~MCR_RTS); 1629 if (line_status & LSR_OE) 1630 CE_RECORD(com, CE_OVERRUN); 1631 } 1632cont: 1633 /* 1634 * "& 0x7F" is to avoid the gcc-1.40 generating a slow 1635 * jump from the top of the loop to here 1636 */ 1637 line_status = inb(com->line_status_port) & 0x7F; 1638 } 1639 1640 /* modem status change? (always check before doing output) */ 1641 modem_status = inb(com->modem_status_port); 1642 if (modem_status != com->last_modem_status) { 1643 if (com->do_dcd_timestamp 1644 && !(com->last_modem_status & MSR_DCD) 1645 && modem_status & MSR_DCD) 1646 microtime(&com->dcd_timestamp); 1647 1648 /* 1649 * Schedule high level to handle DCD changes. Note 1650 * that we don't use the delta bits anywhere. Some 1651 * UARTs mess them up, and it's easy to remember the 1652 * previous bits and calculate the delta. 1653 */ 1654 com->last_modem_status = modem_status; 1655 if (!(com->state & CS_CHECKMSR)) { 1656 com_events += LOTS_OF_EVENTS; 1657 com->state |= CS_CHECKMSR; 1658 swi_sched(sio_fast_ih, SWI_NOSWITCH); 1659 } 1660 1661 /* handle CTS change immediately for crisp flow ctl */ 1662 if (com->state & CS_CTS_OFLOW) { 1663 if (modem_status & MSR_CTS) 1664 com->state |= CS_ODEVREADY; 1665 else 1666 com->state &= ~CS_ODEVREADY; 1667 } 1668 } 1669 1670 /* output queued and everything ready? */ 1671 if (line_status & LSR_TXRDY 1672 && com->state >= (CS_BUSY | CS_TTGO | CS_ODEVREADY)) { 1673 ioptr = com->obufq.l_head; 1674 if (com->tx_fifo_size > 1) { 1675 u_int ocount; 1676 1677 ocount = com->obufq.l_tail - ioptr; 1678 if (ocount > com->tx_fifo_size) 1679 ocount = com->tx_fifo_size; 1680 com->bytes_out += ocount; 1681 do 1682 outb(com->data_port, *ioptr++); 1683 while (--ocount != 0); 1684 } else { 1685 outb(com->data_port, *ioptr++); 1686 ++com->bytes_out; 1687 } 1688 com->obufq.l_head = ioptr; 1689 if (COM_IIR_TXRDYBUG(com->flags)) { 1690 int_ctl_new = int_ctl | IER_ETXRDY; 1691 } 1692 if (ioptr >= com->obufq.l_tail) { 1693 struct lbq *qp; 1694 1695 qp = com->obufq.l_next; 1696 qp->l_queued = FALSE; 1697 qp = qp->l_next; 1698 if (qp != NULL) { 1699 com->obufq.l_head = qp->l_head; 1700 com->obufq.l_tail = qp->l_tail; 1701 com->obufq.l_next = qp; 1702 } else { 1703 /* output just completed */ 1704 if (COM_IIR_TXRDYBUG(com->flags)) { 1705 int_ctl_new = int_ctl & ~IER_ETXRDY; 1706 } 1707 com->state &= ~CS_BUSY; 1708 } 1709 if (!(com->state & CS_ODONE)) { 1710 com_events += LOTS_OF_EVENTS; 1711 com->state |= CS_ODONE; 1712 /* handle at high level ASAP */ 1713 swi_sched(sio_fast_ih, SWI_NOSWITCH); 1714 } 1715 } 1716 if (COM_IIR_TXRDYBUG(com->flags) && (int_ctl != int_ctl_new)) { 1717 outb(com->intr_ctl_port, int_ctl_new); 1718 } 1719 } 1720 1721 /* finished? */ 1722#ifndef COM_MULTIPORT 1723 if ((inb(com->int_id_port) & IIR_IMASK) == IIR_NOPEND) 1724#endif /* COM_MULTIPORT */ 1725 return; 1726 } 1727} 1728 1729static int 1730sioioctl(dev, cmd, data, flag, td) 1731 dev_t dev; 1732 u_long cmd; 1733 caddr_t data; 1734 int flag; 1735 struct thread *td; 1736{ 1737 struct com_s *com; 1738 int error; 1739 int mynor; 1740 int s; 1741 struct tty *tp; 1742#if defined(COMPAT_43) || defined(COMPAT_SUNOS) 1743 u_long oldcmd; 1744 struct termios term; 1745#endif 1746 1747 mynor = minor(dev); 1748 com = com_addr(MINOR_TO_UNIT(mynor)); 1749 if (com == NULL || com->gone) 1750 return (ENODEV); 1751 if (mynor & CONTROL_MASK) { 1752 struct termios *ct; 1753 1754 switch (mynor & CONTROL_MASK) { 1755 case CONTROL_INIT_STATE: 1756 ct = mynor & CALLOUT_MASK ? &com->it_out : &com->it_in; 1757 break; 1758 case CONTROL_LOCK_STATE: 1759 ct = mynor & CALLOUT_MASK ? &com->lt_out : &com->lt_in; 1760 break; 1761 default: 1762 return (ENODEV); /* /dev/nodev */ 1763 } 1764 switch (cmd) { 1765 case TIOCSETA: 1766 error = suser_td(td); 1767 if (error != 0) 1768 return (error); 1769 *ct = *(struct termios *)data; 1770 return (0); 1771 case TIOCGETA: 1772 *(struct termios *)data = *ct; 1773 return (0); 1774 case TIOCGETD: 1775 *(int *)data = TTYDISC; 1776 return (0); 1777 case TIOCGWINSZ: 1778 bzero(data, sizeof(struct winsize)); 1779 return (0); 1780 default: 1781 return (ENOTTY); 1782 } 1783 } 1784 tp = com->tp; 1785#if defined(COMPAT_43) || defined(COMPAT_SUNOS) 1786 term = tp->t_termios; 1787 oldcmd = cmd; 1788 error = ttsetcompat(tp, &cmd, data, &term); 1789 if (error != 0) 1790 return (error); 1791 if (cmd != oldcmd) 1792 data = (caddr_t)&term; 1793#endif 1794 if (cmd == TIOCSETA || cmd == TIOCSETAW || cmd == TIOCSETAF) { 1795 int cc; 1796 struct termios *dt = (struct termios *)data; 1797 struct termios *lt = mynor & CALLOUT_MASK 1798 ? &com->lt_out : &com->lt_in; 1799 1800 dt->c_iflag = (tp->t_iflag & lt->c_iflag) 1801 | (dt->c_iflag & ~lt->c_iflag); 1802 dt->c_oflag = (tp->t_oflag & lt->c_oflag) 1803 | (dt->c_oflag & ~lt->c_oflag); 1804 dt->c_cflag = (tp->t_cflag & lt->c_cflag) 1805 | (dt->c_cflag & ~lt->c_cflag); 1806 dt->c_lflag = (tp->t_lflag & lt->c_lflag) 1807 | (dt->c_lflag & ~lt->c_lflag); 1808 for (cc = 0; cc < NCCS; ++cc) 1809 if (lt->c_cc[cc] != 0) 1810 dt->c_cc[cc] = tp->t_cc[cc]; 1811 if (lt->c_ispeed != 0) 1812 dt->c_ispeed = tp->t_ispeed; 1813 if (lt->c_ospeed != 0) 1814 dt->c_ospeed = tp->t_ospeed; 1815 } 1816 error = (*linesw[tp->t_line].l_ioctl)(tp, cmd, data, flag, td); 1817 if (error != ENOIOCTL) 1818 return (error); 1819 s = spltty(); 1820 error = ttioctl(tp, cmd, data, flag); 1821 disc_optim(tp, &tp->t_termios, com); 1822 if (error != ENOIOCTL) { 1823 splx(s); 1824 return (error); 1825 } 1826 switch (cmd) { 1827 case TIOCSBRK: 1828 sio_setreg(com, com_cfcr, com->cfcr_image |= CFCR_SBREAK); 1829 break; 1830 case TIOCCBRK: 1831 sio_setreg(com, com_cfcr, com->cfcr_image &= ~CFCR_SBREAK); 1832 break; 1833 case TIOCSDTR: 1834 (void)commctl(com, TIOCM_DTR, DMBIS); 1835 break; 1836 case TIOCCDTR: 1837 (void)commctl(com, TIOCM_DTR, DMBIC); 1838 break; 1839 /* 1840 * XXX should disallow changing MCR_RTS if CS_RTS_IFLOW is set. The 1841 * changes get undone on the next call to comparam(). 1842 */ 1843 case TIOCMSET: 1844 (void)commctl(com, *(int *)data, DMSET); 1845 break; 1846 case TIOCMBIS: 1847 (void)commctl(com, *(int *)data, DMBIS); 1848 break; 1849 case TIOCMBIC: 1850 (void)commctl(com, *(int *)data, DMBIC); 1851 break; 1852 case TIOCMGET: 1853 *(int *)data = commctl(com, 0, DMGET); 1854 break; 1855 case TIOCMSDTRWAIT: 1856 /* must be root since the wait applies to following logins */ 1857 error = suser_td(td); 1858 if (error != 0) { 1859 splx(s); 1860 return (error); 1861 } 1862 com->dtr_wait = *(int *)data * hz / 100; 1863 break; 1864 case TIOCMGDTRWAIT: 1865 *(int *)data = com->dtr_wait * 100 / hz; 1866 break; 1867 case TIOCTIMESTAMP: 1868 com->do_timestamp = TRUE; 1869 *(struct timeval *)data = com->timestamp; 1870 break; 1871 case TIOCDCDTIMESTAMP: 1872 com->do_dcd_timestamp = TRUE; 1873 *(struct timeval *)data = com->dcd_timestamp; 1874 break; 1875 default: 1876 splx(s); 1877 error = pps_ioctl(cmd, data, &com->pps); 1878 if (error == ENODEV) 1879 error = ENOTTY; 1880 return (error); 1881 } 1882 splx(s); 1883 return (0); 1884} 1885 1886/* software interrupt handler for SWI_TTY */ 1887static void 1888siopoll(void *dummy) 1889{ 1890 int unit; 1891 1892 if (com_events == 0) 1893 return; 1894repeat: 1895 for (unit = 0; unit < sio_numunits; ++unit) { 1896 struct com_s *com; 1897 int incc; 1898 struct tty *tp; 1899 1900 com = com_addr(unit); 1901 if (com == NULL) 1902 continue; 1903 tp = com->tp; 1904 if (tp == NULL || com->gone) { 1905 /* 1906 * Discard any events related to never-opened or 1907 * going-away devices. 1908 */ 1909 mtx_lock_spin(&sio_lock); 1910 incc = com->iptr - com->ibuf; 1911 com->iptr = com->ibuf; 1912 if (com->state & CS_CHECKMSR) { 1913 incc += LOTS_OF_EVENTS; 1914 com->state &= ~CS_CHECKMSR; 1915 } 1916 com_events -= incc; 1917 mtx_unlock_spin(&sio_lock); 1918 continue; 1919 } 1920 if (com->iptr != com->ibuf) { 1921 mtx_lock_spin(&sio_lock); 1922 sioinput(com); 1923 mtx_unlock_spin(&sio_lock); 1924 } 1925 if (com->state & CS_CHECKMSR) { 1926 u_char delta_modem_status; 1927 1928 mtx_lock_spin(&sio_lock); 1929 delta_modem_status = com->last_modem_status 1930 ^ com->prev_modem_status; 1931 com->prev_modem_status = com->last_modem_status; 1932 com_events -= LOTS_OF_EVENTS; 1933 com->state &= ~CS_CHECKMSR; 1934 mtx_unlock_spin(&sio_lock); 1935 if (delta_modem_status & MSR_DCD) 1936 (*linesw[tp->t_line].l_modem) 1937 (tp, com->prev_modem_status & MSR_DCD); 1938 } 1939 if (com->state & CS_ODONE) { 1940 mtx_lock_spin(&sio_lock); 1941 com_events -= LOTS_OF_EVENTS; 1942 com->state &= ~CS_ODONE; 1943 mtx_unlock_spin(&sio_lock); 1944 if (!(com->state & CS_BUSY) 1945 && !(com->extra_state & CSE_BUSYCHECK)) { 1946 timeout(siobusycheck, com, hz / 100); 1947 com->extra_state |= CSE_BUSYCHECK; 1948 } 1949 (*linesw[tp->t_line].l_start)(tp); 1950 } 1951 if (com_events == 0) 1952 break; 1953 } 1954 if (com_events >= LOTS_OF_EVENTS) 1955 goto repeat; 1956} 1957 1958static int 1959comparam(tp, t) 1960 struct tty *tp; 1961 struct termios *t; 1962{ 1963 u_int cfcr; 1964 int cflag; 1965 struct com_s *com; 1966 int divisor; 1967 u_char dlbh; 1968 u_char dlbl; 1969 int s; 1970 int unit; 1971 1972 /* do historical conversions */ 1973 if (t->c_ispeed == 0) 1974 t->c_ispeed = t->c_ospeed; 1975 1976 /* check requested parameters */ 1977 divisor = ttspeedtab(t->c_ospeed, comspeedtab); 1978 if (divisor < 0 || (divisor > 0 && t->c_ispeed != t->c_ospeed)) 1979 return (EINVAL); 1980 1981 /* parameters are OK, convert them to the com struct and the device */ 1982 unit = DEV_TO_UNIT(tp->t_dev); 1983 com = com_addr(unit); 1984 if (com == NULL) 1985 return (ENODEV); 1986 s = spltty(); 1987 if (divisor == 0) 1988 (void)commctl(com, TIOCM_DTR, DMBIC); /* hang up line */ 1989 else 1990 (void)commctl(com, TIOCM_DTR, DMBIS); 1991 cflag = t->c_cflag; 1992 switch (cflag & CSIZE) { 1993 case CS5: 1994 cfcr = CFCR_5BITS; 1995 break; 1996 case CS6: 1997 cfcr = CFCR_6BITS; 1998 break; 1999 case CS7: 2000 cfcr = CFCR_7BITS; 2001 break; 2002 default: 2003 cfcr = CFCR_8BITS; 2004 break; 2005 } 2006 if (cflag & PARENB) { 2007 cfcr |= CFCR_PENAB; 2008 if (!(cflag & PARODD)) 2009 cfcr |= CFCR_PEVEN; 2010 } 2011 if (cflag & CSTOPB) 2012 cfcr |= CFCR_STOPB; 2013 2014 if (com->hasfifo && divisor != 0) { 2015 /* 2016 * Use a fifo trigger level low enough so that the input 2017 * latency from the fifo is less than about 16 msec and 2018 * the total latency is less than about 30 msec. These 2019 * latencies are reasonable for humans. Serial comms 2020 * protocols shouldn't expect anything better since modem 2021 * latencies are larger. 2022 */ 2023 com->fifo_image = t->c_ospeed <= 4800 2024 ? FIFO_ENABLE : FIFO_ENABLE | FIFO_RX_HIGH; 2025#ifdef COM_ESP 2026 /* 2027 * The Hayes ESP card needs the fifo DMA mode bit set 2028 * in compatibility mode. If not, it will interrupt 2029 * for each character received. 2030 */ 2031 if (com->esp) 2032 com->fifo_image |= FIFO_DMA_MODE; 2033#endif 2034 sio_setreg(com, com_fifo, com->fifo_image); 2035 } 2036 2037 /* 2038 * This returns with interrupts disabled so that we can complete 2039 * the speed change atomically. Keeping interrupts disabled is 2040 * especially important while com_data is hidden. 2041 */ 2042 (void) siosetwater(com, t->c_ispeed); 2043 2044 if (divisor != 0) { 2045 sio_setreg(com, com_cfcr, cfcr | CFCR_DLAB); 2046 /* 2047 * Only set the divisor registers if they would change, 2048 * since on some 16550 incompatibles (UMC8669F), setting 2049 * them while input is arriving them loses sync until 2050 * data stops arriving. 2051 */ 2052 dlbl = divisor & 0xFF; 2053 if (sio_getreg(com, com_dlbl) != dlbl) 2054 sio_setreg(com, com_dlbl, dlbl); 2055 dlbh = (u_int) divisor >> 8; 2056 if (sio_getreg(com, com_dlbh) != dlbh) 2057 sio_setreg(com, com_dlbh, dlbh); 2058 } 2059 2060 sio_setreg(com, com_cfcr, com->cfcr_image = cfcr); 2061 2062 if (!(tp->t_state & TS_TTSTOP)) 2063 com->state |= CS_TTGO; 2064 2065 if (cflag & CRTS_IFLOW) { 2066 if (com->st16650a) { 2067 sio_setreg(com, com_cfcr, 0xbf); 2068 sio_setreg(com, com_fifo, 2069 sio_getreg(com, com_fifo) | 0x40); 2070 } 2071 com->state |= CS_RTS_IFLOW; 2072 /* 2073 * If CS_RTS_IFLOW just changed from off to on, the change 2074 * needs to be propagated to MCR_RTS. This isn't urgent, 2075 * so do it later by calling comstart() instead of repeating 2076 * a lot of code from comstart() here. 2077 */ 2078 } else if (com->state & CS_RTS_IFLOW) { 2079 com->state &= ~CS_RTS_IFLOW; 2080 /* 2081 * CS_RTS_IFLOW just changed from on to off. Force MCR_RTS 2082 * on here, since comstart() won't do it later. 2083 */ 2084 outb(com->modem_ctl_port, com->mcr_image |= MCR_RTS); 2085 if (com->st16650a) { 2086 sio_setreg(com, com_cfcr, 0xbf); 2087 sio_setreg(com, com_fifo, 2088 sio_getreg(com, com_fifo) & ~0x40); 2089 } 2090 } 2091 2092 2093 /* 2094 * Set up state to handle output flow control. 2095 * XXX - worth handling MDMBUF (DCD) flow control at the lowest level? 2096 * Now has 10+ msec latency, while CTS flow has 50- usec latency. 2097 */ 2098 com->state |= CS_ODEVREADY; 2099 com->state &= ~CS_CTS_OFLOW; 2100 if (cflag & CCTS_OFLOW) { 2101 com->state |= CS_CTS_OFLOW; 2102 if (!(com->last_modem_status & MSR_CTS)) 2103 com->state &= ~CS_ODEVREADY; 2104 if (com->st16650a) { 2105 sio_setreg(com, com_cfcr, 0xbf); 2106 sio_setreg(com, com_fifo, 2107 sio_getreg(com, com_fifo) | 0x80); 2108 } 2109 } else { 2110 if (com->st16650a) { 2111 sio_setreg(com, com_cfcr, 0xbf); 2112 sio_setreg(com, com_fifo, 2113 sio_getreg(com, com_fifo) & ~0x80); 2114 } 2115 } 2116 2117 sio_setreg(com, com_cfcr, com->cfcr_image); 2118 2119 /* XXX shouldn't call functions while intrs are disabled. */ 2120 disc_optim(tp, t, com); 2121 /* 2122 * Recover from fiddling with CS_TTGO. We used to call siointr1() 2123 * unconditionally, but that defeated the careful discarding of 2124 * stale input in sioopen(). 2125 */ 2126 if (com->state >= (CS_BUSY | CS_TTGO)) 2127 siointr1(com); 2128 2129 mtx_unlock_spin(&sio_lock); 2130 splx(s); 2131 comstart(tp); 2132 if (com->ibufold != NULL) { 2133 free(com->ibufold, M_DEVBUF); 2134 com->ibufold = NULL; 2135 } 2136 return (0); 2137} 2138 2139/* 2140 * This function must be called with the sio_lock mutex released and will 2141 * return with it obtained. 2142 */ 2143static int 2144siosetwater(com, speed) 2145 struct com_s *com; 2146 speed_t speed; 2147{ 2148 int cp4ticks; 2149 u_char *ibuf; 2150 int ibufsize; 2151 struct tty *tp; 2152 2153 /* 2154 * Make the buffer size large enough to handle a softtty interrupt 2155 * latency of about 2 ticks without loss of throughput or data 2156 * (about 3 ticks if input flow control is not used or not honoured, 2157 * but a bit less for CS5-CS7 modes). 2158 */ 2159 cp4ticks = speed / 10 / hz * 4; 2160 for (ibufsize = 128; ibufsize < cp4ticks;) 2161 ibufsize <<= 1; 2162 if (ibufsize == com->ibufsize) { 2163 mtx_lock_spin(&sio_lock); 2164 return (0); 2165 } 2166 2167 /* 2168 * Allocate input buffer. The extra factor of 2 in the size is 2169 * to allow for an error byte for each input byte. 2170 */ 2171 ibuf = malloc(2 * ibufsize, M_DEVBUF, M_NOWAIT); 2172 if (ibuf == NULL) { 2173 mtx_lock_spin(&sio_lock); 2174 return (ENOMEM); 2175 } 2176 2177 /* Initialize non-critical variables. */ 2178 com->ibufold = com->ibuf; 2179 com->ibufsize = ibufsize; 2180 tp = com->tp; 2181 if (tp != NULL) { 2182 tp->t_ififosize = 2 * ibufsize; 2183 tp->t_ispeedwat = (speed_t)-1; 2184 tp->t_ospeedwat = (speed_t)-1; 2185 } 2186 2187 /* 2188 * Read current input buffer, if any. Continue with interrupts 2189 * disabled. 2190 */ 2191 mtx_lock_spin(&sio_lock); 2192 if (com->iptr != com->ibuf) 2193 sioinput(com); 2194 2195 /*- 2196 * Initialize critical variables, including input buffer watermarks. 2197 * The external device is asked to stop sending when the buffer 2198 * exactly reaches high water, or when the high level requests it. 2199 * The high level is notified immediately (rather than at a later 2200 * clock tick) when this watermark is reached. 2201 * The buffer size is chosen so the watermark should almost never 2202 * be reached. 2203 * The low watermark is invisibly 0 since the buffer is always 2204 * emptied all at once. 2205 */ 2206 com->iptr = com->ibuf = ibuf; 2207 com->ibufend = ibuf + ibufsize; 2208 com->ierroff = ibufsize; 2209 com->ihighwater = ibuf + 3 * ibufsize / 4; 2210 return (0); 2211} 2212 2213static void 2214comstart(tp) 2215 struct tty *tp; 2216{ 2217 struct com_s *com; 2218 int s; 2219 int unit; 2220 2221 unit = DEV_TO_UNIT(tp->t_dev); 2222 com = com_addr(unit); 2223 if (com == NULL) 2224 return; 2225 s = spltty(); 2226 mtx_lock_spin(&sio_lock); 2227 if (tp->t_state & TS_TTSTOP) 2228 com->state &= ~CS_TTGO; 2229 else 2230 com->state |= CS_TTGO; 2231 if (tp->t_state & TS_TBLOCK) { 2232 if (com->mcr_image & MCR_RTS && com->state & CS_RTS_IFLOW) 2233 outb(com->modem_ctl_port, com->mcr_image &= ~MCR_RTS); 2234 } else { 2235 if (!(com->mcr_image & MCR_RTS) && com->iptr < com->ihighwater 2236 && com->state & CS_RTS_IFLOW) 2237 outb(com->modem_ctl_port, com->mcr_image |= MCR_RTS); 2238 } 2239 mtx_unlock_spin(&sio_lock); 2240 if (tp->t_state & (TS_TIMEOUT | TS_TTSTOP)) { 2241 ttwwakeup(tp); 2242 splx(s); 2243 return; 2244 } 2245 if (tp->t_outq.c_cc != 0) { 2246 struct lbq *qp; 2247 struct lbq *next; 2248 2249 if (!com->obufs[0].l_queued) { 2250 com->obufs[0].l_tail 2251 = com->obuf1 + q_to_b(&tp->t_outq, com->obuf1, 2252 sizeof com->obuf1); 2253 com->obufs[0].l_next = NULL; 2254 com->obufs[0].l_queued = TRUE; 2255 mtx_lock_spin(&sio_lock); 2256 if (com->state & CS_BUSY) { 2257 qp = com->obufq.l_next; 2258 while ((next = qp->l_next) != NULL) 2259 qp = next; 2260 qp->l_next = &com->obufs[0]; 2261 } else { 2262 com->obufq.l_head = com->obufs[0].l_head; 2263 com->obufq.l_tail = com->obufs[0].l_tail; 2264 com->obufq.l_next = &com->obufs[0]; 2265 com->state |= CS_BUSY; 2266 } 2267 mtx_unlock_spin(&sio_lock); 2268 } 2269 if (tp->t_outq.c_cc != 0 && !com->obufs[1].l_queued) { 2270 com->obufs[1].l_tail 2271 = com->obuf2 + q_to_b(&tp->t_outq, com->obuf2, 2272 sizeof com->obuf2); 2273 com->obufs[1].l_next = NULL; 2274 com->obufs[1].l_queued = TRUE; 2275 mtx_lock_spin(&sio_lock); 2276 if (com->state & CS_BUSY) { 2277 qp = com->obufq.l_next; 2278 while ((next = qp->l_next) != NULL) 2279 qp = next; 2280 qp->l_next = &com->obufs[1]; 2281 } else { 2282 com->obufq.l_head = com->obufs[1].l_head; 2283 com->obufq.l_tail = com->obufs[1].l_tail; 2284 com->obufq.l_next = &com->obufs[1]; 2285 com->state |= CS_BUSY; 2286 } 2287 mtx_unlock_spin(&sio_lock); 2288 } 2289 tp->t_state |= TS_BUSY; 2290 } 2291 mtx_lock_spin(&sio_lock); 2292 if (com->state >= (CS_BUSY | CS_TTGO)) 2293 siointr1(com); /* fake interrupt to start output */ 2294 mtx_unlock_spin(&sio_lock); 2295 ttwwakeup(tp); 2296 splx(s); 2297} 2298 2299static void 2300comstop(tp, rw) 2301 struct tty *tp; 2302 int rw; 2303{ 2304 struct com_s *com; 2305 2306 com = com_addr(DEV_TO_UNIT(tp->t_dev)); 2307 if (com == NULL || com->gone) 2308 return; 2309 mtx_lock_spin(&sio_lock); 2310 if (rw & FWRITE) { 2311 if (com->hasfifo) 2312#ifdef COM_ESP 2313 /* XXX avoid h/w bug. */ 2314 if (!com->esp) 2315#endif 2316 sio_setreg(com, com_fifo, 2317 FIFO_XMT_RST | com->fifo_image); 2318 com->obufs[0].l_queued = FALSE; 2319 com->obufs[1].l_queued = FALSE; 2320 if (com->state & CS_ODONE) 2321 com_events -= LOTS_OF_EVENTS; 2322 com->state &= ~(CS_ODONE | CS_BUSY); 2323 com->tp->t_state &= ~TS_BUSY; 2324 } 2325 if (rw & FREAD) { 2326 if (com->hasfifo) 2327#ifdef COM_ESP 2328 /* XXX avoid h/w bug. */ 2329 if (!com->esp) 2330#endif 2331 sio_setreg(com, com_fifo, 2332 FIFO_RCV_RST | com->fifo_image); 2333 com_events -= (com->iptr - com->ibuf); 2334 com->iptr = com->ibuf; 2335 } 2336 mtx_unlock_spin(&sio_lock); 2337 comstart(tp); 2338} 2339 2340static int 2341commctl(com, bits, how) 2342 struct com_s *com; 2343 int bits; 2344 int how; 2345{ 2346 int mcr; 2347 int msr; 2348 2349 if (how == DMGET) { 2350 bits = TIOCM_LE; /* XXX - always enabled while open */ 2351 mcr = com->mcr_image; 2352 if (mcr & MCR_DTR) 2353 bits |= TIOCM_DTR; 2354 if (mcr & MCR_RTS) 2355 bits |= TIOCM_RTS; 2356 msr = com->prev_modem_status; 2357 if (msr & MSR_CTS) 2358 bits |= TIOCM_CTS; 2359 if (msr & MSR_DCD) 2360 bits |= TIOCM_CD; 2361 if (msr & MSR_DSR) 2362 bits |= TIOCM_DSR; 2363 /* 2364 * XXX - MSR_RI is naturally volatile, and we make MSR_TERI 2365 * more volatile by reading the modem status a lot. Perhaps 2366 * we should latch both bits until the status is read here. 2367 */ 2368 if (msr & (MSR_RI | MSR_TERI)) 2369 bits |= TIOCM_RI; 2370 return (bits); 2371 } 2372 mcr = 0; 2373 if (bits & TIOCM_DTR) 2374 mcr |= MCR_DTR; 2375 if (bits & TIOCM_RTS) 2376 mcr |= MCR_RTS; 2377 if (com->gone) 2378 return(0); 2379 mtx_lock_spin(&sio_lock); 2380 switch (how) { 2381 case DMSET: 2382 outb(com->modem_ctl_port, 2383 com->mcr_image = mcr | (com->mcr_image & MCR_IENABLE)); 2384 break; 2385 case DMBIS: 2386 outb(com->modem_ctl_port, com->mcr_image |= mcr); 2387 break; 2388 case DMBIC: 2389 outb(com->modem_ctl_port, com->mcr_image &= ~mcr); 2390 break; 2391 } 2392 mtx_unlock_spin(&sio_lock); 2393 return (0); 2394} 2395 2396static void 2397siosettimeout() 2398{ 2399 struct com_s *com; 2400 bool_t someopen; 2401 int unit; 2402 2403 /* 2404 * Set our timeout period to 1 second if no polled devices are open. 2405 * Otherwise set it to max(1/200, 1/hz). 2406 * Enable timeouts iff some device is open. 2407 */ 2408 untimeout(comwakeup, (void *)NULL, sio_timeout_handle); 2409 sio_timeout = hz; 2410 someopen = FALSE; 2411 for (unit = 0; unit < sio_numunits; ++unit) { 2412 com = com_addr(unit); 2413 if (com != NULL && com->tp != NULL 2414 && com->tp->t_state & TS_ISOPEN && !com->gone) { 2415 someopen = TRUE; 2416 if (com->poll || com->poll_output) { 2417 sio_timeout = hz > 200 ? hz / 200 : 1; 2418 break; 2419 } 2420 } 2421 } 2422 if (someopen) { 2423 sio_timeouts_until_log = hz / sio_timeout; 2424 sio_timeout_handle = timeout(comwakeup, (void *)NULL, 2425 sio_timeout); 2426 } else { 2427 /* Flush error messages, if any. */ 2428 sio_timeouts_until_log = 1; 2429 comwakeup((void *)NULL); 2430 untimeout(comwakeup, (void *)NULL, sio_timeout_handle); 2431 } 2432} 2433 2434static void 2435comwakeup(chan) 2436 void *chan; 2437{ 2438 struct com_s *com; 2439 int unit; 2440 2441 sio_timeout_handle = timeout(comwakeup, (void *)NULL, sio_timeout); 2442 2443 /* 2444 * Recover from lost output interrupts. 2445 * Poll any lines that don't use interrupts. 2446 */ 2447 for (unit = 0; unit < sio_numunits; ++unit) { 2448 com = com_addr(unit); 2449 if (com != NULL && !com->gone 2450 && (com->state >= (CS_BUSY | CS_TTGO) || com->poll)) { 2451 mtx_lock_spin(&sio_lock); 2452 siointr1(com); 2453 mtx_unlock_spin(&sio_lock); 2454 } 2455 } 2456 2457 /* 2458 * Check for and log errors, but not too often. 2459 */ 2460 if (--sio_timeouts_until_log > 0) 2461 return; 2462 sio_timeouts_until_log = hz / sio_timeout; 2463 for (unit = 0; unit < sio_numunits; ++unit) { 2464 int errnum; 2465 2466 com = com_addr(unit); 2467 if (com == NULL) 2468 continue; 2469 if (com->gone) 2470 continue; 2471 for (errnum = 0; errnum < CE_NTYPES; ++errnum) { 2472 u_int delta; 2473 u_long total; 2474 2475 mtx_lock_spin(&sio_lock); 2476 delta = com->delta_error_counts[errnum]; 2477 com->delta_error_counts[errnum] = 0; 2478 mtx_unlock_spin(&sio_lock); 2479 if (delta == 0) 2480 continue; 2481 total = com->error_counts[errnum] += delta; 2482 log(LOG_ERR, "sio%d: %u more %s%s (total %lu)\n", 2483 unit, delta, error_desc[errnum], 2484 delta == 1 ? "" : "s", total); 2485 } 2486 } 2487} 2488 2489static void 2490disc_optim(tp, t, com) 2491 struct tty *tp; 2492 struct termios *t; 2493 struct com_s *com; 2494{ 2495 if (!(t->c_iflag & (ICRNL | IGNCR | IMAXBEL | INLCR | ISTRIP | IXON)) 2496 && (!(t->c_iflag & BRKINT) || (t->c_iflag & IGNBRK)) 2497 && (!(t->c_iflag & PARMRK) 2498 || (t->c_iflag & (IGNPAR | IGNBRK)) == (IGNPAR | IGNBRK)) 2499 && !(t->c_lflag & (ECHO | ICANON | IEXTEN | ISIG | PENDIN)) 2500 && linesw[tp->t_line].l_rint == ttyinput) 2501 tp->t_state |= TS_CAN_BYPASS_L_RINT; 2502 else 2503 tp->t_state &= ~TS_CAN_BYPASS_L_RINT; 2504 com->hotchar = linesw[tp->t_line].l_hotchar; 2505} 2506 2507/* 2508 * Following are all routines needed for SIO to act as console 2509 */ 2510#include <sys/cons.h> 2511 2512struct siocnstate { 2513 u_char dlbl; 2514 u_char dlbh; 2515 u_char ier; 2516 u_char cfcr; 2517 u_char mcr; 2518}; 2519 2520#ifndef __alpha__ 2521static speed_t siocngetspeed __P((Port_t, struct speedtab *)); 2522#endif 2523static void siocnclose __P((struct siocnstate *sp, Port_t iobase)); 2524static void siocnopen __P((struct siocnstate *sp, Port_t iobase, int speed)); 2525static void siocntxwait __P((Port_t iobase)); 2526 2527#ifdef __alpha__ 2528int siocnattach __P((int port, int speed)); 2529int siogdbattach __P((int port, int speed)); 2530int siogdbgetc __P((void)); 2531void siogdbputc __P((int c)); 2532#else 2533static cn_probe_t siocnprobe; 2534static cn_init_t siocninit; 2535static cn_term_t siocnterm; 2536#endif 2537static cn_checkc_t siocncheckc; 2538static cn_getc_t siocngetc; 2539static cn_putc_t siocnputc; 2540 2541#ifndef __alpha__ 2542CONS_DRIVER(sio, siocnprobe, siocninit, siocnterm, siocngetc, siocncheckc, 2543 siocnputc, NULL); 2544#endif 2545 2546/* To get the GDB related variables */ 2547#if DDB > 0 2548#include <ddb/ddb.h> 2549#endif 2550 2551static void 2552siocntxwait(iobase) 2553 Port_t iobase; 2554{ 2555 int timo; 2556 2557 /* 2558 * Wait for any pending transmission to finish. Required to avoid 2559 * the UART lockup bug when the speed is changed, and for normal 2560 * transmits. 2561 */ 2562 timo = 100000; 2563 while ((inb(iobase + com_lsr) & (LSR_TSRE | LSR_TXRDY)) 2564 != (LSR_TSRE | LSR_TXRDY) && --timo != 0) 2565 ; 2566} 2567 2568#ifndef __alpha__ 2569 2570/* 2571 * Read the serial port specified and try to figure out what speed 2572 * it's currently running at. We're assuming the serial port has 2573 * been initialized and is basicly idle. This routine is only intended 2574 * to be run at system startup. 2575 * 2576 * If the value read from the serial port doesn't make sense, return 0. 2577 */ 2578 2579static speed_t 2580siocngetspeed(iobase, table) 2581 Port_t iobase; 2582 struct speedtab *table; 2583{ 2584 int code; 2585 u_char dlbh; 2586 u_char dlbl; 2587 u_char cfcr; 2588 2589 cfcr = inb(iobase + com_cfcr); 2590 outb(iobase + com_cfcr, CFCR_DLAB | cfcr); 2591 2592 dlbl = inb(iobase + com_dlbl); 2593 dlbh = inb(iobase + com_dlbh); 2594 2595 outb(iobase + com_cfcr, cfcr); 2596 2597 code = dlbh << 8 | dlbl; 2598 2599 for (; table->sp_speed != -1; table++) 2600 if (table->sp_code == code) 2601 return (table->sp_speed); 2602 2603 return (0); /* didn't match anything sane */ 2604} 2605 2606#endif 2607 2608static void 2609siocnopen(sp, iobase, speed) 2610 struct siocnstate *sp; 2611 Port_t iobase; 2612 int speed; 2613{ 2614 int divisor; 2615 u_char dlbh; 2616 u_char dlbl; 2617 2618 /* 2619 * Save all the device control registers except the fifo register 2620 * and set our default ones (cs8 -parenb speed=comdefaultrate). 2621 * We can't save the fifo register since it is read-only. 2622 */ 2623 sp->ier = inb(iobase + com_ier); 2624 outb(iobase + com_ier, 0); /* spltty() doesn't stop siointr() */ 2625 siocntxwait(iobase); 2626 sp->cfcr = inb(iobase + com_cfcr); 2627 outb(iobase + com_cfcr, CFCR_DLAB | CFCR_8BITS); 2628 sp->dlbl = inb(iobase + com_dlbl); 2629 sp->dlbh = inb(iobase + com_dlbh); 2630 /* 2631 * Only set the divisor registers if they would change, since on 2632 * some 16550 incompatibles (Startech), setting them clears the 2633 * data input register. This also reduces the effects of the 2634 * UMC8669F bug. 2635 */ 2636 divisor = ttspeedtab(speed, comspeedtab); 2637 dlbl = divisor & 0xFF; 2638 if (sp->dlbl != dlbl) 2639 outb(iobase + com_dlbl, dlbl); 2640 dlbh = (u_int) divisor >> 8; 2641 if (sp->dlbh != dlbh) 2642 outb(iobase + com_dlbh, dlbh); 2643 outb(iobase + com_cfcr, CFCR_8BITS); 2644 sp->mcr = inb(iobase + com_mcr); 2645 /* 2646 * We don't want interrupts, but must be careful not to "disable" 2647 * them by clearing the MCR_IENABLE bit, since that might cause 2648 * an interrupt by floating the IRQ line. 2649 */ 2650 outb(iobase + com_mcr, (sp->mcr & MCR_IENABLE) | MCR_DTR | MCR_RTS); 2651} 2652 2653static void 2654siocnclose(sp, iobase) 2655 struct siocnstate *sp; 2656 Port_t iobase; 2657{ 2658 /* 2659 * Restore the device control registers. 2660 */ 2661 siocntxwait(iobase); 2662 outb(iobase + com_cfcr, CFCR_DLAB | CFCR_8BITS); 2663 if (sp->dlbl != inb(iobase + com_dlbl)) 2664 outb(iobase + com_dlbl, sp->dlbl); 2665 if (sp->dlbh != inb(iobase + com_dlbh)) 2666 outb(iobase + com_dlbh, sp->dlbh); 2667 outb(iobase + com_cfcr, sp->cfcr); 2668 /* 2669 * XXX damp oscillations of MCR_DTR and MCR_RTS by not restoring them. 2670 */ 2671 outb(iobase + com_mcr, sp->mcr | MCR_DTR | MCR_RTS); 2672 outb(iobase + com_ier, sp->ier); 2673} 2674 2675#ifndef __alpha__ 2676 2677static void 2678siocnprobe(cp) 2679 struct consdev *cp; 2680{ 2681 speed_t boot_speed; 2682 u_char cfcr; 2683 int s, unit; 2684 struct siocnstate sp; 2685 2686 /* 2687 * Find our first enabled console, if any. If it is a high-level 2688 * console device, then initialize it and return successfully. 2689 * If it is a low-level console device, then initialize it and 2690 * return unsuccessfully. It must be initialized in both cases 2691 * for early use by console drivers and debuggers. Initializing 2692 * the hardware is not necessary in all cases, since the i/o 2693 * routines initialize it on the fly, but it is necessary if 2694 * input might arrive while the hardware is switched back to an 2695 * uninitialized state. We can't handle multiple console devices 2696 * yet because our low-level routines don't take a device arg. 2697 * We trust the user to set the console flags properly so that we 2698 * don't need to probe. 2699 */ 2700 cp->cn_pri = CN_DEAD; 2701 2702 for (unit = 0; unit < 16; unit++) { /* XXX need to know how many */ 2703 int flags; 2704 int disabled; 2705 if (resource_int_value("sio", unit, "disabled", &disabled) == 0) { 2706 if (disabled) 2707 continue; 2708 } 2709 if (resource_int_value("sio", unit, "flags", &flags)) 2710 continue; 2711 if (COM_CONSOLE(flags) || COM_DEBUGGER(flags)) { 2712 int port; 2713 Port_t iobase; 2714 2715 if (resource_int_value("sio", unit, "port", &port)) 2716 continue; 2717 iobase = port; 2718 s = spltty(); 2719 if (boothowto & RB_SERIAL) { 2720 boot_speed = siocngetspeed(iobase, comspeedtab); 2721 if (boot_speed) 2722 comdefaultrate = boot_speed; 2723 } 2724 2725 /* 2726 * Initialize the divisor latch. We can't rely on 2727 * siocnopen() to do this the first time, since it 2728 * avoids writing to the latch if the latch appears 2729 * to have the correct value. Also, if we didn't 2730 * just read the speed from the hardware, then we 2731 * need to set the speed in hardware so that 2732 * switching it later is null. 2733 */ 2734 cfcr = inb(iobase + com_cfcr); 2735 outb(iobase + com_cfcr, CFCR_DLAB | cfcr); 2736 outb(iobase + com_dlbl, 2737 COMBRD(comdefaultrate) & 0xff); 2738 outb(iobase + com_dlbh, 2739 (u_int) COMBRD(comdefaultrate) >> 8); 2740 outb(iobase + com_cfcr, cfcr); 2741 2742 siocnopen(&sp, iobase, comdefaultrate); 2743 2744 splx(s); 2745 if (COM_CONSOLE(flags) && !COM_LLCONSOLE(flags)) { 2746 cp->cn_dev = makedev(CDEV_MAJOR, unit); 2747 cp->cn_pri = COM_FORCECONSOLE(flags) 2748 || boothowto & RB_SERIAL 2749 ? CN_REMOTE : CN_NORMAL; 2750 siocniobase = iobase; 2751 siocnunit = unit; 2752 } 2753 if (COM_DEBUGGER(flags)) { 2754 printf("sio%d: gdb debugging port\n", unit); 2755 siogdbiobase = iobase; 2756 siogdbunit = unit; 2757#if DDB > 0 2758 gdbdev = makedev(CDEV_MAJOR, unit); 2759 gdb_getc = siocngetc; 2760 gdb_putc = siocnputc; 2761#endif 2762 } 2763 } 2764 } 2765#ifdef __i386__ 2766#if DDB > 0 2767 /* 2768 * XXX Ugly Compatability. 2769 * If no gdb port has been specified, set it to be the console 2770 * as some configuration files don't specify the gdb port. 2771 */ 2772 if (gdbdev == NODEV && (boothowto & RB_GDB)) { 2773 printf("Warning: no GDB port specified. Defaulting to sio%d.\n", 2774 siocnunit); 2775 printf("Set flag 0x80 on desired GDB port in your\n"); 2776 printf("configuration file (currently sio only).\n"); 2777 siogdbiobase = siocniobase; 2778 siogdbunit = siocnunit; 2779 gdbdev = makedev(CDEV_MAJOR, siocnunit); 2780 gdb_getc = siocngetc; 2781 gdb_putc = siocnputc; 2782 } 2783#endif 2784#endif 2785} 2786 2787static void 2788siocninit(cp) 2789 struct consdev *cp; 2790{ 2791 comconsole = DEV_TO_UNIT(cp->cn_dev); 2792} 2793 2794static void 2795siocnterm(cp) 2796 struct consdev *cp; 2797{ 2798 comconsole = -1; 2799} 2800 2801#endif 2802 2803#ifdef __alpha__ 2804 2805CONS_DRIVER(sio, NULL, NULL, NULL, siocngetc, siocncheckc, siocnputc, NULL); 2806 2807int 2808siocnattach(port, speed) 2809 int port; 2810 int speed; 2811{ 2812 int s; 2813 u_char cfcr; 2814 struct siocnstate sp; 2815 2816 siocniobase = port; 2817 comdefaultrate = speed; 2818 sio_consdev.cn_pri = CN_NORMAL; 2819 sio_consdev.cn_dev = makedev(CDEV_MAJOR, 0); 2820 2821 s = spltty(); 2822 2823 /* 2824 * Initialize the divisor latch. We can't rely on 2825 * siocnopen() to do this the first time, since it 2826 * avoids writing to the latch if the latch appears 2827 * to have the correct value. Also, if we didn't 2828 * just read the speed from the hardware, then we 2829 * need to set the speed in hardware so that 2830 * switching it later is null. 2831 */ 2832 cfcr = inb(siocniobase + com_cfcr); 2833 outb(siocniobase + com_cfcr, CFCR_DLAB | cfcr); 2834 outb(siocniobase + com_dlbl, 2835 COMBRD(comdefaultrate) & 0xff); 2836 outb(siocniobase + com_dlbh, 2837 (u_int) COMBRD(comdefaultrate) >> 8); 2838 outb(siocniobase + com_cfcr, cfcr); 2839 2840 siocnopen(&sp, siocniobase, comdefaultrate); 2841 splx(s); 2842 2843 cnadd(&sio_consdev); 2844 return (0); 2845} 2846 2847int 2848siogdbattach(port, speed) 2849 int port; 2850 int speed; 2851{ 2852 int s; 2853 u_char cfcr; 2854 struct siocnstate sp; 2855 int unit = 1; /* XXX !!! */ 2856 2857 siogdbiobase = port; 2858 gdbdefaultrate = speed; 2859 2860 printf("sio%d: gdb debugging port\n", unit); 2861 siogdbunit = unit; 2862#if DDB > 0 2863 gdbdev = makedev(CDEV_MAJOR, unit); 2864 gdb_getc = siocngetc; 2865 gdb_putc = siocnputc; 2866#endif 2867 2868 s = spltty(); 2869 2870 /* 2871 * Initialize the divisor latch. We can't rely on 2872 * siocnopen() to do this the first time, since it 2873 * avoids writing to the latch if the latch appears 2874 * to have the correct value. Also, if we didn't 2875 * just read the speed from the hardware, then we 2876 * need to set the speed in hardware so that 2877 * switching it later is null. 2878 */ 2879 cfcr = inb(siogdbiobase + com_cfcr); 2880 outb(siogdbiobase + com_cfcr, CFCR_DLAB | cfcr); 2881 outb(siogdbiobase + com_dlbl, 2882 COMBRD(gdbdefaultrate) & 0xff); 2883 outb(siogdbiobase + com_dlbh, 2884 (u_int) COMBRD(gdbdefaultrate) >> 8); 2885 outb(siogdbiobase + com_cfcr, cfcr); 2886 2887 siocnopen(&sp, siogdbiobase, gdbdefaultrate); 2888 splx(s); 2889 2890 return (0); 2891} 2892 2893#endif 2894 2895static int 2896siocncheckc(dev) 2897 dev_t dev; 2898{ 2899 int c; 2900 Port_t iobase; 2901 int s; 2902 struct siocnstate sp; 2903 2904 if (minor(dev) == siogdbunit) 2905 iobase = siogdbiobase; 2906 else 2907 iobase = siocniobase; 2908 s = spltty(); 2909 siocnopen(&sp, iobase, comdefaultrate); 2910 if (inb(iobase + com_lsr) & LSR_RXRDY) 2911 c = inb(iobase + com_data); 2912 else 2913 c = -1; 2914 siocnclose(&sp, iobase); 2915 splx(s); 2916 return (c); 2917} 2918 2919 2920int 2921siocngetc(dev) 2922 dev_t dev; 2923{ 2924 int c; 2925 Port_t iobase; 2926 int s; 2927 struct siocnstate sp; 2928 2929 if (minor(dev) == siogdbunit) 2930 iobase = siogdbiobase; 2931 else 2932 iobase = siocniobase; 2933 s = spltty(); 2934 siocnopen(&sp, iobase, comdefaultrate); 2935 while (!(inb(iobase + com_lsr) & LSR_RXRDY)) 2936 ; 2937 c = inb(iobase + com_data); 2938 siocnclose(&sp, iobase); 2939 splx(s); 2940 return (c); 2941} 2942 2943void 2944siocnputc(dev, c) 2945 dev_t dev; 2946 int c; 2947{ 2948 int s; 2949 struct siocnstate sp; 2950 Port_t iobase; 2951 2952 if (minor(dev) == siogdbunit) 2953 iobase = siogdbiobase; 2954 else 2955 iobase = siocniobase; 2956 s = spltty(); 2957 if (sio_inited) 2958 mtx_lock_spin(&sio_lock); 2959 siocnopen(&sp, iobase, comdefaultrate); 2960 siocntxwait(iobase); 2961 outb(iobase + com_data, c); 2962 siocnclose(&sp, iobase); 2963 if (sio_inited) 2964 mtx_unlock_spin(&sio_lock); 2965 splx(s); 2966} 2967 2968#ifdef __alpha__ 2969int 2970siogdbgetc() 2971{ 2972 int c; 2973 Port_t iobase; 2974 int s; 2975 struct siocnstate sp; 2976 2977 iobase = siogdbiobase; 2978 s = spltty(); 2979 siocnopen(&sp, iobase, gdbdefaultrate); 2980 while (!(inb(iobase + com_lsr) & LSR_RXRDY)) 2981 ; 2982 c = inb(iobase + com_data); 2983 siocnclose(&sp, iobase); 2984 splx(s); 2985 return (c); 2986} 2987 2988void 2989siogdbputc(c) 2990 int c; 2991{ 2992 int s; 2993 struct siocnstate sp; 2994 2995 s = spltty(); 2996 siocnopen(&sp, siogdbiobase, gdbdefaultrate); 2997 siocntxwait(siogdbiobase); 2998 outb(siogdbiobase + com_data, c); 2999 siocnclose(&sp, siogdbiobase); 3000 splx(s); 3001} 3002#endif 3003